Display substrate, preparation method thereof and display device

Abstract

A display substrate includes a substrate, a plurality of pixel circuits, a plurality of first light emitting elements, and at least one first data line. The substrate includes a first display area and a second display area, the first display area at least partially surrounding the second display area. The first display area includes a first sub-display area and a second sub-display area located on opposite sides of the second display area along a first direction, and a third sub-display area located on at least one side of the second display area along a second direction. The first data line includes a first sub-data line, a second sub-data line, and a third sub-data line connected to the first sub-data line and the second sub-data line. The first sub-data line is located in the first sub-display area and connected to the pixel circuits of the first sub-display area, the second sub-data line is located in the second sub-display area and connected to the pixel circuits of the second sub-display area. The third sub-data line is located in the third sub-display area and connected to at least one second pixel circuit of the third sub-display area.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and its preparation method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely fast response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible display devices that use OLEDs as light-emitting devices and are controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0003] Under-display camera technology is a new technology proposed to improve the screen-to-body ratio of display devices. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a display substrate, a method for preparing the same, and a display device.

[0006] On one hand, this disclosure provides a display substrate, including: a substrate, a plurality of pixel circuits, a plurality of first light-emitting elements, and at least one first data line. The substrate includes a first display area and a second display area, the first display area at least partially surrounding the second display area. The first display area includes: a first sub-display area and a second sub-display area located on opposite sides of the second display area along a first direction, and a third sub-display area located on at least one side of the second display area along a second direction, the first direction intersecting the second direction. The plurality of pixel circuits and the plurality of first light-emitting elements are located in the first display area; the plurality of pixel circuits include: a plurality of first pixel circuits and a plurality of second pixel circuits, the plurality of second pixel circuits being distributed among the plurality of first pixel circuits; at least one pixel circuit among the plurality of first pixel circuits is connected to at least one light-emitting element among the plurality of first light-emitting elements. At least one first data line is located in the first display area, the first data line including: a first sub-data line, a second sub-data line, and a third sub-data line; the third sub-data line is connected to the first sub-data line and the second data line. The first sub-data line is located in the first sub-display area and is connected to the pixel circuit of the first sub-display area; the second sub-data line is located in the second sub-display area and is connected to the pixel circuit of the second sub-display area; and the third sub-data line is located in the third sub-display area and is connected to at least one second pixel circuit of the third sub-display area.

[0007] In some exemplary embodiments, both the first sub-data line and the second sub-data line extend along the first direction.

[0008] In some exemplary embodiments, the third sub-data line includes at least: a first segment and a second segment, the first segment extending along a second direction, and the second segment extending along the first direction. One end of the first segment extends to the first sub-display area and connects to the first sub-data line, and the other end of the first segment connects to the second segment. The second segment is connected to at least one second pixel circuit of the third sub-display area.

[0009] In some exemplary embodiments, the first sub-data line, the second sub-data line, and the second segment of the third sub-data line are in the same layer, while the first segment and the second segment of the third sub-data line are in different layers.

[0010] In some exemplary embodiments, the first sub-data line and the second sub-data line are in the same layer, while the third sub-data line and the first sub-data line are in different layers.

[0011] In some exemplary embodiments, the substrate further includes a border region located around the first display area and the second display area. The border region is provided with at least one data connection line, which connects the third sub-data line and the second sub-data line.

[0012] In some exemplary embodiments, the data connection line includes at least: a first sub-data connection line, a second sub-data connection line, and a third sub-data connection line. The second sub-data connection line is connected between the first sub-data connection line and the third sub-data connection line, the first sub-data connection line is connected to the third sub-data connection line, and the third sub-data connection line is connected to the second sub-data connection line.

[0013] In some exemplary embodiments, the first sub-data connection line and the third sub-data connection line extend along a first direction, and the second sub-data connection line extends along a second direction.

[0014] In some exemplary embodiments, the first sub-data connection line and the third sub-data connection line are in the same layer, while the first sub-data connection line and the second sub-data connection line are in different layers.

[0015] In some exemplary embodiments, the second sub-data connection line is in the same layer as the first sub-data line and the second sub-data line.

[0016] In some exemplary embodiments, the display substrate further includes: a plurality of second light-emitting elements located in the second display area; at least one pixel circuit of the plurality of second pixel circuits is connected to at least one light-emitting element of the plurality of second light-emitting elements via a conductive line.

[0017] In some exemplary embodiments, in a plane perpendicular to the display substrate, the display substrate includes at least: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on the substrate. The semiconductor layer includes at least: an active layer for a plurality of transistors of the pixel circuit. The first conductive layer includes at least: the gate of the plurality of transistors of the pixel circuit and a first electrode of a storage capacitor. The second conductive layer includes at least: a second electrode of the storage capacitor of the pixel circuit. The third conductive layer includes at least: a first power line. The fourth conductive layer includes at least: a first connection electrode connecting the pixel circuit to a light-emitting element.

[0018] In some exemplary embodiments, the second segments of the first sub-data line, the second sub-data line, and the third sub-data line are located in the third conductive layer, and the first segment of the third sub-data line is located in the fourth conductive layer; or, the first sub-data line and the second sub-data line are located in the third conductive layer, and the third sub-data line is located in the fourth conductive layer.

[0019] On the other hand, embodiments of this disclosure provide a display device including a display substrate as described above.

[0020] On the other hand, this disclosure provides a method for fabricating a display substrate, comprising: forming a plurality of pixel circuits, a plurality of first light-emitting elements, and at least one first data line in a first display area of ​​a substrate. The first display area at least partially surrounds a second display area; the first display area includes: a first sub-display area and a second sub-display area located on opposite sides of the second display area along a first direction, and a third sub-display area located on at least one side of the second display area along a second direction; the first direction intersects the second direction. The plurality of pixel circuits include: a plurality of first pixel circuits and a plurality of second pixel circuits, the plurality of second pixel circuits being distributed among the plurality of first pixel circuits; at least one pixel circuit among the plurality of first pixel circuits is connected to at least one light-emitting element among the plurality of first light-emitting elements. The first data line includes: a first sub-data line, a second sub-data line, and a third sub-data line; the third sub-data line is connected to the first sub-data line and the second sub-data line. The first sub-data line is located in the first sub-display area and connected to the pixel circuits of the first sub-display area, the second sub-data line is located in the second sub-display area and connected to the pixel circuits of the second sub-display area, and the third sub-data line is located in the third sub-display area and connected to at least one second pixel circuit of the third sub-display area.

[0021] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0022] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0023] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0024] Figure 2 This is a partial structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0025] Figures 3A to 3C This is a partial structural diagram of the first display area according to at least one embodiment of the present disclosure;

[0026] Figure 4 This is a schematic diagram of the data line arrangement of a display substrate according to at least one embodiment of the present disclosure;

[0027] Figure 5 This is a partial layout diagram of the data lines of a display substrate according to at least one embodiment of the present disclosure;

[0028] Figure 6A This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0029] Figure 6B for Figure 6A The timing diagram of the pixel circuit shown is shown below.

[0030] Figure 7A This is a planar schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0031] Figure 7B for Figure 7A A partial cross-sectional view along the P-P' direction;

[0032] Figure 7C This is a schematic diagram of a pixel circuit after the semiconductor layer has been formed, according to at least one embodiment of the present disclosure;

[0033] Figure 7D This is a schematic diagram of a pixel circuit after the formation of the first conductive layer, according to at least one embodiment of the present disclosure;

[0034] Figure 7E This is a schematic diagram of a pixel circuit after the formation of the second conductive layer according to at least one embodiment of the present disclosure;

[0035] Figure 7F This is a schematic diagram of a pixel circuit after the formation of the third conductive layer, according to at least one embodiment of the present disclosure;

[0036] Figure 7G This is a schematic diagram of a pixel circuit after the formation of the fourth conductive layer, according to at least one embodiment of the present disclosure;

[0037] Figure 8A This is a schematic diagram showing the connection positions of the first sub-data line and the third sub-data line according to at least one embodiment of the present disclosure;

[0038] Figure 8B This is a schematic diagram showing the connection position of the first and second segments of the third sub-data line according to at least one embodiment of the present disclosure.

[0039] Figure 8C This is a schematic diagram showing the cutoff position of the second segment of the third sub-data line according to at least one embodiment of the present disclosure;

[0040] Figure 8D This is a schematic diagram showing the connection between the third sub-data line and the data connection line according to at least one embodiment of the present disclosure;

[0041] Figure 8E This is a schematic diagram showing the connection between the second sub-data line and the data connection line according to at least one embodiment of the present disclosure;

[0042] Figure 9 This is a schematic diagram of another arrangement of data lines on a display substrate according to at least one embodiment of the present disclosure;

[0043] Figure 10 This is a schematic diagram of another arrangement of data lines on a display substrate according to at least one embodiment of the present disclosure;

[0044] Figure 11 This is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0045] Figure 12 This is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0046] Figure 13 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0047] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0048] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0049] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0050] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0051] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0052] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0053] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0054] In this specification, "connection" includes the situation where constituent elements are connected together by a component that has a certain electrical function. There are no particular limitations on the "component that has a certain electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "components that have a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0055] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0056] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0057] This disclosure provides a display substrate in at least one embodiment, comprising: a substrate, a plurality of pixel circuits, a plurality of first light-emitting elements, and at least one first data line. The substrate includes a first display area and a second display area. The first display area at least partially surrounds the second display area. The first display area includes: a first sub-display area and a second sub-display area located on opposite sides of the second display area along a first direction, and a third sub-display area located on at least one side of the second display area along a second direction. The first direction intersects the second direction. The plurality of pixel circuits and the plurality of first light-emitting elements are located in the first display area. The plurality of pixel circuits include: a plurality of first pixel circuits and a plurality of second pixel circuits, with the plurality of second pixel circuits distributed among the plurality of first pixel circuits. At least one pixel circuit among the plurality of first pixel circuits is connected to at least one light-emitting element among the plurality of first light-emitting elements. At least one first data line is located in the first display area. The first data line includes: a first sub-data line, a second sub-data line, and a third sub-data line. The third sub-data line is connected to the first sub-data line and the second data line. The first sub-data line is located in the first sub-display area and is connected to the pixel circuit of the first sub-display area; the second sub-data line is located in the second sub-display area and is connected to the pixel circuit of the second sub-display area; and the third sub-data line is located in the third sub-display area and is connected to at least one second pixel circuit of the third sub-display area.

[0058] In some examples, multiple second pixel circuits are distributed among multiple first pixel circuits, which may include: in a second direction, multiple first pixel circuits are arranged between two adjacent second pixel circuits. The multiple second pixel circuits may be arranged sequentially along a first direction. However, this embodiment is not limited to this.

[0059] In some examples, a first sub-display area has multiple first pixel circuits, a second sub-display area has multiple first pixel circuits, and a third sub-display area has multiple first pixel circuits and multiple second pixel circuits. A first sub-data line of a first data line is connected to at least one first pixel circuit in the first sub-display area, a second sub-data line is connected to at least one first pixel circuit in the second sub-display area, and a third sub-data line is connected to at least one second pixel circuit in the third sub-display area. In other examples, a first sub-display area has multiple first pixel circuits, a second sub-display area has multiple first pixel circuits and multiple second pixel circuits, and a third sub-display area has multiple first pixel circuits and multiple second pixel circuits. A first sub-data line of a first data line is connected to at least one first pixel circuit in the first sub-display area, a second sub-data line is connected to at least one first pixel circuit or at least one second pixel circuit in the second sub-display area, and a third sub-data line is connected to at least one second pixel circuit in the third sub-display area. In other examples, the first sub-display area is provided with multiple first pixel circuits and multiple second pixel circuits, the second sub-display area is provided with multiple first pixel circuits and multiple second pixel circuits, and the third sub-display area is provided with multiple first pixel circuits and multiple second pixel circuits. A first sub-data line of the first data line is connected to at least one first pixel circuit or a second pixel circuit of the first sub-display area, a second sub-data line is connected to at least one first pixel circuit or a second pixel circuit of the second sub-display area, and a third sub-data line is connected to at least one second pixel circuit of the third sub-display area. However, this embodiment is not limited to this.

[0060] In some examples, the first direction is parallel to the column direction of the subpixels within the display area, and the second direction is parallel to the row direction of the subpixels within the display area. The first direction is perpendicular to the second direction.

[0061] The display substrate provided in this embodiment separates the first sub-display area and the second sub-display area in the first direction in the second display area. By setting a third sub-data line in the third sub-display area, the first sub-data line of the first sub-display area and the second sub-data line of the second sub-display area are connected, which can realize the transmission of data signals and avoid affecting the light transmittance of the second display area by wiring in the second display area, thereby improving the display effect.

[0062] In some exemplary embodiments, both the first sub-data line and the second sub-data line extend along a first direction. For example, the extensions of the first and second sub-data lines included in a first data line may coincide. However, this embodiment is not limited to this.

[0063] In some exemplary embodiments, the third sub-data line includes at least: a first segment and a second segment, the first segment extending along a second direction and the second segment extending along a first direction. One end of the first segment extends to the first sub-display area and connects to the first sub-data line, and the other end of the first segment connects to the second segment. The second segment is connected to at least one second pixel circuit of the third sub-display area. However, this embodiment is not limited thereto. In some examples, the third sub-data line may include: a first segment, a second segment, and a third segment, the first segment and the third segment extending along the second direction, and the second segment extending along the first direction; one end of the first segment extends to the first sub-display area and connects to the first sub-data line, and the other end of the first segment connects to the second segment in the third sub-display area; one end of the third segment extends to the second sub-display area and connects to the second sub-data line, and the other end of the third segment connects to the second segment in the third sub-display area.

[0064] In some exemplary embodiments, the first sub-data line, the second sub-data line, and the second segment of the third sub-data line can be of the same layer, while the first segment and the second segment of the third sub-data line can be of different layers. However, this embodiment is not limited in this respect.

[0065] In some exemplary embodiments, the first sub-data line and the second sub-data line can be on the same layer, while the third sub-data line and the first sub-data line can be on different layers. In some examples, the first segment and the second segment of the third sub-data line can be a single unit. However, this embodiment is not limited to this.

[0066] In some exemplary embodiments, the substrate further includes a border region. The border region is located around the first display area and the second display area. The border region is provided with at least one data connection line, which connects the third sub-data line and the second sub-data line. In this exemplary embodiment, the connection between the third sub-data line and the second sub-data line is achieved by providing a data connection line in the border region. However, this embodiment is not limited thereto.

[0067] In some exemplary embodiments, the data connection line includes at least a first sub-data connection line, a second sub-data connection line, and a third sub-data connection line. The second sub-data connection line is connected between the first and third sub-data connection lines, the first sub-data connection line is connected to the third sub-data connection line, and the third sub-data connection line is connected to the second sub-data connection line. In this example, the data connection line includes multiple sub-data connection lines connected sequentially.

[0068] In some exemplary embodiments, the first sub-data connection line and the third sub-data connection line extend along a first direction, and the second sub-data connection line extends along a second direction.

[0069] In some exemplary embodiments, the first sub-data connection line and the third sub-data connection line are on the same layer, while the first sub-data connection line and the second sub-data connection line are on different layers. However, this embodiment is not limited to this. For example, the first sub-data connection line, the second sub-data connection line, and the third sub-data connection line can be a single integrated structure.

[0070] In some exemplary embodiments, the second sub-data connection line is on the same layer as the first and second sub-data lines. However, this embodiment is not limited to this.

[0071] In some exemplary embodiments, the display substrate further includes a plurality of second light-emitting elements located in the second display area. At least one pixel circuit of the plurality of second pixel circuits is connected to at least one light-emitting element of the plurality of second light-emitting elements via a conductive line.

[0072] In some exemplary embodiments, in a plane perpendicular to the display substrate, the display substrate includes at least: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on the substrate. The semiconductor layer includes at least: an active layer for a plurality of transistors in the pixel circuit. The first conductive layer includes at least: the gates of the plurality of transistors in the pixel circuit and a first electrode of a storage capacitor. The second conductive layer includes at least: a second electrode of the storage capacitor. The third conductive layer includes at least: a first power line. The fourth conductive layer includes at least: a first connection electrode connecting the pixel circuit and the light-emitting element. In some examples, the pixel circuit can be a 7T1C structure. However, this embodiment is not limited to this.

[0073] In some exemplary embodiments, the second segments of the first sub-data line, the second sub-data line, and the third sub-data line are located in the third conductive layer, and the first segment of the third sub-data line is located in the fourth conductive layer. Alternatively, the first sub-data line and the second sub-data line are located in the third conductive layer, and the third sub-data line is located in the fourth conductive layer. However, this embodiment is not limited to this.

[0074] The display substrate of this embodiment will be illustrated below with several examples.

[0075] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as Figure 1 As shown, the substrate of the display substrate includes: a display area and a bezel area R3 located around the periphery of the display area. The bezel area R3 surrounds the display area. The display area includes: a first display area R1 and a second display area R2, wherein the first display area R1 at least partially surrounds the second display area R2. For example, Figure 1The second display area R2 shown is located at the top center of the display substrate, and one side of the second display area R2 is adjacent to the bezel area R3. However, this embodiment is not limited to this. For example, the second display area R2 can be located at other positions such as the upper left corner or the upper right corner of the display substrate.

[0076] In some exemplary implementations, such as Figure 1 As shown, the display area can be rectangular, for example, a rounded rectangle. The second display area R2 can be circular. However, this embodiment is not limited to this. For example, the second display area R2 can be rectangular, elliptical, or other shapes.

[0077] In some exemplary embodiments, the first display area R1 can be a non-transparent display area, and the second display area R2 can be a transparent display area. That is, the first display area R1 is opaque, while the second display area R2 is transparent. For example, the orthographic projection of hardware such as a photosensor (e.g., a camera) onto the display substrate can be located within the second display area R2 of the display substrate. The display substrate in this example does not require drilling holes, making a true full-screen display possible while ensuring the practicality of the display substrate.

[0078] In some exemplary implementations, such as Figure 1As shown, the first display area R1 includes: a first sub-display area R11 and a second sub-display area located on opposite sides of the second display area R2 along the first direction D1, and a third sub-display area located on opposite sides of the second display area R2 along the second direction D2. The second sub-display area includes a second sub-display first sub-sub-area R12a and a second sub-display second sub-area R12b, and the third sub-display area includes a third sub-display first sub-area R13a and a third sub-display second sub-area R13b. The first sub-display area R11 is located below the second display area R2, and the second sub-display area is located above the second display area R2. The first sub-display area R11 and the second sub-display area are separated by the second display area R2 along the first direction D1, and the second sub-display area is separated by the second display area R2 along the second direction D2, that is, the second sub-display first sub-area R12a and the second sub-display second sub-area R12b are located on opposite sides of the second display area R2 along the second direction D2. However, this embodiment is not limited in this respect. For example, the second sub-display first sub-area R12a and the second sub-display second sub-area R12b can be connected in the second direction D2. The third sub-display first sub-area R13a is located to the left of the second display area R2, and the third sub-display second sub-area R13b is located to the right of the second display area R2. The third sub-display first sub-area R13a and the third sub-display second sub-area R13b are separated by the first sub-display area R11, the second display area R2, and the second sub-display area. The third sub-display first sub-area R13a is connected to the first sub-display area R11 and the second sub-display first sub-area R12a, and the third sub-display second sub-area R13b is connected to the first sub-display area R11 and the second sub-display second sub-area R12b. The first direction D1 intersects the second direction D2; for example, the first direction D1 is perpendicular to the second direction D2. In some examples, the first direction D1 is parallel to the sub-pixel column direction, and the second direction D2 is parallel to the sub-pixel row direction. However, this embodiment is not limited to this.

[0079] In some exemplary embodiments, the display substrate may include a plurality of sub-pixels disposed on a substrate. At least one sub-pixel includes a pixel circuit and a light-emitting element. The pixel circuit is configured to drive the light-emitting element. For example, the pixel circuit is configured to provide a driving current to drive the light-emitting element to emit light. For example, the light-emitting element may be an organic light-emitting diode (OLED), which emits red, green, blue, or white light under the drive of its corresponding pixel circuit. The color emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: a first electrode (e.g., an anode), a second electrode (e.g., a cathode), and an organic light-emitting layer disposed between the first and second electrodes. The first electrode may be connected to the pixel circuit. However, this embodiment is not limited thereto. In some examples, the light-emitting element may be a quantum dot light-emitting diode (QLED), a micro-LED, or a mini-LED.

[0080] In some exemplary embodiments, a pixel unit may include three sub-pixels (e.g., a red sub-pixel R, a blue sub-pixel B, and a green sub-pixel G), which may be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement. For example, a pixel unit may include four sub-pixels (a red sub-pixel R, a blue sub-pixel B, a green sub-pixel G, and a white sub-pixel), which may be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, the embodiments disclosed herein are not limited to this.

[0081] In some exemplary embodiments, to improve the light transmittance of the second display area R2, only a light-emitting element can be provided in the second display area R2, while the pixel circuit that drives the light-emitting element of the second display area R2 is provided in the first display area R1. That is, the light transmittance of the second display area R2 is improved by separating the light-emitting element and the pixel circuit. In this example, no pixel circuit is provided in the second display area R2.

[0082] Figure 2 This is a partial structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 2As shown, the display substrate includes: a plurality of first pixel circuits 10, a plurality of second pixel circuits 20, and a plurality of first light-emitting elements 30 located in a first display area R1, and a plurality of second light-emitting elements 40 located in a second display area R2. The plurality of second pixel circuits 20 may be spaced apart from the plurality of first pixel circuits 10; for example, the plurality of first pixel circuits 20 may be arranged between two adjacent second pixel circuits 20 in a first direction. At least one of the plurality of first pixel circuits 10 may be connected to at least one of the plurality of first light-emitting elements 30, and the orthographic projection of at least one first pixel circuit 10 on the substrate may at least partially overlap with the orthographic projection of at least one first light-emitting element 30 on the substrate. The first pixel circuit 10 may be configured to provide a driving signal to the connected first light-emitting element 30 to drive the first light-emitting element 30 to emit light. At least one of the plurality of second pixel circuits 20 may be connected to at least one of the plurality of second light-emitting elements 40 via a conductive line L. The second pixel circuit 20 may be configured to provide a driving signal to the connected second light-emitting element 40 to drive the second light-emitting element 40 to emit light. Since the second light-emitting element 40 and the second pixel circuit 20 are located in different regions, there is no overlap between the orthographic projection of at least one second pixel circuit 20 on the substrate and the orthographic projection of at least one second light-emitting element 40 on the substrate.

[0083] In some exemplary embodiments, the density of the second light-emitting element 40 in the second display area R2 can be approximately equal to the density of the first light-emitting element 30 in the first display area R1. That is, the resolution of the second display area R2 can be approximately the same as the resolution of the first display area R1. However, this embodiment is not limited to this. For example, the density of the second light-emitting element 40 can be greater than or less than the density of the first light-emitting element 30. That is, the resolution of the second display area R2 can be greater than or less than the resolution of the first display area R1.

[0084] In some exemplary embodiments, the light-emitting area of ​​the second light-emitting element 40 may be smaller than the light-emitting area of ​​the first light-emitting element 30. That is, the light-emitting area of ​​the first light-emitting element 30 is larger than the light-emitting area of ​​the second region light-emitting element 40. The light-emitting area of ​​the light-emitting element may correspond to the area of ​​the opening in the pixel definition layer. In some examples, a light-transmitting area is provided between adjacent second light-emitting elements 40 in the second display area R2. For example, multiple light-transmitting areas are connected to each other, forming a continuous light-transmitting area spaced apart by multiple second light-emitting elements 40. The conductive line L may be made of a transparent conductive material to maximize the light transmittance of the light-transmitting area.

[0085] In some exemplary embodiments, within the first display area R1, the area where the second pixel circuit 20 is disposed can be obtained by reducing the size of the first pixel circuit 10 in the second direction D2. For example, the size of the first pixel circuit 10 in the second direction D2 can be smaller than the size of the first light-emitting element 30 in the second direction D2. The second direction D2 is, for example, a sub-pixel row direction, but is not limited thereto. In other embodiments, the second direction D2 can be a sub-pixel column direction. This exemplary embodiment is described using the second direction D2 as a sub-pixel row direction as an example. For example, the sizes of the first pixel circuit 10 and the second pixel circuit 20 in the second direction D2 can be the same, and the size of each pixel circuit in the second direction D2 can differ from the size of the first light-emitting element 30 in the second direction D2 by approximately 4 micrometers (μm). The size of each pixel circuit in the first direction D1 is approximately the same as the size of the first light-emitting element 30 in the first direction D1. Wherein, the first direction D1 is perpendicular to the second direction D2.

[0086] In some exemplary embodiments, the first sub-display area R11, the second sub-display area, and the third sub-display area of ​​the first display area R1 are each provided with a plurality of first pixel circuits 10 and second pixel circuits 20. The second light-emitting element 40 in the second display area R2 can be connected to the second pixel circuit 20 in the third sub-display area. The second pixel circuit 20 in the first display area R1 that is not connected to the light-emitting element can be referred to as a dummy pixel circuit. However, this embodiment is not limited in this respect. For example, the first pixel circuit 10 and the second pixel circuit 20 arranged among the plurality of first pixel circuits 10 can be provided in the third sub-display area of ​​the first display area R1, and the first sub-display area R11 and the second sub-display area can only be provided with the first pixel circuit 10 and not with the second pixel circuit 20. Alternatively, the first pixel circuit 10 and the second pixel circuit 20 arranged among the plurality of first pixel circuits 10 can be provided in the third sub-display area and the second sub-display area of ​​the first display area R1, and the first sub-display area R11 can only be provided with the first pixel circuit 10 and not with the second pixel circuit 20.

[0087] Figures 3A to 3C This is a partial structural diagram of the first display area according to at least one embodiment of the present disclosure. To further illustrate the additional columns of pixel circuits after the pixel circuit is compressed, Figure 3A A schematic diagram of the structure of a sub-pixel of the first display area R1 is shown. Figure 3B It shows Figure 3A A schematic diagram of a portion of the structure of the first display area R1 (including only the pixel circuitry). Figure 3C It shows Figure 3A A schematic diagram of a portion of the structure of the first display area R1 (including only the light-emitting elements).

[0088] In some exemplary implementations, such as Figures 3A to 3C As shown, the size of the pixel circuit in the second direction D2 is smaller than the size of the light-emitting element in the second direction D2. Therefore, the pixel circuits in the 2nd and 9th columns from right to left are not connected to any first light-emitting element 30, belonging to multi-column pixel circuits. They can serve as second pixel circuits 20 to connect to the second light-emitting element 40 within the second display area R2, or simply as unused second pixel circuits 20 (i.e., virtual pixel circuits). Figure 3C As shown, any first light-emitting element 30 can be one of four types of light-emitting elements: RG1BG2. The first electrode E1 of the first light-emitting element 30 can be connected to the first transfer electrode CE1 of the first pixel circuit 10 through the second transfer electrode CE2. R represents a red light-emitting element, G1 represents a green light-emitting element, B represents a blue light-emitting element, and G2 represents a green light-emitting element. At least one second pixel circuit 20 can have a first transfer electrode, and at least one second light-emitting element 40 can have a second transfer electrode. For example, connecting at least one second pixel circuit 20 and at least one second light-emitting element 40 through a conductive line L can include: the conductive line L connecting the first transfer electrode of at least one second pixel circuit 20 and the second transfer electrode of at least one second light-emitting element 40 respectively. In order to have sufficient space to set the conductive line L, the axes of the first transfer electrode and the second transfer electrode in the same row of sub-pixels can be located on a straight line. However, this embodiment is not limited to this.

[0089] In some exemplary embodiments, Figure 3C In the illustrated subpixel arrangement, a repeating unit RP includes two green (G) subpixels arranged in the first direction D1, and red (R) and blue (B) subpixels respectively disposed on both sides of the two green subpixels in the second direction D2. The red and green subpixels can form a pixel unit, and a virtual pixel can be formed by borrowing a blue subpixel from an adjacent repeating unit for display. However, this embodiment is not limited to this.

[0090] Figure 4 This is a schematic diagram of the data line arrangement of a display substrate according to at least one embodiment of the present disclosure. Figure 5 This is a partial schematic diagram of the data line arrangement of a display substrate according to at least one embodiment of the present disclosure. Figure 4 and Figure 5 The illustration uses only a few data lines as examples. Figure 4The illustration uses only a few first pixel circuits 10 and second pixel circuits 20 as examples. In this example, the display substrate has a central axis OO' in the second direction D2, and the display substrate can be symmetrical about the central axis OO'. The following explanation uses the data line arrangement of the left half of the display substrate as an example.

[0091] In some exemplary embodiments, the bezel region R3 includes a driver chip region, which may include an integrated circuit configured to be connected to multiple data lines of the display region. The second sub-display area may be located on the side of the second display area R2 away from the driver chip region, and the first sub-display area R11 may be located on the side of the second display area R2 closer to the driver chip region.

[0092] In some exemplary implementations, such as Figure 1 and Figure 4 As shown, the first display area R1 is provided with multiple first data lines. The border area R3 is provided with multiple data connection lines 64. At least one first data line is connected to at least one pixel circuit of the first sub-display area R11, and is connected to at least one pixel circuit of the second sub-display first sub-area R12a of the second sub-display area via at least one data connection line 64. For example, at least one first data line is connected to a column of first pixel circuits of the first sub-display area R11 and a column of first pixel circuits of the second sub-display first sub-area R12a.

[0093] In some exemplary implementations, such as Figure 1 and Figure 4As shown, at least one first data line includes: a first sub-data line 61, a second sub-data line 62, and a third sub-data line 63. The third sub-data line 63 is connected between the first sub-data line 61 and the second sub-data line 62. The first sub-data line 61 is located in the first sub-display area R11 and is connected to a column of first pixel circuits in the first sub-display area R11. The second sub-data line 62 is located in the second sub-display first sub-area R12a of the second sub-display area and is connected to a column of first pixel circuits in the second sub-display first sub-area R12a. The third sub-data line 63 is located in the third sub-display first sub-area R13a of the third sub-display area and extends to connect with the first sub-data line 61 in the first sub-display area R11, and is connected to the data connection line 64 of the border area R3. The third sub-data line 63 is connected to a plurality of second pixel circuits arranged along the first direction D1 in the third sub-display first sub-area R13a. The data connection line 64 of the border area R3 is connected to the second sub-data line 62 of the second sub-display first sub-area R12a. In this example, the data signal provided by the driver chip area can be transmitted to the second sub-data line 62 through the first sub-data line 61, the third sub-data line 63 and the data connection line 64. The third sub-data line 63 is used to provide data signals to the pixel circuit of the second sub-display area after being wound around the third sub-display area. This can avoid the data line being directly wired in the second display area R2 and affecting the light transmittance of the second display area R2, thereby improving the display effect.

[0094] In some exemplary embodiments, the first display area R1 is provided with an array of pixel circuits. For example, the third sub-display area is provided with n1 columns of pixel circuits, the first sub-display area R11 is provided with n2 columns of pixel circuits, and the second sub-display area is provided with a total of n3 columns of pixel circuits. In this example, n3 can be less than n2. However, this embodiment is not limited to this. For example, n3 can be equal to n2.

[0095] In some exemplary implementations, such as Figure 4 and Figure 5 As shown, within the first sub-display area R11, a first sub-data line 61 extends along a first direction D1, and multiple first sub-data lines 61 are arranged sequentially along a second direction D2. One first sub-data line 61 can be connected to a column of first pixel circuits 10, configured to provide data signals introduced from the driver chip area to the corresponding first pixel circuit 10. Alternatively, one first sub-data line 61 can be connected to a column of second pixel circuits. Within the second sub-display area, a second sub-data line 62 can extend along the first direction D1, and multiple second sub-data lines 62 are arranged sequentially along the second direction D2. One second sub-data line 62 can be connected to a column of first pixel circuits 10 or a column of second pixel circuits 20 within the second sub-display area. The first sub-data lines 61 and 62 are separated by the second display area R2. In some examples, the first sub-data lines 61 and 62 can be in the same layer.

[0096] In some exemplary implementations, such as Figure 4 and Figure 5 As shown, within the third sub-display area, the third sub-data line 63 includes: a first segment 631 and a second segment 632 interconnected. The first segment 631 extends along a second direction D2, and multiple first segments 631 are arranged sequentially along a first direction D1. The second segment 632 extends along the first direction D1, and multiple second segments 632 are arranged sequentially along the second direction D2. One end of the first segment 631 extends to the first sub-display area R11 and connects with the first sub-data line 61, while the other end of the first segment 631 connects with the second segment 632 in the third sub-display area. The second segment 632 is connected to multiple second pixel circuits 20 arranged along the first direction D1 within the third sub-display area. In some examples, the multiple second pixel circuits 20 connected to the second segment 632 are connected to the second light-emitting element 40 of the second display area R2. However, this embodiment is not limited to this. For example, the multiple second pixel circuits 20 connected to the second segment 632 can be virtual pixel circuits, i.e., they may not be connected to the light-emitting element. In some examples, the first line segment 631 and the second line segment 632 can be of different layers. For example, the second line segment 632 and the first sub-data line 61 can be of the same layer, while the first line segment 631 and the first sub-data line 61 can be of different layers. In some examples, the first line segment 631 and the second line segment 632 can be of one integrated structure and of different layers from the first sub-data line 61. However, this embodiment is not limited in this respect.

[0097] In some exemplary implementations, such as Figure 4 and Figure 5As shown, multiple data connection lines 64 are located on the side of the second display area R2 away from the driver chip area, for example, in the upper bezel area. At least one data connection line 64 includes: a first sub-data connection line 641, a second sub-data connection line 642, and a third sub-data connection line 643. The first sub-data connection line 641 and the third sub-data connection line 643 extend along a first direction D1, and the second sub-data connection line 642 extends along a second direction D2. For example, the lengths of the multiple second sub-data connection lines 642 along the second direction D2 can be the same. The multiple first sub-data connection lines 641 and the multiple third sub-data connection lines 643 are arranged sequentially along the second direction D2, and the multiple second sub-data connection lines 642 are arranged sequentially along the first direction D1. The second sub-data connection lines 642 are connected to the first sub-data connection line 641 and the third sub-data connection line 643, respectively. The first sub-data connection line 641 is connected to the second segment 632 of the third sub-data line 63, and the third sub-data connection line 643 is connected to the second sub-data line 62. In some examples, the first sub-data connection line 641 and the third sub-data connection line 643 are on the same layer, while the second sub-data connection line 642 is on a different layer. The second sub-data connection line 642 may be on the same layer as the second segment 632 of the third sub-data line 63 and the second sub-data line 62. However, this embodiment is not limited to this.

[0098] In some exemplary embodiments, the first light-emitting element connected to the first pixel circuit connected to the first sub-data line 61 and the second light-emitting element connected to the second pixel circuit connected to the corresponding third sub-data line 63 can be located in the same column, and the first light-emitting element connected to the first pixel circuit connected to the first sub-data line 61 and the first light-emitting element connected to the first pixel circuit connected to the corresponding second sub-data line 62 can be located in the same column. However, this embodiment is not limited in this respect.

[0099] In some exemplary implementations, such as Figure 4 and Figure 5As shown, the first segments 631 of multiple third sub-data lines 63 are arranged along the first direction D1. The first segment 631 closer to the second display area R2 is connected to the first sub-data line 61 closer to the central axis OO'; the first segment 631 closer to the second display area R2 is connected to the second segment 632 farther away from the central axis OO'. Along the second direction D2 away from the second display area R2, the length of the multiple second segments 632 gradually decreases in the first direction D1. Along the first direction D1 away from the second display area R2, the length of the multiple first segments 631 gradually decreases in the second direction D2. However, this embodiment is not limited to this. For example, along the first direction D1 away from the second display area R2, the length of the multiple first segments 631 in the second direction D2 remains unchanged. For example, along the second direction D2 away from the second display area R2, the length of the multiple second segments 632 gradually increases in the first direction D1.

[0100] In some exemplary embodiments, the first display area R1 is further provided with a plurality of second data lines 71. The plurality of second data lines 71 extend along a first direction D1 and are arranged sequentially along a second direction D2. The second data lines 71 within the first display area R1 do not require winding design. At least one second data line 71 can be connected to a column of pixel circuits (a first pixel circuit or a second pixel circuit). Within the third sub-display area, for a column of second pixel circuits 20, a portion of the second pixel circuits 20 is connected to the second segment 632 of the third sub-data line 63, and another portion can be connected to the second data line 71, while the second segment 632 of the third sub-data line 63 and the second data line 71 are disconnected.

[0101] The pixel circuit of this embodiment will be illustrated below.

[0102] Figure 6A This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. Figure 6B for Figure 6A The timing diagram of the pixel circuit shown is shown.

[0103] In some exemplary embodiments, the pixel circuits of the first display area R1 can all be 7T1C structures. However, this embodiment is not limited to this. For example, the pixel circuits may include other numbers of transistors and capacitors, such as 5T1C or 6T1C structures.

[0104] In some exemplary implementations, such as Figure 6AAs shown, each pixel circuit includes six switching transistors (T1, T2, T4 to T7), one driving transistor T3, and one storage capacitor Cst. The six switching transistors are, respectively, a data writing transistor T4, a threshold compensation transistor T2, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, and a second reset transistor T7. The light-emitting element EL includes a first electrode E1, a second electrode E2, and an organic light-emitting layer located between the first electrode E1 and the second electrode E2. For example, the first electrode E1 can be an anode, and the second electrode E2 can be a cathode.

[0105] In some exemplary embodiments, the driving transistor and the six switching transistors can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve product yield. In some possible implementations, the driving transistor and the six switching transistors may include both P-type and N-type transistors.

[0106] In some exemplary embodiments, the driving transistor and the six switching transistors can be low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the OPT TFT is made of oxide semiconductor. LTPS TFTs offer advantages such as high mobility and fast charging, while OPT TFTs offer advantages such as low leakage current. Integrating LTPS and OPT TFTs onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0107] In some exemplary implementations, such as Figure 6A and Figure 6BAs shown, the display substrate includes a scan line GL, a data line DL, a first power line PL1, a second power line PL2, a light emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. In some examples, the first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel circuit, and the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel circuit, wherein the first voltage signal VDD is greater than the second voltage signal VSS. The scan line GL is configured to provide a scan signal SCAN to the pixel circuit, the data line DL is configured to provide a data signal DATA to the pixel circuit, the light emission control line EML is configured to provide a light emission control signal EM to the pixel circuit, the first reset control line RST1 is configured to provide a first reset control signal RESET1 to the pixel circuit, and the second reset control line RST2 is configured to provide a scan signal SCAN to the pixel circuit. For example, in a row of pixel circuits, the second reset control line RST2 can be connected to the scan line GL to be input with the scan signal SCAN. However, this embodiment is not limited to this. For example, the second reset control line RST2 can be input with the second reset control signal RESET2. For instance, in the nth row pixel circuit, the first reset control line RST1 can be connected to the scan line GL of the (n-1)th row pixel circuit to be input with the scan signal SCAN(n-1), meaning the first reset control signal RESET1(n) is the same as the scan signal SCAN(n-1). In this example, the first reset control line RST1 connected to the nth row pixel circuit and the second reset control line RST2 connected to the (n-1)th row pixel circuit can be a single integrated structure. This reduces the number of signal lines on the display substrate, enabling a narrow bezel on the display substrate.

[0108] In some examples, the first initial signal line INIT1 and the second initial signal line INIT2 can provide the same initial signal. For example, the first initial signal line INIT1 connected to the nth row pixel circuit and the second initial signal line INIT2 connected to the (n-1)th row pixel circuit can be a single structure. However, this embodiment is not limited to this.

[0109] In some exemplary implementations, such as Figure 6AAs shown, in the pixel circuit provided in this embodiment, the driving transistor T3 is electrically connected to the light-emitting element EL, and outputs a driving current to drive the light-emitting element EL to emit light under the control of signals such as the scan signal SCAN, data signal DATA, first voltage signal VDD, and second voltage signal VSS. The gate of the data writing transistor T4 is connected to the scan line GL, the first terminal of the data writing transistor T4 is connected to the data line DL, and the second terminal of the data writing transistor T4 is connected to the first terminal of the driving transistor T3. The gate of the threshold compensation transistor T2 is connected to the scan line GL, the first terminal of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3, and the second terminal of the threshold compensation transistor T2 is connected to the second terminal of the driving transistor T3. The gate of the first light-emitting control transistor T5 is connected to the light-emitting control line EML, the first terminal of the first light-emitting control transistor T5 is connected to the first power supply line PL1, and the second terminal of the first light-emitting control transistor T5 is connected to the first terminal of the driving transistor T3. The gate of the second light-emitting control transistor T6 is connected to the light-emitting control line EML, the first terminal of the second light-emitting control transistor T6 is connected to the second terminal of the driving transistor T3, and the second terminal of the second light-emitting control transistor T6 is connected to the first terminal E1 of the light-emitting element EL. The first reset transistor T1 is connected to the gate of the driving transistor T3 and configured to reset the gate of the driving transistor T3. The second reset transistor T7 is connected to the first electrode E1 of the light-emitting element EL and configured to reset the first electrode E1 of the light-emitting element EL. The gate of the first reset transistor T1 is connected to the first reset control line RST1, the first electrode of the first reset transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first reset transistor T1 is connected to the gate of the driving transistor T3. The gate of the second reset transistor T7 is connected to the second reset control line RST2, the first electrode of the second reset transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the second reset transistor T7 is connected to the first electrode E1 of the light-emitting element EL. The first electrode of the storage capacitor Cst is connected to the gate of the driving transistor T3, and the second electrode of the storage capacitor Cst is connected to the first power supply line PL1. In this example, the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the driving transistor T3 and the threshold compensation transistor T2; the second node N2 is the connection point of the first light-emitting control transistor T5, the data writing transistor T4 and the driving transistor T3; the third node N3 is the connection point of the driving transistor T3, the threshold compensation transistor T2 and the second light-emitting control transistor T6; and the fourth node N4 is the connection point of the second light-emitting control transistor T6, the second reset transistor T7 and the light-emitting element EL.

[0110] The following reference Figure 6B right Figure 6A The working process of a pixel circuit will be explained using an example where all the transistors in the pixel circuit are P-type transistors.

[0111] In some exemplary implementations, such as Figure 6B As shown, during a single frame display period, the operation of the pixel circuit of the first structure includes: a first stage A1, a second stage A2, and a third stage A3.

[0112] The first stage, A1, is called the reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first reset transistor T1. The initial signal Vinit provided by the first initial signal line INIT1 is provided to the first node N1 to initialize N1 and clear the original data voltage in the storage capacitor Cst. The scan signal SCAN provided by the scan line GL is a high-level signal, and the light emission control signal EM provided by the light emission control line EML is a high-level signal, turning off the data writing transistor T4, the threshold compensation transistor T2, the first light emission control transistor T5, the second light emission control transistor T6, and the second reset transistor T7. During this stage, the light-emitting element EL does not emit light.

[0113] The second stage, A2, is called the data writing stage or threshold compensation stage. The scan signal SCAN provided by the scan line GL is low, while the first reset control signal RESET1 provided by the first reset control line RST1 and the light emission control signal EM provided by the light emission control line EML are both high. The data line DL outputs the data signal DATA. During this stage, because the second electrode of the storage capacitor Cst is low, the driving transistor T3 is turned on. The low scan signal SCAN turns on the threshold compensation transistor T2, the data writing transistor T4, and the second reset transistor T7. Threshold compensation transistor T2 and data write transistor T4 are turned on, allowing the data voltage Vdata output from data line DT to be supplied to first node N1 via second node N2, the turned-on drive transistor T3, third node N3, and the turned-on threshold compensation transistor T2. The difference between the data voltage Vdata output from data line DT and the threshold voltage of drive transistor T3 is charged into storage capacitor Cst. The voltage at the second electrode of storage capacitor Cst (i.e., first node N1) is Vdata - |Vth|, where Vdata is the data voltage output from data line DT and Vth is the threshold voltage of drive transistor T3. Second reset transistor T7 is turned on, allowing the initial signal Vinit provided by the second initial signal line INIT2 to be supplied to the first terminal E1 of light-emitting element EL, initializing (resetting) the first terminal E1 of light-emitting element EL, clearing its internal pre-stored voltage, completing the initialization, and ensuring that light-emitting element EL does not emit light. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, causing the first reset transistor T1 to turn off. The light emission control signal EM provided by the light emission control signal line EML is a high-level signal, which disconnects the first light emission control transistor T5 and the second light emission control transistor T6.

[0114] The third stage, A3, is called the light-emitting stage. The light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, while the scan signal SCAN provided by the scan line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals. The low-level light-emitting control signal EM provided by the light-emitting control signal line EML turns on the first light-emitting control transistor T5 and the second light-emitting control transistor T6. The first voltage signal VDD output from the first power supply line PL1 provides a driving voltage to the first terminal E1 of the light-emitting element EL through the turned-on first light-emitting control transistor T5, driving transistor T3, and second light-emitting control transistor T6, driving the light-emitting element EL to emit light.

[0115] During the pixel circuit driving process, the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate and its first terminal. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the driving transistor T3 is:

[0116] I = K * (Vgs - Vth) 2 =K*[(VDD-Vdata+|Vth|)-Vth] 2 =K*[(VDD-Vdata)] 2 .

[0117] Where I is the driving current flowing through the driving transistor T3, which is also the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the driving transistor T3, Vth is the threshold voltage of the driving transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0118] As can be seen from the above formula, the current flowing through the light-emitting element EL is independent of the threshold voltage of the driving transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the driving transistor T3.

[0119] Figure 7A This is a planar schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. Figure 7B for Figure 7A A partial cross-sectional view along the P-P' direction. The first direction D1 can be the direction of a sub-pixel column (vertical direction), and the second direction D2 can be the direction of a sub-pixel row (horizontal direction).

[0120] In some exemplary embodiments, the display substrate is provided with a scan line GL, a light emission control line EML, a first reset control line RST1, a first initial signal line INIT1, a second initial signal line INIT2, a first power supply line PL1, a data line DL, and a pixel circuit in a plane parallel to the display substrate. The pixel circuit may include multiple transistors and a storage capacitor Cst. The multiple transistors may include a driving transistor T3, a data writing transistor T4, a threshold compensation transistor T2, a first reset transistor T1, a second reset transistor T7, a first light emission control transistor T5, and a second light emission control transistor T6.

[0121] In some exemplary embodiments, in a plane perpendicular to the display substrate, the display substrate may include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate 50. In some examples, the semiconductor layer may include an active layer of multiple transistors. The first conductive layer may include a scan line GL, a first reset control line RST1, a second reset control line RST2, a light emission control line EML, a first electrode of a storage capacitor Cst, and the gates of multiple transistors. The second conductive layer may include a first initial signal line INIT1, a second initial signal line INIT2, a second electrode of the storage capacitor Cst, and a first shielding electrode SE1. The third conductive layer may include a first power line PL1, a data line DL, and the first and second electrodes of multiple transistors. The fourth conductive layer may include a second shielding electrode SE2 and a first connection electrode CE1.

[0122] In some exemplary implementations, such as Figure 7B As shown, the display substrate may include a first insulating layer 51, a second insulating layer 52, a third insulating layer 53, a fourth insulating layer 54, and a fifth insulating layer 55. The first insulating layer 51 is disposed between the substrate 50 and the semiconductor layer; the second insulating layer 52 is disposed between the semiconductor layer and the first conductive layer; the third insulating layer 53 is disposed between the first conductive layer and the second conductive layer; the fourth insulating layer 54 is disposed between the second conductive layer and the third conductive layer; and the fifth insulating layer 55 is disposed between the third conductive layer and the fourth conductive layer. In some examples, the first insulating layer 51, the second insulating layer 52, the third insulating layer 53, and the fourth insulating layer 54 may be inorganic insulating layers, and the fifth insulating layer 55 may be an organic insulating layer. However, this embodiment is not limited to this.

[0123] Figure 7C This is a schematic diagram of a pixel circuit after the formation of a semiconductor layer, according to at least one embodiment of this disclosure. In some exemplary embodiments, such as... Figure 7C As shown, the semiconductor layer of at least one sub-pixel may include: a first active layer T10 of a first reset transistor T1, a second active layer T20 of a threshold compensation transistor T2, a third active layer T30 of a driving transistor T3, a fourth active layer T40 of a data writing transistor T4, a fifth active layer T50 of a first light-emitting control transistor T5, a sixth active layer T60 of a second light-emitting control transistor T6, and a seventh active layer T70 of a second reset transistor T7. The first active layer T10 to the seventh active layer T70 are interconnected as a single, integral structure.

[0124] In some exemplary implementations, such as Figure 7CAs shown, the shape of the first active layer T10 can be in an "n" shape, the shape of the second active layer T20 can be in a "7" shape, the shape of the third active layer T30 can be in a "ji" shape, the shape of the fourth active layer T40 can be in a "1" shape, and the shapes of the fifth active layer T50, the sixth active layer T06, and the seventh active layer T70 can be in an "L" shape.

[0125] In some exemplary embodiments, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In some examples, as Figure 7C shown, the second region T10-2 of the first active layer T10 simultaneously serves as the first region T20-1 of the second active layer T20, the first region T30-1 of the third active layer T30 simultaneously serves as the second region T40-2 of the fourth active layer T40 and the second region T50-2 of the fifth active layer T50, the second region T30-2 of the third active layer T30 simultaneously serves as the second region T20-2 of the second active layer T20 and the first region T60-1 of the sixth active layer T60, and the second region T60-2 of the sixth active layer T60 simultaneously serves as the second region T70-2 of the seventh active layer T70.

[0126] Figure 7D Schematic diagram of the pixel circuit after forming the first conductive layer for at least one embodiment of the present disclosure. In some exemplary embodiments, as Figure 7D shown, the first conductive layer at least includes: the first electrode Cst-1 of the storage capacitor Cst, the scan line GL extending along the second direction D2, the emission control line EML, the first reset control line RST1, and the second reset control line RST2. The first electrode Cst-1 of the storage capacitor Cst can be rectangular, chamfers can be provided at the corners of the rectangular shape, and there is an overlapping area between the orthographic projection of the first electrode Cst-1 on the substrate and the orthographic projection of the third active layer T30 of the driving transistor T3 on the substrate. The first electrode Cst-1 of the storage capacitor Cst simultaneously serves as the gate T33 of the driving transistor T3. The scan line GL, the gate T43 of the data writing transistor T4, and the gate T23 of the threshold compensation transistor T2 can be an integrated structure. The emission control line EML, the gate T53 of the first emission control transistor T5, and the gate T63 of the second emission control transistor T6 can be an integrated structure. The first reset control line RST1 and the gate T13 of the first reset transistor T1 can be an integrated structure. The second reset control line RST12 and the gate T73 of the second reset transistor T7 can be an integrated structure.

[0127] Figure 7E Schematic diagram of the pixel circuit after forming the second conductive layer for at least one embodiment of the present disclosure. In some exemplary embodiments, as Figure 7EAs shown, the second conductive layer includes at least: a first initial signal line INIT1, a second initial signal line INIT2, a second electrode Cst-2 of the storage capacitor Cst, and a first shielding electrode BK. Both the first initial signal line INIT1 and the second initial signal line INIT2 extend along the second direction D2 and are located on opposite sides of the second electrode Cst-2 of the storage capacitor Cst in the first direction D1. The orthographic projection of the second electrode Cst-2 of the storage capacitor Cst on the substrate lies between the orthographic projections of the scan line GL and the light-emitting control line EML on the substrate. The orthographic projection of the second electrode Cst-2 of the storage capacitor Cst on the substrate overlaps with the orthographic projection of the first electrode Cst-1 on the substrate. An opening OP1 is provided on the second electrode Cst-2, exposing a third insulating layer 53 covering the first electrode Cst-1, and the orthographic projection of the first electrode Cst-1 on the substrate includes the orthographic projection of the opening OP1 on the substrate. In some examples, the opening OP1 is configured to accommodate a subsequently formed first via H1, which is located within the opening OP1 and exposes a first electrode Cst-1, so that the second electrode of a subsequently formed first reset transistor T1 is connected to the first electrode Cst-1.

[0128] In some exemplary implementations, such as Figure 7E As shown, the first shielding electrode SE1 is located on the side of the scan line GL furthest from the storage capacitor Cst. The first shielding electrode SE1 is configured to shield the impact of data voltage jumps on critical nodes, preventing data voltage jumps from affecting the potential of critical nodes in the pixel circuit and improving the display effect.

[0129] Figure 7F This is a schematic diagram of a pixel circuit after the formation of the third conductive layer, according to at least one embodiment of this disclosure. In some exemplary embodiments, such as... Figure 7F As shown, a first via H1, a plurality of second vias V1 to V4, and a plurality of third vias K1 to K6 are formed on the fourth insulating layer. The fourth insulating layer 54 and the third insulating layer 53 within the first via H1 are etched away, exposing the surface of the first conductive layer. The fourth insulating layer 54 within the plurality of second vias V1 to V4 is etched away, exposing the surface of the second conductive layer. The fourth insulating layer 54, the third insulating layer 53, and the second insulating layer 52 within the plurality of third vias K1 to K8 are etched away, exposing the surface of the semiconductor layer.

[0130] In some exemplary implementations, such as Figure 7FAs shown, the third conductive layer may include: a data line DL, a first power line PL1, a first terminal T11 of a first reset transistor T1, a first terminal T71 of a second reset transistor T7, a first terminal T21 of a threshold compensation transistor T2, and a second terminal T62 of a second light-emitting control transistor T6. The data line DL and the first power line PL1 extend along a first direction D1.

[0131] In some exemplary implementations, such as Figure 7F As shown, the data line DL is connected to the first region T40-1 of the fourth active layer T40 of the data writing transistor T4 through the third via K2. The first power line PL1 is connected to the second electrode Cst-2 of the storage capacitor Cst through the second via V1, to the first shielding electrode SE1 through the second via V2, and to the first region T50-1 of the fifth active layer T50 of the first light-emitting control transistor T5 through the third via K4. The first electrode T21 of the threshold compensation transistor T2 is connected to the first electrode Cst-1 of the storage capacitor Cst through the first via H1, and to the first region T20-1 of the second active layer T20 of the threshold compensation transistor T2 through the third via K1. The second electrode T62 of the second light-emitting control transistor T6 is connected to the second region T60-2 of the sixth active layer T60 of the second light-emitting control transistor T6 through the third via K5. The first terminal T11 of the first reset transistor T1 is connected to the first initial signal line INIT1 through the second via V3, and to the first region T10-1 of the first active layer T10 of the first reset transistor T1 through the third via K3. The first terminal T71 of the second reset transistor T7 is connected to the first region T70-1 of the seventh active layer T70 of the second reset transistor T7 through the third via K6, and the first terminal T71 of the second reset transistor T7 is also connected to the second initial signal line INIT2 through the second via V4.

[0132] Figure 7G This is a schematic diagram of a pixel circuit after the formation of the fourth conductive layer according to at least one embodiment of the present disclosure. In some exemplary embodiments, a plurality of fourth vias F1 to F2 are formed on the fifth insulating layer 55. The fifth insulating layer 55 within the plurality of fourth vias F1 to F2 is removed, exposing the surface of the third conductive layer.

[0133] In some exemplary embodiments, the fourth conductive layer includes at least a second shielding electrode SE2 and a first transition electrode CE1. The first transition electrode CE1 is connected to the second electrode T62 of the second light-emitting control transistor T6 through a fourth via F1. The first transition electrode CE1 can be directly connected to the first region light-emitting element, or connected to the second transition electrode of the first region light-emitting element, or connected to the second transition electrode of the second region light-emitting element through a conductive line. The second shielding electrode SE2 is connected to the first power line PL1 through a fourth via F2. The orthographic projection of the second shielding electrode SE2 on the substrate overlaps with the orthographic projection of the driving transistor T3 on the substrate. The second shielding electrode SE2 is configured to shield the influence of the conductive line on the driving transistor T3, thereby improving the display effect.

[0134] Figure 8A This is a schematic diagram showing the connection position of the first segment of the first sub-data line and the third sub-data line in at least one embodiment of the present disclosure. Figure 8B This is a schematic diagram showing the connection position of the first and second segments of the third sub-data line according to at least one embodiment of the present disclosure.

[0135] In some exemplary implementations, such as Figure 8A As shown, within the first sub-display area R11, the first sub-data line 61 is the data line DL connecting a column of pixel circuits (e.g., the first pixel circuit). A fourth via F3 is formed in the fifth insulating layer 55. The first segment 631 of the third sub-data line 63 is located in the fourth conductive layer. The first segment 631 of the third sub-data line 63 is connected to the first sub-data line 61 through the fourth via F3 formed in the fifth insulating layer 55.

[0136] In some exemplary implementations, such as Figure 8B As shown, within the third sub-display area (e.g., the first sub-display area R13a), the second segment 632 of the third sub-data line 63 is the data line DL connecting multiple second pixel circuits arranged along the first direction D1, and the second data line 71 is the data line DL connecting a column of first pixel circuits. The second segment 632 of the third sub-data line 63 is located in the third conductive layer, and the first segment 631 is located in the fourth conductive layer. The first segment 631 is connected to the second segment 632 through a fourth via F4 formed on the fifth insulating layer 55. The length of the first segment 631 along the second direction D2 is greater than the distance between the fourth vias F3 and F4 to ensure an effective connection between the first segment 631, the second segment 632, and the first sub-data line 61.

[0137] In some exemplary implementations, such as Figure 8A and Figure 8BAs shown, the orthographic projection of the first line segment 631 on the substrate 50 may overlap with the orthographic projections of the first initial signal line INIT1 and the second reset control line RST2 on the substrate 50, and the orthographic projection of the first line segment 631 on the substrate 50 may be located between the orthographic projections of the first initial signal line INIT1 and the second reset control line RST2 on the substrate 50. However, this embodiment is not limited in this respect.

[0138] Figure 8C This is a schematic diagram showing the termination position of the second segment of the third sub-data line according to at least one embodiment of this disclosure. In some exemplary embodiments, such as... Figure 8C As shown, after the second segment 632 of the third sub-data line 63 is connected to the second segment 632 through the fourth via F4, it can extend along the first direction D1 until it terminates at a certain position. The remaining second pixel circuits located in the same column as the second pixel circuit connected to the second segment 632 can be connected to a second data line 71, and the second segment 632 and the second data line 71 are disconnected. However, this embodiment is not limited in this respect.

[0139] Figure 8D This is a schematic diagram showing the connection between the third sub-data line and the data connection line in at least one embodiment of this disclosure. Figure 8E This is a schematic diagram showing the connection between the second sub-data line and the data connection line according to at least one embodiment of the present disclosure.

[0140] In some exemplary implementations, such as Figure 8D and Figure 8E As shown, one end of the second segment 632 of the third sub-data line 63 extends along the first direction D1 to the border area adjacent to the third sub-display area (e.g., the first sub-display area R13a). The first sub-data connection line 641 and the third sub-data connection line 643 may be located in the fourth conductive layer, and the second sub-data connection line 642 may be located in the third conductive layer. The second segment 632 of the third sub-data line 63 can be connected to one end of the first sub-data connection line 641 through a fourth via F5 formed on the fifth insulating layer 55. The other end of the first sub-data connection line 641 can be connected to one end of the second sub-data connection line 642 through a fourth via F6 formed on the fifth insulating layer 55. The other end of the second sub-data connection line 642 can be connected to one end of the third sub-data connection line 643 through a fourth via F7 formed on the fifth insulating layer 55. The other end of the third sub-data connection line 643 can be connected to one end of the second sub-data line 62 extending to the border area through a fourth via F8 formed on the fifth insulating layer 55.

[0141] In some exemplary implementations, such as Figure 8D and Figure 8EAs shown, multiple second sub-data connection lines 642 extend along the second direction D2 and are arranged sequentially along the first direction D1. The lengths of the multiple second sub-data connection lines 642 along the second direction D2 can be the same. Multiple first sub-data connection lines 641 and multiple third sub-data connection lines 643 extend along the first direction D1. The multiple first sub-data connection lines 641 are arranged sequentially along the second direction D2, and the multiple third sub-data connection lines 643 are arranged sequentially along the second direction D2. The lengths of the multiple first sub-data connection lines 641 and the multiple third sub-data connection lines 643 along the first direction D1 can be approximately the same. However, this embodiment is not limited to this.

[0142] In some exemplary implementations, such as Figure 8E As shown, a plurality of first pixel circuits 10 and a plurality of second pixel circuits 20 are provided in the second sub-display area (e.g., the second sub-display first sub-display area R12a). Figure 8E The second pixel circuit 20 shown serves as a virtual pixel circuit and is not connected to the second light-emitting element of the second display area R2, thus requiring no data signal. In this example, within the second sub-display area, the second sub-data connection line 62, which is connected to the first pixel circuit 10, is connected to the second sub-data connection line 642 via a third sub-data connection line 643 to receive data signals. However, this embodiment is not limited to this. In some examples, when Figure 8E When the second pixel circuit 20 shown is connected to the second light-emitting element of the second display area R2, the data line connected to the second pixel circuit 20 can also be connected to the second sub-data connection line 642 through the third sub-data connection line 643 to receive data signals.

[0143] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0144] The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. "The orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0145] In some exemplary embodiments, the fabrication process of the display substrate may include the following operations.

[0146] (1) Forming a semiconductor layer pattern.

[0147] In some exemplary embodiments, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate 50, patterning the semiconductor film using a patterning process to form a first insulating layer 51 covering the substrate 50, and a semiconductor layer disposed on the first insulating layer 51, such as... Figure 7C As shown.

[0148] After this process, the display substrate includes a first insulating layer 51 disposed on the substrate 50 and a semiconductor layer disposed on the first insulating layer 51. The semiconductor layer may include the active layer of a plurality of transistors of the pixel circuit. In this exemplary embodiment, the active layer of the second reset transistor of the pixel circuit and the active layer of the first reset transistor of the adjacent pixel circuit may be an integral structure.

[0149] (2) Forming the first conductive layer pattern.

[0150] In some exemplary embodiments, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first metal film on a substrate 50 on which the aforementioned pattern is formed, patterning the first metal film using a patterning process to form a second insulating layer 52 covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer 52. Figure 7D As shown, the first conductive layer pattern may include: gates of multiple transistors in the pixel circuit, a first reset control line RST1, a scan line GL, a light emission control line EML, a first electrode Cst-1 of the storage capacitor Cst, and a second reset control line RST2. The first reset control line RST1, the second reset control line RST2, the scan line GL, and the light emission control line EML extend along a second direction D2, and the first electrode Cst-1 of the storage capacitor Cst is located between the scan line GT and the light emission control line EML. In some examples, the first conductive layer may be referred to as a first gate metal (GATE 1) layer.

[0151] In some exemplary embodiments, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the region shielded by the first conductive layer forms the channel region of multiple transistors, and the semiconductor layer in the region not shielded by the first conductive layer is conducted, that is, the first region and the second region of the first active layer T10 to the seventh active layer T70 are both conducted.

[0152] (3) Forming the pattern of the second conductive layer.

[0153] In some exemplary embodiments, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second metal film on the base 50 on which the aforementioned pattern is formed, patterning the second metal film using a patterning process to form a third insulating layer 53 covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer 53. Figure 7E As shown, the second conductive layer pattern may include: a first initial signal line INIT1, a second initial signal line INIT2, a second electrode Cst-2 of the storage capacitor Cst, and a first shielding electrode SE1. In some examples, the second conductive layer may be referred to as a second gate metal (GATE 2) layer.

[0154] (4) Form the fourth insulating layer pattern.

[0155] In some exemplary embodiments, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate 50 on which the aforementioned pattern is formed, and patterning the fourth insulating film using a patterning process to form a fourth insulating layer 54 covering the second conductive layer. For example... Figure 7F As shown, a plurality of first vias H1, a plurality of second vias V1 to V3, and a plurality of third vias K1 to K6 are disposed on the fourth insulating layer. The fourth insulating layer 54 and the third insulating layer 53 in the plurality of first vias are etched away to expose the surface of the first conductive layer; the fourth insulating layer 54 in the plurality of second vias is etched away to expose the surface of the second conductive layer; and the fourth insulating layer 54, the third insulating layer 53, and the second insulating layer 52 in the plurality of third vias are etched away to expose the surface of the semiconductor layer.

[0156] (5) Forming the pattern of the third conductive layer.

[0157] In some exemplary embodiments, forming the third conductive layer may include: depositing a third metal thin film on the substrate 50 on which the aforementioned pattern is formed, and patterning the third metal thin film using a patterning process to form a third conductive layer disposed on the fourth insulating layer 54. For example... Figure 7F , Figure 8D and 8EAs shown, the third conductive layer may include: a second data line 71, a second sub-data line 61, a second sub-data line 62, a third sub-data line 63, a first power line PL1, the first and second terminals of a plurality of transistors in the pixel circuit, and a second sub-data connection line 642 located in the border area R3. In some examples, the third conductive layer may be referred to as the first source-drain metal (SD1) layer.

[0158] (6) Form the fifth insulating layer pattern.

[0159] In some exemplary embodiments, forming the fifth insulating layer pattern may include: coating a planar thin film on the substrate 50 where the aforementioned pattern is formed, and patterning the planar thin film using a patterning process to form a fifth insulating layer 55 covering the third conductive layer, such as... Figure 7G As shown, a plurality of fourth vias F1 to F8 are formed on the fifth insulating layer 55. The fifth insulating layer 55 within the plurality of fourth vias is removed, exposing the surface of the third conductive layer. In some examples, the fifth insulating layer 55 may be referred to as a planarization layer.

[0160] (7) Form the fourth conductive layer pattern.

[0161] In some exemplary embodiments, forming the fourth conductive layer pattern may include: depositing a fourth metal thin film on the substrate 50 on which the aforementioned pattern is formed, and patterning the fourth metal thin film using a patterning process to form a fourth conductive layer disposed on the fifth insulating layer 55.

[0162] like Figure 7G As shown, the fourth conductive layer pattern may include: a first connection electrode CE1, a second shielding electrode SE, and a first segment 631 of a third sub-data line 63 located in the first display area R1; and a first sub-data connection line 641 and a third sub-data connection line 643 located in the border area R3. The second shielding electrode SE is connected to the first power line PL1 through a fourth via F2, and the first connection electrode CE1 is connected to the second electrode T62 of the second light-emitting control transistor T6 through a fourth via F1. The first segment 631 of the third sub-data line 63 is connected to the first sub-data line 61 through a fourth via F3, and to the second segment 632 of the third sub-data line 63 through a fourth via F4. The first sub-data connection line 641 is connected to the second segment 632 through a fourth via F5, and to the second sub-data connection line 642 through a fourth via F6. The third sub-data connection line 643 is connected to the second sub-data connection line 642 through a fourth via F7, and to the second sub-data line 62 through a fourth via F8. In some examples, the fourth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0163] In some exemplary embodiments, subsequent fabrication processes may include forming a conductive line layer. In some examples, the multiple conductive lines connecting the second pixel circuit of the first display area and the second light-emitting element of the second display area may be of the same layer structure. Forming the conductive line layer may include: coating a planar thin film on a substrate forming a fourth conductive layer, patterning the planar thin film using a patterning process to form a sixth insulating layer covering the fourth conductive layer; then, depositing a transparent conductive thin film, patterning the transparent conductive thin film using a patterning process to form a conductive line layer disposed on the sixth insulating layer. The first connection electrode CE1 of the second pixel circuit of the first display area R1 is connected to the conductive line, and the conductive line can extend from the first display area R1 to the second display area R2 to connect with the second light-emitting element of the second display area R2. However, this embodiment is not limited to this. In some examples, the multiple conductive lines connecting the second pixel circuit of the first display area R1 and the second light-emitting element of the second display area R2 may be of different layers structure. Alternatively, at least one conductive line may be formed by connecting multiple conductive line segments located in different conductive line layers.

[0164] In some exemplary embodiments, the fabrication process after forming the conductive line layer may include: forming a planarization layer covering the conductive line layer; depositing a transparent conductive film, patterning the transparent conductive film using a patterning process to form an anode disposed on the planarization layer; coating a pixel definition film, patterning the pixel definition film using a patterning process to form a pixel definition layer, wherein each sub-pixel's pixel definition layer has a pixel opening that exposes the anode. An organic light-emitting layer is formed using a vapor deposition or inkjet printing process, and a cathode is formed on the organic light-emitting layer. An encapsulation layer is formed, which may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to prevent external moisture from entering the light-emitting element.

[0165] In some exemplary embodiments, the substrate 50 may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, while the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some examples, the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0166] In some exemplary embodiments, the first, second, third, and fourth conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first insulating layer 51, second insulating layer 52, third insulating layer 53, and fourth insulating layer 54 can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers. The first insulating layer 51 is called a buffer layer, used to improve the substrate's resistance to water and oxygen. The second and third insulating layers 52 are called gate insulating (GI) layers, and the fourth insulating layer 54 is called an interlayer insulating (ILD) layer. The planarization layer can be made of organic materials. The transparent conductive film can be made of indium tin oxide (ITO) or indium zinc oxide (IZO). The active layer can be made of polycrystalline silicon (p-Si), meaning this embodiment is applicable to LTPS thin-film transistors. However, this embodiment is not limited to this. For example, the transistors in the pixel circuit can all be made of oxide thin-film transistors.

[0167] The structure and fabrication process of the display substrate in this embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure and patterning processes can be modified and increased or decreased according to actual needs. For example, the second reset transistor in the pixel circuit can be connected to the second initial signal line. For example, the pixel circuit may include other numbers of transistors and storage capacitors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, or the number of transistors may be less than 7. For example, the second segment of the first sub-data line, the second sub-data line, the second data line, the second segment of the third sub-data line, and the second sub-data connection line may be located in the fourth conductive layer, and the first segment of the third sub-data line, the first sub-data connection line, and the third sub-data connection line may be located in the third conductive layer. However, this embodiment is not limited in this respect.

[0168] The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0169] Figure 9 This is another schematic diagram of the data lines of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 9 As shown, the first and second segments of the third sub-data line 63 are an integral structure. The first, second, and third sub-data line of the data connection line 64 can also be an integral structure. The data connection line 64 is connected between the third sub-data line 63 and the second sub-data line 62, and the third sub-data line 63 is connected to the first sub-data line 61. In some examples, the first sub-data line 61 and the data connection line 64 can be located in the third conductive layer, and the third sub-data line 63 and the second data line 62 can be located in the fourth conductive layer. However, this embodiment is not limited to this.

[0170] The remaining structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here. The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0171] Figure 10 This is a schematic diagram illustrating another arrangement of data lines on a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 10As shown, the third sub-data line 63 includes a first segment 631, a second segment 632, and a third segment 633. The second segment 632 is connected to a plurality of second pixel circuits disposed along the first direction D1 in the third sub-display area. The second segment 632 is connected to both the first segment 631 and the third segment 633. The first segment 631 and the third segment 633 extend along the second direction D2, and the second segment 632 extends along the first direction D1. The first segment 631 extends to the first sub-display area R11 and connects to the first sub-data line 61 of the first sub-display area R11. The third segment 632 extends to the second sub-display area R12a and connects to the second sub-data line 62 of the second sub-display area R12a. In some examples, the first sub-data line 61, the second sub-data line 62, and the second segment 632 may be located in the third conductive layer, and the first segment 631 and the third segment 633 may be located in the fourth conductive layer. However, this embodiment is not limited to this.

[0172] The remaining structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here. The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0173] Figure 11 This is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 11 As shown, the second display area R2 is located in the left half of the display substrate. The first display area R1 includes a first sub-display area R11, a second sub-display area R12, and a third sub-display area R13. The first sub-display area R11 and the second sub-display area R12 are located on opposite sides of the second display area R2 along the first direction D1. The first sub-display area R11 and the second sub-display area R12 are separated by the second display area R2 in the first direction D1. The third sub-display area R13 is located on one side of the second display area R2, for example, on the right side of the second display area R2. The first sub-data line 61 of the first sub-display area R11 can be connected to the second sub-data line 62 of the second sub-display area R12 through the third sub-data line 63 of the third sub-display area R13 and the data connection line 64 of the border area R3, so as to provide data signals to the pixel circuit (e.g., the first pixel circuit, or the first pixel circuit and the second pixel circuit) of the second sub-display area R12.

[0174] The remaining structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here. The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0175] Figure 12 This is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 12As shown, the second display area R2 can be rectangular and is located in the central region of the display substrate. The first display area R1 includes a first sub-display area R11 and a second sub-display area R12 located on opposite sides of the second display area R2 in the first direction D1, and a third sub-display area located on opposite sides of the second display area R2 in the second direction D2. The third sub-display area includes: a third sub-display first sub-area R13a and a third sub-display second sub-area R13b.

[0176] The remaining structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here. The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0177] This disclosure also provides a method for fabricating a display substrate, comprising: forming a plurality of pixel circuits, a plurality of first light-emitting elements, and at least one first data line in a first display area of ​​a substrate. The first display area at least partially surrounds a second display area. The first display area includes: a first sub-display area and a second sub-display area located on opposite sides of the second display area along a first direction, and a third sub-display area located on at least one side of the second display area along a second direction; the first direction intersects the second direction. The plurality of pixel circuits include: a plurality of first pixel circuits and a plurality of second pixel circuits, the plurality of second pixel circuits being distributed among the plurality of first pixel circuits. At least one of the plurality of first pixel circuits is connected to at least one light-emitting element among the plurality of first light-emitting elements. The first data line includes: a first sub-data line, a second sub-data line, and a third sub-data line; the third sub-data line is connected to the first sub-data line and the second sub-data line. The first sub-data line is located in the first sub-display area and connected to the pixel circuits of the first sub-display area, the second sub-data line is located in the second sub-display area and connected to the pixel circuits of the second sub-display area, and the third sub-data line is located in the third sub-display area and connected to at least one second pixel circuit of the third sub-display area.

[0178] The method for preparing the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0179] Figure 13 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 13 As shown, this embodiment provides a display device 91, including the display substrate 910 of the aforementioned embodiment. In some examples, the display substrate 910 can be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device 91 can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited to this.

[0180] The accompanying drawings in this disclosure only illustrate the structures relevant to this disclosure; other structures can be referenced to common designs. Unless otherwise specified, embodiments of this disclosure, i.e., features within the embodiments, can be combined with each other to obtain new embodiments.

[0181] Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions disclosed herein without departing from the spirit and scope of the technical solutions disclosed herein, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A display substrate, comprising: A substrate includes a first display area and a second display area, wherein the first display area at least partially surrounds the second display area, and the first display area includes: a first sub-display area and a second sub-display area located on opposite sides of the second display area along a first direction, and a third sub-display area located on at least one side of the second display area along a second direction, wherein the first direction intersects the second direction; A plurality of pixel circuits and a plurality of first light-emitting elements are located in the first display area; the plurality of pixel circuits include: a plurality of first pixel circuits and a plurality of second pixel circuits, the plurality of second pixel circuits being distributed among the plurality of first pixel circuits; at least one pixel circuit of the plurality of first pixel circuits is connected to at least one light-emitting element of the plurality of first light-emitting elements. At least one first data line is located in the first display area; the first data line includes: a first sub-data line, a second sub-data line, and a third sub-data line; the third sub-data line is connected to the first sub-data line and the second sub-data line; The first sub-data line is located in the first sub-display area and is connected to the pixel circuit of the first sub-display area; the second sub-data line is located in the second sub-display area and is connected to the pixel circuit of the second sub-display area; and the third sub-data line is located in the third sub-display area and is connected to at least one second pixel circuit of the third sub-display area. The substrate further includes: a border region located around the first display area and the second display area; the border region is provided with at least one data connection line, which is connected between the third sub-data line and the second sub-data line.

2. The display substrate according to claim 1, wherein, Both the first sub-data line and the second sub-data line extend along the first direction.

3. The display substrate according to claim 1, wherein, The third sub-data line includes at least: a first segment and a second segment, wherein the first segment extends along the second direction and the second segment extends along the first direction; One end of the first line segment extends to the first sub-display area and connects to the first sub-data line, and the other end of the first line segment connects to the second line segment; The second line segment is connected to at least one second pixel circuit of the third sub-display area.

4. The display substrate according to claim 3, wherein, The first sub-data line, the second sub-data line, and the second segment of the third sub-data line are in the same layer, while the first segment and the second segment of the third sub-data line are in different layers.

5. The display substrate according to claim 1, wherein, The first sub-data line and the second sub-data line are in the same layer, while the third sub-data line and the first sub-data line are in different layers.

6. The display substrate according to claim 1, wherein, The data connection line includes at least: a first sub-data connection line, a second sub-data connection line, and a third sub-data connection line; The second sub-data connection line is connected between the first sub-data connection line and the third sub-data connection line. The first sub-data connection line is connected to the third sub-data line, and the third sub-data connection line is connected to the second sub-data line.

7. The display substrate according to claim 6, wherein, The first sub-data connection line and the third sub-data connection line extend along the first direction, and the second sub-data connection line extends along the second direction.

8. The display substrate according to claim 6, wherein, The first sub-data connection line and the third sub-data connection line are in the same layer, while the first sub-data connection line and the second sub-data connection line are in different layers.

9. The display substrate according to claim 8, wherein, The second sub-data connection line is in the same layer as the first sub-data line and the second sub-data line.

10. The display substrate according to any one of claims 1 to 9, further comprising: Multiple second light-emitting elements are located in the second display area; At least one pixel circuit of the plurality of second pixel circuits is connected to at least one light-emitting element of the plurality of second light-emitting elements via a conductive line.

11. The display substrate according to any one of claims 1 to 9, wherein, In a plane perpendicular to the display substrate, the display substrate includes at least: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on the substrate. The semiconductor layer includes at least: an active layer of a plurality of transistors in the pixel circuit; The first conductive layer includes at least: the gates of a plurality of transistors in the pixel circuit and the first electrode of the storage capacitor; The second conductive layer includes at least: the second electrode of the storage capacitor of the pixel circuit; The third conductive layer includes at least: a first power line; The fourth conductive layer includes at least a first connection electrode that connects the pixel circuit to the light-emitting element.

12. The display substrate according to claim 11, wherein, The first sub-data line, the second sub-data line, and the second segment of the third sub-data line are located in the third conductive layer, and the first segment of the third sub-data line is located in the fourth conductive layer; or, the first sub-data line and the second sub-data line are located in the third conductive layer, and the third sub-data line is located in the fourth conductive layer.

13. A display device, comprising: The display substrate as described in any one of claims 1 to 12.

14. A method for preparing a display substrate, comprising: Multiple pixel circuits, multiple first light-emitting elements, and at least one first data line are formed in the first display area of ​​the substrate, and at least one data connection line is formed in the border area of ​​the substrate. The first display area at least partially surrounds the second display area; the first display area includes: a first sub-display area and a second sub-display area located on opposite sides of the second display area along a first direction, and a third sub-display area located on at least one side of the second display area along a second direction; the first direction intersects the second direction; the border area is located outside the first display area and the second display area; The plurality of pixel circuits includes: a plurality of first pixel circuits and a plurality of second pixel circuits, wherein the plurality of second pixel circuits are distributed among the plurality of first pixel circuits; at least one of the plurality of first pixel circuits is connected to at least one of the plurality of first light-emitting elements; the first data line includes: a first sub-data line, a second sub-data line, and a third sub-data line; the third sub-data line is connected to the first sub-data line and the second sub-data line; the first sub-data line is located in the first sub-display area and is connected to the pixel circuit of the first sub-display area, the second sub-data line is located in the second sub-display area and is connected to the pixel circuit of the second sub-display area, and the third sub-data line is located in the third sub-display area and is connected to at least one second pixel circuit of the third sub-display area; the data connection line is connected between the third sub-data line and the second sub-data line.

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