Method and system for terminating standby operation of a power management system

Abstract

The present invention discloses a method and system for terminating the standby operation of a power management system. The method comprises: after a power management controller (PMC) receives a deep sleep instruction, generating a holdsleepn signal to prevent the CPU from executing the instruction; controlling the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a low-active state; if the PMC does not receive a response message fed back by the CPU based on the holdsleepn signal and recognizes the presence of a wakeup signal, controlling the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a high-inactive state; and completing information synchronization between the power management controller and the CPU based on the holdsleepn signal being in a high-inactive state. The present invention enables the CPU and the power management controller to operate using the same mechanism, thereby achieving information synchronization under normal operation mode.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply, and in particular to a method and system for suspending standby operation of a power management system. Background Art

[0002] The System on Chip (SOC) supports normal operating modes (RUN), standby mode (STANDBY), and stop mode (STOP). RUN mode is entered after a power-on reset (POR) on the chip. In RUN mode, all chip power supplies, clocks, and functional modules are in normal working order. In STOP mode, the power module maintains power and shuts down the core clock. The CPU in the SoC, or power management system, stops reading and writing flash memory and static memory (SRAM). Other clock sources can be shut down or disabled by the system software. STANDBY mode minimizes the power consumption of the SoC. In STANDBY mode, the SoC shuts down power to most digital circuits, retaining only external wakeup sources. The clock module maintains a low-speed 128KHz clock, the flash enters deep power down or power off, and the SRAM enters memory retention.

[0003] The on-chip system includes: CPU and power management controller (PMC), etc. After receiving the deep sleep operation sent by the CPU, the PMC will control the entire system to prepare to enter the standby mode. It needs to put the CPU, flash memory unit flash, static memory SRAM, etc. into the power-down preparation state. If there is an external wake-up source in this case, the PMC receives the wake-up source, the PMC is in the normal operation mode, and the CPU is in the power-down preparation stage, making the two states of the CPU and the power management controller out of sync. The CPU can continue to execute the set operation behavior, which will cause the CPU operation to hang or run away, and cannot be synchronized with the state of the PMC, and then cause the entire system to pause and unable to enter the RUN mode. Summary of the Invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art. The present invention provides a method and system for terminating the standby operation of a power management system. When the power management system is preparing to enter the standby process, the operating status of each unit in the power management system is synchronized through the internal low-speed SIRC clock timing, and the normal operating mode is entered synchronously to prevent the CPU of each functional unit from running away or hanging during the power-off process.

[0005] In order to solve the above problem, the present invention proposes a method for suspending the standby operation of a power management system, the method comprising the following steps:

[0006] After receiving the deep sleep instruction, the PMC generates a holdsleepn signal indicating that the CPU holds the instruction and sends the holdsleepn signal to the CPU.

[0007] Control the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a low-active state, so that the power management system is ready to enter the standby state;

[0008] In the process of preparing to enter the standby state, if the PMC does not receive the response message fed back by the CPU based on the holdsleepn signal and recognizes that the wakeup source wakeup signal appears, it controls the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a high invalid state;

[0009] Based on the holdsleepn signal being in a high invalid state, information synchronization between the power management controller and the CPU is completed, so that the power management system enters a normal operating mode.

[0010] The step of preparing the power management system to enter the standby state includes:

[0011] Determining whether the power management system supports the CPU memory function;

[0012] If it is determined that the CPU supports the CPU memory function, the PMC sends a CPU memory instruction to the CPU memory control unit;

[0013] If it is determined that the CPU does not support the CPU memory function, the PMC triggers the power management system to enter the isolation enabled state.

[0014] The method further comprises:

[0015] The CPU memory control unit receives the CPU memory instruction and performs a CPU memory information reading operation based on the CPU memory instruction.

[0016] The operation of reading CPU memory information based on the CPU memory instruction includes:

[0017] The CPU memory information is read from the CPU and stored in the CPU memory static storage unit.

[0018] The completing information synchronization between the power management controller and the CPU based on the holdsleepn signal being in a high invalid state includes:

[0019] When the internal low-speed SIRC clock timing is controlled so that the holdsleepn signal acting on the CPU is in a high invalid state, the internal low-speed SIRC clock timing is controlled to jump the PMC back to the normal operating mode.

[0020] The method further comprises:

[0021] The internal low-speed SIRC clock timing is controlled to act on the flash memory unit so that the flash memory unit jumps back to the normal operating mode from the standby state.

[0022] The controlling of the internal low-speed SIRC clock timing to act on the flash memory unit so that the flash memory unit jumps from the standby state to the normal operating mode includes:

[0023] Identify low-power modes of flash memory cells;

[0024] The internal low-speed SIRC clock timing is controlled to act on the control signal timing corresponding to the low power mode, so that the flash memory unit jumps back to the normal operating mode from the standby mode.

[0025] Accordingly, the present invention also proposes a power management system, which includes:

[0026] The PMC is used to generate a holdsleepn signal for the CPU to hold the non-executed instruction after receiving a deep sleep instruction, and send the holdsleepn signal to the CPU; control the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a low-active state, so that the power management system is ready to enter the standby state; in the process of preparing to enter the standby state, if the PMC does not receive a response message fed back by the CPU based on the holdsleepn signal and recognizes that a wakeup source wakeup signal appears, then control the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a high-inactive state; based on the holdsleepn signal being in a high-inactive state, complete the information synchronization between the power management controller and the CPU, so that the power management system enters the normal operating mode;

[0027] The CPU is configured to generate a deep sleep instruction and send the deep sleep instruction to the PMC; and receive a holdsleepn signal.

[0028] The power management system further includes:

[0029] The CPU memory control unit is used to receive the CPU memory instruction sent by the PMC when preparing to enter the standby state, and read the current running instruction from the CPU based on the memory instruction and write the running instruction into the CPU memory static storage unit;

[0030] The CPU memory static storage unit is used to store the current running instructions written by the CPU memory control unit.

[0031] The power management system further includes:

[0032] The flash memory unit is used to jump back to the normal operating mode from the standby state under the control of the internal low-speed SIRC clock timing when preparing to enter the standby state.

[0033] The method and system of the present invention set a holdsleepn signal between the PMC and the CPU, which is associated with the internal low-speed SIRC clock timing, so that the CPU can keep from executing instructions when preparing to enter the standby state. When the wake-up source trigger is received, the holdsleepn signal is in a high invalid state, and the CPU can enter the normal operating mode, so that the CPU and the power management controller are both in normal operating mode, avoiding CPU operation hanging or running away, and making the CPU and the power management controller operate with the same mechanism, and achieving information synchronization under normal mode operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0035] Figure 1 is a schematic structural diagram of a power management system in an embodiment of the present invention;

[0036] Figure 2 is a flow chart of a first method for suspending the standby operation of the power management system in an embodiment of the present invention;

[0037] Figure 3 This is a flow chart of the second method for suspending the standby operation of the power management system in an embodiment of the present invention.

[0038] Figure 4 This is a first schematic diagram of the wake-up control signal timing when the PMC enters the standby mode in an embodiment of the present invention;

[0039] Figure 5 This is a second schematic diagram of the wake-up control signal timing when the PMC enters the standby mode in an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0041] Example 1

[0042] Specifically, Figure 1 The schematic diagram of the power management system structure in an embodiment of the present invention is shown. The power management system can be a SOC or an independent power module. The power management system includes:

[0043] CPU, CPU memory control unit, CPU memory static storage unit, system static storage unit, flash memory unit flash, analog unit, PMC control unit, etc.

[0044] The system supports CPU memory retention control, that is, before entering the standby mode STANDBY, it controls the reading of instructions from the CPU and stores them in SRAM (CPU memory static storage unit). In the standby mode STANDBY, after the system is powered on again, it controls the reloading of instructions from SRAM (CPU memory static storage unit) and writes them into the CPU.

[0045] In normal operating mode (RUN), the power management system's 1.1V supply is provided by linear regulator LDO11_MR. In low-power mode (STANDBY), LDO11_MR is disabled, and LDO11_LR supplies power to the chip. LDO11_LR also provides the 1.1V supply for the CPU memory static storage unit, system static storage unit, and flash.

[0046] In the standby mode, the CPU, CPU memory control unit, and some analog units including the oscillator, phase-locked loop, CMP, ADC, and flash memory unit have no power supply and belong to the shutdown domain (shut). The PMC control unit and some analog unit LDOs are always powered and belong to the always-on domain (alon).

[0047] The flash memory unit is internally provided with a power switch, which can be turned on and off by controlling the supply signal SUPPLYON. When SUPPLYON=0, the 1.1V and 3.3V power supplies of the flash are turned off.

[0048] The system supports PAD keep enable control, and when preparing to enter the standby state, it mainly controls the shutdowndomain related data output and the enable signal to maintain the state before power failure.

[0049] When the system is not powered off, the CPU and PMC can handshake to perform an abort standby operation to prevent the CPU from hanging or running away.

[0050] During the specific implementation process, the PMC here is used to generate a holdsleepn signal for the CPU to hold the non-executed instruction after receiving a deep sleep instruction, and send the holdsleepn signal to the CPU; control the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a low-active state, so that the power management system is ready to enter the standby state; in the process of preparing to enter the standby state, if the PMC does not receive the response message fed back by the CPU based on the holdsleepn signal, and recognizes that the wake-up source wakeup signal appears, then control the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a high-inactive state; based on the holdsleepn signal being in a high-inactive state, complete the information synchronization between the power management controller and the CPU, so that the power management system enters the normal operating mode; the CPU is used to generate a deep sleep instruction, send the deep sleep instruction to the PMC; and receive the holdsleepn signal.

[0051] The CPU memory control unit here is used to receive the CPU memory instructions sent by the PMC when preparing to enter the standby state, and read the current running instructions from the CPU based on the memory instructions and write the running instructions into the CPU memory static storage unit; the CPU memory static storage unit is used to store the current running instructions written by the CPU memory control unit.

[0052] The flash memory unit here is used to jump back to the normal operation mode from the standby state under the control of the internal low-speed SIRC clock timing when preparing to enter the standby state.

[0053] The power management system in the embodiment of the present invention sets a holdsleepn signal between the PMC and the CPU, which is associated with the internal low-speed SIRC clock timing, so that the CPU can keep from executing instructions when preparing to enter the standby state. When the wake-up source is triggered, the holdsleepn signal is in a high invalid state, and the CPU can enter the normal operating mode, so that the CPU and the power management controller are both in normal operating mode, avoiding CPU operation hanging or running away, and making the CPU and the power management controller operate with the same mechanism, and can achieve information synchronization under normal mode operation.

[0054] Specifically, Figure 2 A flow chart of a first method for suspending the standby operation of a power management system according to an embodiment of the present invention is shown, which specifically includes the following steps:

[0055] S201, after receiving the deep sleep instruction, the PMC generates a holdsleepn signal indicating that the CPU holds the instruction and does not execute it, and sends the holdsleepn signal to the CPU;

[0056] S202, controlling the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a low-active state, so that the power management system is ready to enter the standby state;

[0057] S203. During the preparation for entering the standby state, if the PMC does not receive a response message fed back by the CPU based on the holdsleepn signal and recognizes that a wakeup signal from the wakeup source appears, the PMC controls the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a high invalid state;

[0058] S204 : completing information synchronization between the power management controller and the CPU based on the holdsleepn signal being in a high invalid state, so that the power management system enters a normal operating mode.

[0059] based on Figure 1 and Figure 2 In the example shown, a holdsleepn signal is set between the PMC and the CPU, and is associated with the internal low-speed SIRC clock timing, so that the CPU can keep from executing instructions when preparing to enter the standby state. When the wake-up source is triggered, the holdsleepn signal is in a high invalid state, and the CPU can enter the normal operating mode, so that the CPU and the power management controller are both in normal operating mode, avoiding CPU operation hanging or running away, and making the CPU and the power management controller operate with the same mechanism, and can achieve information synchronization under normal mode operation.

[0060] Example 2

[0061] Specifically, Figure 3 FIG. 1 shows a flow chart of a second method for suspending the standby operation of the power management system in an embodiment of the present invention. Figure 3 The method shown is based on Figure 1 The power management system shown in the figure is implemented, and the power management system supports CPU memory retention control. The method includes the following steps:

[0062] S301, the CPU generates a deep sleep instruction and sends the deep sleep instruction to the PMC;

[0063] When the SOC is in normal operation RUN mode and is required to enter the standby mode STANDBY, in order to ensure the state change, it needs to go through the waiting PMC_WAIT_CPU_HOLD, PMC_RDCPU_REQ, PMC_ISO_ON and other states before entering the STANDBY mode, where:

[0064] When the RUN mode in the SOC enters the PMC_WAIT_CPU_HOLD state, the CPU generates a deep sleep instruction, which is sent to the PMC. The PMC generates a holdsleepn signal to hold the CPU from executing the instruction. During this process, the PMC needs to wait for the CPU to be held in sleep (hold sleep) by the PMC, that is, the PMC_WAIT_CPU_HOLD state. In this state, the CPU has power but does not execute instructions.

[0065] When the CPU is preparing to power off, because the system supports CPU memory retention control, it must enter the CPU retention read request phase, transitioning from the PMC_WAIT_CPU_HOLD state to the PMC_RDCPU_REQ state. In the PMC_RDCPU_REQ state, the CPU is powered but not executing instructions. The PMC generates CPU retention instructions and sends them to the CPU's static memory unit. Based on the CPU retention instructions, the CPU's static memory unit reads the current running instructions from the CPU and writes them to the CPU's static memory unit. Once retention control is complete, the PMC enters the isolation-on state, or PMC_ISO_ON. In the PMC_ISO_ON state, the CPU is held in sleep mode by the PMC, while the PMC is operating normally. The system isolation state must be enabled by transitioning the PMC from normal operation to the lowest power mode. After the system isolation state is established, the system-on-chip shuts down the voltage to most digital circuits, retaining only external wakeup sources and entering standby mode.

[0066] The isolation enable state refers to the isolation enable of the shutdown domain output signal. When the isolation enable is valid, the output signal has no effect on the control logic of the always-on domain. When the isolation enable signal is invalid, the output signal is a normal control logic signal.

[0067] S302, after receiving the deep sleep instruction, the PMC generates a holdsleepn signal indicating that the CPU holds the instruction and does not execute it, and sends the holdsleepn signal to the CPU;

[0068] In the process of waiting for PMC_WAIT_CPU_HOLD, PMC_RDCPU_REQ, PMC_ISO_ON and other states to enter the STANDBY mode, the CPU only does not execute instructions but receives power from the power module.

[0069] The deep sleep instruction, holdsleepn signal, and holdsleep_ackn are set between the CPU and PMC to realize the synchronization process between the CPU and PMC.

[0070] The deep sleep command is a deep sleep signal generated by the CPU. After receiving this signal, the PMC starts to control the system to enter the STANDBY mode.

[0071] The holdsleepn signal is a signal that holds the CPU from executing instructions. It is generated by the PMC and sent to the CPU. When the CPU receives this signal, it holds the CPU state. When the holdsleepn signal enters STANDBY mode and a PMC synchronous wakeup source occurs, the holdsleepn signal is deasserted in the second beat.

[0072] holdsleep_ackn is the acknowledgment signal that the CPU is held, which is fed back by the CPU after receiving the holdsleepn signal. It is generated by the CPU and sent to the PMC component. When holdsleepn is invalid, the holdsleep_ackn signal is invalid after the second beat.

[0073] After receiving the deep sleep instruction, the PMC generates a holdsleepn signal for the CPU to hold the non-execution instruction, and sends the holdsleepn signal to the CPU, including: after receiving the deep sleep instruction, the PMC generates the holdsleepn signal based on the internal low-speed SIRC clock (sirc_clk) timing.

[0074] S303, the PMC controls the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a low-active state, so that the power management system is ready to enter the standby state;

[0075] It should be noted that preparing the power management system to enter the standby state includes: determining whether the power management system supports the CPU memory function; if it is determined that the CPU supports the CPU memory function, the PMC sends a CPU memory instruction to the CPU memory control unit; if it is determined that the CPU does not support the CPU memory function, the PMC triggers the power management system to enter the isolation enabled state.

[0076] In this embodiment, since the system supports CPU memory retention control, the CPU memory control unit here receives the CPU memory instruction and performs a CPU memory information reading operation based on the CPU memory instruction.

[0077] Here, the operation of reading the CPU memory information based on the CPU memory instruction includes: reading the CPU memory information from the CPU, and storing the CPU memory information in the CPU memory static storage unit.

[0078] S304: The PMC recognizes that a wakeup signal from a wakeup source appears.

[0079] S305: Determine whether the CPU has fed back a response message. If no response message is received, proceed to S306; if a response message is received, proceed to S306;

[0080] holdsleep_ackn is the acknowledge signal that the CPU is held, which is fed back by the CPU after receiving the holdsleepn signal. It is the response message here. Receipt of this response message indicates that the CPU power-down in the three stages of PMC_WAIT_CPU_HOLD, PMC_RDCPU_REQ, and PMC_ISO_ON has not been completed. It can release the holdsleepn valid state and enter the RUN mode according to the generation of the wake-up source.

[0081] S306, controlling the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a high invalid state;

[0082] In the process of preparing to enter the standby state, if the PMC does not receive the response message fed back by the CPU based on the holdsleepn signal and recognizes that the wakeup source wakeup signal appears, it controls the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a high invalid state.

[0083] S307, completing information synchronization between the power management controller and the CPU based on the holdsleepn signal being in a high invalid state;

[0084] Here, completing the information synchronization between the power management controller and the CPU based on the holdsleepn signal being in a high invalid state includes: when controlling the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a high invalid state, controlling the internal low-speed SIRC clock timing to jump the PMC back to the normal operating mode.

[0085] The first case: When the system supports CPU retention and its state jumps to PMC_CPURD_REQ state, a wakeup source suddenly appears when the system reads CPU retention information. The PMC can be controlled to jump to normal run mode in the third cycle of sirc_clk to terminate the operation of reading CPU retention information.

[0086] The second case: When the system supports CPU retention, when the PMC enters the isolation enable to power down stage, that is, it is in the PMC_ISO_ON state, when a wakeup source appears in this stage, the PMC can be controlled to jump to normal run mode in the third cycle of sirc_clk.

[0087] In the first and second cases, the holdsleepn signal can be pulled high in the third cycle of sirc_clk to synchronize the PMC with the CPU. This means that the PMC controls the internal low-speed SIRC clock timing to keep the power management controller in normal operating mode and the holdsleepn signal acting on the CPU in an inactive high state, allowing the CPU to transition to normal operating mode.

[0088] S308, sending a wakeup signal from the synchronous wakeup source to the CPU for CPU wakeup processing;

[0089] In the process of preparing to enter the standby state, if the PMC receives a response message fed back by the CPU based on the holdsleepn signal and recognizes that a wakeup source wakeup signal appears, it is necessary to synchronize the wakeup source wakeup signal to the CPU to wake up the CPU.

[0090] S309: Enable the power management system to enter a normal operating mode.

[0091] The above is based on the fact that the holdsleepn signal is in a high invalid state to complete the information synchronization between the power management controller and the CPU, so that the power management system enters the normal operating mode, and the entire power management system enters the normal operating mode, avoiding the risk of the CPU hanging or running away.

[0092] based on Figure 3 The method shown can set the holdsleepn signal between the PMC and the CPU, which is associated with the internal low-speed SIRC clock timing, so that the CPU can keep from executing instructions when preparing to enter the standby state. When the wake-up source is triggered, the holdsleepn signal is in a high invalid state. When the CPU is in the CPU memory retention control state, the CPU can enter the normal operating mode, so that the CPU and the power management controller are both in normal operating mode, avoiding CPU operation hanging or running away, and making the CPU and the power management controller operate with the same mechanism, and achieving information synchronization under normal mode operation.

[0093] Example 3:

[0094] Specifically, Figure 3 FIG. 1 shows a flow chart of a second method for suspending the standby operation of the power management system in an embodiment of the present invention. Figure 3 The method shown is based on Figure 1 The power management system shown in the embodiment is implemented. The power management system in the third embodiment supports CPU memory retention control and requires low power consumption control of the flash. The method includes the following steps:

[0095] S301, the CPU generates a deep sleep instruction and sends the deep sleep instruction to the PMC;

[0096] When the SOC is in normal operation RUN mode and is required to enter the standby mode STANDBY, in order to ensure the state change, it needs to go through the waiting PMC_WAIT_CPU_HOLD, PMC_RDCPU_REQ, PMC_ISO_ON and other states before entering the STANDBY mode, where:

[0097] When the RUN mode in the SOC enters the PMC_WAIT_CPU_HOLD state, the CPU generates a deep sleep instruction, which is sent to the PMC. The PMC generates a holdsleepn signal to hold the CPU from executing the instruction. During this process, the PMC needs to wait for the CPU to be held in sleep (hold sleep) by the PMC, that is, the PMC_WAIT_CPU_HOLD state. In this state, the CPU has power but does not execute instructions.

[0098] When the CPU is preparing to power off, because the system supports CPU memory retention control, it must enter the CPU retention read request phase, transitioning from the PMC_WAIT_CPU_HOLD state to the PMC_RDCPU_REQ state. In the PMC_RDCPU_REQ state, the CPU is powered but not executing instructions. The PMC generates CPU retention instructions and sends them to the CPU's static memory unit. Based on the CPU retention instructions, the CPU's static memory unit reads the current running instructions from the CPU and writes them to the CPU's static memory unit. Once retention control is complete, the PMC enters the isolation-on state, or PMC_ISO_ON. In the PMC_ISO_ON state, the CPU is held in sleep mode by the PMC, while the PMC is operating normally. The system isolation state must be enabled by transitioning the PMC from normal operation to the lowest power mode. After the system isolation state is established, the SoC shuts down most digital circuits, retaining only external wakeup sources and entering standby mode.

[0099] S302, after receiving the deep sleep instruction, the PMC generates a holdsleepn signal indicating that the CPU holds the instruction and does not execute it, and sends the holdsleepn signal to the CPU;

[0100] In the process of waiting for PMC_WAIT_CPU_HOLD, PMC_RDCPU_REQ, PMC_ISO_ON and other states to enter the STANDBY mode, the CPU only does not execute instructions but receives power from the power module.

[0101] The deep sleep instruction, holdsleepn signal, and holdsleep_ackn are set between the CPU and PMC to realize the synchronization process between the CPU and PMC.

[0102] The deep sleep command is a deep sleep signal generated by the CPU. After receiving this signal, the PMC starts to control the system to enter the STANDBY mode.

[0103] The holdsleepn signal is a signal that holds the CPU from executing instructions. It is generated by the PMC and sent to the CPU. When the CPU receives this signal, it holds the CPU state. When the holdsleepn signal enters STANDBY mode and a PMC synchronous wakeup source occurs, the holdsleepn signal is deasserted in the second beat.

[0104] holdsleep_ackn is the acknowledgment signal that the CPU is held, which is fed back by the CPU after receiving the holdsleepn signal. It is generated by the CPU and sent to the PMC component. When holdsleepn is invalid, the holdsleep_ackn signal is invalid after the second beat.

[0105] After receiving the deep sleep instruction, the PMC generates a holdsleepn signal for the CPU to hold the non-execution instruction, and sends the holdsleepn signal to the CPU, including: after receiving the deep sleep instruction, the PMC generates the holdsleepn signal based on the internal low-speed SIRC clock (sirc_clk) timing.

[0106] S303, the PMC controls the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a low-active state, so that the power management system is ready to enter the standby state;

[0107] It should be noted that preparing the power management system to enter the standby state includes: determining whether the power management system supports the CPU memory function; if it is determined that the CPU supports the CPU memory function, the PMC sends a CPU memory instruction to the CPU memory control unit; if it is determined that the CPU does not support the CPU memory function, the PMC triggers the power management system to enter the isolation enabled state.

[0108] In this embodiment, since the system supports CPU memory retention control, the CPU memory control unit here receives the CPU memory instruction and performs a CPU memory information reading operation based on the CPU memory instruction.

[0109] Here, the operation of reading the CPU memory information based on the CPU memory instruction includes: reading the CPU memory information from the CPU, and storing the CPU memory information in the CPU memory static storage unit.

[0110] In step S303, the PMC controls the flash to enter a low power consumption mode. The PMC needs to control the control signal of the flash in different power consumption modes so that the flash is ready to enter a standby state.

[0111] S304: The PMC recognizes that a wakeup signal from a wakeup source appears.

[0112] S305: Determine whether the CPU has fed back a response message. If no response message is received, proceed to S306; if a response message is received, proceed to S306;

[0113] holdsleep_ackn is the acknowledge signal that the CPU is held, which is fed back by the CPU after receiving the holdsleepn signal. It is the response message here. Receipt of this response message indicates that the CPU power-down in the three stages of PMC_WAIT_CPU_HOLD, PMC_RDCPU_REQ, and PMC_ISO_ON has not been completed. It can release the holdsleepn valid state and enter the RUN mode according to the generation of the wake-up source.

[0114] S306, controlling the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a high invalid state;

[0115] In the process of preparing to enter the standby state, if the PMC does not receive the response message fed back by the CPU based on the holdsleepn signal and recognizes that the wakeup source wakeup signal appears, it controls the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a high invalid state.

[0116] S307, completing information synchronization between the power management controller and the CPU based on the holdsleepn signal being in a high invalid state;

[0117] Here, completing the information synchronization between the power management controller and the CPU based on the holdsleepn signal being in a high invalid state includes: when controlling the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a high invalid state, controlling the internal low-speed SIRC clock timing to jump the PMC back to the normal operating mode.

[0118] The first case: When the system supports CPU retention and its state jumps to PMC_CPURD_REQ state, a wakeup source suddenly appears when the system reads CPU retention information. The PMC can be controlled to jump to normal run mode in the third cycle of sirc_clk to terminate the operation of reading CPU retention information.

[0119] The second case: When the system supports CPU retention, when the PMC enters the isolation enable to power down stage, that is, it is in the PMC_ISO_ON state, when a wakeup source appears in this stage, the PMC can be controlled to jump to normal run mode in the third cycle of sirc_clk.

[0120] In the first and second cases, the holdsleepn signal can be pulled high in the third cycle of sirc_clk to synchronize the PMC with the CPU. This means that the PMC controls the internal low-speed SIRC clock timing to keep the power management controller in normal operating mode and the holdsleepn signal acting on the CPU in an inactive high state, allowing the CPU to transition to normal operating mode.

[0121] S308, sending a wakeup signal from the synchronous wakeup source to the CPU for CPU wakeup processing;

[0122] In the process of preparing to enter the standby state, if the PMC receives a response message fed back by the CPU based on the holdsleepn signal and recognizes that a wakeup source wakeup signal appears, it is necessary to synchronize the wakeup source wakeup signal to the CPU to wake up the CPU.

[0123] S309: Enable the power management system to enter a normal operating mode.

[0124] The above is based on the holdsleepn signal being in a high invalid state to complete the information synchronization between the power management controller and the CPU, so that the power management system enters the normal operating mode, and the entire power management system enters the normal operating mode, avoiding the risk of the CPU running away or hanging.

[0125] During step S309 , when the power management system enters the normal operating mode, it is necessary to control the internal low-speed SIRC clock timing to act on the flash memory unit so that the flash memory unit jumps back to the normal operating mode from the standby state.

[0126] It should be noted that the control of the internal low-speed SIRC clock timing to act on the flash memory unit so that the flash memory unit jumps from the standby state back to the normal operating mode includes: identifying the low power consumption mode of the flash memory unit; controlling the internal low-speed SIRC clock timing to act on the control signal timing corresponding to the low power consumption mode, so that the flash memory unit jumps from the standby mode back to the normal operating mode.

[0127] Since flash has two low power consumption modes: DPD and power off, the control signal of the flash needs to be controlled in different power consumption modes.

[0128] Figure 4The first schematic diagram shows the wake-up control signal timing when the PMC enters the standby mode in an embodiment of the present invention. Here, the flash is in deep power down (DPD) low power mode. After the first power-on, the fls_dpd signal will always remain low. The PMC will control other control signals of the flash during the process of entering the standby mode.

[0129] Figure 5 A second schematic diagram shows the wake-up control signal timing when the PMC enters the standby mode in an embodiment of the present invention. Here, the flash is in the power-off low-power mode. When the low-power mode of the flash is power-off, after the first power-on, the fls_porb and fls_supplyon signals will always be maintained high. If the PMC controls the fls_porb and fls_supplyon signals during the process of entering the standby mode, the specific timing of some control signals when the PMC wakes up during the process of entering the standby mode.

[0130] It should be noted that the wakeup (sync2) here occurs in the ds2iso stage. Except for holdsleepn being pulled low, other control signals will maintain their original values. The holdsleepn signal will be pulled high immediately when the PMC enters run mode.

[0131] The method involved in the embodiment of the present invention sets a holdsleepn signal between the PMC and the CPU, which is associated with the internal low-speed SIRC clock timing, so that the CPU can keep from executing instructions when preparing to enter the standby state. When the wake-up source is triggered, the holdsleepn signal is in a high invalid state, and the CPU can enter the normal operating mode, so that the CPU and the power management controller are both in normal operating mode, avoiding CPU operation hanging or running away, and making the CPU and the power management controller operate with the same mechanism, and achieving information synchronization under normal mode operation.

[0132] Example 4

[0133] Specifically, Figure 3 FIG. 1 shows a flow chart of a second method for suspending the standby operation of the power management system in an embodiment of the present invention. Figure 3 The method shown is based on Figure 1 The power management system shown in FIG. 4 is implemented. In this fourth embodiment, the power management system does not support CPU memory retention control. The method includes the following steps:

[0134] S301, the CPU generates a deep sleep instruction and sends the deep sleep instruction to the PMC;

[0135] When the SOC is in normal operation RUN mode and is required to enter the standby mode STANDBY, in order to ensure the state change, it needs to go through the waiting PMC_WAIT_CPU_HOLD, PMC_ISO_ON and other states before entering the STANDBY mode, where:

[0136] When the RUN mode in the SOC enters the PMC_WAIT_CPU_HOLD state, the CPU generates a deep sleep instruction, which is sent to the PMC. The PMC generates a holdsleepn signal to hold the CPU from executing the instruction. During this process, the PMC needs to wait for the CPU to be held in sleep (hold sleep) by the PMC, that is, the PMC_WAIT_CPU_HOLD state. In this state, the CPU has power but does not execute instructions.

[0137] When the CPU is preparing to power off, the power management system here does not support CPU memory retention control, so it is necessary to switch from the PMC_WAIT_CPU_HOLD state to the PMC_ISO_ON state. That is, in the PMC_ISO_ON state, the CPU is held in sleep mode by the PMC, and the PMC is in normal operation. It is necessary to make the PMC enter the lowest power consumption mode from normal operation to complete the system isolation enable state. After the system isolation enable state is completed, the on-chip system turns off the power supply of most digital circuits and only retains the external wake-up source to enter the STANDBY mode.

[0138] S302, after receiving the deep sleep instruction, the PMC generates a holdsleepn signal indicating that the CPU holds the instruction and does not execute it, and sends the holdsleepn signal to the CPU;

[0139] When entering the STANDBY mode after waiting for PMC_WAIT_CPU_HOLD, PMC_ISO_ON and other states, the CPU simply does not execute instructions but receives power from the power module.

[0140] The deep sleep instruction, holdsleepn signal, and holdsleep_ackn are set between the CPU and PMC to realize the synchronization process between the CPU and PMC.

[0141] The deep sleep command is a deep sleep signal generated by the CPU. After receiving this signal, the PMC starts to control the system to enter the STANDBY mode.

[0142] The holdsleepn signal is a signal that holds the CPU from executing instructions. It is generated by the PMC and sent to the CPU. When the CPU receives this signal, it holds the CPU state. When the holdsleepn signal enters STANDBY mode and a PMC synchronous wakeup source occurs, the holdsleepn signal is deasserted in the second beat.

[0143] holdsleep_ackn is the acknowledgment signal that the CPU is held, which is fed back by the CPU after receiving the holdsleepn signal. It is generated by the CPU and sent to the PMC component. When holdsleepn is invalid, the holdsleep_ackn signal is invalid after the second beat.

[0144] After receiving the deep sleep instruction, the PMC generates a holdsleepn signal for the CPU to hold the non-execution instruction, and sends the holdsleepn signal to the CPU, including: after receiving the deep sleep instruction, the PMC generates the holdsleepn signal based on the internal low-speed SIRC clock (sirc_clk) timing.

[0145] S303, the PMC controls the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a low-active state, so that the power management system is ready to enter the standby state;

[0146] It should be noted that preparing the power management system to enter the standby state includes: determining whether the power management system supports the CPU memory function; if the CPU is determined to support the CPU memory function, the PMC sends a CPU memory instruction to the CPU memory control unit; if the CPU is determined not to support the CPU memory function, the PMC triggers the power management system to enter the isolation-enabled state. Since the CPU memory function is not supported here, the PMC triggers the power management system to directly enter the isolation-enabled state.

[0147] It should be noted that during this process, the PMC will control the flash to enter a low power consumption mode. It needs to control the control signal of the flash in different power consumption modes so that it is ready to enter a standby state.

[0148] S304: The PMC recognizes that a wakeup signal from a wakeup source appears.

[0149] S305: Determine whether the CPU has fed back a response message. If no response message is received, proceed to S306; if a response message is received, proceed to S306;

[0150] holdsleep_ackn is the acknowledge signal that the CPU is held, which is fed back by the CPU after receiving the holdsleepn signal. It is the response message here. Receipt of this response message indicates that the CPU power-off in the three stages of PMC_WAIT_CPU_HOLD, PMC_RDCPU_REQ, and PMC_ISO_ON has not been completed, and the CPU can release the holdsleepn valid state at any time to enter the RUN mode.

[0151] S306, controlling the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a high invalid state;

[0152] In the process of preparing to enter the standby state, if the PMC does not receive the response message fed back by the CPU based on the holdsleepn signal and recognizes that the wakeup source wakeup signal appears, it controls the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a high invalid state.

[0153] S307, completing information synchronization between the power management controller and the CPU based on the holdsleepn signal being in a high invalid state;

[0154] Here, completing the information synchronization between the power management controller and the CPU based on the holdsleepn signal being in a high invalid state includes: when controlling the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a high invalid state, controlling the internal low-speed SIRC clock timing to jump the PMC back to the normal operating mode.

[0155] Because the system does not support CPU retention, when the PMC enters the isolation enable to power down stage, that is, it is in the PMC_ISO_ON state. If a wakeup source appears in this stage, the PMC can be controlled to jump to normal run mode in the third cycle of sirc_clk.

[0156] In this case, the holdsleepn signal can be pulled high in the third cycle of sirc_clk to synchronize the PMC with the CPU. This means that the PMC controls the internal low-speed SIRC clock timing to keep the power management controller in normal operating mode, and sets the holdsleepn signal on the CPU to an inactive high state, allowing the CPU to transition to normal operating mode.

[0157] S308, sending a wakeup signal from the synchronous wakeup source to the CPU for CPU wakeup processing;

[0158] In the process of preparing to enter the standby state, if the PMC receives a response message fed back by the CPU based on the holdsleepn signal and recognizes that a wakeup source wakeup signal appears, it is necessary to synchronize the wakeup source wakeup signal to the CPU to wake up the CPU.

[0159] S309: Enable the power management system to enter a normal operating mode.

[0160] It should be noted that, in the process of making the power management system enter the normal operating mode, it is necessary to control the internal low-speed SIRC clock timing to act on the flash memory unit so that the flash memory unit jumps back to the normal operating mode from the standby state.

[0161] It should be noted that the control of the internal low-speed SIRC clock timing to act on the flash memory unit so that the flash memory unit jumps from the standby state back to the normal operating mode includes: identifying the low power consumption mode of the flash memory unit; controlling the internal low-speed SIRC clock timing to act on the control signal timing corresponding to the low power consumption mode, so that the flash memory unit jumps from the standby mode back to the normal operating mode.

[0162] Since flash has two low power consumption modes: DPD and power off, the control signal of the flash needs to be controlled in different power consumption modes.

[0163] Figure 4 The first schematic diagram shows the wake-up control signal timing when the PMC enters the standby mode in an embodiment of the present invention. Here, the flash is in deep power down (DPD) low power mode. After the first power-on, the fls_dpd signal will always remain low. The PMC will control other control signals of the flash during the process of entering the standby mode.

[0164] Figure 5A second schematic diagram shows the wake-up control signal timing when the PMC enters the standby mode in an embodiment of the present invention. Here, the flash is in the power-off low-power mode. When the low-power mode of the flash is power-off, after the first power-on, the fls_porb and fls_supplyon signals will always be maintained high. If the PMC controls the fls_porb and fls_supplyon signals during the process of entering the standby mode, the specific timing of some control signals when the PMC wakes up during the process of entering the standby mode.

[0165] It should be noted that the wakeup (sync2) here occurs in the ds2iso stage. Except for holdsleepn being pulled low, other control signals will maintain their original values. The holdsleepn signal will be pulled high immediately when the PMC enters run mode.

[0166] The method involved in the embodiment of the present invention sets a holdsleepn signal between the PMC and the CPU, which is associated with the internal low-speed SIRC clock timing, so that the CPU can keep from executing instructions when preparing to enter the standby state. When the wake-up source is triggered, the holdsleepn signal is in a high invalid state, and the CPU can enter the normal operating mode, so that the CPU and the power management controller are both in normal operating mode, avoiding CPU operation hanging or running away, and making the CPU and the power management controller operate with the same mechanism, and achieving information synchronization under normal mode operation.

[0167] The computer-readable storage medium may be an internal storage unit of the device described in the aforementioned embodiment, such as a hard disk or memory. The computer-readable storage medium may also be an external storage device of the device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. Furthermore, the computer-readable storage medium may include both an internal storage unit and an external storage device of the device. The computer-readable storage medium is used to store the computer program and other programs and data required by the device. The computer-readable storage medium may also be used to temporarily store data that has been output or is about to be output.

[0168] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing related hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When executed, the program can include the processes in the above-described method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0169] The embodiments of the present invention are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A method for suspending standby operation of a power management system, characterized in that: The method comprises the following steps: After receiving the deep sleep instruction, the power management controller PMC generates a holdsleepn signal for the CPU to hold and not execute the instruction, and sends the holdsleepn signal to the CPU. The holdsleepn signal for the CPU to hold and not execute the instruction requires the PMC to wait for the CPU to be maintained in a sleep state by the PMC and for the CPU to be powered but not execute instructions in this state. Control the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a low-active state, so that the power management system is ready to enter the standby state; In the process of preparing to enter the standby state, if the PMC does not receive the response message fed back by the CPU based on the holdsleepn signal and recognizes that the wakeup source wakeup signal appears, it controls the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a high invalid state; Based on the holdsleepn signal being in a high invalid state, information synchronization between the power management controller and the CPU is completed, so that the power management system enters a normal operating mode.

2. The method for suspending the standby operation of the power management system according to claim 1, wherein: The step of preparing the power management system to enter the standby state includes: Determining whether the power management system supports the CPU memory function; If it is determined that the CPU supports the CPU memory function, the PMC sends a CPU memory instruction to the CPU memory control unit; If it is determined that the CPU does not support the CPU memory function, the PMC triggers the power management system to enter the isolation enabled state.

3. The method for suspending the standby operation of the power management system according to claim 2, wherein: The method further comprises: The CPU memory control unit receives the CPU memory instruction and performs a CPU memory information reading operation based on the CPU memory instruction.

4. The method for suspending the standby operation of the power management system according to claim 3, wherein: The operation of reading CPU memory information based on the CPU memory instruction includes: The CPU memory information is read from the CPU and stored in the CPU memory static storage unit.

5. The method for suspending the standby operation of the power management system according to claim 1, wherein: The completing information synchronization between the power management controller and the CPU based on the holdsleepn signal being in a high invalid state includes: When the internal low-speed SIRC clock timing is controlled so that the holdsleepn signal acting on the CPU is in a high invalid state, the internal low-speed SIRC clock timing is controlled to jump the PMC back to the normal operating mode.

6. The method for suspending the standby operation of the power management system according to claim 1, wherein: The method further comprises: The internal low-speed SIRC clock timing is controlled to act on the flash memory unit so that the flash memory unit jumps back to the normal operating mode from the standby state.

7. The method for suspending the standby operation of the power management system according to claim 6, wherein: The controlling of the internal low-speed SIRC clock timing to act on the flash memory unit so that the flash memory unit jumps from the standby state to the normal operating mode includes: Identify low-power modes of flash memory cells; The internal low-speed SIRC clock timing is controlled to act on the control signal timing corresponding to the low power mode, so that the flash memory unit jumps back to the normal operating mode from the standby mode.

8. A power management system, characterized in that: The power management system includes: The power management controller PMC is used to generate a holdsleepn signal for the CPU to hold and not execute the instruction after receiving a deep sleep instruction, and send the holdsleepn signal to the CPU; control the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a low-active state, so that the power management system is ready to enter the standby state; in the process of preparing to enter the standby state, if the PMC does not receive a response message fed back by the CPU based on the holdsleepn signal, and recognizes that the wakeup source wakeup signal appears, then control the internal low-speed SIRC clock timing so that the holdsleepn signal acting on the CPU is in a high-inactive state; based on the holdsleepn signal being in a high-inactive state, complete the information synchronization between the power management controller and the CPU, so that the power management system enters the normal operating mode, the CPU holds the holdsleepn signal for not executing the instruction so that the PMC needs to wait for the CPU to be maintained in a sleep state by the PMC and the CPU has power supply but does not execute instructions in this state; The CPU is configured to generate a deep sleep instruction and send the deep sleep instruction to the PMC; and receive a holdsleepn signal.

9. The power management system according to claim 8, wherein: The power management system further includes: The CPU memory control unit is used to receive the CPU memory instruction sent by the PMC when preparing to enter the standby state, and read the current running instruction from the CPU based on the memory instruction and write the running instruction into the CPU memory static storage unit; The CPU memory static storage unit is used to store the current running instructions written by the CPU memory control unit.

10. The power management system according to claim 8, wherein: The power management system further includes: The flash memory unit is used to jump back to the normal operating mode from the standby state under the control of the internal low-speed SIRC clock timing when preparing to enter the standby state.

Images