On-the-fly multiplexing scheme for compressed soft bit data in non-volatile memory

Abstract

The present invention relates to non-volatile memory that uses hard and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from the memory to the controller and to improve memory system performance, the soft bit data can be compressed prior to transfer. After the soft bit data is read and stored into internal data latches associated with sense amplifiers, the soft bit data is compressed within the internal data latches. The compressed soft bit data can then be transferred to transfer data latches of a cache buffer, where the compressed soft bit data can be merged and transferred out through an input-output interface. Within the input-output interface, the compressed data can be reformatted, if needed, to place it in logical user data order.

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