A transceiving system having a multiplexed FIFO

Abstract

The application discloses a transceiving system with a multiplexing FIFO, which comprises a multiplexing FIFO, a sending buffer control module and a receiving buffer control module. The sending buffer control module is used for controlling the conversion of the to-be-sent message data into corresponding symbol codes according to a first preset data coding format and buffering the symbol codes in the multiplexing FIFO; the sending buffer control module is also used for calculating a check code, controlling the conversion of the check code into corresponding symbol codes according to the first preset data coding format, controlling the BMC coding of the symbol codes and the corresponding symbol codes of the check code buffered in the multiplexing FIFO, and sending the coding result to a CC line. The receiving buffer control module is used for receiving the coding result from the CC line and performing BMC decoding to obtain corresponding symbol codes; the receiving buffer control module is also used for converting the to-be-received data packet into the second preset data coding format and buffering the to-be-received data packet in the multiplexing FIFO; and the receiving buffer control module is also used for reading the to-be-received data packet from the multiplexing FIFO and performing a check, and saving the to-be-received data packet to outside of the multiplexing FIFO when the to-be-received data packet is error-free.

Description

Technical Field

[0001] This application relates to the field of circuit multiplexing technology, and more particularly to a transceiver system with a multiplexed FIFO. Background Technology

[0002] Chinese invention patent application CN201810679019.1 discloses the newly released USB Type-C Power Delivery Protocol (hereinafter referred to as PD protocol), which is based on USB 3.1 and is a power delivery protocol based on the Type-C interface. USB PD can support a maximum power delivery of 100W (20V / 5A) and supports power supply role switching, meeting the power supply needs of most electronic devices. In the USB Type-C interface, USB PD communication uses Biphase Mark Coding (BMC) to transmit data on the CC channel. This method is simple and flexible, has been released as a PD communication standard, and is gradually being widely used. BMC encoding is a phase modulation encoding technique that mixes clock and data for transmission. A key feature of BMC encoding is that the level changes at the beginning of each bit cycle. Within a bit cycle, level changes represent logic; if the level changes in the middle of the bit cycle, it represents logic "1"; otherwise, it represents logic "0". Using BMC encoding allows the transmitting and receiving ends to transmit and receive data correctly with only one data line. Each communication data packet contains a frame header and multiple message data. In order to buffer the communication data packets, starting from the frame header, the frame header and the high-order bits of the first message data are concatenated to form the first buffered data. Then, the partial bits of the two adjacent message data are concatenated to form the subsequent data that need to be buffered. The bit width of each buffered data is relatively large. Both the transmitting and receiving ends need to set up a large-depth buffer FIFO for buffering, and then wait for the opportunity to receive encoding, decoding or verification on the transmission line. Moreover, the large depth also makes the buffer FIFO occupy a large circuit chip area.

[0003] In addition, Chinese invention patent application CN202011274235.1 discloses a data encryption control system based on a USB interface. It reveals that the memory in the same device needs to include a data transmission buffer and a data reception buffer, and two levels of buffer memory are set up to cache the data to be encrypted and the encrypted data respectively. This leads to an increase in the usage of the buffer FIFO, which makes it easy for buffer redundancy design to occur in a USB interface system with data transmission and reception functions. Summary of the Invention

[0004] This application discloses a transceiver system with a multiplexed FIFO, and the specific technical solution is as follows: A transceiver system with a multiplexed FIFO includes a multiplexed FIFO, a transmit buffer control module, and a receive buffer control module. Both the transmit and receive buffer control modules are connected to the multiplexed FIFO and are connected via a CC line. The transmit buffer control module controls the conversion of the message data to be transmitted into a symbol code corresponding to the message data according to a first preset data encoding format, and buffers the symbol code corresponding to the message data to be transmitted in the multiplexed FIFO. The transmit buffer control module calculates a checksum using the message data to be transmitted, then controls the conversion of the checksum into a symbol code corresponding to the checksum according to the first preset data encoding format, then controls the symbol code buffered in the multiplexed FIFO and the symbol code corresponding to the checksum to perform BMC encoding to form an encoding result, and then sends the encoding result to the CC line. The receive buffer control module is used to receive the encoding result from the CC line and perform BMC decoding to obtain the symbol code corresponding to the message data to be sent and the symbol code corresponding to the check code. The receive buffer control module is used to convert the symbol code corresponding to the message data to be sent and the symbol code corresponding to the check code into a data packet to be received according to the second preset data encoding format, and buffer the data packet to be received in the multiplexing FIFO. The data packet to be received consists of the message data to be sent and the check code. The receive buffer control module is used to read the data packet to be received from the multiplexing FIFO and verify it according to the check code in the data packet to be received. When the data packet to be received is found to be without error, the message data to be sent in the read data packet to be received is saved outside the multiplexing FIFO, so that the multiplexing FIFO can free up memory space for the send buffer control module to buffer new data.

[0005] In summary, the transmit buffer control module and the receive buffer control module can send data to and receive data from the CC line through the multiplexed FIFO, allowing the multiplexed FIFO to integrate data transmission and reception functions. This enables shared buffer space resources between the transmission and reception paths, reducing the amount of FIFO usage. Furthermore, the transmit buffer control module disclosed in this application controls the data to be transmitted to be encoded according to the first preset data encoding format, buffered in the multiplexed FIFO, and a checksum is calculated before being encoded together using BMC and sent to the CC line. The receive buffer control module reads the data encoded and converted by the transmit buffer control module from the multiplexed FIFO based on the checksum generated internally by the transmit buffer control module and performs verification. If the verification is successful, the data before encoding and conversion by the transmit buffer control module is restored, ensuring normal interaction and storage of valid message data between the transmit buffer control module and the receive buffer control module connected to the CC line. This improves the reliability and efficiency of data transmission by multiplexing access to the same FIFO. Therefore, whether the first preset data encoding format used by the transmitting buffer control module or the second preset data encoding format used by the receiving buffer control module is used to process the data transmitted on the CC line, compared with the prior art which designs at least one FIFO before and after encoding, this application realizes the reuse of a FIFO, reuses part of the FIFO resources in the prior art, improves resource utilization, reduces the number of FIFOs, reduces chip area, and avoids redundant design. Attached Figure Description

[0006] Figure 1 This application provides a schematic diagram of the module distribution of a transceiver system with a multiplexed FIFO.

[0007] Figure 2 This application provides a connection diagram showing that the transmit buffer control module and the receive buffer control module share a multiplexed FIFO. Detailed Implementation

[0008] The present application will be described in further detail below with reference to embodiments and accompanying drawings, but the implementation of the present application is not limited thereto. It should be noted that a data packet packaged during communication includes three parts: a frame header, a data code, and a frame trailer. The frame header and frame trailer contain necessary control information. The frame header is the start of the frame and contains control information such as source address, destination address, and sequence number, used for identifying and synchronizing data. The frame trailer contains checksums or end markers, used for data error detection and to indicate the end of the frame. The data code contains multiple bits of data and is the main content of the frame, containing the actual transmitted data information. The length of this part can be adjusted according to actual needs.

[0009] The newly released USB Type-C Power Delivery Protocol (hereinafter referred to as the PD protocol) discloses that a USB PD data packet consists of a preamble, a Scenario Opening (SOP*) code, a Message Header, a data code, a Checksum (CRC), and an End Opening (EOP) code. If there is no data after the Message Header, the data packet is a control message, indicating that the data packet is only used as a control command, and is called a control message. If there is data content after the Message Header, the data packet is called a data message, which usually contains information such as the voltage and current values ​​to be changed. In the entire USB PD data packet, except for the preamble which does not need to be 4b5b encoded, all other parts of the data packet need to be 4b5b encoded. After the specified data is 4b5b encoded, all data in the data packet needs to be encoded using the Configuration Channel (BMC) before it can be sent via the CC. The PD protocol uses the CC (Configuration channel) pin of the USB Type-C interface as a data transmission channel to negotiate the voltage, current, and power transmission direction of charging.

[0010] In USB PD protocol data packets, except for the preamble, all other parts require 4b5b encoding to reduce the complexity and increase the flexibility of receiver design. The principle of 4b5b encoding is to establish a 4b5b encoding table, mapping 4-bit data to 5-bit data. The transmitting end encodes the 4-bit data according to the encoding table. The principle of 5b4b encoding is to use the aforementioned 4b5b encoding table to map 5-bit data to 4-bit data. The receiving end decodes the 5-bit data according to the encoding table. Regardless of whether it's 4b5b or 5b4b encoding, at least one FIFO (First In First Out, a data storage buffer) is designed before and after encoding. Sometimes, an additional FIFO is designed to select valid data for storage based on CRC check results; sometimes, a FIFO is designed for buffering to overcome the problem of data transmission across clock cycles. Therefore, as a USB interface system with data transmission and reception functions, redundant buffer design is prone to occur. The USB Type-C interface is a USB interface that conforms to the PD protocol and has a CC pin.

[0011] To address the aforementioned technical deficiencies, this application discloses a transceiver system with a multiplexed FIFO, such as... Figure 1As shown, the transceiver system includes a multiplexed FIFO (First In First Out, a type of data storage and buffer), a transmit buffer control module, and a receive buffer control module. Both the transmit and receive buffer control modules are connected to the multiplexed FIFO and share a single multiplexed FIFO. The transmit and receive buffer control modules can be integrated into a fast charging device using the PD protocol, or they can be separately located in a transmitting device (e.g., a power supply device using the PD protocol) and a receiving device (e.g., a power receiving device using the PD protocol). Therefore, the transmit and receive buffer control modules each have a CC pin and are connected via a CC line.

[0012] The transmit buffer control module is used to control the conversion of the message data to be transmitted into the symbol code corresponding to the message data to be transmitted according to the first preset data encoding format, and to cache the symbol code corresponding to the message data to be transmitted in the multiplexed FIFO, thereby reducing the design complexity of the receive buffer control module. The message data to be transmitted mentioned in this application may be the message content of the USBPD data packet, but the message data to be transmitted shall at least include a function code (Message Header) and a data code.

[0013] The message data to be sent is pre-stored in the message register inside the transmission buffer control module and participates in the conversion under the first preset data encoding format through shift transmission. When the 4b5b encoding specified by the PD protocol is used for conversion, the preamble does not need to be converted. After the message data to be sent is converted, the bit width of the converted data increases, the amount of stored data is reduced, and the newly added bits can be reserved for use in extended instructions, thereby improving the design flexibility of the receive buffer control module.

[0014] During data transmission within the transmit buffer control module, the data of each bit in the message to be transmitted will not change, and no cross-clock processing is required. The multiplexed FIFO can complete the buffering operation of the symbol code corresponding to the message to be transmitted completely and stably without the cooperation of other FIFOs.

[0015] The transmit buffer control module is used to calculate the checksum using the data to be transmitted. The checksum is then used for verification and protection. The checksum generation mechanism generally uses a lookup table approach, which can be referenced in the CRC checksum algorithm rules in the USB charging standards and technologies defined by the USB IF Association. Details will not be provided here. The transmit buffer control module, after calculating the checksum, controls the conversion of the checksum into its corresponding symbol code according to the first preset data encoding format. It then controls the symbol code buffered in the multiplexed FIFO and the symbol code corresponding to the checksum to perform BMC encoding to form the encoding result. The transmit buffer control module is also used to send the encoding result to the CC line. Generally, it first controls the symbol code corresponding to the data to be transmitted to perform BMC encoding and sends it to the CC line, then controls the symbol code corresponding to the checksum to perform BMC encoding and sends the encoding result to the CC line, allowing the transmitting end to send the data to be transmitted first and then send the checksum.

[0016] It should be noted that the transmit buffer control module and the receive buffer control module communicate via the configuration signal line (CC line). The transmit buffer control module can attach a checksum to the data to be transmitted and transmit the payload, including the checksum, through biphase mark coding (BMC) on the CC line. The CC line (Configuration Channel) is a type of USB Type-C. The CC line transmits signals using BMC (Biphase Mark Coding) encoding, where one phase change represents logic 0 and two phase changes represent logic 1. The CC line supports pull-up / pull-down resistors and power role monitoring. The interface circuit within the transmit buffer control module is connected to the interface circuit within the receive buffer control module via the CC pin. The transmit buffer control module or the receive buffer control module can simultaneously include both a transmitter and a receiver, and its application scenarios include power transfer communication with mobile terminal devices.

[0017] The receive buffer control module is used to receive the encoding result from the CC line and perform BMC decoding to obtain the symbol code corresponding to the message data to be sent and the symbol code corresponding to the check code. Specifically, when the receive buffer control module performs BMC decoding, it will decode the symbol code sent from the CC line by restoring the clock and locking it to a frame of encoding result sent by the transmit buffer control module.

[0018] The receive buffer control module is used to convert the symbol code corresponding to the message data to be sent and the symbol code corresponding to the check code into a data packet to be received according to the second preset data encoding format, and to buffer the data packet to be received in the multiplexing FIFO. The data packet to be received is composed of the message data to be sent and the check code, and the symbol code corresponding to the data packet to be received is composed of the symbol code corresponding to the message data to be sent and the symbol code corresponding to the check code. The data bit width allowed by the first preset data encoding format is smaller than the data bit width allowed by the second preset data encoding format. When using 5b4b encoding under the PD protocol for conversion, each 5 bits of the symbol code corresponding to the data packet to be received can be converted separately and used to form the message data to be sent and the check code respectively. This reduces the data bit width and increases the amount of stored data, thus increasing the depth requirement of the multiplexing FIFO. Therefore, the depth of the multiplexing FIFO required by the send buffer control module is selected to configure the multiplexing FIFO, which is sufficient to buffer the data packet to be received or its corresponding symbol code. The first preset data encoding format is the encoding format specified by 4b5b encoding, and the second preset data encoding format is the encoding format specified by 5b4b encoding.

[0019] In a power delivery communication scenario, the device containing the transmit buffer control module sends the symbol code corresponding to the data packet to be received to the receive buffer control module to provide power supply capability information. The device containing the receive buffer control module can select from the power supply capability information and send a response command to the device containing the transmit buffer control module.

[0020] The receive buffer control module reads data packets to be received from the multiplexed FIFO and verifies them according to the checksum in the data packets. This is equivalent to using the checksum calculated by the transmit buffer control module to verify the data packets to be received. When the data packets to be received are found to be error-free (verification successful), the read data packets are saved outside the multiplexed FIFO, possibly into a message register, for use by the power control unit inside the receive buffer control module when necessary. When the data packets to be received are found to be error-free (verification failed), the data packets to be received are directly cleared from the multiplexed FIFO. Therefore, when the receive buffer control module verifies successfully, the data buffered in the multiplexed FIFO has been read by the receive buffer control module, freeing up memory space in the multiplexed FIFO for the transmit buffer control module to cache new data; when the receive buffer control module verifies unsuccessfully, the data buffered in the multiplexed FIFO has been cleared by the receive buffer control module, freeing up memory space in the multiplexed FIFO for the transmit buffer control module to cache new data. On the other hand, the receiving buffer control module can determine whether the data buffered in the multiplexing FIFO is valid based on the verification result, without the need to set up an additional FIFO between the multiplexing FIFO and the message register to buffer the data participating in the verification.

[0021] In summary, the transmit buffer control module and the receive buffer control module can send data to and receive data from the CC line through the multiplexed FIFO, allowing the multiplexed FIFO to integrate data transmission and reception functions. This enables shared buffer space resources between the transmission and reception paths, reducing the amount of FIFO usage. Furthermore, the transmit buffer control module disclosed in this application controls the data to be transmitted to be encoded according to the first preset data encoding format, buffered in the multiplexed FIFO, and a checksum is calculated before being encoded together using BMC and sent to the CC line. The receive buffer control module reads the data encoded and converted by the transmit buffer control module from the multiplexed FIFO based on the checksum generated internally by the transmit buffer control module and performs verification. If the verification is successful, the data before encoding and conversion by the transmit buffer control module is restored, ensuring normal interaction and storage of valid message data between the transmit buffer control module and the receive buffer control module connected to the CC line. This improves the reliability and efficiency of data transmission by multiplexing access to the same FIFO.

[0022] Therefore, whether the first preset data encoding format used by the transmitting buffer control module or the second preset data encoding format used by the receiving buffer control module is used to process the data transmitted on the CC line, compared with the prior art which designs at least one FIFO before and after encoding, this application realizes the reuse of a FIFO, reuses part of the FIFO resources in the prior art, improves resource utilization, reduces the number of FIFOs, reduces chip area, and avoids redundant design.

[0023] As one embodiment, the transmit buffer control module and the receive buffer control module do not access the multiplexed FIFO simultaneously; that is, they do not simultaneously transmit and receive data. When the transmit buffer control module buffers data into the multiplexed FIFO, the receive buffer control module does not buffer data into the multiplexed FIFO, nor does it read data from the multiplexed FIFO. Similarly, when the transmit buffer control module reads data from the multiplexed FIFO, the receive buffer control module does not read data from the multiplexed FIFO, nor does it buffer data into the multiplexed FIFO. Therefore, the transmit buffer control module and the receive buffer control module do not simultaneously use the multiplexed FIFO for data transmission. According to the read / write operation, when the data sent by the transmission buffer control module to the multiplexed FIFO is cached, it will not be read away by the receiving buffer control module in real time. Instead, after the data cached in the multiplexed FIFO is successfully verified and sent to the CC line after being encoded by BMC, the receiving buffer control module will first perform BMC decoding and then convert it according to the second preset data encoding format before caching it into the multiplexed FIFO. At this time, the transmission buffer control module will neither cache new data into the multiplexed FIFO nor read the currently cached data from the multiplexed FIFO. Then, the receiving buffer control module will read the data, perform verification, and then read it away when the verification is successful, so that the transmission buffer control module can cache the symbol code corresponding to a new frame of data packet into the multiplexed FIFO.

[0024] In some hardware circuit implementations of the transceiver system, a two-input OR gate / multiplexer is configured between the port where the transmit buffer control module outputs the symbol code and the port where the receive buffer control module outputs the data packet to be received. One input of the two-input OR gate / multiplexer is connected to the corresponding output of the transmit buffer control module, and the other input is connected to the corresponding output of the receive buffer control module. The output of the two-input OR gate / multiplexer is connected to the data input of the multiplexed FIFO. When the multiplexer outputs the output data of the transmit buffer control module to the multiplexing FIFO, the transmit buffer control module buffers data in the multiplexing FIFO, while the receive buffer control module does not buffer data in the multiplexing FIFO or read data from the multiplexing FIFO; when the two-input OR gate circuit / multiplexer outputs the output data of the receive buffer control module to the multiplexing FIFO, the receive buffer control module buffers data in the multiplexing FIFO, while the transmit buffer control module does not buffer data in the multiplexing FIFO or read data from the multiplexing FIFO.

[0025] Additionally, a multiplexer is configured between the port (or encoding input) of the transmit buffer control module where the symbol code is input and the verification input of the receive buffer control module. This multiplexer can be used for reverse data transmission. One input of the multiplexer is connected to the encoding input of the transmit buffer control module, and the other input is connected to the verification input of the receive buffer control module. The output of the multiplexer is connected to the data output of the multiplexed FIFO. When the multiplexer selects between the encoding input of the transmit buffer control module and the data output of the multiplexed FIFO, it triggers the output of the symbol code buffered in the multiplexed FIFO to the transmit buffer control module. BMC encoding is performed within the control module. At this time, the transmit buffer control module reads data from the multiplexed FIFO, while the receive buffer control module neither buffers data in the multiplexed FIFO nor reads data from the multiplexed FIFO. When the multiplexer selects the verification input of the receive buffer control module and the data output of the multiplexed FIFO, it triggers the output of the data packets to be received buffered in the multiplexed FIFO to the receive buffer control module, where verification is performed. At this time, the receive buffer control module reads data from the multiplexed FIFO, while the transmit buffer control module neither buffers data in the multiplexed FIFO nor reads data from the multiplexed FIFO.

[0026] Based on the above embodiments, whenever the transmit buffer control module finishes caching the symbol code corresponding to the message data to be transmitted in the multiplexing FIFO, or whenever the transmit buffer control module finishes reading the symbol code corresponding to the message data to be transmitted from the multiplexing FIFO, the transmit buffer control module configures its access address to the multiplexing FIFO to the starting address of the multiplexing FIFO or clears its access address to the multiplexing FIFO to zero. When the starting address of the multiplexing FIFO is zero, the read / write pointer can be cleared to prevent interference to the transmit buffer control module's next access to the multiplexing FIFO.

[0027] Specifically, whenever the transmit buffer control module finishes caching the symbol code corresponding to the message data to be transmitted in the multiplexed FIFO, the transmit buffer control module clears its write access address to the multiplexed FIFO to zero, or it can configure its write access address to the multiplexed FIFO to the starting address of the multiplexed FIFO; this prevents interference with the data caching of the multiplexed FIFO during subsequent data transmission accesses. Similarly, whenever the transmit buffer control module finishes reading the symbol code corresponding to the message data to be transmitted from the multiplexed FIFO, the transmit buffer control module clears its read access address to the multiplexed FIFO to zero, or it can configure its read access address to the multiplexed FIFO to the starting address of the multiplexed FIFO; this prevents interference with data reading from the multiplexed FIFO during subsequent data transmission accesses.

[0028] Whenever the receive buffer control module finishes buffering the data packet to be received in the multiplexed FIFO, or whenever the receive buffer control module finishes reading the data packet to be received from the multiplexed FIFO, the receive buffer control module configures its access address to the multiplexed FIFO to the starting address of the multiplexed FIFO or clears its access address to the multiplexed FIFO to zero. When the starting address of the multiplexed FIFO is zero, the read / write pointer can be cleared to prevent interference with the receive buffer control module's next access to the multiplexed FIFO.

[0029] Specifically, each time the receive buffer control module finishes buffering the data packet to be received in the multiplexing FIFO, it clears its write access address to the multiplexing FIFO to zero, or it can configure its write access address to the multiplexing FIFO to the starting address of the multiplexing FIFO; this prevents interference with the data buffer during subsequent data reception accesses. Similarly, each time the receive buffer control module finishes reading the data packet from the multiplexing FIFO, it clears its read access address to the multiplexing FIFO to zero, or it can configure its read access address to the multiplexing FIFO to the starting address of the multiplexing FIFO; this prevents interference with data reading from the multiplexing FIFO during subsequent data reception accesses.

[0030] As one embodiment, before the sending buffer control module controls the conversion of the message data to be sent into the symbol code corresponding to the message data according to the first preset data encoding format, the clock used to drive the message data to be sent stored in the sending buffer control module is the first clock. For example, when no data transmission access is initiated, the message data to be sent is stored in the sending message register, and the clock used by the sending message register to store the message data to be sent is the first clock, until the message data to be sent is read from the sending message register to start encoding. The first clock is as follows: Figure 2 As shown in the Osclk diagram; referring to the foregoing embodiments, the transmit buffer control module sequentially performs: controlling the conversion of the message data to be transmitted according to the first preset data encoding format, buffering the symbol code corresponding to the message data to be transmitted in the multiplexing FIFO, calculating the checksum, and performing BMC encoding. In this embodiment, the clock that drives the transmit buffer control module to control the conversion of the message data to be transmitted according to the first preset data encoding format, buffering the symbol code corresponding to the message data to be transmitted in the multiplexing FIFO, calculating the checksum, and performing BMC encoding are all the second clock. The second clock is as follows: Figure 2 As shown in Bclk; in this embodiment, when the multiplexed FIFO buffers the symbol code corresponding to the message data to be sent, it is configured with a write enable signal that has undergone cross-clock timing processing. The transmit buffer control module controls the write enable signal to undergo cross-clock timing processing. The edge of the write enable signal that has undergone cross-clock timing processing changes from being synchronized with the rising edge of the first clock Osclk to being synchronized with the rising edge of the second clock Bclk. Then, the write enable signal that has undergone cross-clock timing processing controls the multiplexed FIFO to start buffering data according to the second clock. During the process of the write enable signal that has undergone cross-clock timing processing controls the multiplexed FIFO to start buffering data according to the second clock, if a transmit data access or transmit request is valid, the message data to be sent stored in the transmit message register is read externally, for example, by... Figure 2The first right shift register is read, and data transmission occurs between the first right shift register and the transmit message register. The data to be transmitted remains unchanged throughout the entire write enable signal period after the cross-clock timing process, meeting the requirement for stable data transmission. It is unaffected by the data transmission from the first clock (Osclk) to the second clock (Bclk), eliminating the need for an additional FIFO to buffer data. This reduces the use of FIFOs for buffering cross-clock data, i.e., it reduces the need for FIFOs to buffer cross-clock domain data before controlling the conversion of the data to be transmitted according to the first preset data encoding format, significantly reducing chip area and simplifying design. Based on this, reducing the number of FIFOs reduces latency in the data transmission path, improving system response speed; it also reduces system power consumption, improving energy efficiency.

[0031] The clock that drives the receive buffer control module is the first clock. This includes the clock that drives the receive buffer control module to perform BMC decoding, conversion according to the second preset data encoding format, buffering the data packets to be received in the multiplexed FIFO, reading the data packets to be received from the multiplexed FIFO and calculating the checksum, and saving the read data packets to be received into the receive message register. This ensures that the clock that drives the data packets to be sent and saves them in the send buffer control module is the same as the clock that drives the data packets to be received and saves them in the receive buffer control module. Therefore, there is no need to consider cross-clock domain processing during data transmission within the receive buffer control module.

[0032] Based on the foregoing embodiments, the bit width of the multiplexed FIFO is the maximum value between the data bit width allowed to be converted by the first preset data encoding format and the data bit width allowed to be converted by the second preset data encoding format. It is compatible with the data bit width of the symbol code output by the transmit buffer control module according to the first preset data encoding format and the data bit width of the data packet to be received output by the receive buffer control module according to the second preset data encoding format. The bit width of the multiplexed FIFO is the maximum bit width capable of reading and writing data.

[0033] The depth of the multiplexing FIFO is the maximum of the data size of the symbol codes converted by the transmit buffer control module (e.g., how many 5-bit symbol codes) and the data size of the data packets to be received converted by the receive buffer control module (e.g., how many 4-bit data codes). It should be noted that the product of the data bit width allowed by the first preset data encoding format and the data size of the symbol codes converted by the transmit buffer control module is equal to the data length of the symbol codes converted by the transmit buffer control module; similarly, the product of the data bit width allowed by the second preset data encoding format and the data size of the data packets to be received converted by the receive buffer control module is equal to the data length of the data packets to be received converted by the receive buffer control module. The product of the depth of the multiplexing FIFO and the bit width of the multiplexing FIFO is greater than the data length of the symbol codes converted by the transmit buffer control module, and also greater than the data length of the data packets to be received converted by the receive buffer control module. The product of the depth of the multiplexed FIFO and the bit width of the multiplexed FIFO is used as the data length of the multiplexed FIFO.

[0034] Therefore, the multiplexed FIFO can accommodate all symbol codes converted and output by the transmit buffer control module according to the first preset data encoding format, and can also accommodate all data in the data packets to be received converted and output by the receive buffer control module according to the second preset data encoding format. This ensures compatibility with the maximum data bit width and maximum data length in the data transmitted between the receive buffer control module and the multiplexed FIFO, as well as the data transmitted between the transmit buffer control module and the multiplexed FIFO. Even if the bit width of the multiplexed FIFO is slightly larger than the maximum data bit width and / or its data length is slightly larger than the maximum data length, it will not affect its use, providing a memory parameter basis for the multiplexed FIFO. Thus, it is not necessary to design a FIFO with a depth equal to the amount of data of the converted symbol codes in the transmit buffer control module and a FIFO with a depth equal to the amount of data contained in one frame of data packets to be received in the receive buffer control module, thereby achieving area optimization.

[0035] As one example, combined with Figure 2 It can be seen that the transmit buffer control module includes a transmit message register and a first right shift register, with the output of the transmit message register connected to the input of the first right shift register; wherein, the message data to be transmitted includes a message header and a data code. The transmit message register is used to sequentially store the message header and data code in the message data to be transmitted, as illustrated below. Figure 2As shown, the data width of the sending message register is 32 bits, and the storage depth is 8. One frame of message content is stored in eight 32-bit memory spaces. The sending message register sequentially stores a 16-bit message header (txheader), and 32-bit data codes (TXOBJ1, TXOBJ2, TXOBJ3, TXOBJ4, TXOBJ5, TXOBJ6, and TXOBJ7). Upon receiving a send request, it continuously transmits one unit of data width to the first right shift register multiple times. Each transmission of one unit of data width fills the first right shift register, continuing until the message header and data codes in the message to be sent are transmitted. This eliminates the need to concatenate adjacent transmissions into a larger data width before transmission, facilitating subsequent grouping and conversion of each unit of data width according to the first preset data encoding format.

[0036] In specific implementation, the message data to be sent includes one message header and m data codes. The order in which the low-bit data to the high-bit data in the same frame of message data is stored in the sending message register can be from right to left. Schematic, the preferred unit transmission width is 16 bits, and m=7. In the sending message register, the first row of storage addresses stores the 16-bit message header (txheader); starting from the second row of storage addresses, seven consecutive rows store 32-bit data codes TXOBJ1, TXOBJ2, TXOBJ3, TXOBJ4, TXOBJ5, TXOBJ6, and TXOBJ7, respectively. Each row of storage addresses stores one data code twice the unit transmission width from right to left, ensuring that the low-bit data is input to the first right shift register before the high-bit data, thus ensuring that the message header is input to the first right shift register before the data codes.

[0037] It should be noted that the data bit width of the data code is equal to twice the data bit width of the message header, and the data bit width of the first right shift register is equal to the data bit width of the message header; wherein, the data bit width of the message header is the unit transmission bit width; m is an integer greater than or equal to 0; the sum of the data length of one message header and the data length of m data codes is considered to be equal to the data length of the message data to be sent; according to the extended message application scenarios of the USB PD protocol and the actual software application requirements, the data length of the message data to be sent is controlled within 30 bytes, then when the unit transmission bit width is equal to 16 bits, m is less than or equal to the value 7.

[0038] The first right shift register is used to input data of one unit transmission bit width at a time. Specifically, starting from the message header of the data packet to be received, data of one unit transmission bit width is input one at a time in ascending order of low bits. The first right shift register is filled by inputting one unit transmission bit width of data each time, and then the register waits to be sent out in batches, thus realizing the input of the message data to be sent unit by unit transmission bit width. (Illustratively, as shown...) Figure 2 As shown, the first right shift register is a 16-bit register reg. The first right shift register sequentially inputs / reads 16-bit message header txheader, two 16-bit data arranged in data code TXOBJ1, two 16-bit data arranged in data code TXOBJ2, two 16-bit data arranged in data code TXOBJ3, two 16-bit data arranged in data code TXOBJ4, two 16-bit data arranged in data code TXOBJ5, two 16-bit data arranged in data code TXOBJ6, and two 16-bit data arranged in data code TXOBJ7 from the transmit message register. This process continues until the length of the data transmitted by the first right shift register reaches the sum of 2*m+1 units of transmission width, thus completing the shift transmission of the message data to be transmitted. The number of transmissions is equal to 2*m+1 times. Thus, the first right shift register is used to transmit the message header and m data codes arranged in an ordered manner in a frame of the message data to be sent in batches, so as to facilitate subsequent division into integer groups and grouping and conversion according to the first preset data encoding format.

[0039] Based on the above embodiments, such as Figure 2 As shown, the transmit buffer control module further includes a first 4b to 5b converter; the output of the first right shift register is connected to the input of the first 4b to 5b converter; the output of the first 4b to 5b converter is connected to the input of the multiplexed FIFO; wherein, the first right shift register receives 1 unit of transmission bit width data from the transmit message register each time, and the first 4b to 5b converter extracts 4 bits of data from the first right shift register each time for conversion.

[0040] The first right shift register is used to output one unit of data width to the first 4b to 5b module in batches whenever one unit of data width is input. Specifically, the first right shift register outputs 4 bits of data to the first 4b to 5b module each time. Figure 2As shown, for each unit of data transmitted from the transmit message register, the first right shift register transmits data to the first 4b to 5b module in batches from the lower 4 bits [3:0] to the higher bits, transmitting 4 bits of data each time until bits [15:12] are transmitted. This triggers the first 4b to 5b module to convert each 4-bit data transmission into a 5-bit symbol code according to the first preset data encoding format. This determines that the first preset data encoding format is 4b5b encoding. 4b5b encoding is a line encoding method used to encode 4-bit data into a 5-bit symbol code to ensure DC balance and clock recovery on the transmission line.

[0041] The first 4b to 5b conversion module is used to convert the 4-bit data output from the first right shift register into a 5-bit symbol code according to the first preset data encoding format, and input the converted 5-bit symbol code into the multiplexing FIFO until the length of the data input to the multiplexing FIFO reaches the product of the ratio of the sum of 2*m+1 units of transmission bit width and the value 4 and the value 5, and then determines to buffer the symbol code corresponding to the message data to be sent in the multiplexing FIFO. Essentially, during the continuous input of each bit of the message data to be sent from the first right shift register, the input data is grouped into 4-bit segments and converted according to a first preset data encoding format. Schematic, the first 4b to 5b module groups the first unit transmission width of data into bits [3:0], [7:4], [11:8], and [15:12] sequentially. The first 4b to 5b module then groups the second unit transmission width of data into bits [19:16], [23:20], [27:24], and [31:28] sequentially. The first 4b to 5b module then converts each group of data into a 5-bit symbol code according to the first preset data encoding format and inputs the converted 5-bit symbol code into the multiplexed FIFO. At this point, the multiplexed FIFO is required to store data with a bit width of... 5 bits of data; until the data length of the symbol code input to the multiplexed FIFO reaches the product of the ratio of the sum of 2*m+1 units of transmission bit width and the value 4 and the value 5, it is determined that the symbol code corresponding to the message data to be sent will be buffered in the multiplexed FIFO, that is, the symbol code corresponding to the message data to be sent will be input into the multiplexed FIFO. If the input bit data is grouped into 5-bit groups, the number of groups is the ratio of the sum of 2*m+1 units of transmission bit width and the value 4, which is also equal to the total number of times the symbol code corresponding to the message data to be sent is continuously input into the multiplexed FIFO. Thus, it is determined that the data length of the multiplexed FIFO is greater than or equal to the product of the ratio of the sum of 2*m+1 units of transmission bit width and the value 4 and the value 5, the bit width of the multiplexed FIFO is greater than or equal to 5 bits, and the depth of the multiplexed FIFO is greater than or equal to the ratio of the sum of 2*m+1 units of transmission bit width and the value 4.

[0042] The symbol code corresponding to the message data to be sent includes a symbol code corresponding to one message header and a symbol code corresponding to m data codes; the data bit width of a single symbol code is equal to 5 bits; the unit transmission bit width is an integer multiple of 4. Preferably, the unit transmission bit width is 16 bits, and m equals 7, so that the message data to be sent includes one message header and 7 data codes, thus constituting... Figure 2The parameter below the multiplexed FIFO is 5*68bit, which is the register reg data length. When the data length input to the multiplexed FIFO reaches the product of the ratio of the sum of 2*m+1 units of transmission bit width and the value 4 and the value 5, the data length input to the multiplexed FIFO is (16+2*7*16) / 4*5bit=5*60bit. At this time, the depth of the multiplexed FIFO is required to reach 60, so that it can be stored by the multiplexed FIFO.

[0043] In summary, in this embodiment, the first 4b to 5b converter groups the message header and data code transmitted from the first right shift register according to the number of bits required to be converted in the first preset data encoding format, then converts each group into a symbol code that can be converted into the first preset data encoding format, and then passes it to the multiplexed FIFO for buffering, thereby realizing the batch transmission, group conversion and buffering of the message data to be sent.

[0044] Based on the above embodiments, for processing the checksum in the data packet to be received, the sending buffer control module further includes a first CRC check module and a second 4b-to-5b conversion module; the output of the first right shift register is connected to the input of the first CRC check module, and the output of the first CRC check module is connected to the input of the second 4b-to-5b conversion module. The first right shift register is used to shift and output each bit of the message data to be sent to the first CRC check module. Specifically, starting from the message header of the data packet to be received, it outputs 1 bit of data to the first CRC check module each time in the order of low bits to high bits until all the message data to be sent is output to the first CRC check module; schematically, as shown... Figure 2 As shown, for a unit transmission bit width of data transmitted from the transmit message register, the first right shift register transmits data to the first CRC check module from the least significant bit bit[0] to the most significant bit, transmitting 1 bit of data to the first CRC check module each time.

[0045] The first CRC check module is used to process the message data to be sent according to the CRC check algorithm and calculate the check code, preferably the CRC check code; the first CRC check module performs cyclic redundancy check on the message data to be sent, including adding multiple redundant bits to the message data to be sent and calculating the remainder by taking the remainder, which is used as the check code.

[0046] Combination Figure 2It can be seen that the first CRC check module is used to output 4 bits of the check code to the second 4b to 5b module each time, starting from the highest 4 bits of the calculated check code data crc[31:28] and following the order of high bits to low bits. This realizes that the data to be encoded and converted is output to the second 4b to 5b module in units of 4 bits, triggering the second 4b to 5b module to convert the input 4 bits of data into 5 bits of symbol code according to the first preset data encoding format.

[0047] The second 4b-to-5b module is used to convert each input 4-bit data into a 5-bit symbol code according to the first preset data encoding format. This is equivalent to first grouping the input bit data into 4-bit groups and then converting each group into a symbol code. The converted symbol codes are not cached in the multiplexing FIFO, but are directly processed by BMC encoding until the checksum is transmitted. Therefore, in this embodiment, the checksum is calculated first, and then encoded and converted to a symbol code that can be converted according to the first preset data encoding format, but it is not cached in the multiplexing FIFO.

[0048] Based on the above embodiments, the transmit buffer control module further includes a BMC encoder, such as... Figure 2 As shown, the input terminals of the BMC encoder are connected to the output terminals of the multiplexed FIFO and the second 4b-to-5b module, respectively. The multiplexed FIFO is used to output the buffered symbol codes to the BMC encoder. The second 4b-to-5b module is used to output the converted symbol codes to the BMC encoder, which are essentially equivalent to the symbol codes corresponding to the check codes. The symbol codes output by the multiplexed FIFO and the symbol codes output by the second 4b-to-5b module can be concatenated to form... Figure 2 The data packet Bdata to be encoded shown is equivalent to the combination of the symbol code corresponding to the message data to be sent and the symbol code corresponding to the check code, and is used to output it to the BMC encoder in an orderly manner.

[0049] The BMC encoder is used to first input the symbol code buffered in the multiplexed FIFO, and then input the symbol code converted by the second 4b to 5b module. The BMC encoder sequentially performs BMC encoding on the input symbol codes to form an encoding result, and then outputs the encoding result CC_out to the CC line. This appends the symbol code corresponding to the checksum to the symbol code corresponding to the message data to be sent, and sends it sequentially to the CC line. Generally, the encoding result corresponding to the symbol code buffered in the multiplexed FIFO is first sent to the CC line, and then the encoding result corresponding to the symbol code converted by the second 4b to 5b module is sent to the CC line. The CC line transmits the encoding results corresponding to the message header and data code in the message data to be sent first, and then transmits the encoding result corresponding to the checksum. The encoding result corresponding to the checksum (i.e., the symbol code converted by the second 4b to 5b module and its corresponding encoding result) does not need to be buffered in the multiplexed FIFO in advance; it only needs to wait for the encoding result corresponding to the symbol code buffered in the multiplexed FIFO to be sent before sending the encoding result corresponding to the checksum.

[0050] It should be noted that BMC encoding is a physical layer operation, and the encoded data is transmitted via the CC line. The BMC encoding rule is a version of Manchester encoding, and the corresponding symbol code is set to logic level 0 and logic level 1 according to the pulse width; BMC decoding, according to the BMC encoding rule, restores the corresponding symbol code from the set logic level 0 and logic level 1.

[0051] As one embodiment, the receive buffer control module includes a BMC decoder; the BMC decoder is used to read the encoding result bit by bit from the CC line, starting from the least significant bit. Specifically, it reads the encoding result corresponding to the symbol code of the message data to be transmitted from the CC line in ascending order of low bits, and then reads the encoding result corresponding to the symbol code of the checksum from the CC line. The BMC decoder's read operation can be performed after an external receive request is initiated.

[0052] The BMC decoder is used to perform BMC decoding on the encoding result, that is, to perform BMC decoding on the symbol codes read sequentially, thereby obtaining the symbol codes corresponding to the message data to be sent and the symbol codes corresponding to the check codes, such as... Figure 2 The symbol code rxdata is shown; specifically, when the BMC decoder performs BMC decoding under the drive of the first clock Osclk, it will decode the symbol code corresponding to the message data to be sent and the symbol code corresponding to the check code by restoring the clock and locking it to the frame encoding result sent by the transmission buffer control module, and specifically restore 1 message header, m data codes and 1 check code.

[0053] It should be noted that BMC encoding, or Biphasic Marking, is a physical layer signaling scheme used for transmitting USB power transmission messages. This encoding assumes a dedicated DC connection, identified as the CC line, for sending PD messages. BMC decoding is Biphasic Marking Decoding, and both Biphasic Marking and Biphasic Marking are versions of Manchester encoding (see [IEC 60958-1]). In BMC, there is a transition at the beginning of each bit time (UI), and a second transition occurs in the middle of the UI when a 1 is transmitted. Because Biphasic Marking inverts the level at the beginning of each bit cycle, logic can be represented by level changes within a bit cycle. If the level inverts in the middle of the bit cycle, it represents logic 1; otherwise, it represents logic 0. Therefore, by checking for level inversion within a bit cycle at the end of each bit, logic 0 and 1 can be distinguished. Based on this, Biphasic Marking Decoding can restore logic 0 and 1 to the cases where there is no level inversion within a bit cycle and the cases where there is a level inversion within a bit cycle, respectively.

[0054] Based on the above embodiments, the receive buffer control module further includes a left shift register, with the output of the BMC decoder connected to the input of the left shift register; the BMC decoder is used to sequentially output the symbol code corresponding to the message data to be sent and the symbol code corresponding to the check code to the left shift register; the left shift register is used to serially transmit each bit of the symbol code corresponding to the message data to be sent and the symbol code corresponding to the check code output by the BMC decoder; wherein, the data bit width of the left shift register is equal to the product of the ratio of the unit transmission bit width to the value 4 and the value 5. Each time a symbol code the width of one left shift register is transmitted, the serially input symbol code fills the left shift register. Then, when a new bit of data is serially input into the left shift register, the left shift register serially outputs the oldest bit of data stored internally. This transmission continues, with each serial input of a symbol code the width of one left shift register's data. This allows the left shift register to serially output a symbol code the width of one left shift register's data, while the BMC decoder continuously outputs the same symbol code to the left shift register. This enables the left shift register to serially transmit each bit of the symbol code corresponding to the message data to be sent and the symbol code corresponding to the checksum output by the BMC decoder. Therefore, compared to the aforementioned first right shift register, this embodiment uses a left shift register for serial transmission of the symbol code corresponding to the message data to be sent and the symbol code corresponding to the checksum, facilitating subsequent bit-by-bit reading and encoding conversion.

[0055] Based on the second preset data encoding format, the data bit width of the left shift register is equal to the product of the ratio of the unit transmission bit width to the value 4 and the value 5. Preferably, as shown below... Figure 2 As shown, the unit transmission bit width is 16 bits, and the data bit width of the left shift register is 20 bits, 20 bits = 16 bits / 4 * 5. The 20-bit left shift register (reg) completes the serial transmission of the symbol code corresponding to the message data to be sent and the symbol code corresponding to the checksum when the left shift register transmits (1 + 2 * m + 2) / 4 * 5 units of transmission bit width. It should be noted that, since the message data to be sent includes one message header and m data codes, and the data bit width of the data codes is twice the data bit width of the message header, and the data bit width of the message header is a unit transmission bit width, and the data bit width of the check code is twice the unit transmission bit width, the sum of the data length of the symbol code corresponding to the message header with a transmission bit width of 1 unit, the data length of the symbol code corresponding to the data codes with a transmission bit width of 2*m units, and the data length of the symbol code corresponding to the check code with a transmission bit width of 2 units is (1+2*m+2) / 4*5 units of transmission bit width, which is equal to the sum of the data lengths of the symbol code corresponding to the message data to be sent and the symbol code corresponding to the check code.

[0056] Based on the above embodiments, the receive buffer control module further includes a 5b to 4b conversion module; such as Figure 2 As shown, the output of the left shift register is connected to the input of the 5b to 4b module; the output of the 5b to 4b module is connected to the input of the multiplexed FIFO. Specifically, the left shift register receives a symbol code with a data width of one left shift register serially from the BMC decoder each time. The 5b to 4b module extracts 5 bits of the symbol code from the left shift register each time for conversion, and outputs 4 bits of data to the multiplexed FIFO each time.

[0057] In one hardware circuit implementation, the output terminals of the first 4b-to-5b module and the 5b-to-4b module in the transmit buffer control module are respectively connected to the two input terminals of a multiplexer, and the output terminal of the multiplexer is connected to the input terminal of the multiplexed FIFO. The multiplexer selects the symbol code converted and output by the first 4b-to-5b module to the multiplexed FIFO, while simultaneously prohibiting the 5b-to-4b module from converting and outputting data to the multiplexed FIFO; or, the multiplexer selects the 5b-to-4b module to convert and output data to the multiplexed FIFO, while simultaneously prohibiting the first 4b-to-5b module from converting and outputting symbol code to the multiplexed FIFO.

[0058] A left shift register is used to output a sign code of the same data bit width to the 5b-to-4b converter in batches, each time a sign code of the same data bit width is input. The left shift register outputs a 5-bit sign code to the 5b-to-4b converter each time; the data bit width of the sign bit can be considered as 5 bits. Figure 2 As shown, after each 20-bit symbol code is input, the left shift register is filled and begins to output the symbol code to the 5b to 4b module in batches. The left shift register can be selected to start from the high 5 bits [19:15] and transmit 4 bits of the symbol bit to the 5b to 4b module from high to low bits each time, triggering the 5b to 4b module to convert the input 5-bit symbol code into 4 bits of data according to the second preset data encoding format, until the low 5 bits [4:0] are transmitted. This determines that the aforementioned second preset data encoding format is 5b4b encoding. 5b4b encoding is also a line encoding method used to restore the 5-bit symbol code to 4 bits of data.

[0059] The 5b-to-4b module is used to convert the 5-bit symbol code output from the left shift register into 4-bit data according to a second preset data encoding format whenever a 5-bit symbol code is obtained from the left shift register. The converted 4-bit data is then input into the multiplexed FIFO until the data length input to the multiplexed FIFO reaches the sum of 2*m+3 units of transmission bit width. At this point, the module determines to buffer the data packet to be received into the multiplexed FIFO. Specifically, during the continuous transmission of symbol codes from the left shift register, the 5b-to-4b module groups the symbol codes transmitted from the left shift register into 5-bit groups. Then, according to the second preset data encoding format, each group of symbol codes is converted into 4-bit data corresponding to the symbol code of the message data to be sent and the symbol code of the checksum. The 4-bit data converted from each group of symbol codes is then shifted and input into the multiplexed FIFO. This requires the multiplexed FIFO to be able to store data with a bit width of 4 bits. Figure 2 The multiplexing FIFO shown has a bit width of 5 bits, which meets the bit width requirement. The data length input to the multiplexing FIFO by the 5b-to-4b converter reaches the sum of 2*m+3 units of transmission bit width. At this point, it is determined that the data packet to be received has been buffered in the multiplexing FIFO. Therefore, the data length of the multiplexing FIFO is greater than or equal to the sum of 2*m+3 units of transmission bit width, the bit width of the multiplexing FIFO is greater than or equal to 4 bits, and the depth of the multiplexing FIFO is greater than or equal to the ratio of the sum of 2*m+3 units of transmission bit width to the value 4.

[0060] It should be noted that the data packet to be received includes one message header, m data codes, and one checksum; the data bit width of the checksum is equal to twice the unit transmission bit width. Preferably, the unit transmission bit width is 16 bits, and m equals the value 7, so that one data packet to be received includes one message header, seven data codes, and one checksum; when the data length of the symbol code input to the multiplexed FIFO reaches the sum of 2*m + 3 unit transmission bit widths, the sum of 2*m + 3 unit transmission bit widths = (2*7 + 3) * 16 bits = (2*7 * 4 + 3 * 4) * 4 bits = (56 + 12) * 4 = 68 * 4 bits, which is less than 5 * 68 bits, so a FIFO with a data bit width of 4 bits and a depth of 68 can be constructed. On the other hand, during the stage of the transmit buffer control module reusing FIFO buffer data, when the data length of the input data of the multiplexed FIFO reaches the product of the ratio of the sum of 2*m+1 units of transmission bit width and the value 4 and the value 5, the data length of the input data of the multiplexed FIFO = (16+2*7*16) / 4*5bit = 5*60bit. A FIFO with a data bit width of 5 bits and a depth of 60 can be constructed. Then, by comparing the two FIFOs, it can be determined that the maximum data bit width is 5 bits and the maximum depth is 68. Therefore, the bit width of the multiplexed FIFO is set to 5 bits and the depth of the multiplexed FIFO is set to 68. This realizes the multiplexing of a 5*60bit FIFO and a 4*68bit FIFO into a FIFO with a data bit width of 5 bits and a depth of 68, which is shared by the receive buffer control module and the transmit buffer control module. By reusing the existing FIFO, the latency in the data transmission path can be reduced, the data flow management can be better optimized, the data transmission efficiency can be improved, and the response speed of the transceiver system can be improved.

[0061] Based on the above embodiments, such as Figure 2As shown, the receive buffer control module further includes a second CRC check module, a receive message register, and a second right shift register; the output of the second right shift register is connected to the input of the receive message register; the output of the multiplexed FIFO is connected to the input of the second right shift register and the input of the second CRC check module, respectively; in one hardware circuit implementation, one input of the multiplexer is connected to the input of the second right shift register in the receive buffer control module, the other input of the multiplexer is connected to the input of the BMC encoder in the transmit buffer control module, and the output of the multiplexer is connected to the data output of the multiplexed FIFO. When the multiplexer selects the input of the BMC encoder to be connected to the data output of the multiplexed FIFO, the multiplexed FIFO outputs the corresponding symbol code to the BMC encoder for BMC encoding; or when the multiplexer selects the input of the second right shift register to be connected to the data output of the multiplexed FIFO, the multiplexed FIFO outputs the data packets to be received to the second right shift register in batches.

[0062] The multiplexed FIFO is used to output the data packet to be received to the second CRC check module before outputting the data packet to be received to the second right shift register. It can be shifted and transmitted bit by bit from the highest bit to the second CRC check module to trigger the second CRC check module to perform CRC check on the data packet to be received.

[0063] The second CRC check module is used to calculate the current check code according to the rules of the first CRC check module, and then determine whether the current check code is the same as the check code calculated by the first CRC check module. The rules of the first CRC check module for calculating the check code are the check code generation algorithm in the cyclic redundancy check technique that is familiar to those skilled in the art. Generally, the data read from the multiplexed FIFO by the second CRC check module will be CRC checked frame by frame, and each received frame will be divided.

[0064] The second CRC check module is used to determine that when the current checksum is the same as the checksum calculated by the first CRC check module, it verifies that there is no error in the data packet to be received, that is, it determines that the calculated result and the received checksum are consistent, indicating that the data verification is correct, and this frame of data packet to be received can be used. Therefore, when the second CRC check module verifies that there is no error in the data packet to be received, it triggers the multiplexing FIFO to output the data packet to be received to the second right shift register. The second right shift register generally waits for the data to complete the CRC check and the check is successful before reading data from the multiplexing FIFO. Since the validity of the data buffered in the multiplexing FIFO can be determined based on the CRC check result, there is no need to use other FIFOs to buffer and verify the data.

[0065] The second right shift register is used to transmit data to the receive message register one unit at a time, starting from the message header of the input message data, in ascending order of low bits to high bits. Each time, one unit of data is transmitted in parallel to the receive message register, filling it completely each time. This continues until the message header and data codes of the received data packet are transmitted. When the length of the data input to the receive message register reaches the sum of 2*m+1 units of transmission width, the message data to be sent is stored in the receive message register. The 2*m+1 units of transmission width data consists of one message header and m data codes. Compared to existing receive buffering methods, this embodiment does not use a FIFO to buffer and verify the data packets to be transmitted during the data transmission process from the second right shift register to the receive message register, thus avoiding affecting the receive buffer control module's reception of the next frame of data packets and reducing latency and power consumption in the data transmission path.

[0066] Indicatively, such as Figure 2As shown, the data width of the receive message register is 32 bits, and the storage depth is 8. The message data to be sent is stored in 8 memory spaces, each 32 bits wide. During the process of the second right shift register transmitting data to the receive message register bit by bit, starting from the message header of the message data to be sent, the receive message register sequentially stores a 16-bit message header (Rxheader), 32-bit data codes (RXOBJ1, RXOBJ2, RXOBJ3, RXOBJ4, RXOBJ5, and 32-bit data...). The first row of the received message register stores the 16-bit message header Rxheader at the storage address. Starting from the storage address of the second row, seven consecutive rows store the 32-bit data codes RXOBJ1, RXOBJ2, RXOBJ3, RXOBJ4, RXOBJ5, RXOBJ6, and RXOBJ7, with each row storing data of 2 units of transmission width at the storage address.

[0067] The second CRC check module is used to determine if an error has occurred in the data packet to be received when the current checksum is different from the checksum calculated by the first CRC check module. The data packet buffered in the multiplexing FIFO needs to be discarded. The second CRC check module also triggers the multiplexing FIFO to clear its buffered data packets when an error is detected. Clearing the data buffered in the multiplexing FIFO frees up memory space for the transmission buffer control module to buffer the next frame of data packets, thus preventing any impact on the reception of the next frame.

[0068] This application also discloses a chip, which includes the transceiver system disclosed in the aforementioned embodiments. It should be noted that PD (power delivery) is a fast charging technology, a charging method that can bring a battery to or near full charge within 1-5 hours. It is commonly used for traction batteries when they need to be fully charged in a short time. A PD chip is a chip with fast charging functionality, generally used as a chip module in a power adapter. The chip disclosed in this application can be applied as a PD chip.

[0069] Furthermore, the power adapter adjusts the output voltage and current in real time according to the mobile terminal's requests, and adjusts and controls various parts of the system. Therefore, the stability and reliability of communication between the mobile terminal and the power adapter directly affect the stability and safety of the charging process. Thus, it is necessary to establish a communication protocol between the mobile terminal and the power adapter, which may be verified by interfacing two PD chips. The CC (Channel Configuration) line is used to configure the power supply to the two connected devices. USB PD uses BMC (Biphase Marking Code) for transmission. This application can set the transmit buffer control module as a PD chip located within the power supply device (e.g., the power adapter), and the receive buffer control module as a PD chip located within the powered device. The two PD chips establish communication through the CC (Channel Configuration) line and share the same multiplexed FIFO, reducing the design area of ​​the PD chip's buffer memory.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them; although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications can still be made to the specific implementation of the present invention or equivalent substitutions can be made to some technical features without departing from the spirit of the technical solutions of the present invention, and all such modifications and substitutions should be covered within the scope of the technical solutions claimed in the present invention.

Claims

1. A transceiver system with a multiplexed FIFO, characterized in that, The transceiver system includes a multiplexed FIFO, a transmit buffer control module, and a receive buffer control module. Both the transmit buffer control module and the receive buffer control module are connected to the multiplexed FIFO and are connected via a CC line. The transmit buffer control module is used to control the data to be transmitted to be converted into the symbol code corresponding to the data to be transmitted according to the first preset data encoding format, and to cache the symbol code corresponding to the data to be transmitted in the multiplexed FIFO buffer; The transmit buffer control module is used to calculate the check code using the message data to be transmitted, then control the check code to be converted into the symbol code corresponding to the check code according to the first preset data encoding format, then control the symbol code buffered in the multiplexed FIFO and the symbol code corresponding to the check code to perform BMC encoding to form the encoding result, and then send the encoding result to the CC line. The receive buffer control module is used to receive the encoding result from the CC line and perform BMC decoding to obtain the symbol code corresponding to the message data to be sent and the symbol code corresponding to the check code. The receive buffer control module is used to convert the symbol code corresponding to the message data to be sent and the symbol code corresponding to the check code into a data packet to be received according to the second preset data encoding format, and to buffer the data packet to be received in the multiplexed FIFO; wherein, the data packet to be received is composed of the message data to be sent and the check code; The receive buffer control module is used to read the data packet to be received from the multiplexed FIFO and verify it according to the check code in the data packet to be received. When it is found that there is no error in the data packet to be received, the message data to be sent in the read data packet to be received is saved outside the multiplexed FIFO, so that the multiplexed FIFO can free up memory space for the send buffer control module to cache new data.

2. The transceiver system according to claim 1, characterized in that, The transmit buffer control module and the receive buffer control module do not access the multiplexed FIFO at the same time, so that when the transmit buffer control module caches data in the multiplexed FIFO, the receive buffer control module does not cache or read data from the multiplexed FIFO.

3. The transceiver system according to claim 2, characterized in that, Whenever the transmit buffer control module finishes caching the symbol code corresponding to the message data to be transmitted in the multiplexing FIFO, or whenever the transmit buffer control module finishes reading the symbol code corresponding to the message data to be transmitted from the multiplexing FIFO, the transmit buffer control module configures its access address to the multiplexing FIFO to the starting address of the multiplexing FIFO or clears its access address to the multiplexing FIFO to zero. Whenever the receive buffer control module finishes buffering the data packet to be received in the multiplexing FIFO, or whenever the receive buffer control module finishes reading the data packet to be received from the multiplexing FIFO, the receive buffer control module configures its access address to the multiplexing FIFO to the starting address of the multiplexing FIFO or clears its access address to the multiplexing FIFO to zero.

4. The transceiver system according to claim 1, characterized in that, Before the transmit buffer control module controls the conversion of the message data to be transmitted into the symbol code corresponding to the message data according to the first preset data encoding format, the clock that drives the message data to be transmitted to be stored in the transmit buffer control module is the first clock; the clock that drives the transmit buffer control module to control the conversion of the message data to be transmitted according to the first preset data encoding format, cache the symbol code corresponding to the message data to be transmitted in the multiplexed FIFO, calculate the check code, and perform BMC encoding are all the second clock. When the multiplexed FIFO caches the symbol code corresponding to the message data to be transmitted, it is configured with a write enable signal that has undergone cross-clock pausing processing to reduce the use of FIFO to cache cross-clock data. The clock that drives the receive buffer control module is a first clock, such that the clock that drives the data to be sent and stored in the send buffer control module is the same as the clock that drives the data to be received and stored in the receive buffer control module.

5. The transceiver system according to claim 1, characterized in that, The bit width of the multiplexed FIFO is the maximum value between the data bit width allowed to be converted by the first preset data encoding format and the data bit width allowed to be converted by the second preset data encoding format; The depth of the multiplexing FIFO is the maximum value between the amount of symbol code data converted by the transmit buffer control module and the amount of data contained in the data packet to be received converted by the receive buffer control module. Wherein, the product between the data bit width that the first preset data encoding format can be converted into and the data amount of the symbol code converted by the sending buffer control module is equal to the data length of the symbol code converted by the sending buffer control module; Wherein, the product between the data bit width allowed to be converted by the second preset data encoding format and the amount of data contained in the data packet to be received converted by the receiving buffer control module is equal to the data length of the data packet to be received converted by the receiving buffer control module.

6. The transceiver system according to claim 4, characterized in that, The transmit buffer control module includes a transmit message register and a first right shift register, with the output of the transmit message register connected to the input of the first right shift register; wherein, the message data to be transmitted includes a message header and a data code; The transmit message register is used to sequentially store the message header and data code in the message data to be transmitted. After receiving a transmit request, it continuously transmits data of 1 unit transmission bit width to the first right shift register multiple times until the message header and data code in the message data to be transmitted are completely transmitted. During the process of transmitting data from the transmit message register to the first right shift register, no FIFO is used to buffer the message data to be transmitted across clock cycles.

7. The transceiver system according to claim 6, characterized in that, The message data to be sent includes one message header and m data codes; wherein, the data bit width of the data code is equal to twice the data bit width of the message header, and the data bit width of the first right shift register is equal to the data bit width of the message header; the data bit width of the message header is a unit transmission bit width; m is an integer greater than or equal to 0, and m is less than or equal to the value 7; The first right shift register is used to input data with a transmission width of one unit at a time.

8. The transceiver system according to claim 7, characterized in that, The transmit buffer control module further includes a first 4b to 5b converter; the output of the first right shift register is connected to the input of the first 4b to 5b converter; the output of the first 4b to 5b converter is connected to the input of the multiplexed FIFO. The first right shift register is used to output one unit of data width to the first 4b to 5b module in batches whenever one unit of data width is input. The first right shift register outputs 4 bits of data to the first 4b to 5b module each time. The first 4b to 5b module is used to convert the 4-bit data output from the first right shift register into a 5-bit symbol code according to the first preset data encoding format, and input the converted 5-bit symbol code into the multiplexing FIFO until the data length of the symbol code input to the multiplexing FIFO reaches the product of the ratio of the sum of 2*m+1 units of transmission bit width and the value 4 and the value 5, and then determines to buffer the symbol code corresponding to the message data to be sent in the multiplexing FIFO. The symbol code corresponding to the message data to be sent includes the symbol code corresponding to one message header and the symbol code corresponding to m data codes; the unit transmission bit width is an integer multiple of 4.

9. The transceiver system according to claim 8, characterized in that, The transmit buffer control module further includes a first CRC check module and a second 4b to 5b converter module; the output of the first right shift register is connected to the input of the first CRC check module, and the output of the first CRC check module is connected to the input of the second 4b to 5b converter module. The first right shift register is used to shift and output the bits of the message data to be sent to the first CRC check module. The first CRC check module is used to process the message data to be sent according to the CRC check algorithm and calculate the check code; The first CRC check module is used to output 4 bits of the check code to the second 4b to 5b converter each time, starting from the highest 4 bits of the calculated check code and following the order from high bits to low bits, until the check code is completely output; wherein, the data bit width of the check code is equal to twice the unit transmission bit width; The second 4b to 5b module is used to convert each input 4-bit data into a 5-bit symbol code according to the first preset data encoding format, so as to convert the symbol code corresponding to the check code.

10. The transceiver system according to claim 9, characterized in that, The transmit buffer control module also includes a BMC encoder, the input of which is connected to the output of the multiplexed FIFO and the output of the second 4b to 5b module, respectively. The multiplexed FIFO is used to output the cached symbol codes to the BMC encoder; The second 4b to 5b module is used to output the converted symbol code to the BMC encoder; The BMC encoder is used to first input the symbol code of the multiplexed FIFO buffer, and then input the symbol code converted by the second 4b to 5b module; The BMC encoder is used to sequentially encode the input symbol codes to form an encoding result, and then output the encoding result to the CC line to append the symbol code corresponding to the check code to the symbol code corresponding to the message data to be sent, and send it to the CC line in sequence.

11. The transceiver system according to claim 7, characterized in that, The receive buffer control module includes a BMC decoder; The BMC decoder is used to read the encoded result bit by bit from the CC line, starting from the least significant bit. The BMC decoder is used to perform BMC decoding on the encoding result, thereby obtaining the symbol code corresponding to the message data to be sent and the symbol code corresponding to the check code.

12. The transceiver system according to claim 11, characterized in that, The receive buffer control module also includes a left shift register, and the output of the BMC decoder is connected to the input of the left shift register; The BMC decoder is used to sequentially output the symbol code corresponding to the message data to be sent and the symbol code corresponding to the check code to the left shift register; The left shift register is used for serial transmission of each bit in the symbol code corresponding to the message data to be transmitted and the symbol code corresponding to the check code output by the BMC decoder; wherein, the data bit width of the left shift register is equal to the product of the ratio of the unit transmission bit width to the value 4 and the value 5.

13. The transceiver system according to claim 12, characterized in that, The receive buffer control module also includes a 5b to 4b converter; The output of the left shift register is connected to the input of the 5b to 4b module; the output of the 5b to 4b module is connected to the input of the multiplexed FIFO. The left shift register is used to output the sign code of the left shift register in batches to the 5b to 4b module whenever a sign code of the data width of the left shift register is input. The 5b to 4b module is used to convert the 5-bit symbol code output from the left shift register into 4-bit data according to the second preset data encoding format whenever a 5-bit symbol code is obtained from the left shift register. The converted 4-bit data is then input into the multiplexed FIFO until the data length of the data input to the multiplexed FIFO reaches the sum of 2*m+3 units of transmission bit width. At this point, the module determines to buffer the data packet to be received in the multiplexed FIFO.

14. The transceiver system according to claim 13, characterized in that, The receive buffer control module further includes a second CRC check module, a receive message register, and a second right shift register; the output of the second right shift register is connected to the input of the receive message register; the output of the multiplexed FIFO is connected to the input of the second right shift register and the input of the second CRC check module, respectively. The multiplexed FIFO is used to output the data packet to be received to the second CRC check module before outputting the data packet to be received to the second right shift register; The second CRC check module is used to calculate the current check code according to the rules for calculating the check code by the first CRC check module, and then determine whether the current check code is the same as the check code calculated by the first CRC check module. The second CRC check module is used to determine that when the current check code is the same as the check code calculated by the first CRC check module, the data packet to be received is found to be without error. The second CRC check module is used to trigger the multiplexed FIFO to output the message data to be sent in the data packet to be received to the second right shift register when the data packet to be received is found to be error-free. The second right shift register is used to transmit data to the receive message register one unit at a time, starting from the message header of the input message data, in ascending order of low bits to high bits, until the data length of the input message register reaches the sum of 2*m+1 units of transmission width. At this point, the message data to be sent is stored in the receive message register. The data with a transmission width of 2*m+1 units consists of one message header and m data bits.

15. The transceiver system according to claim 14, characterized in that, The second CRC check module is used to detect an error in the data packet to be received when the current check code is different from the check code calculated by the first CRC check module. The second CRC check module is used to trigger the multiplexed FIFO to clear the buffered data packets when an error is detected in the data packet to be received.

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