Wafer bonding method

Abstract

This application provides a wafer bonding method, comprising providing a first wafer and a second wafer, each having a first surface. The first surfaces of the first wafer and the second wafer respectively include a first metal pad and a second metal pad with a pit structure. An anisotropic conductive adhesive layer is formed on the surfaces of the first metal pad and the second metal pad, and on the first surfaces of the first wafer and the second wafer. The anisotropic conductive adhesive layer includes conductive particles. The anisotropic conductive adhesive layer serves as a bonding layer to bond the first wafer and the second wafer, wherein the conductive particles fill the pit structure and connect the first metal pad and the second metal pad. This wafer bonding method can significantly improve bonding yield.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices and integrated circuits, and in particular to a wafer bonding method. Background Technology

[0002] With the continuous development of micro- and nanotechnology, the feature size of semiconductor devices is constantly shrinking, significantly improving the integration density of transistors in chips and chip performance. In recent years, chip feature sizes have approached the limits of Moore's Law. Therefore, scientists and practitioners are constantly exploring post-Moore's Law technologies to continue improving chip performance and functionality.

[0003] 3D integrated circuit (3DIC) technology has attracted significant attention in the industry. 3DIC can increase transistor density per unit area without increasing the difficulty of chip manufacturing. 3D stacking packaging technology can integrate different chips, including logic chips, memory chips, and RF chips, into a single system, greatly improving system integration and opening up broader development directions for semiconductor technology. However, how to better achieve wafer stacking and bonding, and improve bonding yield, remains a problem that urgently needs improvement. Summary of the Invention

[0004] The technical problem to be solved by this application is to provide a wafer bonding method that can significantly improve the bonding yield.

[0005] To address the aforementioned technical problems, this application provides a wafer bonding method, comprising: providing a first wafer and a second wafer including a first surface, wherein the first surface of the first wafer and the second wafer respectively include a first metal pad and a second metal pad having a pit structure; forming an anisotropic conductive adhesive layer on the surfaces of the first metal pad and the second metal pad and on the first surface of the first wafer and the second wafer, wherein the anisotropic conductive adhesive layer includes conductive particles; or, processing the surfaces of the first metal pad and the second metal pad to transform the pit structure into a raised structure, forming an ultraviolet curable layer or a thermosetting layer on the surfaces of the first metal pad and the second metal pad and on the first surface of the first wafer and the second wafer; using the anisotropic conductive adhesive layer as a bonding layer to bond the first wafer and the second wafer, wherein the conductive particles fill the pit structure and connect the first metal pad and the second metal pad; or using the ultraviolet curable layer or the thermosetting layer as a bonding layer to bond the first wafer and the second wafer, wherein the first metal pad and the second metal pad are connected.

[0006] In the embodiments of this application, the anisotropic conductive adhesive layer has unidirectional conductivity and also includes an adhesive film in which the conductive particles are dispersed.

[0007] In the embodiments of this application, the material of the adhesive film includes acrylate and / or polyurethane, and the material of the conductive particles includes copper or copper-silver-tin alloy.

[0008] In embodiments of this application, the process of bonding the first wafer and the second wafer using the anisotropic conductive adhesive layer as a bonding layer includes: aligning the first wafer and the second wafer to align the first metal pad and the second metal pad; pressing the first wafer and the second wafer together to fill the pit structure with the conductive particles and connect the first metal pad and the second metal pad; and performing ultraviolet curing or thermal curing.

[0009] In the embodiments of this application, the surfaces of the first metal pad and the second metal pad are etched with an acid solution to transform the pit structure into a raised structure. The acid solution includes hydrogen peroxide and copper sulfate, and the etching rate is 20 angstroms / second to 50 angstroms / second.

[0010] In embodiments of this application, the process of bonding the first wafer and the second wafer using the UV-curable layer or the thermosetting layer as the bonding layer includes: aligning the first wafer and the second wafer to align the first metal pad and the second metal pad; pressing the first wafer and the second wafer together to connect the raised structures of the first metal pad and the second metal pad; and performing UV curing or thermosetting.

[0011] In embodiments of this application, the wafer bonding method further includes: electrical testing; if electrical defects are confirmed, a laser lift-off process is used to remove the defective wafer from the first and second wafers. The laser lift-off process includes: placing the bonded wafer structure with the defective wafer on top and the qualified wafer on the bottom; using a laser with a wavelength of 308nm or 355nm to irradiate the defective wafer from above, causing the adhesiveness of the anisotropic conductive adhesive layer to fail, thereby peeling off the defective wafer and the qualified wafer.

[0012] In embodiments of this application, the wafer bonding method further includes: electrical testing; if electrical defects are confirmed, a laser lift-off process is used to remove the defective wafer from the first and second wafers. The laser lift-off process includes: placing the bonded wafer structure with the defective wafer on top and the qualified wafer on the bottom; using a laser with a wavelength of 308nm or 355nm to irradiate the defective wafer from above, causing the adhesiveness of the ultraviolet curing layer or thermal curing layer to fail, thereby peeling off the defective wafer and the qualified wafer.

[0013] In embodiments of this application, the wafer bonding method further includes: electrical testing, and when the electrical properties are confirmed to meet the standards, continuing to bond other wafers on the second wafer.

[0014] In an embodiment of this application, the process for forming the first metal pad includes: providing a first wafer, the first wafer including a first bare wafer and a first dielectric layer located on the surface of the first bare wafer, wherein a first conductive structure is formed in the first dielectric layer; forming a first metal pad in the first dielectric layer on the first conductive structure using a double damask process, wherein the first metal pad is connected to the first conductive structure; and etching the first dielectric layer to expose the surface and sidewalls of the first metal pad.

[0015] In an embodiment of this application, the double damask process includes: etching a first dielectric layer on the surface of the first conductive structure to form a first via; forming a first sacrificial layer in the first via, wherein the surface of the first sacrificial layer is lower than the top of the first via; etching a portion of the first dielectric layer on both sides of the first via and above the first sacrificial layer to form a first trench; etching the first sacrificial layer in the first via; forming a first metal material layer on the surface of the first dielectric layer and in the first via and the first trench; removing the first metal material layer on the surface of the first dielectric layer using a chemical mechanical polishing process; and forming a first conductive line and a first metal pad in the first via and the first trench, respectively.

[0016] In embodiments of this application, the first dielectric layer includes a silicon oxide layer and a silicon nitride layer sequentially stacked on the surface of the first bare wafer.

[0017] In embodiments of this application, the process for forming the second wafer includes: providing a stacked wafer, the stacked wafer including a stacked bare wafer having opposing first and second surfaces and a second dielectric layer located on the first surface of the stacked bare wafer, wherein a first portion of a second conductive interconnect layer is formed in the second dielectric layer and the stacked bare wafer; providing a carrier wafer, the carrier wafer including a carrier bare wafer and a third dielectric layer located on the carrier bare wafer; bonding the stacked wafer to the carrier wafer using the second dielectric layer and the third dielectric layer as bonding layers; thinning the stacked bare wafer to expose a first portion of the surface and a portion of the sidewalls of the second conductive interconnect layer; forming a fourth dielectric layer on the second surface of the stacked bare wafer and the first portion of the surface of the second conductive interconnect layer; and forming a second portion of the second conductive interconnect layer in the fourth dielectric layer on the first portion of the surface of the second conductive interconnect layer.

[0018] In embodiments of this application, the wafer bonding method further includes: forming a fifth dielectric layer on the surface of the fourth dielectric layer; forming a second metal pad in the fifth dielectric layer above the second portion of the second conductive interconnect layer; and removing the fifth dielectric layer on both sides of the second metal pad.

[0019] In embodiments of this application, the second dielectric layer includes a silicon oxide layer and a silicon nitride layer sequentially stacked on the surface of the stacked bare wafer.

[0020] In embodiments of this application, the material of the third dielectric layer includes silicon nitride.

[0021] In embodiments of this application, the fourth dielectric layer comprises a silicon nitride layer and a silicon oxide layer stacked sequentially.

[0022] Compared with the prior art, the wafer bonding method of this application has the following advantages:

[0023] The technical solution of this application forms an anisotropic conductive adhesive layer on the surfaces of the first and second metal pads and on the first surfaces of the first and second wafers. The anisotropic conductive adhesive layer includes conductive particles. After bonding, the conductive particles can fill the pit structure on the surfaces of the first and second metal pads and play the role of connecting the first and second metal pads. This solves the problem of poor contact of the metal pads after bonding caused by the pit structure on the surface of the metal pads in the prior art, and greatly improves the yield of the bonding process.

[0024] The anisotropic conductive adhesive layer can act as a buffer to improve the problem that occurs during fusion bonding, where hard contact between wafers causes premature closed-loop formation of the wafer, preventing gas from being properly vented and ultimately leading to the formation of bubbles at the boundary. At the same time, it can also leave a larger warpage window, improving the yield of the bonding process.

[0025] The technical solution of this application can also form an ultraviolet curable layer or a thermosetting layer on the surfaces of the first metal pad and the second metal pad, as well as on the first surface of the first wafer and the second wafer. The ultraviolet curable layer or thermosetting layer serves as a bonding adhesive layer. At the same time, the pit structure is processed to transform it into a raised structure. After pressing, the raised structures of the first metal pad and the second metal pad are connected, which solves the problem of poor contact of the metal pad after bonding caused by the pit structure on the surface of the metal pad in the prior art, and greatly improves the yield of the bonding process.

[0026] The UV-curable layer or thermal curable layer can act as a buffer to improve the problem that occurs during fusion bonding, where hard contact between wafers causes premature closed-loop formation of the wafer, preventing gas from being properly vented and ultimately leading to the formation of bubbles at the boundary. At the same time, it can also leave a larger warpage window to improve the yield of the bonding process.

[0027] The first and second wafers are bonded by a pressure bonding method, so the bonding process does not require high temperature. This not only reduces annealing time and the thermal budget of the bonding process, but also mitigates the irreversible performance impact of high temperature on devices in the stacked wafers.

[0028] This application's technical solution achieves bonding between wafers through a bonding adhesive layer, overcoming the problem of inconvenient peeling caused by rigid connections in existing technologies. Furthermore, after a defective wafer is discovered, this application's technical solution can smoothly peel it off using a laser lift-off method without damaging the stacked wafers. Attached Figure Description

[0029] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0030] Figure 1 This is a schematic flowchart of a wafer bonding method according to an embodiment of this application;

[0031] Figure 2 This is a schematic flowchart of the formation process of the first metal gasket according to an embodiment of this application;

[0032] Figures 3 to 8 This is a schematic diagram of the structural steps of the formation process of the first metal gasket in an embodiment of this application;

[0033] Figures 9 to 23 This is a schematic diagram of the structure of each step in the formation process of the second wafer according to an embodiment of this application;

[0034] Figures 24 to 26 This is a schematic diagram of the bonding operation in a wafer bonding method according to an embodiment of this application;

[0035] Figure 27 This is a schematic flowchart of another wafer bonding method according to an embodiment of this application;

[0036] Figures 28 to 32 This is a schematic diagram of the bonding operation in another wafer bonding method according to an embodiment of this application. Detailed Implementation

[0037] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0038] Existing wafer multilayer stacking bonding methods mostly employ fusion bonding and hybrid bonding. Both of these methods rely on van der Waals forces between SiO2 and SiN in the dielectric layer to enhance the bonding strength. Once bonding is complete, it is difficult to separate the two wafers effectively. The yield of 3D IC products is related to the number of stacked layers and the yield of each stacked wafer; the product yield is the product of the yield of each stacked wafer. If a defect occurs in any of the middle wafer layers, the entire stacking process may fail, and this process is irreversible. Furthermore, fusion bonding and hybrid bonding processes begin at the wafer center and proceed sequentially towards the wafer edge to complete the bonding. During the bonding process, the gas between the wafers is driven from the wafer center to the edge, and finally, when the wafer boundary contacts, the gas is expelled, and the bonding is successful. If the wafer boundary contacts prematurely, it will cause the wafer to form a closed loop prematurely, preventing the gas from escaping properly and ultimately forming bubbles at the boundary.

[0039] In view of this, the technical solution of this application provides a wafer bonding method that can effectively avoid poor contact of the metal pads during the metal bonding process caused by the pit structure on the surface of the metal pads, thereby improving the bonding yield. The bonding process of the first wafer and the second wafer does not require high temperature, reducing annealing time, which can reduce the thermal budget of the bonding process and also alleviate the irreversible impact of high temperature on the performance of devices in the stacked wafers. The bonding strength of the wafers is not enhanced by the van der Waals forces between SiO2 and SiN in the dielectric layer. When a defective wafer is found, it can be removed by laser lift-off without damaging the stacked wafers. When using anisotropic conductive adhesive layers, UV-curable layers, or thermosetting layers as bonding layers, the anisotropic conductive adhesive layers, UV-curable layers, or thermosetting layers can act as buffers to improve fusion. During the bonding process, the hard contact between wafers caused by wafer warpage leads to premature closed loop formation of the wafer, resulting in the inability of gas to be properly vented and ultimately forming bubbles at the boundary. At the same time, it can also leave a larger warpage window, improving the yield of the bonding process.

[0040] The wafer bonding method of this application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] refer to Figure 1 This application provides a wafer bonding method, including:

[0042] Step S100: Provide a first wafer and a second wafer including a first surface, wherein the first wafer and the second wafer respectively include a first metal pad and a second metal pad having a pit structure on their first surfaces;

[0043] Step S200: An anisotropic conductive adhesive layer is formed on the surfaces of the first metal pad and the second metal pad and on the first surfaces of the first wafer and the second wafer, wherein the anisotropic conductive adhesive layer includes conductive particles.

[0044] Step S300: Using the anisotropic conductive adhesive layer as a bonding layer, the first wafer and the second wafer are bonded together, and the conductive particles fill the pit structure and connect the first metal pad and the second metal pad.

[0045] refer to Figure 2 The forming process for the first metal gasket includes:

[0046] Step 111: Provide a first wafer, the first wafer including a first bare wafer and a first dielectric layer located on the surface of the first bare wafer, wherein a first conductive structure is formed in the first dielectric layer;

[0047] Step 112: A first metal pad is formed in the first dielectric layer on the first conductive structure using a double damask process, and the first metal pad is connected to the first conductive structure.

[0048] Step 113: Etch the first dielectric layer until the surface and sidewalls of the first metal pad are exposed.

[0049] Combination Figure 2 and Figure 3 A first wafer is provided. The first wafer includes a first bare wafer 100 and a first dielectric layer 110 located on the surface of the first bare wafer 100. The first bare wafer 100 may be a conventional silicon wafer. The first dielectric layer 110 may be a stacked structure, for example, the first dielectric layer 110 may be formed by alternating stacks of silicon oxide layers and silicon nitride layers, wherein the bottom layer and the top layer may be silicon oxide layers. The number of stacked silicon oxide layers and silicon nitride layers and the thickness of each layer are determined according to actual conditions. A first conductive structure 121 is formed in the first dielectric layer 110. In some embodiments, other conductive structures 122 may be formed in the first dielectric layer 110 as needed.

[0050] refer to Figures 4 to 7 The first metal pad 152 is formed using a double damask process, and the first metal pad 152 is connected to the first conductive structure 121.

[0051] refer to Figure 4 The first dielectric layer 110 on the surface of the first conductive structure 121 is etched to form a first via 131. The etching process can be photolithography. The first via 131 exposes the surface of the first conductive structure 121, and the width of the first via 131 can be determined according to actual conditions. In some embodiments, the width of the first via 131 is equal to the width of the first conductive structure 121. In another embodiment, the width of the first via 131 is greater than the width of the first conductive structure 121. In yet another embodiment, the width of the first via 131 is less than the width of the first conductive structure 121.

[0052] refer to Figure 5 A first sacrificial layer 140 is formed in the first via 131, and the surface of the first sacrificial layer 140 is lower than the top of the first via 131. The method of forming the first sacrificial layer 140 may include: depositing a first sacrificial material layer 141 on the surface of the first dielectric layer 110 and in the first via 131; etching back the first sacrificial material layer 141 to remove the first sacrificial material layer 141 from the surface of the first dielectric layer 110, and ensuring that the surface of the first sacrificial material layer 141 in the first via 131 is lower than the top of the first via 131. The height difference between the surface of the first sacrificial layer 140 and the top of the first via 131 determines the thickness of the first metal pad.

[0053] refer to Figure 6 The first dielectric layer 110 on both sides of the first via 131 and above the first sacrificial layer 140 is etched to form a first trench 132. The etching method can employ photolithography. The first trench 132 defines the first metal pad to be formed subsequently. Then, the first sacrificial layer 140 in the first via 131 is etched to form a double damask structure, the double damask process including the first via 131 and the first trench 132 located above the first via 131.

[0054] refer to Figure 7A first conductive line 151 is formed in the first through-hole 131, and a first metal pad 152 is formed in the first trench 132. Specifically, a first metal material layer is first formed on the surface of the first dielectric layer 110 and in the first through-hole 131 and the first trench 132; then, a chemical mechanical polishing (CMP) process is used to remove the first metal material layer on the surface of the first dielectric layer 110, leaving the first metal material layer in the first through-hole 131 and the first trench 132, wherein the first metal material layer in the first through-hole 131 forms the first conductive line 151, and the first metal material layer in the first trench 132 forms the first metal pad 152. Because the polishing rate of the polishing slurry in the CMP process is less than that in the first metal material layer, a pit structure appears on the surface of the first metal pad 152, which affects the bonding yield of existing bonding processes. However, the subsequent processes of this embodiment will treat the pit structure to eliminate the adverse effects of the pit structure on the bonding process.

[0055] refer to Figure 8 Step 113 is performed to etch the first dielectric layer 110 until the surface and sidewalls of the first metal pad 152 are exposed. The etching process used can be photolithography.

[0056] In step S100, the formation process of the second wafer includes:

[0057] Step S121: Provide a stacked wafer, the stacked wafer including a stacked bare wafer having opposing first and second surfaces and a second dielectric layer located on the first surface of the stacked bare wafer, the second dielectric layer and a first portion of the stacked bare wafer having a second conductive interconnect layer formed therein;

[0058] Step S122: Provide a carrier wafer, the carrier wafer including a bare carrier wafer and a third dielectric layer located on the bare carrier wafer;

[0059] Step S123: Using the second dielectric layer and the third dielectric layer as bonding layers, the stacked wafer is bonded to the carrier wafer;

[0060] Step S124: Thin the stacked bare wafer until a first portion of the surface and a portion of the sidewalls of the second conductive interconnect layer are exposed;

[0061] Step S125: A fourth dielectric layer is formed on the second surface of the stacked bare wafer and the first portion of the second conductive interconnect layer;

[0062] Step S126: Form a second portion of the second conductive connection layer in the fourth dielectric layer on the surface of the first portion of the second conductive connection layer.

[0063] Figures 9 to 14 This is a schematic diagram of the structural steps in the process of forming stacked wafers.

[0064] refer to Figure 9 A stacked bare wafer 200 is provided. The stacked bare wafer 200 may be a silicon wafer. The stacked bare wafer 200 includes opposing first and second surfaces. A first portion 211 of a second dielectric layer and a mask layer 212 are sequentially formed on the first surface of the stacked bare wafer 200. The first portion 211 of the second dielectric layer may include stacked silicon oxide and silicon nitride layers, wherein other devices, such as aluminum pads, may also be formed in the silicon oxide layer. The mask layer 212 may be a stacked structure. As an example, the mask layer 212 may include a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked sequentially.

[0065] refer to Figure 10 A second via 221 is formed by etching in the mask layer 212, the first portion 211 of the second dielectric layer, and the stacked bare wafer 200, wherein the second via 221 does not penetrate the stacked bare wafer 200. Then, a portion of the mask layer 212 is removed. As an example, the topmost silicon oxide layer and silicon nitride layer are removed, leaving only the silicon oxide layer on the surface of the first portion 211 of the second dielectric layer.

[0066] refer to Figure 11 A conductive connection structure 220 is formed in the second through-hole 221. The material of the conductive connection structure can be a metal, such as copper. The process for forming the conductive connection structure 220 can be an electroplating process.

[0067] refer to Figure 12 The remaining mask layer 212 and part of the conductive connection structure 220 are ground, stopping at the first portion 211 of the second dielectric layer. At this point, the surfaces of the conductive connection structure 220 and the first portion 211 of the second dielectric layer are coplanar or substantially coplanar.

[0068] refer to Figure 13 A second portion 213 of the second dielectric layer is formed on the surface of the conductive connection structure 220 and the first portion 211 of the second dielectric layer. The second portion 213 of the second dielectric layer can be a stacked structure. As an example, the second portion 213 of the second dielectric layer may include a silicon oxide layer and a silicon nitride layer stacked sequentially. A conductive connection structure 232 is formed in the silicon oxide layer on the surface of the conductive connection structure 220. Other conductive connection structures can also be formed simultaneously with the conductive connection structure 232, such as... Figure 13The conductive connection structure 231 is shown in the figure. As an example, the surfaces of the conductive connection structures 231 and 232 are coplanar with the surface of the silicon oxide layer. That is, the silicon nitride layer is located on the surfaces of the conductive connection structures 231, 232, and the silicon oxide layer. The conductive connection structures 231 and 232 constitute a first portion of the second conductive connection layer.

[0069] refer to Figure 14 Furthermore, the stacked wafers can be trimmed. Specifically, the second portion 213 of the second dielectric layer, the first portion 211 of the second dielectric layer, and the stacked bare wafer 200 are etched at their edges. The first portion 211 and the second portion 213 of the second dielectric layer constitute the second dielectric layer, which serves as the bonding layer during bonding. Specifically, the second portion 213 of the second dielectric layer serves as the bonding layer.

[0070] refer to Figure 15 A carrier wafer is provided, the carrier wafer including a bare carrier wafer 300 and a third dielectric layer 310 located on the bare carrier wafer 300. The bare carrier wafer 300 may be a silicon wafer, and the material of the third dielectric layer 310 may be silicon nitride. In some embodiments, grooves as bonding marks are also formed in the third dielectric layer 310. The third dielectric layer 310 serves as a bonding layer during bonding.

[0071] refer to Figure 16 The stacked wafer is bonded to the carrier wafer using the second and third dielectric layers as bonding layers. The bonding process can employ fusion bonding.

[0072] refer to Figure 17 and Figure 18 The stacked bare wafer 200 is thinned to expose the surface and part of the sidewalls of the first portion of the second conductive interconnect layer.

[0073] refer to Figure 19 A fourth dielectric layer 240 is formed on the second surface of the stacked bare wafer 200 and the surface of the first portion of the second conductive interconnect layer. The fourth dielectric layer 240 may be a stacked structure. As an example, the fourth dielectric layer 240 may include a silicon nitride layer and a silicon oxide layer stacked sequentially, wherein the silicon nitride layer is located on the exposed sidewall of the first portion of the second conductive interconnect layer, and the silicon oxide layer is located on the surface of the silicon nitride layer and the first portion of the second conductive interconnect layer.

[0074] refer to Figure 20A second portion 250 of the second conductive connection layer is formed in the fourth dielectric layer 240 on the surface of the first portion of the second conductive connection layer. As an example, the second portion 250 of the second conductive connection layer has the same material as the first portion of the first conductive connection layer.

[0075] refer to Figure 21 Furthermore, an edge trimming process can be performed. Specifically, the third dielectric layer 310 at the edge is etched so that the sidewalls of the third dielectric layer 310 and the sidewalls of the second dielectric layer are coplanar.

[0076] refer to Figure 22 and Figure 23 A fifth dielectric layer 260 is formed on the surface of the fourth dielectric layer 240. The material of the fifth dielectric layer 260 may include, for example, silicon oxide. The fifth dielectric layer 260 above the second portion of the second conductive interconnect layer is etched, and a second metal pad material is filled at the corresponding locations to form a second metal pad 270. Because there is a polishing process before the formation of the second metal pad 270, the polishing rate of the polishing slurry used in the polishing process on the fifth dielectric layer 260 is less than the polishing rate on the second metal pad material, thus forming grooves on the surface of the second metal pad 270. Next, the fifth dielectric layer 260 on both sides of the second metal pad 270 is removed, exposing the sidewalls of the second metal pad 270.

[0077] Combination Figure 1 , Figure 24 and Figure 25 Step S200 is then performed. An anisotropic conductive adhesive layer is formed on the surface of the first metal pad 152 and the first surface of the first wafer. The anisotropic conductive adhesive layer has unidirectional conductivity and includes an adhesive film 400 and conductive particles 410 dispersed within the adhesive film 400. In some embodiments, the material of the adhesive film 400 may include acrylate and / or polyurethane, and the material of the conductive particles 410 may include copper or a copper-silver-tin alloy. Similarly, an anisotropic conductive adhesive layer is also formed on the surface of the second metal pad 270 and the first surface of the second wafer.

[0078] refer to Figure 26 The process of bonding the first wafer and the second wafer using the anisotropic conductive adhesive layer as the bonding layer may include: aligning the first wafer and the second wafer to align the first metal pad 152 and the second metal pad 270; pressing the first wafer and the second wafer together to fill the pit structure with the conductive particles 410 and connect the first metal pad 152 and the second metal pad 270; and performing ultraviolet curing or thermal curing.

[0079] During the lamination process of the first and second wafers, conductive particles 410 fill the recessed structures of the first metal pad 152 and the second metal pad 270, thereby solving the problem of poor metal pad contact caused by the recessed structure. The lamination bonding method of this embodiment reduces the annealing time for fusion bonding and hybrid bonding, lowers the thermal budget of the bonding process, and can effectively mitigate the irreversible effects of high temperatures on devices in the stacked wafers. Simultaneously, during the lamination bonding process, conductive particles can fill the recessed structures on the surface of the metal pads, effectively solving the problem of poor metal pad contact caused by the recessed structure and improving the yield of the bonding process.

[0080] After the bonding operation is completed, the bonding quality can be inspected. If electrical defects are confirmed through electrical testing, a laser lift-off process can be used to remove the defective wafer from the first and second wafers. The laser lift-off process may include: placing the bonded wafers with the defective wafer on top and the qualified wafer on the bottom; using a laser with a wavelength of 308nm or 355nm to irradiate the defective wafer from above, causing the adhesive of the anisotropic conductive adhesive layer to fail, thereby peeling off the defective wafer and the qualified wafer. This embodiment of the application can achieve complete removal of defective stacked wafers without damaging the stacked wafers, significantly improving the bonding yield.

[0081] After the laser lift-off process is completed, the wafer bonding process is repeated. Once the electrical properties are satisfactory, the next wafer bonding operation is performed.

[0082] refer to Figure 27 This application also provides another wafer bonding method, including:

[0083] Step S1000: Provide a first wafer and a second wafer including a first surface, wherein the first wafer and the second wafer respectively include a first metal pad and a second metal pad having a pit structure on their first surfaces;

[0084] Step S2000: Process the surfaces of the first metal pad and the second metal pad to transform the pit structure into a raised structure, and form an ultraviolet curable layer or a thermosetting layer on the surfaces of the first metal pad and the second metal pad and on the first surface of the first wafer and the second wafer.

[0085] Step S3000: Using the UV-curable layer or the thermosetting layer as a bonding layer, the first wafer and the second wafer are bonded together, and the first metal pad and the second metal pad are connected.

[0086] In step S1000, the method for forming the first wafer, the first metal pad, the second wafer, and the second metal pad can be referred to Figures 3 to 23 This will not be elaborated upon here.

[0087] refer to Figure 28 and Figure 29 Step S2000 is performed to process the surface of the first metal pad 152, transforming the pit structure into a raised structure. Specifically, an acid solution can be used to etch the surface of the first metal pad 152. The acid solution may include hydrogen peroxide and copper sulfate, and the etching rate is 20 Å / s to 50 Å / s. In some embodiments, the acid solution may also include hydrofluoric acid. The same pickling process is used to process the surface of the second metal pad 270.

[0088] refer to Figure 30 and Figure 31 An ultraviolet-curable layer 500 is formed on the surfaces of the first metal pad 152 and the second metal pad 270, and on the first surfaces of the first and second wafers. In other embodiments, a thermosetting layer is formed on the surfaces of the first metal pad 152 and the second metal pad 270, and on the first surfaces of the first and second wafers. The material of the ultraviolet-curable layer 500 may include any material with ultraviolet-curable properties. The material of the thermosetting layer may include any material with thermosetting properties. The following description uses the ultraviolet-curable layer 500 as an example.

[0089] refer to Figure 32 Using the UV-curable layer 500 as a bonding layer, the process of bonding the first wafer and the second wafer may include: aligning the first wafer and the second wafer to align the first metal pad 152 and the second metal pad 270; pressing the first wafer and the second wafer together to connect the raised structures of the first metal pad 152 and the second metal pad 270; and performing UV curing. If a thermosetting layer is used, the final step is thermosetting.

[0090] After the bonding operation is completed, the bonding quality can be inspected. If electrical defects are confirmed through electrical testing, a laser lift-off process can be used to remove the defective wafer from the first and second wafers. The laser lift-off process may include: placing the bonded wafers with the defective wafer on top and the qualified wafer on the bottom; using a laser with a wavelength of 308nm or 355nm to irradiate the defective wafer from above, causing the adhesiveness of the UV-cured layer or thermally cured layer to fail, thereby peeling off the defective wafer and the qualified wafer. Therefore, the embodiments of this application can achieve complete removal of defective stacked wafers without damaging the stacked wafers, and can significantly improve the bonding yield.

[0091] After the laser lift-off process is completed, the wafer bonding process is repeated. Once the electrical properties are satisfactory, the next wafer bonding operation is performed.

[0092] In other embodiments, at least one stacked wafer can be bonded using the aforementioned method to meet the requirement for multilayer stacked wafers.

[0093] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0094] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0095] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," when used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0096] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0097] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A wafer bonding method, characterized in that, include: A first wafer and a second wafer are provided, each having a first metal pad and a second metal pad having a pit structure on their respective first surfaces. An anisotropic conductive adhesive layer is formed on the surfaces of the first metal pad and the second metal pad, and on the first surface of the first wafer and the second wafer, wherein the anisotropic conductive adhesive layer includes conductive particles; or, the surfaces of the first metal pad and the second metal pad are treated to transform the pit structure into a raised structure, and an ultraviolet curable layer or a thermosetting layer is formed on the surfaces of the first metal pad and the second metal pad, and on the first surface of the first wafer and the second wafer. Using the anisotropic conductive adhesive layer as a bonding layer, the first wafer and the second wafer are bonded together, and the conductive particles fill the pit structure and connect the first metal pad and the second metal pad; or using the ultraviolet curing layer or the thermosetting layer as a bonding layer, the first wafer and the second wafer are bonded together, and the first metal pad and the second metal pad are connected.

2. The wafer bonding method according to claim 1, characterized in that, The anisotropic conductive adhesive layer has unidirectional conductivity and also includes an adhesive film in which the conductive particles are dispersed.

3. The wafer bonding method according to claim 2, characterized in that, The adhesive film is made of acrylate and / or polyurethane, and the conductive particles are made of copper or copper-silver-tin alloy.

4. The wafer bonding method according to claim 1, characterized in that, The process of bonding the first wafer and the second wafer using the anisotropic conductive adhesive layer as the bonding layer includes: Align the first wafer and the second wafer to align the first metal pad and the second metal pad; The first wafer and the second wafer are pressed together so that the conductive particles fill the pit structure and connect the first metal pad and the second metal pad. Curing can be performed using ultraviolet light or heat.

5. The wafer bonding method according to claim 1, characterized in that, The surfaces of the first and second metal pads are etched using an acid solution to transform the pit structure into a raised structure. The acid solution includes hydrogen peroxide and copper sulfate, and the etching rate is 20 Å / s to 50 Å / s.

6. The wafer bonding method according to claim 1, characterized in that, The process of bonding the first wafer and the second wafer using the UV-curable layer or the thermosetting layer as the bonding layer includes: Align the first wafer and the second wafer to align the first metal pad and the second metal pad; The first wafer and the second wafer are pressed together to connect the raised structures of the first metal pad and the second metal pad. Curing can be performed using ultraviolet light or heat.

7. The wafer bonding method according to claim 1, characterized in that, Also includes: If electrical testing confirms electrical defects, a laser lift-off process is used to remove the defective wafer from the first and second wafers. The laser lift-off process includes: The wafer structure after bonding is as described above, with defective wafers on top and qualified wafers on the bottom; A laser with a wavelength of 308nm or 355nm is used to irradiate the defective wafer from above, causing the adhesive of the anisotropic conductive adhesive layer to fail, thereby peeling off the defective wafer and the qualified wafer.

8. The wafer bonding method according to claim 1, characterized in that, Also includes: If electrical testing confirms electrical defects, a laser lift-off process is used to remove the defective wafer from the first and second wafers. The laser lift-off process includes: The wafer structure after bonding is as described above, with defective wafers on top and qualified wafers on the bottom; A laser with a wavelength of 308nm or 355nm is used to irradiate the defective wafer from above, causing the adhesiveness of the ultraviolet curing layer or thermal curing layer to fail, thereby peeling off the defective wafer and the qualified wafer.

9. The wafer bonding method according to claim 1, characterized in that, Also includes: After electrical testing confirms that the electrical properties meet the standards, other wafers are then bonded onto the second wafer.

10. The wafer bonding method according to claim 1, characterized in that, The process for forming the first metal gasket includes: A first wafer is provided, the first wafer including a first bare wafer and a first dielectric layer located on the surface of the first bare wafer, wherein a first conductive structure is formed in the first dielectric layer; A first metal pad is formed in the first dielectric layer on the first conductive structure using a double damask process, and the first metal pad is connected to the first conductive structure. The first dielectric layer is etched until the surface and sidewalls of the first metal pad are exposed.

11. The wafer bonding method according to claim 10, characterized in that, The double damask process includes: The first dielectric layer on the surface of the first conductive structure is etched to form a first via. A first sacrificial layer is formed in the first through hole, and the surface of the first sacrificial layer is lower than the top of the first through hole; The portion of the first dielectric layer on both sides of the first via and above the first sacrificial layer is etched to form a first trench; Etch the first sacrificial layer in the first through-hole; A first metallic material layer is formed on the surface of the first dielectric layer and in the first through hole and the first trench; A chemical mechanical polishing process is used to remove the first metal material layer on the surface of the first dielectric layer, and a first conductive line and a first metal pad are formed in the first through hole and the first trench, respectively.

12. The wafer bonding method according to claim 11, characterized in that, The first dielectric layer includes a silicon oxide layer and a silicon nitride layer sequentially stacked on the surface of the first bare wafer.

13. The wafer bonding method according to claim 1, characterized in that, The formation process of the second wafer includes: A stacked wafer is provided, the stacked wafer comprising a stacked bare wafer having opposing first and second surfaces and a second dielectric layer located on the first surface of the stacked bare wafer, wherein the second dielectric layer and a first portion of the stacked bare wafer are formed with a second conductive interconnect layer; A carrier wafer is provided, the carrier wafer comprising a bare carrier wafer and a third dielectric layer located on the bare carrier wafer; Using the second dielectric layer and the third dielectric layer as bonding layers, the stacked wafer is bonded to the carrier wafer; Thin the stacked bare wafer until a first portion of the surface and a portion of the sidewalls of the second conductive interconnect layer are exposed; A fourth dielectric layer is formed on the second surface of the stacked bare wafer and on a first portion of the surface of the second conductive interconnect layer; A second portion of the second conductive connection layer is formed in a fourth dielectric layer on the surface of the first portion of the second conductive connection layer.

14. The wafer bonding method according to claim 13, characterized in that, Also includes: A fifth dielectric layer is formed on the surface of the fourth dielectric layer; A second metal pad is formed in a fifth dielectric layer above a second portion of the second conductive interconnect layer; Remove the fifth dielectric layer from both sides of the second metal pad.

15. The wafer bonding method according to claim 13, characterized in that, The second dielectric layer includes a silicon oxide layer and a silicon nitride layer sequentially stacked on the surface of the stacked bare wafer.

16. The wafer bonding method according to claim 13, characterized in that, The material of the third dielectric layer includes silicon nitride.

17. The wafer bonding method according to claim 13, characterized in that, The fourth dielectric layer comprises a silicon nitride layer and a silicon oxide layer stacked sequentially.

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