Resonant switch controller dead time adaptive adjustment circuit

Abstract

This invention relates to an adaptive dead-time adjustment circuit for a resonant switch controller, comprising a current detection circuit, a current loss tracking detection circuit, an oscillation clock generation circuit, a comprehensive control logic circuit, and a programmable dead-time generation circuit. Unlike existing dead-time setting methods, the adaptive dead-time adjustment circuit for the resonant switch controller proposed in this invention adjusts the dead-time adaptively. Firstly, it is controlled by a reference clock (OSC), setting different dead times according to the frequency. Secondly, it can also respond to changes in soft-switching losses caused by external loads and other operating characteristics, adjusting the dead-time value accordingly to minimize switching losses.

Description

Technical Field

[0001] This invention relates to an adaptive dead-time adjustment circuit for a resonant switch controller chip, belonging to the field of integrated circuit switching power supply technology. Background Technology

[0002] As portable electronic devices increasingly demand higher power supply specifications, the switching power supply market is fiercely competing for performance in areas such as low power consumption, high precision, and small size, leading to increasingly stringent performance requirements for power management chips. As power modules evolve towards miniaturization, lightweight design, and portability, battery life has become one of the most crucial technical indicators. In traditional PWM converters, power devices operate in a hard-switching state, resulting in high switching losses and limiting the increase in switching frequency. Due to the influence of circuit parasitic parameters, switching elements experience high switching stress. Resonant soft-switching converters utilize circuit parasitic parameters to achieve zero-voltage or zero-current switching of the switching transistors, significantly reducing switching losses and allowing the converter to operate at higher switching frequencies to improve power density. Among various types of resonant soft-switching converters, LLC resonant converters possess both strong no-load operating capability and the ability to reflect load conditions with resonant current—advantages unmatched by ordinary series and parallel resonant converters—and are therefore widely used.

[0003] A typical LLC full-bridge resonant converter topology is shown below. Figure 1 As shown, Q1-Q4 are the main switching IGBTs, C1-C4 are the IGBT output capacitors, D1-D4 are the IGBT freewheeling diodes, and DR1-DR4 are the secondary-side rectifier diodes. The resonant inductor Ls, resonant capacitor Cs, and the transformer's magnetizing inductance Lm constitute an LLC resonant network. This circuit topology is a ZVS full-bridge LLC converter with constant input and output voltages. Fixed-frequency control is used; the drive signals for the two IGBTs on the same bridge arm are complementary, while the drive signals for the two IGBTs on the diagonal are the same. Figure 1 The main operating waveforms of the circuit during normal operation are as follows: Figure 2As shown, Vin is the input voltage, Vo is the output voltage, RLd is the resistive load, and n is the transformer turns ratio. When Q1 is off, the transformer magnetizing current charges C1 and discharges C3. When the voltage across C3 drops to zero, Q3 can be turned on to achieve zero-voltage turn-on (ZVS). Therefore, the dead time between the Q1 and Q3 drive signals must be greater than the discharge time of C3 to create the conditions for ZVS turn-on of Q3. Improper dead time settings will prevent the IGBT from achieving ZVS turn-on. If the dead time is set too small, the IGBT will be turned on before the junction capacitor voltage has discharged to 0V, resulting in a hard turn-on. If the dead time is set too large, the junction capacitor voltage may have already discharged to 0V, but due to the excessive dead time, the junction capacitor will begin to charge in reverse, resulting in another hard turn-on and increased losses. It can be seen that, with a fixed frequency, the choice of dead time directly determines the soft-switching range of the converter, thus affecting the voltage stress on the IGBT and the overall efficiency of the converter.

[0004] Figure 1 In the conventional resonant converter, the control signals of the main switches IGBTs Q1 to Q4 are determined by the LLC resonant control chip based on the converter output voltage Vo and current i. R The dead time is typically set to a fixed value, and the charging / discharging time of the IGBT output capacitor and the dead time are estimated based on the output capacitor data in the IGBT's technical specifications. When load conditions and temperature change, the dead time will deviate, potentially affecting the IGBT's zero-voltage turn-on. Therefore, providing a resonant controller dead time generation circuit that can adaptively adjust the system dead time is of significant practical importance for improving the efficiency of LLC resonant control chips and resonant switch controllers. Summary of the Invention

[0005] Based on existing technology, this invention provides a dead-time adaptive adjustment circuit for a resonant switch controller chip, thereby improving the overall efficiency and stability of the controller.

[0006] The resonant switch controller dead time adaptive adjustment circuit according to the present invention includes a current detection circuit, an oscillation clock generation circuit, a current loss follower detection circuit, a comprehensive control logic circuit, and a programmable dead time generation circuit.

[0007] The current detection circuit is used to detect the current signal CS output by the bridge LLC resonant converter power system, and outputs a current loss detection signal Vcs and an output current detection signal Ics under the control of the current sampling control clock Ckcs and the dead time control clock Ckdt. The current loss detection signal Vcs is connected to the input of the current loss follower detection circuit, and the output current detection signal Ics is connected to the input of the oscillation clock generation circuit. The oscillation clock generation circuit generates a reference clock OSC, a current sampling control clock Ckcs, a current follower control clock Ckcom, and a dead time control clock Ckdt based on the output current detection signal Ics. The reference clock OSC is connected to the integrated control logic circuit, the current sampling control clock Ckcs is connected to the current detection circuit and the current loss follower detection circuit, and the dead time control clock Ckdt is connected to the current detection circuit and the dead time control circuit. A current loss following detection circuit is connected to a current following control clock Ckcom. Under the control of the current sampling control clock Ckcs, the current following control clock Ckcom, and the dead time control clock Ckdt, the current loss following detection circuit generates a current loss quantization signal Dcs based on the current loss detection signal Vcs, which is connected to the input of the integrated control logic circuit. The integrated control logic circuit outputs a power switch control signal Din and an N-bit dead time control code Dt(N) based on the state of the reference clock OSC and the current loss quantization signal Dcs, which are connected to the control terminal of the programmable dead time generation circuit. The programmable dead time generation circuit outputs X sets of high-side output switch control signals and low-side output switch control signals with dead time protection based on the power switch control signal Din and the dead time control code Dt(N); where N and X are both positive integers.

[0008] When the above circuit is operating normally, the oscillation clock generation circuit first generates a set of default initial reference clock OSC, current sampling control clock Ckcs, current following control clock Ckcom, and dead time control clock Ckdt. Then, the integrated control logic circuit first generates a default power switch control signal Din and a dead time control code Dt(N). Following this, the programmable dead time generation circuit generates X sets of high-side output switch control signals and X sets of low-side output switch control signals with dead time protection to the output drive circuit, which are used to generate various drive signals for the bridge LLC resonant converter power supply system. The current output of the bridge LLC resonant converter power supply system... The signal CS will generate corresponding characteristic changes. The changes in the CS signal will be detected by the current detection circuit and the current loss follower detection circuit, which will generate the output current detection signal Ics and the current loss quantization signal Dcs, respectively. The output current detection signal Ics enters the oscillation clock generation circuit to adjust the clock frequencies of the reference clock OSC, the current sampling control clock Ckcs, the current follower control clock Ckcom, and the dead time control clock Ckdt. The current loss quantization signal Dcs is used to adjust the dead time of the programmable dead time generation circuit to generate the X groups of high-side output switch control signals and X groups of low-side output switch control signals with dead time protection.

[0009] Specifically, the current detection circuit includes: a Dt sampling switch, a Cs sampling switch, a current compensation buffer circuit, and a voltage buffer circuit; the Dt sampling switch and the Cs sampling switch sample the current signal CS under the control of the dead time control clock Ckdt and the current sampling control clock Ckcs, respectively, and obtain the sampling signal Vdtin and the sampling signal Vcsin, respectively; the current compensation buffer outputs the current detection signal Ics based on the reference voltage Vref and the sampling signal Vcsin; the voltage buffer isolates and buffers the sampling signal Vdtin and outputs the current loss detection signal Vcs; the Dt sampling switch and the Cs sampling switch are the same sampling switch, and the control clocks Ckdt and Ckcs of the Dt sampling switch and the Cs sampling switch are clock signals with non-overlapping sampling effective times, that is, the Dt sampling switch and the Cs sampling switch cannot sample at the same time.

[0010] Specifically, in the above circuit, the current compensation buffer circuit includes PMOS transistors M701, M702, M704, M705, M706, NMOS transistors M707, M708, and M709, resistors R71 and R72, and capacitors C71 and C72; wherein, the gate of PMOS transistor M705 is connected to the reference voltage Vref; the gates of PMOS transistors M701 and M702 are connected to the bias voltage Vbc71; the drain of PMOS transistor M701 is connected to the source of PMOS transistors M705 and M706; the drain of PMOS transistor M705 is connected to the drain of NMOS transistor M707, the gate of NMOS transistor M707, and the gate of NMOS transistor M708; the drain of PMOS transistor M706 is connected to... Connect the drain of NMOS transistor M708, the gate of NMOS transistor M709, and the upper end of resistor R72. The lower end of resistor R72 is connected to the upper end of capacitor C72. The drain of PMOS transistor M702 is connected to the drain of NMOS transistor M709, the right end of capacitor C71, and the gate of PMOS transistor M704. The gate of PMOS transistor M706 is connected to the left end of capacitor C71 and the right end of resistor R71. The left end of resistor R71 is connected to the sampling signal Vcsin. The drain of PMOS transistor M704 serves as the output terminal of the current detection signal Ics of the current compensation buffer circuit. The sources of PMOS transistors M701, M702, and M704 are simultaneously connected to the power supply voltage VCC. The sources of NMOS transistors M707, M708, and M709, along with the lower end of capacitor C72, are simultaneously connected to the ground voltage GND.

[0011] PMOS transistors M701, M702, M705, M706, NMOS transistors M707, M708, and M709, along with resistor R72 and capacitor C72, constitute a two-stage operational amplifier. This two-stage operational amplifier, along with resistor R71 and capacitor C71, forms an integrator circuit. This integrator circuit integrates the sampled signal Vcsin based on the reference voltage Vref, controlling the gate signal of PMOS transistor M704. This causes the magnitude of the output current detection signal Ics to follow the change in the sampled signal Vcsin, thus providing a real-time response to the current signal CS.

[0012] Specifically, the current loss tracking detection circuit includes: a sampling switch, a hold circuit, and a high-precision comparator; the control clock input terminal of the sampling switch is connected to the current sampling control clock Ckcs, and the input current loss detection signal Vcs is connected to the analog signal input terminal of the sampling switch; the first analog signal output terminal of the sampling switch is connected to the positive input terminal of the high-precision comparator, and the connection is controlled by the current tracking control clock CKcom; the second analog signal output terminal of the sampling switch is connected to the signal input terminal of the hold circuit, and the connection is controlled by the dead time control clock CKdt; the analog signal output terminal of the hold circuit is connected to the negative input terminal of the high-precision comparator, and the connection is controlled by the current tracking control clock CKcom; the current sampling control clock Ckcs, the current tracking control clock Ckcom, and the dead time control clock Ckdt are three-phase non-overlapping clocks; the data output of the quantization output terminal of the high-precision comparator is output to the integrated control logic circuit.

[0013] The operation of the above current loss tracking detection circuit is as follows: In phase Ckcs, the sampling switch samples the input current loss detection signal Vcs. The voltage obtained at the Kth sampling is called V. cs (K); Ckcom phase, high-precision comparator samples the voltage V from the switch. cs (K) and the voltage V held by the holding circuit in the previous clock cycle. cs The (K-1) comparison is performed, and the quantized data D(K) is output to the integrated control logic circuit. The quantized data D(K) obtained by the high-precision comparator is the current loss quantization signal Dcs. The output D(K) is 1, indicating that V cs The voltage increases, and the output D(K) is 0, then the opposite occurs; Ckdt phase, V cs (K) enters the holding circuit to hold; K is an integer greater than 1.

[0014] Specifically, the integrated control logic circuit includes: a counter, a control logic circuit, a waveform data generation circuit, an input serial register, a serial-to-parallel conversion circuit, a buffer, and an N-bit buffer. The counter generates a working control clock Ck_ctrl based on an externally input reference clock OSC. The working control clock Ck_ctrl is simultaneously connected to the control clock input terminals of the control logic circuit, the input serial register, and the serial-to-parallel conversion circuit. The control logic circuit generates control signals Ctrl and Ctrl1 based on the working control clock Ck_ctrl. The control signal Ctrl is connected to the control signal input terminals of the waveform data generation circuit and the buffer, and the control signal Ctrl1 is connected to the control signal input terminals of the input serial register, the serial-to-parallel conversion circuit, and the N-bit buffer. The waveform data generation circuit... Under the control of the control signal Ctrl, the circuit generates a power switch control pre-output signal Din_pre based on the reference clock OSC, which is connected to the input of the buffer. Then, the output of the buffer generates a power switch control signal Din. Under the control of the working control clock Ck_ctrl and the control signal Ctrl1, the input serial register receives the current loss quantization signal Dcs in chronological order and outputs it to the serial / parallel conversion circuit in a first-in-first-out order. Under the control of the working control clock Ck_ctrl and the control signal Ctrl1, the serial / parallel conversion circuit converts the serially input current loss quantization signal Dcs into a parallel output N-bit dead-time pre-output control code Dt(N)_pre, which is connected to the input of the N-bit buffer. The N-bit buffer then outputs the N-bit dead-time control code Dt(N).

[0015] After the chip is powered on, the counter in the above-mentioned integrated control logic circuit starts working first. After the counter is working normally, it outputs the working control clock Ck_ctrl according to the reference clock OSC signal, and simultaneously inputs it to the control logic circuit, the input serial register, and the serial / parallel conversion circuit. Next, the control logic circuit generates the control signal Ctrl according to the working control clock Ck_ctrl, and turns on the waveform data generation circuit and the buffer. The waveform data generation circuit generates the power switch control pre-output signal Din_pre according to the reference clock OSC, and generates the power switch control signal Din after being buffered and driven by the buffer. After a certain time delay, the control logic circuit will generate the control signal Ctrl1, turn on the input serial register, the serial / parallel conversion circuit, and the N-bit buffer. The input serial register receives the current loss quantization signal Dcs and outputs it to the serial / parallel conversion circuit in a first-in-first-out order. Finally, the N-bit dead time control code Dt(N) is obtained through the N-bit buffer.

[0016] Specifically, the programmable dead time generation circuit converts the power switch control signal Din into a high-side output switch control signal and a low-side output switch control signal with dead time protection. It includes one or more unit circuits, one unit circuit generating one set of signals Dh1 and Dl1 with dead time protection. The length of the dead time is adjusted by the numerically controlled delay unit in the unit circuit. The delay time of the numerically controlled delay unit is controlled by different dead time control codes Dt(N), ultimately controlling the overall dead time. X unit circuits generate X sets of signals with dead time protection, that is, they generate high-side output switch control signals Dh1~DhX and low-side output switch control signals Dl1~DlX.

[0017] The advantages of this invention are: Firstly, the adaptive adjustment process of the dead time is controlled by the reference clock OSC, setting different dead times according to the frequency. Secondly, it can also respond to changes in soft switching losses caused by external loads and other operating characteristics, adjusting the dead time accordingly to minimize switching losses. The solution of this invention can be widely applied to various LLC resonant controller systems. Attached Figure Description

[0018] Figure 1 This is a block diagram of a typical LLC full-bridge resonant converter system.

[0019] Figure 2 for Figure 1 A schematic diagram of the main waveforms in the circuit.

[0020] Figure 3 This is a block diagram of the adaptive dead time adjustment circuit for the resonant switch controller of the present invention.

[0021] Figure 4 This is a block diagram of the current detection circuit structure of the present invention.

[0022] Figure 5 This is a schematic diagram of the current loss tracking detection circuit of the present invention.

[0023] Figure 6 for Figure 5 The control clock waveform of the medium current loss follower detection circuit.

[0024] Figure 7 for Figure 4 An embodiment of a medium current compensation buffer circuit.

[0025] Figure 8 This is one embodiment of the oscillation clock generation circuit of the present invention.

[0026] Figure 9 This is one embodiment of the programmable dead time generation circuit of the present invention.

[0027] Figure 10 This is an internal block diagram of the integrated control logic circuit of the present invention.

[0028] Figure 11 This is a schematic diagram illustrating the application of the present invention in an LLC half-bridge resonant controller.

[0029] Figure 12 This is a schematic diagram illustrating the application of the present invention in an LLC full-bridge resonant controller. Detailed Implementation

[0030] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0031] like Figure 3 As shown, the resonant switch controller dead time adaptive adjustment circuit of the present invention includes: a current detection circuit 1, a current loss following detection circuit 3, an oscillation clock generation circuit 2, a comprehensive control logic circuit 4, and a programmable dead time generation circuit 5.

[0032] The current detection circuit 1 is used to detect the current signal CS output by the power supply system of the bridge LLC resonant converter, and generates a current loss detection signal Vcs and an output current detection signal Ics under the control of the current sampling control clock Ckcs and the dead time control clock Ckdt. The current loss detection signal Vcs is connected to the current loss following detection circuit 3, and the output current detection signal Ics is connected to the oscillation clock generation circuit 2.

[0033] The oscillation clock generation circuit 2 generates a reference clock OSC, a current sampling control clock Ckcs, a current following control clock Ckcom, and a dead time control clock Ckdt based on the output current detection signal Ics.

[0034] Under the control of the current sampling control clock Ckcs, the current following control clock Ckcom, and the dead time control clock Ckdt, the current loss following detection circuit 3 generates a current loss quantization signal Dcs based on the current loss detection signal Vcs.

[0035] The integrated control logic circuit 4 generates a power switch control signal Din and an N-bit dead-time control code Dt(N) based on the state of the reference clock OSC and the current loss quantization signal Dcs. The programmable dead-time generation circuit 5 generates X sets of high-side output switch control signals and low-side output switch control signals with dead-time protection based on the power switch control signal Din and the dead-time control code Dt(N). N and X are both arbitrary positive integers.

[0036] This invention Figure 3The circuit shown detects the state of the current signal CS output by the power supply system of the bridge LLC resonant converter at different times to determine whether the dead time setting is optimal. Then, it adaptively adjusts the size of the dead time to minimize the switching loss of the LLC resonant control system and achieve the best soft-switching characteristics.

[0037] When the circuit is operating normally, the oscillation clock generation circuit 2 first generates a set of default initial reference clock OSC, current sampling control clock Ckcs, current following control clock Ckcom, and dead time control clock Ckdt; then the integrated control logic circuit 4 first generates a default power switch control signal Din and dead time control code Dt(N); then the programmable dead time generation circuit 5 generates X sets of high-side output switch control signals Dh1~DhX and X sets of low-side output switch control signals Dl1~DlX with dead time protection; the current signal CS output by the bridge LLC resonant converter power system will correspondingly generate characteristic changes. The changes in the CS signal will be detected by the current detection circuit 1 and the current loss follower detection circuit 3, and will generate the output current detection signal Ics and the current loss quantization signal Dcs respectively. The output current detection signal Ics enters the oscillation clock generation circuit 2 to adjust the clock frequencies of the reference clock OSC, the current sampling control clock Ckcs, the current follower control clock Ckcom, and the dead time control clock Ckdt. The current loss quantization signal Dcs is used to adjust the dead time of the programmable dead time generation circuit 5 to generate the high-side output switch control signals Dh1~DhX and the low-side output switch control signals Dl1~DlX with dead time protection.

[0038] As can be seen from the above working process, unlike the existing dead time setting method, the adaptive dead time adjustment circuit of the resonant switch controller proposed in this invention is controlled by the reference clock OSC on the one hand, and different dead times are set according to the frequency; on the other hand, it can also respond to the changes in soft switching losses caused by external load and other operating characteristics, and adjust the size of the dead time, thereby minimizing the switching losses.

[0039] Figure 4 This is a block diagram of the current detection circuit 1 of the present invention. The current detection circuit 1 internally includes: a Dt sampling switch 40, a Cs sampling switch 41, a current compensation buffer circuit 42, and a voltage buffer circuit 43.

[0040] Dt sampling switch 40 and Cs sampling switch 41 sample the current signal CS output by the bridge LLC resonant converter power system under the control of the dead time control clock Ckdt and the current sampling control clock Ckcs, respectively, and obtain the sampling signal Vdtin and the sampling signal Vcsin, respectively.

[0041] The current compensation buffer circuit 42 generates an output current detection signal Ics based on the reference voltage Vref and the sampling signal Vcsin.

[0042] The voltage buffer circuit 43 isolates and buffers the sampling signal Vdtin to obtain the current loss detection signal Vcs.

[0043] Figure 4 The Dt sampling switch 40 and the Cs sampling switch 41 are the same sampling switches and can be implemented using various existing voltage sampling switches. The control clocks Ckdt and Ckcs of the Dt sampling switch 40 and the Cs sampling switch 41 are clock signals whose valid sampling times do not overlap, that is, the Dt sampling switch 40 and the Cs sampling switch 41 cannot sample at the same time.

[0044] Figure 5 The current loss tracking detection circuit 3 of this invention includes a sampling switch 50, a hold circuit 51, and a high-precision comparator 53. The input current loss detection signal Vcs is connected to the analog signal input terminal of the sampling switch 50. The first analog signal output terminal of the sampling switch 50 is connected to the positive input terminal of the high-precision comparator 53 under the control of the current tracking control clock CKcom. The second analog signal output terminal of the sampling switch 50 is connected to the signal input terminal of the hold circuit 51 under the control of the current sampling control clock CKcs. The analog signal output terminal of the hold circuit 51 is connected to the negative input terminal of the high-precision comparator 53 under the control of the current tracking control clock CKcom. The data D(K) at the quantization output terminal of the high-precision comparator 53 is the current loss quantization signal Dcs, which is output to the integrated control logic circuit 4.

[0045] Figure 6 for Figure 5 The operating control clock waveform of the current loss following detection circuit 3 is shown. In this invention, the reference clock OSC is further subdivided into a three-phase non-overlapping clock consisting of a current sampling control clock Ckcs, a current following control clock Ckcom, and a dead time control clock Ckdt. The simplified working process of the current loss following detection circuit is as follows: In the Ckcs phase, the sampling switch 50 samples the input current loss detection signal Vcs. Assuming that this is the Kth sampling, the switch samples the voltage V. cs (K); Ckcom phase, high-precision comparator 53 will sample the voltage V from the switch. cs (K) will hold the voltage V held by the holding circuit 51 for the previous clock cycle. csThe comparison is performed using (K-1). The high-precision comparator 53 outputs the quantized data D(K) to the integrated control logic circuit 4. The comparison is only meaningful if K>1 (the high-precision comparator 53 outputs a default signal during the first sampling). An output D(K) of 1 indicates that V... cs If the voltage increases, the high-precision comparator 53 outputs quantized data D(K) of 0, and vice versa. (Ckdt phase, V) cs (K) will be held in the holding circuit 51.

[0046] The integrated control logic circuit 4 can obtain the changing trend of the current loss detection signal Vcs by reading the quantized data D(K). For example, if D(K) is continuously 1, it means that the current loss detection signal Vcs continues to rise. The current loss of the current signal CS output by the bridge LLC resonant converter power system increases during the dead time, and the dead time needs to be modulated. Figure 5 The accuracy of the circuit shown depends on the performance of the hold circuit 51 and the high-precision comparator 53. Obviously, speed and accuracy are contradictory indicators. To improve accuracy, the frequency of the control clock can be reduced. Different application backgrounds have very different requirements for the speed and accuracy of the hold circuit 51 and the high-precision comparator 53, and different circuit structures need to be designed.

[0047] Figure 7 for Figure 4One embodiment of the medium current compensation buffer circuit 42 includes PMOS transistors M701, M702, M704, M705, M706, NMOS transistors M707, M708, and M709, resistors R71 and R72, and capacitors C71 and C72. In this configuration, the gate of PMOS transistor M705 is connected to the reference voltage Vref; the gates of PMOS transistors M701 and M702 are connected to the bias voltage Vbc71; the drain of PMOS transistor M701 is connected to the source of both PMOS transistors M705 and M706; the drain of PMOS transistor M705 is connected to the drain of NMOS transistor M707, and also to the gates of both NMOS transistors M707 and M708; the drain of PMOS transistor M706 is connected to the drain of NMOS transistor M708, and also to the gate of NMOS transistor M709, as well as the upper end of resistor R72. The lower end of resistor R72 is connected to the upper end of capacitor C72; PMOS transistor M70... The drain of transistor 2 is connected to the drain of NMOS transistor M609, and to the right end of capacitor C71 and the gate of PMOS transistor M704; the gate of PMOS transistor M706 is connected to the left end of capacitor C71 and the right end of resistor R71, and the left end of resistor R71 is connected to the sampling signal Vcsin; the drain of PMOS transistor M704 serves as the output terminal of the current detection signal Ics of the current compensation buffer circuit; the sources of PMOS transistors M701, M702, and M704 are simultaneously connected to the power supply voltage VCC; the sources of NMOS transistors M708, M709, and M707 and the lower end of capacitor C72 are simultaneously connected to the ground voltage GND.

[0048] Figure 7 In this circuit, PMOS transistors M701, M702, M705, and M706, NMOS transistors M708, M709, and M707, along with resistor R72 and capacitor C72, constitute a two-stage operational amplifier. These two operational amplifiers, along with resistor R71 and capacitor C71, form an integrator circuit. This integrator circuit integrates the sampled signal Vcsin based on the reference voltage provided by Vref, controlling the gate signal of PMOS transistor M704. This causes the magnitude of Ics to follow the changes in the sampled signal Vcsin, thus providing a real-time response to the CS signal.

[0049] Figure 8This is one embodiment of the oscillation clock generation circuit 2 of the present invention. The oscillation clock generation circuit 2 includes: a PMOS transistor M80, an NMOS transistor M81, a delay capacitor C80, a Schmitt trigger S80, an inverter Inv80, an inverter Inv81, an inverter Inv82, an output buffer Buf80, and a multi-phase clock generation circuit. Inverters Inv80, Inv81, and Inv82 form an odd-stage inverter chain. PMOS transistor M80 and NMOS transistor M81 form a delay-controlled inverter. The output of the delay-controlled inverter is simultaneously connected to the upper end of the delay capacitor C80 and the input terminal of the Schmitt trigger S80. The output terminal of the Schmitt trigger S80 is connected to the input terminal of the odd-stage inverter chain. The output terminal of the odd-stage inverter chain is simultaneously connected to the input terminal of the output buffer Buf80, the input terminal of the delay-controlled inverter, and the input terminal of the multi-phase clock generation circuit. The output terminal of the output buffer Buf80 is the reference clock OSC. The multiphase clock generation circuit generates three non-overlapping current sampling control clocks Ckcs, current following control clocks Ckcom, and dead-time control clocks Ckdt. Delay-controlled inverters, Schmitt triggers S80, and an odd-stage inverter chain are cascaded to form an odd-stage ring oscillator, generating an oscillation clock signal. The frequency of the oscillator output clock is controlled by the output current detection signal Ics, which delays the charging and discharging of the delay capacitor C80.

[0050] Figure 9 This is one embodiment of the programmable dead-time generation circuit 5 of the present invention. The circuit's input is Din, and its output is a set of signals Dh and Dl with dead-time protection. Dh serves as the high-side output switch control signal, and Dl serves as the low-side output switch control signal. The circuit's function is to convert the power switch control signal Din into high-side and low-side output switch control signals with dead-time protection. The dead time is achieved through cross-coupling and logic control of a numerically controlled delay unit, and the length of the dead time is adjusted by the numerically controlled delay unit. By using different dead-time control codes Dt(N), the delay time of the numerically controlled delay unit is adjusted, ultimately achieving the purpose of controlling the overall dead time. Figure 9 The circuit shown is for generating one set of signals with dead time protection. By using multi-channel cross-coupling, multiple sets of this circuit can generate multiple sets of signals with dead time protection.

[0051] Figure 10 This is an internal block diagram of the integrated control logic circuit 4 of the present invention. The integrated control logic circuit 4 of the present invention includes: a counter 100, a control logic circuit 101, a waveform data generation circuit 102, an input serial register 103, a serial-to-parallel conversion circuit 104, a buffer 105, and an N-bit buffer 106.

[0052] The counter 100 generates a working control clock Ck_ctrl based on an external input reference clock OSC. The working control clock Ck_ctrl is simultaneously connected to the control clock input terminals of the control logic circuit 101, the input serial register 103, and the serial / parallel conversion circuit 104. The control logic circuit 101 generates control signals Ctrl and Ctrl1 based on the working control clock Ck_ctrl. Control signal Ctrl is connected to the control signal input terminals of the waveform data generation circuit 102 and the buffer 105, while control signal Ctrl1 is connected to the control signal input terminals of the input serial register 103, the serial / parallel conversion circuit 104, and the N-bit buffer 106. The waveform data generation circuit 102, under the control of the working control clock Ck_ctrl and the control signal Ctrl, generates a working control clock Ck_ctrl based on the external input reference clock OSC ... An external input reference clock OSC generates a power switch control pre-output signal Din_pre, which is connected to buffer 105 to generate a power switch control signal Din. Under the control of the working control clock Ck_ctrl and the control signal Ctrl1, the input serial register 103 receives the current loss quantization signal Dcs in chronological order and outputs it to the serial / parallel conversion circuit 104 in a first-in-first-out order. Under the control of the working control clock Ck_ctrl and the control signal Ctrl1, the serial / parallel conversion circuit 104 converts the serially input current loss quantization signal Dcs into a parallel output N-bit dead-time pre-output control code Dt(N)_pre, which is then passed through an N-bit buffer 106 to obtain the N-bit dead-time control code Dt(N).

[0053] After the chip is powered on, the counter 100 in the integrated control logic circuit 4 starts to work normally first. After the counter 100 works normally, it outputs the working control clock Ck_ctrl according to the OSC signal and inputs it to the control logic circuit 101, the input serial register 103 and the serial / parallel conversion circuit 104. Then, the control logic circuit 101 generates the control signal Ctrl according to the working control clock Ck_ctrl and turns on the waveform data generation circuit 102 and the buffer 105. The waveform data generation circuit 102 generates the power switch control pre-output signal Din_pre according to the external input reference clock OSC. After being buffered by the buffer 105, the power switch control signal Din is generated. After a certain time delay, the control logic circuit 101 will generate the control signal Ctrl1 and turn on the input serial register 103, the serial / parallel conversion circuit 104 and the N-bit buffer 106. The input serial register 103 receives the current loss quantization signal Dcs and outputs it to the serial / parallel conversion circuit 104 in a first-in-first-out order. Finally, the N-bit dead time control code Dt(N) is obtained through the N-bit buffer 106.

[0054] In the above process, the working control clock Ck_ctrl is usually a clock signal with a frequency no higher than OSC; the delay time for generating control signals Ctrl and Ctrl1 must be greater than a positive integer multiple of the period of the working control clock Ck_ctrl, and the specific duration can be set according to the application scenario. The control logic circuit 101 can be implemented in various ways, the most common being state machine control.

[0055] Figure 11 This is a schematic diagram illustrating the application of the present invention in an LLC half-bridge resonant controller. The resonant switch controller dead-time adaptive adjustment circuit of the present invention is used as a circuit module of the LLC half-bridge resonant controller chip. It is used to generate a high-side output switch control signal Dho and a low-side output switch control signal Dlo with dead-time protection. The high-side output switch control signal Dho enters a level shifting circuit to generate a high-side output signal Dhho, which then passes through a high-side output drive circuit H to generate a high-side gate drive signal HG and floating power supply BST and floating ground SW. The low-side output switch control signal Dlo enters a delay compensation circuit to generate a low-side output signal Dllo, which then passes through a low-side output drive circuit L to generate a low-side gate drive signal LG. The high-side gate drive signal HG and the low-side gate drive signal LG respectively drive the gates of the high-speed power switching devices (such as MOSFETs, IGBTs, or GaN HEMTs) in the LLC half-bridge resonant power system, enabling the system to operate normally.

[0056] When the load characteristics change, the output drive current of the LLC half-bridge resonant power system is detected by the CS signal and fed back to the dead time adaptive adjustment circuit of the resonant switch controller described in this invention. This circuit adjusts the dead time between the high-side output switch control signal Dho and the low-side output switch control signal Dlo, thereby changing the dead time and switching losses of the power system.

[0057] Figure 12This is a schematic diagram illustrating the application of the present invention in an LLC full-bridge resonant controller. The dead-time adaptive adjustment circuit of the resonant switch controller of the present invention is used as a circuit module of the LLC full-bridge resonant controller chip. It generates two sets of switch control signals with dead-time protection. One set consists of a high-side output switch control signal Dh1 and a low-side output switch control signal Dl1, and the other set consists of a high-side output switch control signal Dh2 and a low-side output switch control signal Dl2. The high-side output switch control signals Dh1 and Dh2 respectively enter a level shifting circuit, generating high-side output signals Dhh1 and Dhh2, which then pass through output drive circuits H1 and H2 to generate high-side gate drive signal HG1, high-side gate drive signal HG2, floating ground SW1, floating ground SW2, and a floating power supply BST. The low-side output switch control signals Dl1 and Dl2 enter the first delay compensation circuit and the second delay compensation circuit, respectively, to generate low-side output signals Dll1 and Dll2. These signals then pass through the output drive L1 circuit and the output drive L2 circuit to generate low-side gate drive signals LG1 and LG2. The high-side gate drive signals HG1 and HG2 and the low-side gate drive signals LG1 and LG2 drive the gates of the high-speed power switching devices (such as MOSFETs, IGBTs, or GaN HEMTs) in the LLC full-bridge resonant power system, enabling the system to operate normally.

[0058] When the load characteristics change, the output drive current of the LLC full-bridge resonant power system is detected by the CS signal and fed back to the dead time adaptive adjustment circuit of the resonant switch controller described in this invention. The dead time between the high-side gate drive signals HG1 and HG2 and the low-side gate drive signals LG1 and LG2 is adjusted to change the dead time and switching loss of the power system.

[0059] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A resonant switch controller dead time adaptive adjustment circuit, characterized by, It includes a current detection circuit (1), an oscillation clock generation circuit (2), a current loss tracking detection circuit (3), a comprehensive control logic circuit (4), and a programmable dead time generation circuit (5). The current detection circuit (1) is used to detect the current signal CS output by the power supply system of the bridge LLC resonant converter, and outputs the current loss detection signal Vcs and the current detection signal Ics under the control of the current sampling control clock Ckcs and the dead time control clock Ckdt. The current loss detection signal Vcs is connected to the input terminal of the current loss follower detection circuit (3), and the output current detection signal Ics is connected to the input terminal of the oscillation clock generation circuit (2). The oscillation clock generation circuit (2) generates a reference clock OSC, a current sampling control clock Ckcs, a current following control clock Ckcom, and a dead time control clock Ckdt based on the output current detection signal Ics. The reference clock OSC is connected to the integrated control logic circuit (4), the current sampling control clock Ckcs is connected to the current detection circuit (1) and the current loss following detection circuit (3), the dead time control clock Ckdt is connected to the current detection circuit (1) and the current loss following detection circuit (3), and the current following control clock Ckcom is connected to the current loss following detection circuit (3). Under the control of the current sampling control clock Ckcs, the current following control clock Ckcom and the dead time control clock Ckdt, the current loss following detection circuit (3) generates a current loss quantization signal Dcs based on the current loss detection signal Vcs and connects it to the input terminal of the integrated control logic circuit (4). The integrated control logic circuit (4) outputs a power switch control signal Din and an N-bit dead time control code Dt(N) based on the status of the reference clock OSC and the current loss quantization signal Dcs and connects it to the control terminal of the programmable dead time generation circuit (5). The programmable dead time generation circuit (5) outputs X sets of high-side output switch control signals and low-side output switch control signals with dead time protection based on the power switch control signal Din and the dead time control code Dt(N); where N and X are both positive integers. The integrated control logic circuit (4) includes: a counter (100), a control logic circuit (101), a waveform data generation circuit (102), an input serial register (103), a serial-to-parallel conversion circuit (104), a buffer (105), and an N-bit buffer (106). The counter (100) generates a working control clock Ck_ctrl based on an externally input reference clock OSC. The working control clock Ck_ctrl is simultaneously connected to the control clock input terminals of the control logic circuit (101), the input serial register (103), and the serial-to-parallel conversion circuit (104). The control logic circuit (101) generates control signals Ctrl and Ctrl1 based on the working control clock Ck_ctrl. The control signal Ctrl is connected to the control signal input terminals of the waveform data generation circuit (102) and the buffer (105), and the control signal Ctrl1 is connected to the input serial register (103), the serial-to-parallel conversion circuit (104), and the N-bit buffer (106). The control signal input terminal of 106); the waveform data generation circuit (102) generates a power switch control pre-output signal Din_pre according to the reference clock OSC under the control of the control signal Ctrl, and connects to the input terminal of the buffer (105), and then the output terminal of the buffer (105) generates a power switch control signal Din; the input serial register (103) receives the current loss quantization signal Dcs in the order of time according to the working control clock Ck_ctrl and the control signal Ctrl1, and outputs it to the serial / parallel conversion circuit (104) in the order of first-in-first-out; the serial / parallel conversion circuit (104) converts the serial input current loss quantization signal Dcs into the parallel output N-bit dead time pre-output control code Dt(N)_pre, connects to the input terminal of the N-bit buffer (106), and outputs the N-bit dead time control code Dt(N) through the N-bit buffer (106); The programmable dead time generation circuit (5) converts the power switch control signal Din into a high-side output switch control signal and a low-side output switch control signal with dead time protection; it includes one or more unit circuits, one unit circuit generates one set of signals Dh1 and Dl1 with dead time protection; the length of the dead time is adjusted by the numerically controlled delay unit in the unit circuit, and the delay time of the numerically controlled delay unit is controlled by different dead time control codes Dt(N), so as to finally control the overall dead time; X unit circuits generate X sets of signals with dead time protection, that is, they generate high-side output switch control signals Dh1~DhX and low-side output switch control signals Dl1~DlX.

2. The resonant switch controller dead time adaptive adjustment circuit of claim 1, wherein, When the circuit is working normally, the oscillation clock generation circuit (2) first generates a set of default initial reference clock OSC, current sampling control clock Ckcs, current following control clock Ckcom and dead time control clock Ckdt. Then, the integrated control logic circuit (4) first generates a default power switch control signal Din and dead time control code Dt(N). Then, the programmable dead time generation circuit (5) generates X sets of high-side output switch control signals and X sets of low-side output switch control signals with dead time protection to the output drive circuit, which are used to generate various drive signals of the bridge LLC resonant converter power supply system. The current signal CS output by the bridge LLC resonant converter power supply system will generate corresponding characteristic changes. The changes in the CS signal will be detected by the current detection circuit (1) and the current loss following detection circuit (3), which will generate the output current detection signal Ics and the current loss quantization signal Dcs, respectively. The output current detection signal Ics enters the oscillation clock generation circuit (2) to adjust the clock frequency of the reference clock OSC, the current sampling control clock Ckcs, the current following control clock Ckcom and the dead time control clock Ckdt. The current loss quantization signal Dcs is used to adjust the dead time of the programmable dead time generation circuit (5) to generate the dead time of the X-group high-side output switch control signal and the X-group low-side output switch control signal with dead time protection.

3. The resonant switch controller dead time adaptive adjustment circuit of claim 1, wherein, The current detection circuit (1) includes: a Dt sampling switch (40), a Cs sampling switch (41), a current compensation buffer circuit (42), and a voltage buffer circuit (43); the Dt sampling switch (40) and the Cs sampling switch (41) sample the current signal CS under the control of the dead time control clock Ckdt and the current sampling control clock Ckcs, respectively, and obtain the sampling signal Vdtin and the sampling signal Vcsin, respectively; the current compensation buffer circuit (42) calculates the current signal based on the reference voltage Vref and the sampling signal Vdtin. The voltage buffer circuit (43) isolates and buffers the sampling signal Vdtin and outputs the current loss detection signal Vcs. The Dt sampling switch (40) and the Cs sampling switch (41) are the same sampling switches. The control clocks Ckdt and Ckcs of the Dt sampling switch (40) and the Cs sampling switch (41) are clock signals with non-overlapping sampling effective times, that is, the Dt sampling switch (40) and the Cs sampling switch (41) cannot sample at the same time.

4. The resonant switch controller dead time adaptive adjustment circuit of claim 3, wherein, The current compensation buffer circuit (42) includes PMOS transistors M701, M702, M704, M705, M706, M707, M708, and M709, resistors R71 and R72, and capacitors C71 and C72. The gate of PMOS transistor M705 is connected to the reference voltage Vref; the gates of PMOS transistors M701 and M702 are connected to the bias voltage Vbc71; the drain of PMOS transistor M701 is connected to the source of PMOS transistors M705 and M706; the drain of PMOS transistor M705 is connected to the drain of NMOS transistor M707, the gate of NMOS transistor M707, and the gate of NMOS transistor M708; and the drain of PMOS transistor M706 is connected to the gate of NMOS transistor M709. The drain of transistor M708, the gate of NMOS transistor M709, and the upper end of resistor R72 are connected, and the lower end of resistor R72 is connected to the upper end of capacitor C72; the drain of PMOS transistor M702 is connected to the drain of NMOS transistor M709, the right end of capacitor C71, and the gate of PMOS transistor M704; the gate of PMOS transistor M706 is connected to the left end of capacitor C71 and the right end of resistor R71, and the left end of resistor R71 is connected to the sampling signal Vcsin; the drain of PMOS transistor M704 serves as the output terminal of the current detection signal Ics of the current compensation buffer circuit (42); the source of PMOS transistor M701, the source of PMOS transistor M702, and the source of PMOS transistor M704 are simultaneously connected to the power supply voltage VCC; the source of NMOS transistor M707, the source of NMOS transistor M708, the source of NMOS transistor M709, and the lower end of capacitor C72 are simultaneously connected to the ground voltage GND; PMOS transistors M701, M702, M705, M706, NMOS transistors M707, M708, and M709, along with resistor R72 and capacitor C72, constitute a two-stage operational amplifier. This two-stage operational amplifier, along with resistor R71 and capacitor C71, forms an integrator circuit. This integrator circuit integrates the sampled signal Vcsin based on the reference voltage Vref, controlling the gate signal of PMOS transistor M704. This causes the magnitude of the output current detection signal Ics to follow the change in the sampled signal Vcsin, thus providing a real-time response to the current signal CS.

5. The resonant switch controller dead-time adaptive adjustment circuit of claim 1, wherein, The current loss tracking detection circuit (3) includes: a sampling switch (50), a holding circuit (51), and a high-precision comparator (53); the control clock input terminal of the sampling switch (50) is connected to the current sampling control clock Ckcs, and the input current loss detection signal Vcs is connected to the analog signal input terminal of the sampling switch (50); the first analog signal output terminal of the sampling switch (50) is connected to the positive input terminal of the high-precision comparator (53), and the connection is controlled by the current tracking control clock CKcom; the second analog signal output terminal of the sampling switch (50) is connected to the signal input terminal of the holding circuit (51), and the connection is controlled by the dead time control clock CKdt; the analog signal output terminal of the holding circuit (51) is connected to the negative input terminal of the high-precision comparator (53), and the connection is controlled by the current tracking control clock CKcom; the current sampling control clock Ckcs, the current tracking control clock Ckcom, and the dead time control clock Ckdt are three-phase non-overlapping clocks; the data output of the quantization output terminal of the high-precision comparator (53) is output to the integrated control logic circuit (4).

6. The resonant switch controller dead time adaptive adjustment circuit of claim 5, wherein, The operation of the current loss tracking detection circuit (3) is as follows: In phase Ckcs, the sampling switch (50) samples the input current loss detection signal Vcs. The voltage obtained during the Kth sampling is called V. cs (K); Ckcom phase, high-precision high-precision comparator (53) samples the voltage V from the switch. cs (K) and the voltage V held by the holding circuit (51) in the previous clock cycle. cs (K-1) is compared, and the quantized data D(K) is output to the integrated control logic circuit (4); the quantized data D(K) obtained by the high-precision comparator (53) is the current loss quantization signal Dcs, and the output D(K) is 1, indicating that V cs The voltage increases, and the output D(K) is 0, then the opposite occurs; Ckdt phase, V cs (K) enters the holding circuit (51) to hold; K is an integer greater than 1.

7. The resonant switch controller dead time adaptive adjustment circuit of claim 1, wherein, After the chip is powered on, the counter (100) in the integrated control logic circuit (4) starts working first. After the counter (100) is working normally, it outputs the working control clock Ck_ctrl according to the reference clock OSC signal, and inputs it to the control logic circuit (101), the input serial register (103) and the serial / parallel conversion circuit (104). Then, the control logic circuit (101) generates the control signal Ctrl according to the working control clock Ck_ctrl, and turns on the waveform data generation circuit (102) and the buffer (105). The waveform data generation circuit (102) outputs the working control clock Ck_ctrl according to the reference clock OSC signal. C generates a power switch control pre-output signal Din_pre, which is buffered by a buffer (105) to drive the generation of a power switch control signal Din. After a certain time delay, the control logic circuit (101) will generate a control signal Ctrl1, which will enable the input serial register (103), the serial / parallel conversion circuit (104) and the N-bit buffer (106). The input serial register (103) receives the current loss quantization signal Dcs and outputs it to the serial / parallel conversion circuit (104) in a first-in-first-out order. Finally, the N-bit dead time control code Dt(N) is obtained through the N-bit buffer (106).

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