A signal demodulation circuit and a digital isolation circuit

Abstract

The application discloses a signal demodulation circuit and a digital isolation circuit, wherein the signal demodulation circuit is arranged at a receiving end of the digital isolation circuit and comprises a common-gate amplification module, a demodulation module and a common-gate amplification module; the common-gate amplification module is used for receiving full-differential signals output by an isolation module in the digital isolation circuit and amplifying the full-differential signals; the demodulation module is connected with the common-gate amplification module and is used for demodulating the amplified full-differential signals and outputting the demodulated full-differential signals; and the common-gate amplification module comprises a first active load, a second active load, a first NMOS tube, a second NMOS tube, a first coupling capacitor, a second coupling capacitor, a first sampling resistor and a second sampling resistor. The circuit has high anti-interference capability.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and in particular to an interference suppression correction circuit and a digital isolation circuit. Background Technology

[0002] Isolation refers to the electrical separation between various functional circuits in a system, preventing signal transmission through direct conductive paths. Instead, it physically separates high-voltage and low-voltage domains, minimizing mutual interference between circuits at different potentials. Currently, capacitive coupling is commonly used. A typical capacitive isolation drive circuit includes a transmitter (modulation module on the low-voltage side), a receiver (demodulation module on the high-voltage side), and an isolation capacitor. The transmitter modulates the transmitted signal into a signal that can pass through the isolation capacitor module, while the receiver demodulates the signal from the isolation capacitor module back into the transmitted signal. The isolation capacitor module connects the transmitter and receiver.

[0003] Because the signal modulation module and the signal demodulation module of the isolation drive circuit are in different voltage domains, the signal is transmitted through the voltage domain from the signal modulation module to the signal demodulation module. This will generate a common-mode transient pulse in the signal demodulation module. Different voltage rise rates will generate common-mode transient pulses of different sizes. This common-mode transient pulse will have a common-mode to differential-mode effect at the signal demodulation module, which will cause misjudgment at the signal demodulation module.

[0004] Therefore, how to effectively suppress common-mode transient pulse interference in digital isolation circuits has become an urgent problem to be solved. Summary of the Invention

[0005] Therefore, in order to solve the above-mentioned problems in the prior art, this application provides a signal demodulation circuit that can accommodate more common-mode transient events and has a high anti-interference capability, and further provides a digital isolation circuit that can effectively suppress common-mode transient interference.

[0006] According to a first aspect, the present invention provides a signal demodulation circuit disposed at the receiving end of a digital isolation circuit, comprising:

[0007] The common-gate amplifier module is used to receive the fully differential signal output by the isolation module in the digital isolation circuit and amplify the fully differential signal.

[0008] The demodulation module, connected to the common-gate amplifier module, is used to demodulate and output the amplified fully differential signal;

[0009] The common-gate amplifier module includes a first active load, a second active load, a first NMOS transistor, a second NMOS transistor, a first coupling capacitor, a second coupling capacitor, a first sampling resistor, and a second sampling resistor. The source of the first NMOS transistor is connected to the first sampling resistor and then grounded, and the source of the second NMOS transistor is connected to the second sampling resistor and then grounded. The gate of the first NMOS transistor is connected to the cathode of the second coupling capacitor, and the anode of the second coupling capacitor is connected between the source of the second NMOS transistor and the second sampling resistor, and is connected to the inverted input signal in the fully differential signal. The gate of the second NMOS transistor is connected to the cathode of the first coupling capacitor, and the anode of the first coupling capacitor is connected between the source of the first NMOS transistor and the first sampling resistor, and is connected to the non-inverted input signal in the fully differential signal. The drain of the first NMOS transistor is connected to the first active load and outputs an inverted output signal, and the drain of the second NMOS transistor is connected to the second active load and outputs a non-inverted output signal.

[0010] Both the first and second active loads include a load PMOS transistor and a load NMOS transistor. The source of the load PMOS transistor and the drain of the load NMOS transistor are connected to the high-level output terminal of the drive power supply. The gate of the load PMOS transistor is connected to the source of the load NMOS transistor and connected to a bias current source. The drain of the load PMOS transistor is connected to the gate of the load NMOS transistor. The drain of the load PMOS transistor is the connection terminal.

[0011] In an optional embodiment, the common-gate amplification module further includes:

[0012] The gates of the third and fourth NMOS transistors are interconnected and connected to another bias current source. The drain of the third NMOS transistor is connected to the first active load, and the source is connected to the drain of the first NMOS transistor. The drain of the fourth NMOS transistor is connected to the second active load, and the source is connected to the drain of the second NMOS transistor.

[0013] In an optional embodiment, the signal demodulation circuit further includes:

[0014] The common-source common-gate amplifier module is located between the common-gate amplifier module and the demodulation module, and is used to amplify the fully differential signal after passing through the common-gate amplifier module;

[0015] The common-source common-gate module includes a third active load, a fourth active load, a fifth NMOS transistor, and a sixth NMOS transistor. The drain of the fifth NMOS transistor is connected to the third active load and outputs an inverted signal, while its gate is connected to a non-inverted input signal. Its source is connected to the source of the sixth NMOS transistor and connected to another bias current source. The drain of the sixth NMOS transistor is connected to the fourth active load and outputs a non-inverted signal, while its gate is connected to an inverted input signal.

[0016] Furthermore, the structures of the third and fourth active loads are the same as those of the first and second active loads.

[0017] In an optional embodiment, the common-source cascode amplifier module further includes:

[0018] The gates of the seventh and eighth NMOS transistors are connected to each other. The drain of the seventh NMOS transistor is connected to the third active load and outputs an inverted signal. Its source is connected to the drain of the fifth NMOS transistor. The drain of the eighth NMOS transistor is connected to the fourth active load and outputs a non-inverted signal. Its source is connected to the drain of the sixth NMOS transistor.

[0019] In an optional embodiment, the signal demodulation circuit further includes:

[0020] A band-stop filter module is positioned between the common-source cascode amplifier module and the demodulation module;

[0021] The band-stop filter module includes a first active capacitor, a second active capacitor, a first active resistor, a second active resistor, a first inductor, and a second inductor. The first active capacitor and the first active resistor are connected in series to form a first parallel circuit, the second active capacitor and the second active resistor are connected in series to form a second parallel circuit, the first parallel circuit and the second parallel circuit are connected in parallel and then connected in series with the first inductor to form a third parallel circuit, and the third parallel circuit is connected in parallel with the second inductor. The two ends of the first active capacitor are respectively connected to a positive input signal and an inverted input signal, the second active capacitor and the second active resistor are connected to output an inverted output signal, and the end of the first inductor connected to the second inductor is connected to output a positive output signal.

[0022] In an optional embodiment, the band-stop filter module further includes:

[0023] The three adder capacitors are a first adder capacitor, a second adder capacitor, and a third adder capacitor. The first adder capacitor is connected between the first active capacitor and the first active resistor. The second adder capacitor is connected between the first active capacitor and the second active capacitor. The third adder capacitor is connected between the second active capacitor and the second active resistor.

[0024] In an optional embodiment, the signal demodulation circuit further includes:

[0025] The common-mode stabilization module is located between the band-stop filter module and the demodulation module;

[0026] The common-mode stabilization module includes a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a first PMOS transistor, a second PMOS transistor, and a first capacitor. The drain of the ninth NMOS transistor is connected to another bias current source, and its gate is connected to the drain of the tenth NMOS transistor, the positive terminal of the first capacitor, and the gate of the eleventh NMOS transistor. Its source is connected to the source of the first PMOS transistor, and the gate of the ninth NMOS transistor is also connected to its own drain. The gate of the first PMOS transistor is connected to an inverted input signal, and its drain is connected to the source of the tenth NMOS transistor, the cathode of the first capacitor, the drain of the second PMOS transistor, and another bias current source. The gate of the tenth NMOS transistor is connected to its own drain. The drain of the eleventh NMOS transistor is connected to the high-level output terminal of the drive power supply, and its source is connected to the source of the second PMOS transistor, outputting a common-mode voltage signal. The gate of the second PMOS transistor is connected to a non-inverted input signal.

[0027] According to a second aspect, the present invention also provides a digital isolation circuit, comprising:

[0028] A modulation and transmission circuit is used to convert the received input signal into a fully differential signal;

[0029] The isolation module, connected to the modulation and transmission module, is used to transmit fully differential signals;

[0030] And the signal demodulation circuit in any of the embodiments of the first aspect above, the signal demodulation circuit being connected to the isolation module, for demodulating and outputting the fully differential signal.

[0031] The technical solution provided by this invention has the following advantages:

[0032] 1. The signal demodulation circuit provided by the present invention sets the amplification module before the demodulation module to a common-gate amplification module, and sets an active load to be used in the common-gate amplification module. The zero point generated by the load can enable the circuit to have a high gain at or near the carrier frequency fc, thereby widening the gain gap between the effective signal and noise, and making the circuit have better anti-interference capability.

[0033] Meanwhile, by setting an active load and inserting a load NMOS transistor with its source connected to the bias current source between the drain and gate of the load PMOS transistor (i.e., inserting an NMOS source follower), the voltage drop consumed on the active load can be reduced, increasing the output swing of the common-gate amplifier module. When a transient common-mode event occurs, the common-mode level of the signal will be suddenly raised or lowered. The instantaneous change in the common-mode level can easily cause the transistor to operate in the cutoff region at certain times, thus affecting the function of the overall circuit. Therefore, a larger circuit output swing can accommodate more common-mode transient events, further improving the anti-interference capability of the signal demodulation circuit.

[0034] 2. The signal demodulation circuit provided by this invention, by setting NMOS transistors (the third NMOS transistor and the fourth NMOS transistor) between the input and output signals of the common-gate amplifier module for isolation, can shield the Miller effect of parasitic capacitance in the active load to a certain extent, that is, reduce the influence of the active load on the main pole of the circuit, so that the subsequent circuit of the common-gate amplifier module can be designed independently and has a high gain at or near the carrier frequency fc. This allows the common-gate amplifier module and its subsequent circuit to be cascaded, resulting in even higher gain at or near the carrier frequency fc, further improving the anti-interference capability of the signal demodulation circuit.

[0035] 3. The signal demodulation circuit provided by the present invention attenuates noise components within a preset frequency range by setting a band-stop filter module, and effectively suppresses noise components near the center frequency when a shift occurs, thereby reducing the impact of noise on the function of subsequent circuits and further improving the anti-interference capability of the signal demodulation circuit.

[0036] Meanwhile, by setting the capacitors in the band-stop filter module to active capacitors with more precise capacitance values ​​(compared to passive components), and the resistors to active resistors with relatively more precise resistance values ​​(compared to passive components), the offset of the band-stop filter module when offset occurs can be reduced, ensuring the noise suppression function of the band-stop filter module is realized.

[0037] 4. The signal demodulation circuit provided by the present invention can improve the flexibility and accuracy of the attenuation frequency adjustment of the band-stop filter module by setting an adder (first adder capacitor, second adder capacitor and third adder capacitor) in the band-stop filter module (the attenuation frequency can also be adjusted by active resistor and inductor, but the adjustable range based on inductor is small, while the adjustment accuracy based only on active resistor is poor).

[0038] 5. The signal demodulation circuit provided by the present invention, by setting a common-mode stabilization module between the band-stop filter module and the demodulation module, can provide a relatively stable and suitable common-mode center level, further reducing the possibility of deviation in the final output common-mode level, thereby increasing the demodulation difficulty and the demodulation signal error, and improving the anti-interference capability of the signal demodulation circuit. Attached Figure Description

[0039] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of a signal demodulation circuit provided in an embodiment of the present invention;

[0041] Figure 2 This is a schematic diagram of a common-gate amplifier module provided in an embodiment of the present invention;

[0042] Figure 3 This is a schematic diagram of another signal demodulation circuit provided in an embodiment of the present invention;

[0043] Figure 4 This is a schematic diagram of a common-source cascode amplifier module provided in an embodiment of the present invention;

[0044] Figure 5 This is a schematic diagram of the structure of a band-stop filter module provided in an embodiment of the present invention;

[0045] Figure 6 This is a schematic diagram of a common-mode stabilization module provided in an embodiment of the present invention. Detailed Implementation

[0046] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] In the description of this invention, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0048] Example 1

[0049] Figure 1 This diagram illustrates the structure of a signal demodulation circuit in one embodiment of the present invention. Specifically, as shown... Figure 1 As shown, the signal demodulation circuit is located at the receiving end of the digital isolation circuit, that is, on the high-voltage side of the isolation module (such as an isolation capacitor), and is used to demodulate and output the fully differential signal transmitted by the isolation module.

[0050] like Figure 1As shown, the signal demodulation circuit includes a common-gate amplifier module and a demodulation module. The common-gate amplifier module is connected to the isolation module to receive the fully differential signal output by the isolation module in the digital isolation circuit and amplify the fully differential signal. The demodulation module is connected to the common-gate amplifier module to demodulate and output the amplified fully differential signal.

[0051] Specifically, the demodulation module can have any of the existing structures, and this embodiment does not limit it.

[0052] And such Figure 2 As shown, the common-gate amplifier module includes a first active load Q1, a second active load Q2, a first NMOS transistor MN1, a second NMOS transistor MN2, a first coupling capacitor C1, a second coupling capacitor C2, a first sampling resistor R1, and a second sampling resistor R2. The source of the first NMOS transistor MN1 is connected to the first sampling resistor R1 and then grounded; the source of the second NMOS transistor MN2 is connected to the second sampling resistor R2 and then grounded; the gate of the first NMOS transistor MN1 is connected to the cathode of the second coupling capacitor C2; the anode of the second coupling capacitor C2 is connected between the source of the second NMOS transistor MN2 and the second sampling resistor R2, and is connected to the inverted input signal VIN in the fully differential signal; the gate of the second NMOS transistor MN2 is connected to the cathode of the first coupling capacitor C1; the anode of the first coupling capacitor C1 is connected between the source of the first NMOS transistor MN1 and the first sampling resistor R1, and is connected to the non-inverted input signal VIP in the fully differential signal; the drain of the first NMOS transistor MN1 is connected to the first active load Q1 and outputs the inverted output signal VON; the drain of the second NMOS transistor MN2 is connected to the second active load Q2 and outputs the non-inverted output signal VOP.

[0053] At the same time, such as Figure 2 As shown, both the first active load Q1 and the second active load Q2 include a load PMOS transistor and a load NMOS transistor. The source of the load PMOS transistor and the drain of the load NMOS transistor are connected to the high-level output terminal of the drive power supply. The gate of the load PMOS transistor is connected to the source of the load NMOS transistor and connected to a bias current source. The drain of the load PMOS transistor is connected to the gate of the load NMOS transistor. The drain of the load PMOS transistor is the connection terminal. Specifically, as shown... Figure 2 As shown, the first active load Q1 includes a load PMOS transistor MQ1, a load NMOS transistor MQ2, and a bias current source I1, and the first active load Q2 includes a load PMOS transistor MQ3, a load NMOS transistor MQ4, and a bias current source I2.

[0054] Specifically, the gate control signals (bias1 and bias2) of the aforementioned common-gate amplifier module are equivalent to AC ground in the small-signal AC mode. After adding coupling capacitors (C1 and C2), the gate-source voltages of the first NMOS transistor MN1 and the second NMOS transistor MN2 increase to twice the original gate-source voltages. Therefore, the transconductance also changes and increases to twice its original value, thereby enabling signal amplification and reducing the demodulation difficulty of the demodulation module. Furthermore, based on the small-signal equivalent model of Q1 and Q2 and solving the transfer function, it can be found that Q1 and Q2 have one zero and two poles. Since the zero is always less than the sum of the two poles, the output waveform of the common-gate amplifier module will form a gain spike at the carrier signal fc or have a high gain near fc. This can widen the gain gap between the effective signal and noise, giving the signal demodulation circuit better anti-interference capability.

[0055] Meanwhile, the output terminals VON and VOP of the aforementioned common-gate amplifier module only consume the overdrive voltage drop of transistors MQ1 and MQ3 in terms of swing. Δ MQ1 Δ MQ3 (typically not exceeding 0.3mV) therefore has a larger output swing compared to existing circuits that use diode connections as loads; and since the gate-source capacitances of MQ1 and MQ3 are driven by source followers (MQ2 and MQ4), the load-related frequency response will be greater than the frequency response of existing diode connections as loads.

[0056] In addition, such as Figure 2 As shown, the common-gate amplifier module, based on the above structure, may further include a third NMOS transistor MN3 and a fourth NMOS transistor MN4. Specifically, the gates of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are interconnected and connected to another bias current source I3. The drain of the third NMOS transistor MN3 is connected to the first active load Q1 (specifically, to the drain of MQ1), and its source is connected to the drain of the first NMOS transistor MN1. The drain of the fourth NMOS transistor MN4 is connected to the second active load Q2 (specifically, to the drain of MQ2), and its source is connected to the drain of the second NMOS transistor MN2.

[0057] Specifically, the shielding characteristics of MN3 and MN4 can reduce the influence of active loads Q1 and Q2 on the main pole of the circuit. That is, they can shield the Miller effect of the parasitic capacitance of transistors MQ1 and MQ3 to a certain extent, so that the main pole of the common-gate amplifier module can be ignored or independent of frequency as much as possible. In this way, when the common-gate amplifier module is cascaded (such as cascaded with the common-source common-gate module described below), the offset of the main pole can be reduced, and the main pole is still provided by active loads Q1 and Q2. Finally, higher gain is achieved at or near the carrier frequency fc after cascading.

[0058] Figure 3A schematic diagram of the signal demodulation circuit in another embodiment of this invention is shown. Figure 3 As shown, the signal demodulation circuit also includes a common-source cascode amplifier module, which is located between the common-gate amplifier module and the demodulation module and is used to amplify the fully differential signal that has passed through the common-gate amplifier module.

[0059] like Figure 4 As shown, the common-source common-gate amplifier module includes a third active load Q3, a fourth active load Q4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6. The drain of the fifth NMOS transistor MN5 is connected to the third active load Q3, outputting an inverted output signal VON. Its gate is connected to a non-inverted input signal VIP. Its source is connected to the source of the sixth NMOS transistor MN6 and then to another bias current source I4. The drain of the sixth NMOS transistor MN6 is connected to the fourth active load Q4, outputting a non-inverted output signal VOP. Its gate is connected to an inverted input signal VIN. The structures of the third active load Q3 and the fourth active load Q4 are the same as those of the first active load Q1 and the second active load Q2. Specifically, as shown... Figure 4 As shown, the third active load Q3 includes a load PMOS transistor MQ5, a load NMOS transistor MQ6, and a bias current source I5, and the fourth active load Q4 includes a load PMOS transistor MQ7, a load NMOS transistor MQ8, and a bias current source I6.

[0060] In addition, such as Figure 4 As shown, the common-source common-gate amplifier module, based on the above structure, may further include a seventh NMOS transistor MN7 and an eighth NMOS transistor MN8. The gates of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are interconnected. The drain of the seventh NMOS transistor MN7 is connected to the third active load Q3 (specifically, the drain of the load PMOS transistor MQ5) and outputs an inverted output signal VON. Its source is connected to the drain of the fifth NMOS transistor MN5. The drain of the eighth NMOS transistor MN8 is connected to the fourth active load Q4 (specifically, the drain of the load PMOS transistor MQ7) and outputs a non-inverted output signal VOP. Its source is connected to the drain of the sixth NMOS transistor MN6.

[0061] Figure 3 A schematic diagram of the signal demodulation circuit in another embodiment of this invention is also shown. Figure 3 As shown, the signal demodulation circuit may also include a band-stop filter module, which is located between the common-source cascode amplifier module and the demodulation module.

[0062] like Figure 5As shown, the band-stop filter module includes a first active capacitor C1, a second active capacitor C2, a first active resistor R3, a second active resistor R4, a first inductor L1, and a second inductor L2. The first active capacitor C1 and the first active resistor R3 are connected in series to form a first parallel circuit. The second active capacitor C2 and the second active resistor R4 are connected in series to form a second parallel circuit. The first and second parallel circuits are connected in parallel and then connected in series with the first inductor L1 to form a third parallel circuit. The third parallel circuit is connected in parallel with the second inductor L2. The two ends of the first active capacitor C1 are respectively connected to a positive input signal VIN and an inverted input signal VIP (specifically, one end of the first active capacitor C1 connected to the first active resistor R3 is connected to the positive input signal VIN, and the other end is connected to the inverted input signal VIP). The second active capacitor C2 and the second active resistor R4 are connected to output an inverted output signal VON. The end of the first inductor L1 connected to the second inductor L2 is connected to output a positive output signal VOP.

[0063] Specifically, the active circuit structure of the first active capacitor C1, the second active capacitor C2, the first active resistor R3, and the second active resistor R4 can be any existing type. Figure 5 The circuit structure shown is just one example.

[0064] Specifically, the attenuation frequency range of the above-mentioned band-stop filter module can be adjusted by adjusting the resistance value of the first active resistor R3, the resistance value of the second active resistor R4, the inductance value of the first inductor L1, or the inductance value of the second inductor L2.

[0065] However, since the adjustable range of the attenuation frequency range based on the inductance values ​​of the first inductor L1 and the second inductor L2 is small, and the adjustment accuracy based solely on the resistance values ​​of the first active resistor R3 and the second active resistor R4 is poor (the adjustment capability of the first active capacitor C1 and the second active capacitor C2 is even smaller and can be ignored in practical applications), this embodiment also provides a band-stop filter module in another implementation, such as... Figure 5 As shown, the band-stop filter module may further include a first adder capacitor Cc1, a second adder capacitor Cc2, and a third adder capacitor Cc3. The first adder capacitor Cc1 is connected between the first active capacitor C1 and the first active resistor R3. The second adder capacitor Cc2 is connected between the first active capacitor C1 and the second active capacitor C2. The third adder capacitor Cc3 is connected between the second active capacitor C2 and the second active resistor R4. Because the first adder capacitor Cc1, the second adder capacitor Cc2, and the third adder capacitor Cc3 have a wide range of values, the adder formed by these three capacitors can fully adjust the attenuation frequency range of the band-stop filter module. Furthermore, their synergistic effect with the first active resistor R3 and the second active resistor R4 improves the adjustment accuracy.

[0066] Figure 3 A schematic diagram of the signal demodulation circuit in another embodiment of this invention is also shown. Figure 3 As shown, the signal demodulation circuit may also include a common-mode stabilization module, which is located between the band-stop filter module and the demodulation module.

[0067] like Figure 6 As shown, the common-mode stabilization module includes a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a first PMOS transistor MP1, a second PMOS transistor MP2, and a first capacitor C3. The drain of the ninth NMOS transistor MN9 is connected to another bias current source I7, and its gate is connected to the drain of the tenth NMOS transistor MN10, the positive terminal of the first capacitor C3, and the gate of the eleventh NMOS transistor MN11. Its source is connected to the source of the first PMOS transistor MP1, and the gate of the ninth NMOS transistor MN9 is also connected to its own drain. Connections: The gate of the first PMOS transistor MP1 is connected to the inverted input signal VIN, and its drain is connected to the source of the tenth NMOS transistor MN10, the cathode C3 of the first capacitor, the drain of the second PMOS transistor MP2, and another bias current source I8; the gate of the tenth NMOS transistor MN10 is connected to its own drain; the drain of the eleventh NMOS transistor MN11 is connected to the high-level output terminal of the drive power supply, and its source is connected to the source of the second PMOS transistor MP2, and outputs a common-mode voltage signal VCM; the gate of the second PMOS transistor MP2 is connected to the non-inverted input signal VIP.

[0068] Specifically, although the active loads (Q1-Q4) of the aforementioned common-gate amplifier module and cascode amplifier module are weak current mirrors, theoretically the overall circuit itself does not have the problem of common-mode instability caused by common-mode point interference. Therefore, the output common-mode level of each node can be directly provided by the active load without the need for external common-mode stabilization. However, in practical applications, errors may occur during layout matching and manufacturing processes that lead to deviations in the final output common-mode level. This results in an unstable common-mode level of the signal output to the demodulation module, making the demodulation process more difficult. The aforementioned common-mode stabilization module is designed to address this issue, ultimately providing a relatively stable and suitable common-mode center level for the demodulation module.

[0069] Specifically, the common-mode stabilization module extracts or injects current related to the differential signal pair (VIN and VIP) transmitted from the preamplifier module, thereby maintaining a stable common-mode center level VCM. The first PMOS transistor MP1, the ninth NMOS transistor MN9, and the bias current source I7 form the bias circuit. Its output impedance is the parallel impedance seen from the sources of the second PMOS transistor MP2 and the eleventh NMOS transistor MN11, making it a low-impedance output stage. The bias circuit sets the common-mode voltage VCM approximately to the gate-to-source voltage of the second PMOS transistor MP2 to allow for a directional swing margin at the input of the demodulation module.

[0070] Example 2

[0071] Figure 1 and Figure 3 A schematic diagram of the digital isolation circuit in this embodiment is shown, as follows: Figure 1 and Figure 3 As shown, the digital isolation circuit includes a modulation and transmission circuit, an isolation module, and a signal demodulation circuit in any of the embodiments of Example 1 above. The modulation and transmission circuit is used to convert the received input signal into a fully differential signal. The isolation module is connected to the modulation and transmission module and is used to transmit the fully differential signal. The signal demodulation circuit is connected to the isolation module and is used to demodulate the fully differential signal and output it.

[0072] Specifically, the specific structure of the modulation and transmission circuit, the isolation module, and the demodulation module in the signal demodulation circuit can be any of the existing structures, and this embodiment does not limit them.

[0073] The digital isolation circuit in this embodiment has a high anti-interference capability.

[0074] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A signal demodulation circuit, characterized in that, The receiving end of the digital isolation circuit includes: A common-gate amplifier module is used to receive the fully differential signal output by the isolation module in the digital isolation circuit and amplify the fully differential signal. The demodulation module, connected to the common-gate amplifier module, is used to demodulate and output the amplified fully differential signal; The common-gate amplifier module includes a first active load, a second active load, a first NMOS transistor, a second NMOS transistor, a first coupling capacitor, a second coupling capacitor, a first sampling resistor, and a second sampling resistor. The source of the first NMOS transistor is connected to the first sampling resistor and then grounded, and the source of the second NMOS transistor is connected to the second sampling resistor and then grounded. The gate of the first NMOS transistor is connected to the cathode of the second coupling capacitor, and the anode of the second coupling capacitor is connected between the source of the second NMOS transistor and the second sampling resistor, and is connected to the inverted input signal in the fully differential signal. The gate of the second NMOS transistor is connected to the cathode of the first coupling capacitor, and the anode of the first coupling capacitor is connected between the source of the first NMOS transistor and the first sampling resistor, and is connected to the non-inverted input signal in the fully differential signal. The drain of the first NMOS transistor is connected to the first active load and outputs an inverted output signal, and the drain of the second NMOS transistor is connected to the second active load and outputs a non-inverted output signal. Both the first active load and the second active load include a load PMOS transistor and a load NMOS transistor. The source of the load PMOS transistor and the drain of the load NMOS transistor are both connected to the high-level output terminal of the driving power supply. The gate of the load PMOS transistor is connected to the source of the load NMOS transistor and connected to a bias current source. The drain of the load PMOS transistor is connected to the gate of the load NMOS transistor. The drain of the load PMOS transistor is the connection terminal.

2. The signal demodulation circuit according to claim 1, characterized in that, The common-gate amplification module also includes: The third and fourth NMOS transistors have their gates interconnected and connected to another bias current source. The drain of the third NMOS transistor is connected to the first active load, and its source is connected to the drain of the first NMOS transistor. The drain of the fourth NMOS transistor is connected to the second active load, and its source is connected to the drain of the second NMOS transistor.

3. The signal demodulation circuit according to claim 1 or 2, characterized in that, Also includes: A common-source common-gate amplifier module is disposed between the common-gate amplifier module and the demodulation module, and is used to amplify the fully differential signal that has passed through the common-gate amplifier module; The common-source common-gate module includes a third active load, a fourth active load, a fifth NMOS transistor, and a sixth NMOS transistor. The drain of the fifth NMOS transistor is connected to the third active load and outputs an inverted signal, while its gate is connected to a non-inverted input signal. Its source is connected to the source of the sixth NMOS transistor and connected to another bias current source. The drain of the sixth NMOS transistor is connected to the fourth active load and outputs a non-inverted signal, while its gate is connected to an inverted input signal. Furthermore, the structures of the third and fourth active loads are the same as those of the first and second active loads.

4. The signal demodulation circuit according to claim 3, characterized in that, The common-source, common-gate amplifier module further includes: The gates of the seventh and eighth NMOS transistors are connected to each other. The drain of the seventh NMOS transistor is connected to the third active load and outputs an inverted signal. Its source is connected to the drain of the fifth NMOS transistor. The drain of the eighth NMOS transistor is connected to the fourth active load and outputs a non-inverted signal. Its source is connected to the drain of the sixth NMOS transistor.

5. The signal demodulation circuit according to claim 3, characterized in that, Also includes: A band-stop filter module is disposed between the common-source cascode amplifier module and the demodulation module; The band-stop filter module includes a first active capacitor, a second active capacitor, a first active resistor, a second active resistor, a first inductor, and a second inductor. The first active capacitor and the first active resistor are connected in series to form a first parallel circuit, the second active capacitor and the second active resistor are connected in series to form a second parallel circuit, the first parallel circuit and the second parallel circuit are connected in parallel and then connected in series with the first inductor to form a third parallel circuit, and the third parallel circuit is connected in parallel with the second inductor. The two ends of the first active capacitor are respectively connected to a positive input signal and an inverted input signal, the second active capacitor and the second active resistor are connected to output an inverted output signal, and the end of the first inductor connected to the second inductor is connected to output a positive output signal.

6. The signal demodulation circuit according to claim 5, characterized in that, The band-stop filter module further includes: The system comprises a first adder capacitor, a second adder capacitor, and a third adder capacitor. The first adder capacitor is connected between the first active capacitor and the first active resistor. The second adder capacitor is connected between the first active capacitor and the second active capacitor. The third adder capacitor is connected between the second active capacitor and the second active resistor.

7. The signal demodulation circuit according to claim 5, characterized in that, Also includes: A common-mode stabilization module is disposed between the band-stop filter module and the demodulation module; The common-mode stabilization module includes a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a first PMOS transistor, a second PMOS transistor, and a first capacitor. The drain of the ninth NMOS transistor is connected to another bias current source, its gate is connected to the drain of the tenth NMOS transistor, the positive terminal of the first capacitor, and the gate of the eleventh NMOS transistor, and its source is connected to the source of the first PMOS transistor. The gate of the ninth NMOS transistor is also connected to its own drain. The gate of the first PMOS transistor is connected to an inverting input signal, and its drain is connected to the source of the tenth NMOS transistor, the cathode of the first capacitor, the drain of the second PMOS transistor, and the other bias current source. The gate of the tenth NMOS transistor is connected to its own drain. The drain of the eleventh NMOS transistor is connected to the high-level output terminal of the driving power supply, and its source is connected to the source of the second PMOS transistor, outputting a common-mode voltage signal. The gate of the second PMOS transistor is connected to a non-inverting input signal.

8. A digital isolation circuit, characterized in that, include: A modulation and transmission circuit is used to convert the received input signal into a fully differential signal; An isolation module, connected to the modulation and transmission circuit, is used to transmit the fully differential signal; And the signal demodulation circuit according to any one of claims 1-7, wherein the signal demodulation circuit is connected to the isolation module and is used to demodulate and output the fully differential signal.

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