An oFEC decoding system for the next generation optical fiber communication standard

Abstract

The present invention provides an oFEC decoding system for the next generation optical fiber communication standard, including an oFEC code decoder, wherein the oFEC code decoder follows a single instruction multiple data SIMD process, that is, P BCH subcodes are decoded under each instruction, where P is the degree of parallelism. Based on the idea of ​​SIMD, the system derives that the position of the oFEC code in the memory follows a certain rule, and then effectively solves the structural hazard problem in the decoding process by using two completely identical odd and even dual-port memories; and solves the data hazard problem during decoding output by additional hardware overhead. The above means avoid pipeline pauses and improve throughput.

Description

Technical Field

[0001] The present invention relates to an oFEC decoding system oriented to the next generation optical fiber communication standard. Background Art

[0002] Fiber-optic communication is a key component of modern communication systems. Its huge throughput perfectly meets the needs of contemporary Internet communications. In order to ensure the reliability of such a large amount of transmitted data, forward error correction code (FEC) plays a vital role in fiber-optic communication. Error correction code is also called error control coding, also known as channel coding. Its purpose is to overcome the interference of channel noise on transmitted data. The receiving end can correct errors in the received information by itself through a decoding algorithm. The realization of the error correction function requires redundancy as a cost, sacrificing valid data and improving the reliability of data transmission. More redundancy means higher error correction capability.

[0003] At present, the standardization of 400G optical fiber communication system has been completed, and the next generation 800G optical fiber communication has also entered the research stage. The 400G optical fiber communication standard 400ZR has been proposed. The error correction code used in the 400G optical fiber communication system is the staircase code, which can provide a throughput of up to 400Gbps. With the continuous deepening of the research on 400G optical fiber communication system, and the advent and commercialization of related products, the next generation optical fiber communication system with a throughput of up to 800Gbps has attracted widespread attention. At present, the Open ROADM standardization work proposes that the error correction code used in the next generation optical fiber communication standard is the oFEC code, which is essentially a convolutional code with the BCH code as a subcode. BCH decoding algorithms include the Berlekamp-Massey (BM) algorithm, the Euclidean algorithm, the Peterson-Gorenstein-Zierler (PGZ) algorithm, etc. Among them, the Peterson algorithm is suitable for BCH codes with low error correction capabilities.

[0004] The existing optical fiber communication system adopts the design proposed in the 400ZR standard. The error correction code used in this system is the staircase code. In the current public design (reference: Truhachev D, El-Sankary K, Karami A, et al. Efficient Implementation of 400Gbps Optical Communication FEC [J]. Circuits and Systems I: Regular Papers, IEEE Transactions on, 2020, PP (99)), the maximum throughput that the staircase code decoder can achieve is 511Gbps, which cannot meet the throughput requirements of the next generation of optical fiber communications. Summary of the invention

[0005] Purpose of the invention: The technical problem to be solved by the present invention is to provide an oFEC decoding system for the next generation optical fiber communication standard in view of the deficiencies in the prior art, including an oFEC code decoder. The oFEC code decoder follows a single instruction multiple data SIMD process, that is, P BCH subcodes are decoded under each instruction, where P is the degree of parallelism.

[0006] The oFEC code decoder includes a memory, a BCH decoder, an input transposition module and an output transposition module;

[0007] The oFEC code decoder completes the decoding process by the following operations:

[0008] Read rd operation: The input of the oFEC code decoder is P rows of the oFEC code, which is also the second half of the P BCH code words; at the same time, the first half of the P BCH code words are read out from the memory; the first half of the P BCH code words are in storage format, and the second half are in decoding format;

[0009] Input transposition tp operation: The input transposition module converts the first half of the BCH codeword in the storage format of the input into a format output for decoding by the decoder, and directly splices it with the second half of the BCH codeword into P complete BCH codewords for decoding;

[0010] Decoding dec operation: BCH decoder decodes the BCH codeword;

[0011] Output transpose tb operation: The output transpose module converts the BCH codewords of the output BCH decoder into storage format after decoding;

[0012] Write wr operation: write the BCH codeword in storage format into the memory;

[0013] Output out operation: The decoded oFEC P rows are read out from the memory as output.

[0014] The throughput θ of the oFEC decoder is defined by the following formula:

[0015]

[0016] Where T is the clock cycle, CPI represents the clock cycle of each instruction, N is the number of bits in one row of oFEC code, and Rate is the code rate of BCH code.

[0017] The memory is composed of two identical dual-port memories, which are called odd and even. One port of the dual-port memory is used for read rd operation, and the other port is used for write wr operation.

[0018] The memory adopts a forwarding technology, that is, a selector is used to output in advance the data output by the output transposition module that may generate a data hazard with the data read out of the memory.

[0019] The input transposition module is used to take the bits of the first half of the BCH codeword out of the memory, transpose them, and then splice them with the second half of the input oFEC decoder;

[0020] The output transposition module is used to transpose the bits of the second half of the BCH codeword after decoding and put it back to the position where the first half of the BCH codeword is taken out in the memory.

[0021] The input transposition module converts the data in the two-dimensional storage format into the data in the one-dimensional decoding format, and the output transposition module converts the data in the one-dimensional decoding format into the data in the two-dimensional storage format. The transposition operation is directly implemented through hardware routing, specifically, the elements in the two-dimensional binary matrix are connected to the corresponding positions of the one-dimensional vector through routing. The formula is as follows:

[0022]

[0023] Since the matrix is ​​binary, the parameter a i ,b i ,…,d i Both are 0 or 1, 0≤i≤n-1.

[0024] The BCH decoder is designed based on the Peterson algorithm, and can complete the decoding of the entire BCH code in one cycle, and a first-level pipeline is inserted into the BCH decoder.

[0025] The present invention is aimed at the codeword open Forward Error Correction (oFEC) code adopted by the next generation 800G high-speed optical fiber communication system proposed in the Open Reconfigurable Optical Add / Drop Multiplexers (ROADM) standardization work, and based on pipeline technology and Single Instruction Multiple Data (SIMD) technology, a decoding architecture of oFEC code with a throughput exceeding 800Gbps is realized. However, the pipeline implementation of the decoder will bring about transposition hazard, structural hazard and data hazard problems. The present invention solves the above-mentioned hazard problems respectively through data dimensionality reduction and hardware wiring, storage parity block and forwarding technology.

[0026] The present invention designs a corresponding decoder based on the solution proposed in Open ROADM. Compared with the 400G optical fiber communication system, it adopts a brand-new oFEC error correction code. Compared with staircase, oFEC adopts a completely different decoding strategy, and the architecture described in the present invention can achieve a throughput of over 800Gbps, meeting the throughput requirements of the next generation of optical fiber communication.

[0027] The present invention has the following beneficial effects:

[0028] (1) The present invention proposes an oFEC code decoding system with a throughput of up to 800 Gbps. Based on the SIMD concept, the system divides the decoding process into five stages: rd, td, dt, wr, and out, and introduces pipeline technology to improve the throughput;

[0029] (2) An efficient data storage format and transposition scheme are proposed. The two-dimensional data is reduced to one dimension for easy storage. For small-scale one-dimensional data, the transposition operation is directly implemented using hardware routing, avoiding transposition risks and reducing hardware overhead.

[0030] (3) An efficient decoding storage strategy is proposed. The present invention deduces that the position of the oFEC code in the memory follows a certain rule, and then uses two completely identical odd and even dual-port memories to effectively solve the structural hazard problem in the decoding process; and solves the data hazard problem during decoding output through additional hardware overhead. The above means avoid pipeline pauses and improve throughput. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more clear.

[0032] Figure 1This is a schematic diagram of an oFEC codeword.

[0033] Figure 2 It is a schematic diagram of the single-cycle decoding architecture of the oFEC code.

[0034] Figure 3 It is a pipelined decoding flow chart.

[0035] Figure 4 is with Figure 3 The corresponding reading and writing diagrams of the parity memory in the 4th and 5th cycles. DETAILED DESCRIPTION

[0036] 1. oFEC code basics and its encoding and decoding algorithm

[0037] First, the oFEC code used in the present invention is introduced. The oFEC code is a convolutional code with the BCH code as a subcode. The codeword in the oFEC is a semi-infinite bit set stored in a matrix with a semi-infinite number of rows and N columns. This semi-infinite matrix can be divided into many blocks of size B×B, such as Figure 1 As shown, each block stores B bits per row and B bits per column. Each row of the matrix has N / B such blocks, and each block is identified by a block row number R and a block column number C (0≤C<N / B), which appear in Figure 1 The left and top of the large matrix. Each bit in the block is identified by its row number r and column number c, where 0≤r<B, 0≤c<B. In general, each bit in this semi-infinite matrix can be identified by the four-element array {R, r, C, c}.

[0038] Each row of the matrix consists of K information bits and NK parity bits. Because oFEC is a convolutional code, the NK parity bits are determined not only by the K information bits in the current row, but also by the N specific bits in the previous row. The N bits from the previous row and the N bits in the current row together form a (2N, N+K) BCH subcode. A row of bits in the oFEC code is identified by the binary array {R,r} or the formula RB+r, both of which contain a block row number R and a bit row number r. A BCH codeword can be identified by the number of rows containing all the bits in the second half of the codeword. The i-th bit of the BCH codeword {R,r} can be identified by the quaternary array {R(i),r(i),C(i),c(i)}. Where R(i) represents the position function of the row value of the block where the i-th bit is located in the entire semi-infinite matrix with respect to i, C(i) represents the position function of the column value of the block where the i-th bit is located in the entire semi-infinite matrix with respect to i, r(i) represents the position function of the row value of the i-th bit inside the block with respect to i, and c(i) represents the position function of the column value of the i-th bit inside the block with respect to i;

[0039] For the second half of the BCH codeword (N≤i<2N), the position function is:

[0040] R(i)=R(1)

[0041] r(i)=r (2)

[0042]

[0043] c(i)=(k%B)⊕t (4)

[0044] For the first half of the BCH codeword (0≤i<N), the position function is:

[0045]

[0046] r(i)=(k%B)⊕r (6)

[0047]

[0048] c(i)=r (8)

[0049] Among them, % represents the modulo operation, Indicates rounding down, and ⊕ indicates the XOR operation.

[0050] The encoding and decoding process of oFEC adopted by the present invention is introduced below.

[0051] oFEC encoding is based on a coding window, such as Figure 1First, K bits are input to the input port, and these K bits are combined with the N bits taken from the previous block (such as Figure 1 As shown, in the previous block, the bits are taken by column, and the specific bits are given by the position function of the first half of the BCH codeword) to form the N+K information bits of BCH, and then BCH encoding is performed, and the K input bits and the NK check bits obtained by encoding are placed in the current row (the specific location of each bit is given by the position function of the second half of the BCH codeword). Figure 1 As shown, bits belonging to the same BCH codeword are marked with the same pattern, for example, Figure 1 The bits in the previous row of bold vertical dashed boxes and the bits in the current row of bold horizontal dashed boxes are sequentially concatenated to form a (2N, N+K) BCH code. Each round of encoding will fill up two rows of blocks. If the current encoding window is filled, the encoding window will slide down, freeing up new rows of blocks. The data outside the window will no longer be saved, and the encoding will be based on the data in the new window. For example, Figure 1 The black thick rectangle is the encoding window of the previous moment. When the blocks in the last row are filled, the window slides down. The new encoding window is marked by the dotted rectangle in the figure. At this time, a new row is freed and the next round of encoding continues until it is filled. Generally speaking, the memory block row address a is calculated by the following formula R :

[0052] a R =(R+W)%(W+2) (9)

[0053] Where W+2 is the size of the window, and W is an even number.

[0054] The decoding process of oFEC can be regarded as the inverse process of the encoding process. The decoding process is also based on a decoding window of the same size as the encoding window. The decoder receives the newly input bit sequence and the bits of the previous row to form a complete BCH code, and then performs BCH decoding. The decoded bits of the previous row are stored back to the position where they were taken out, and the decoded newly input bit sequence is stored in the row block at the bottom of the window. Finally, the window slides down, freeing up a new row block, ready to receive a new bit sequence to start the next round of decoding, and the bits that are no longer included in the window due to sliding are used as the output of the oFEC code.

[0055] 2. oFEC code decoder

[0056] The oFEC code single cycle decoding architecture proposed by the present invention is as follows Figure 2As shown, it includes a memory, a BCH decoder and two transposition modules. The decoder follows the "Single Instruction Multiple Data (SIMD)" process, that is, P code words are decoded under each instruction, where P is the parallelism. The present invention divides the decoding process of the oFEC code into 6 operations:

[0057] (1) Read (rd) operation: The input is the P rows of the oFEC code, which is also the second half of the P BCH codewords. At the same time, the first half of the P BCH codewords is read from the memory. The first half of the P BCH codewords is now in the storage format, and the second half is in the decoding format.

[0058] (2) Input transposition (tp) operation: The input transposition module converts the first half of the BCH codeword in the storage format into a format that is convenient for the decoder to decode, and directly concatenates it with the second half of the BCH codeword into P complete BCH codewords for decoding.

[0059] (3) Decoding (dec) operation: The BCH decoder decodes the BCH codeword.

[0060] (4) Output transpose (tb) operation: The decoded BCH codeword is converted back to the storage format.

[0061] (5) Write (wr) operation: Write the BCH codeword in the storage format into the memory.

[0062] (6) Output (out) operation: The decoded oFEC P rows are read out from the memory as output.

[0063] The throughput θ of the oFEC decoder is defined by the following formula:

[0064]

[0065] Where T is the clock cycle, CPI represents the clock cycle of each instruction, and Rate is the code rate of the BCH code. For the single-cycle decoder proposed in the present invention, the value of CPI is 1. In order to improve the throughput, the present invention adopts pipeline technology. In order to reduce the critical path, the present invention inserts a pipeline in the BCH decoder to divide the decoding (dec) instruction into two parts, which are respectively combined with the input transposition (tp) and output transposition (tb) operations, and are marked with td and dt instructions. The working timing of the entire decoder is as follows Figure 2 and Figure 3 As shown, 5 cycles are required to complete the rd, td, dt, wr and out instructions.

[0066] The application of the pipeline in the present invention causes transposition hazard, structure hazard and data hazard in the decoding process, which may cause pipeline pause and reduce throughput. In view of these potential risks, the present invention has made a special design to avoid them. The various parts of the oFEC code decoder in the present invention are described below.

[0067] Memory:

[0068] Before BCH decoding, the BCH codeword needs to be read from the memory, and after BCH decoding is completed, the decoded codeword needs to be written back to the memory. Due to the decoding characteristics of the oFEC code, two groups of codewords need to be read from the memory at the same time and the two groups of decoded codewords need to be written to the memory. Therefore, the memory needs to be read and written twice at the same time, which requires a true four-port memory to achieve, which will cause a larger area overhead. If a dual-port memory is used, it will cause the same address of the memory to be read and written at the same time, that is, a structural hazard will occur. However, for oFEC codewords, the memory access during the BCH decoding process has the following two theorems:

[0069] Theorem 1: If the second half of a BCH codeword is located in an even (odd) block row, then the first half of a BCH codeword is located in an odd (even) block row;

[0070] Theorem 2: If the second half of a BCH codeword is located at an even (odd) memory address, then the first half of the BCH codeword is located at an odd (even) memory address.

[0071] The proof is as follows:

[0072] The block rows of the first half and the second half (the first half and the second half are divided into two equal parts) of the BCH codeword are set to R1(i) and R2(i) respectively, and the number of block rows in the two parts is equal. From formulas (1) and (5), we can get: R2(i)=R. Performing modulo 2 operation on these two equations, we can get R1(i)%2=(R⊕1)%2, R2(i)%2=R%2. Therefore, if R2 is even (odd), then R is even (odd). Therefore, R⊕1 is odd (even), and then, R1(i) is odd (even). Assuming the memory addresses of the first half and the second half of the BCH codeword are a1(i) and a2(i) respectively, it can be seen from equation (9) that a1(i)=(R1(i)+W)%(W+2), a2(i)=(R2(i)+W)%(W+2). Performing modulo 2 operation on a1(i), since W is an even number, we can get a1(i)%2=R1(i)%2, a2(i)%2=R2(i)%2. Therefore, while satisfying Theorem 1, if a2(i) is an even number (odd number), then a1(i) is an odd number (even number).

[0073] According to the above theorem, the present invention divides the memory into two blocks, odd and even, which can solve the structural hazard. Figure 4 The figure shows the memory read and write status during the 4th and 5th cycles. Figure 4 The pattern and Figure 3 In the present invention, the dual-port memory is mainly considered, one port is used for read (rd) operation, and the other port is used for write (wr) operation, so when r and w appear in the same storage block at the same time, no conflict will occur.

[0074] In addition, even if the storage is divided into blocks, there is still Figure 4 The situation of simultaneous reading and writing of the same address shown in the black thick rectangle in the even block when the number of cycles is 4. In cycle 4, for I0, the data at address 0 (filled with vertical lines) in the even memory block is read out as output. However, the data at address 0 in the memory block at C=0 (marked by the black thick rectangle) has not been updated, and a data hazard occurs. The present invention adopts forwarding technology to solve the data hazard problem by adding additional hardware. Figure 3 As shown in the black thick rectangle, the decoded data in the dt period of I1 is forwarded to the output of I0. The hardware architecture with forwarding is as follows Figure 2 As shown, the hardware overhead is approximately one selector.

[0075] Transpose module:

[0076] There are two transposition modules in the system designed by the present invention: an input transposition (tp) module and an output transposition (tb) module. As described in the basic part of the oFEC code, when taking out a BCH codeword from the memory, it is necessary to read the first half and the second half of a BCH code at the same time. The first half is arranged in columns in the memory, and the second half is arranged in rows in the memory; similarly, after the BCH decoding is completed, the decoded codeword needs to be put back in the same way. For the same block of memory, there can only be one organization method, either by row or by column. Therefore, it is necessary to take out the bits of the first half of the BCH codeword, transpose them, and then splice them with the second half before decoding; similarly, after decoding, the bits of the first half need to be transposed and put back. The present invention reduces the two-dimensional data in a block to one dimension, so it can be conveniently stored in a unit of the memory, and the transposition operation is directly implemented through hardware wiring. Since the scale of the transposed bit matrix is ​​small, it will not generate excessive overhead. The transposition methods of taking out and putting back are consistent. Theoretically, the same transposition circuit can be used. However, due to the existence of the pipeline, the transposition module will be preempted. Therefore, the present invention avoids the transposition risk by adding the same hardware and designs two transposition modules: input transposition (tp) and output transposition (tb).

[0077] BCH decoder:

[0078] Since the BCH code used in the oFEC codeword has a small error correction capability and a short code length, in order to reduce the number of clock cycles for decoding a single codeword, the BCH decoder used in the present invention is designed based on the Peterson algorithm, and the decoding of the entire BCH code can be completed in one cycle. In order to reduce the critical path, a first-level pipeline is inserted in the BCH decoder.

[0079] The present invention is based on the above module design, so that the introduction of the pipeline will not cause pauses and risks, and the CPI reaches 1.

[0080] Example:

[0081] Take the oFEC code based on eBCH (256, 239) as an example. N = 128, B = 16, that is, the size of each block is 16*16. The number of rows in the decoding window is W+2=22, and the number of columns is N / B=128 / 16=8. The degree of parallelism is P=32, that is, the BCH codes of two rows of blocks are decoded each time. According to the storage strategy of the present invention, the storage block is divided into two odd and even blocks, each block is 11*8 in size, and is composed of 8 RAMs with a width of 16*16=256 and a depth of 11. The SMIC 28nm process is used for comprehensive simulation, and the obtained results are compared with the 400G staircase solution proposed in the paper "Truhachev D, El-Sankary K, Karami A, et al. Efficient Implementation of 400Gbps Optical Communication FEC[J]. Circuits and Systems I: Regular Papers, IEEE Transactions on, 2020, PP(99)". The results are shown in Table 1:

[0082] Table 1

[0083]

[0084] The present invention provides an oFEC decoding system for the next generation optical fiber communication standard. There are many methods and ways to implement the technical solution. The above is only a preferred implementation of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention. All components not specified in this embodiment can be implemented by existing technologies.

Claims

1. An oFEC decoding system for the next generation optical fiber communication standard, characterized in that: The oFEC code decoder includes an oFEC code decoder, which follows a single instruction multiple data SIMD process, that is, P BCH subcodes are decoded under each instruction, where P is the degree of parallelism; The oFEC code decoder includes a memory, a BCH decoder, an input transposition module and an output transposition module; The oFEC code decoder completes the decoding process by the following operations: Read rd operation: The input of the oFEC code decoder is P rows of the oFEC code, which is also the second half of the P BCH code words; at the same time, the first half of the P BCH code words are read out from the memory; the first half of the P BCH code words are in storage format, and the second half are in decoding format; Input transposition tp operation: The input transposition module converts the first half of the BCH codeword in the storage format of the input into a format output for decoding by the decoder, and directly splices it with the second half of the BCH codeword into P complete BCH codewords for decoding; Decoding dec operation: BCH decoder decodes the BCH codeword; Output transpose tb operation: The output transpose module converts the BCH codewords of the output BCH decoder into storage format after decoding; Write wr operation: write the BCH codeword in storage format into the memory; Output out operation: The decoded oFEC P rows are read out from the memory as output.

2. The system according to claim 1, characterized in that The throughput θ of the oFEC code decoder is defined by the following formula: Where T is the clock cycle, CPI represents the clock cycle of each instruction, N is the number of bits in one row of oFEC code, and Rate is the code rate of BCH code.

3. The system according to claim 2, characterized in that The memory is composed of two identical dual-port memories, which are called odd and even. One port of the dual-port memory is used for read rd operation, and the other port is used for write wr operation.

4. The system according to claim 3, characterized in that The memory adopts a forwarding technology, that is, a selector is used to output in advance the data output by the output transposition module that may generate a data hazard with the data read out of the memory.

5. The system according to claim 4, characterized in that The input transposition module is used to take the bits of the first half of the BCH codeword out of the memory, transpose them, and then splice them with the second half of the input oFEC code decoder; The output transposition module is used to transpose the bits of the second half of the BCH codeword after decoding and put it back to the position where the first half of the BCH codeword is taken out in the memory.

6. The system according to claim 5, characterized in that The input transposition module converts the data in the two-dimensional storage format into the data in the one-dimensional decoding format, and the output transposition module converts the data in the one-dimensional decoding format into the data in the two-dimensional storage format. The transposition operation is directly implemented through hardware routing, specifically, the elements in the two-dimensional binary matrix are connected to the corresponding positions of the one-dimensional vector through routing. The formula is as follows: Parameter a i ,b i ,…,d i Both are 0 or 1, 0≤i≤n-1.

7. The system according to claim 6, characterized in that The BCH decoder is designed based on the Peterson algorithm, and can complete the decoding of the entire BCH code in one cycle, and a first-level pipeline is inserted into the BCH decoder.

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