A memory and data migration method

Abstract

The application discloses a memory and a data migration method, and relates to the storage field, which can shorten the time for realizing data migration between adjacent storage unit subarrays in DRAM in-memory computing, thereby reducing the power consumption of the memory and improving the efficiency. The memory comprises a row of interval distributed sense amplifiers and switch units between adjacent storage unit subarrays; between the adjacent storage unit subarrays, in every two adjacent columns of bit lines, a sense amplifier is arranged on one column of bit lines, and a switch unit is connected in series on the other column of bit lines; wherein, on the same column of bit lines, the sense amplifiers and the switch units are alternately arranged between the storage unit subarrays.

Description

Technical Field

[0001] This application relates to the field of storage, and more particularly to a memory and a data migration method. Background Technology

[0002] Dynamic random access memory (DRAM) is a common type of random access memory with wide applications in the storage field. In newer non-von Neumann computing architectures, in-memory computing (computation performed directly within memory) has attracted significant attention because it eliminates the need for data exchange between the processor and memory, greatly reducing latency and power consumption.

[0003] Currently, DRAM comprises multiple memory banks, each containing multiple subarrays. Each subarray contains arrayed memory cells (MCs, or simply cells). Each MC is connected to several word lines (WLs) and bit lines (BLs), and adjacent subarrays are connected by multiple sense amplifiers (SAs). Each SA has a positive input (BL) and an inverting input (…). Each subarray is connected to a column of MC on one of its two adjacent subarrays. Each subarray contains Y columns of BL, and each bank has X bits of input / output data bus, where Y is greater than or equal to X.

[0004] In the aforementioned DRAM, batch bit logic operations, as the most basic operators for in-memory computation, are called extensively. For example, when performing operations on subarrays i and i+1 of two adjacent memory cell subarrays in a DRAM bank (such as...) Figure 5 When performing bitwise logic operations such as AND and OR on vectors a[1,2…m,n] (where vector a is a row of data stored in one storage unit, with a data width of 128 / 256 / 512 bits) and vector b[1,2…m,n] (with a data width of 128 / 256 / 512 bits) and vector b[1,2…m,n] (with a data width of 128 / 256 / 512 bits), the data needs to be placed in the same subarray, thus requiring data migration.

[0005] During data migration (e.g.) Figure 5 , Figure 6As shown, two vectors, i and i+1, are mapped to MCs connected by two word lines (WLi and WLi+1) in subarray i and subarray i+1, respectively. Before performing bitwise logic operations on these two vectors, they need to be placed into the same subarray. For example, vector i in WLi of subarray i needs to be moved to subarray i+1. Therefore, WLi in subarray i within bank_SRC needs to be activated first, and then the data of vector i in WLi needs to be read out sequentially and written into subarray i in another bank_INT for intermediate storage. Then, the data in bank_INT is read out and moved to subarray i+1 in bank_SRC. This not only places the data in two adjacent subarrays into the same subarray, but also prepares for subsequent bitwise logic operations. Since the data reading process of MC requires an activation operation and a precharge operation of the BL connected to MC, the data writing process of MC also requires an activation operation and a precharge operation of the BL connected to MC. Therefore, based on this method, when data migrates between adjacent subarrays within the same bank, if the data bit width is Y and the data bus bit width between different banks is X, then 4Y / X activation operations and 4Y / X precharge operations are required throughout the process. As a result, the entire data transmission process is slow, energy-intensive, and inefficient. Summary of the Invention

[0006] This application provides a memory and a data migration method that can shorten the time for data migration between adjacent memory cell subarrays during in-memory computation in DRAM, thereby reducing memory power consumption and improving efficiency.

[0007] Firstly, a memory is provided. The memory includes: a plurality of memory banks, wherein each bank comprises: a plurality of memory cell subarrays arranged in a column-oriented manner, each memory cell subarray comprising array-distributed memory cells, wherein memory cells located in the same row within the memory cell subarray are connected to the same word line, and memory cells located in the same column are connected to the same bit line; adjacent memory cell subarrays include inductive amplifiers (SAs) and switching units arranged at row intervals; between adjacent memory cell subarrays, in every two adjacent columns of bit lines, an inductive amplifier is disposed on one column of bit lines, and a switching unit is connected in series on the other bit line; furthermore, on the same column of bit lines, inductive amplifiers and switching units are alternately disposed between memory cell subarrays. Thus, when any switching unit is turned on, the SAs connecting two rows of memory cell subarrays can be turned on, for example, the positive input terminal BL of the first SA connected to a column of memory cells in memory cell subarray i+1 and the negative input terminal of the second SA connected to a column of memory cells in memory cell subarray i+2 can be connected. When the first SA is turned on, after reading data from any storage cell in a column of storage cells in storage cell subarray i+1 through the positive input terminal BL of the first SA, the data read by the first SA can be transmitted to the second SA through the switching unit. Finally, the received data is written to any storage cell in a column of storage cells in storage cell subarray i+2 connected to the second SA through the second SA. This enables data migration between adjacent subarrays within the same bank without the need for migration between different banks, thus improving the speed of data transmission, reducing the energy consumption of data migration, and improving efficiency.

[0008] In one possible implementation, the bit line is disposed on an inductive amplifier divided into two segments, one segment connected to the positive input terminal of the inductive amplifier and the other segment connected to the negative input terminal of the inductive amplifier.

[0009] In one possible implementation, the control terminal of the switching unit is connected to a word line, wherein when the switching unit is turned on by the control signal of the control terminal, it turns on the inductive amplifier of the previous row and the inductive amplifier of the next row to transmit data between the inductive amplifier of the previous row and the inductive amplifier of the next row.

[0010] In one possible implementation, the switching unit includes a switching transistor, with the source and drain of the switching transistor connected to a row of bit lines in an adjacent memory cell subarray. In this scheme, the switching unit is primarily implemented using a switching transistor. Since the memory cell includes access transistors, the switching unit can also be implemented using transistors, facilitating fabrication using the same process technology.

[0011] In one possible implementation, a word line control circuit is also included, which is connected to the control terminal of the switching unit via a word line and is used to input control signals to the control terminal of the switching unit.

[0012] In one possible implementation, the inductive amplifier includes a switching unit.

[0013] In one possible implementation, the memory cell includes an access transistor and a storage capacitor, wherein one end of the storage capacitor is connected to the source line, the other end of the storage capacitor is connected to the first terminal of the access transistor, the second terminal of the access transistor is connected to the bit line, and the control terminal of the access transistor is connected to the word line.

[0014] Secondly, a data migration method for a memory as described in the first aspect is provided. It includes the following steps: reading data from a first memory cell in a first memory cell subarray via a first inductive amplifier, wherein a first terminal of the first inductive amplifier is connected to the first memory cell via a first bit line; controlling a switching unit to turn on, writing data from the first memory cell to a second inductive amplifier, wherein a first terminal of the switching unit is connected to the first terminal of the first inductive amplifier via the first bit line, and a second terminal of the switching unit is connected to the second terminal of the second inductive amplifier via a second bit line; writing data from the first memory cell to a second memory cell in a second memory cell subarray via the second inductive amplifier, wherein a second terminal of the second inductive amplifier is connected to the second memory cell via a second bit line; wherein the first terminal of the first inductive amplifier is a positive input terminal, and the second terminal of the second inductive amplifier is a negative input terminal; or the first terminal of the first inductive amplifier is a negative input terminal, and the second terminal of the second inductive amplifier is a positive input terminal.

[0015] In one possible implementation, the first memory cell is also connected to a first word line, and before reading data from the first memory cell of the first memory cell subarray via a first inductive amplifier, the first word line is activated.

[0016] In one possible implementation, the second storage cell is also connected to a second word line, and before writing the data of the first storage cell into the second storage cell of the second storage cell subarray via the second sensing amplifier, the method further includes: activating the second word line.

[0017] In one possible implementation, after writing the data of the first storage cell into the second storage cell of the second storage cell subarray via the second sensing amplifier, the method further includes: turning off the switching unit; pre-charging the first bit line; and pre-charging the second bit line.

[0018] Thirdly, an integrated circuit is provided for use in a memory as described in the first aspect. The integrated circuit includes a memory controller and a memory interface; the memory controller is configured to read data from a first memory cell in a first memory cell subarray via a first sensing amplifier, wherein a first terminal of the first sensing amplifier is connected to the first memory cell via a first bit line; control a switching unit to turn on and write data from the first memory cell to a second sensing amplifier, wherein a first terminal of the switching unit is connected to the first terminal of the first sensing amplifier via the first bit line, and a second terminal of the switching unit is connected to the second terminal of the second sensing amplifier via a second bit line; and write data from the first memory cell to a second memory cell in a second memory cell subarray via the second sensing amplifier, wherein a second terminal of the second sensing amplifier is connected to the second memory cell via a second bit line; wherein the first terminal of the first sensing amplifier is a positive input terminal, and the second terminal of the second sensing amplifier is a negative input terminal; or the first terminal of the first sensing amplifier is a negative input terminal, and the second terminal of the second sensing amplifier is a positive input terminal.

[0019] In one possible implementation, the first memory cell is also connected to a first word line, and the memory controller is further configured to activate the first word line before reading data from the first memory cell of the first memory cell subarray via a first sensing amplifier.

[0020] In one possible implementation, the second memory cell is also connected to a second word line, and the memory controller is further configured to activate the second word line before writing the data of the first memory cell into the second memory cell subarray via the second sensing amplifier.

[0021] In one possible implementation, the memory controller is further configured to, after writing the data of the first memory cell into the second memory cell of the second memory cell subarray via the second sensing amplifier, turn off the switching unit; precharge the first bit line; and precharge the second bit line.

[0022] Fourthly, an electronic device is provided, comprising the aforementioned integrated circuit and the aforementioned memory, wherein the integrated circuit includes a memory controller and a memory interface, and wherein the memory is connected to the memory controller via the memory interface.

[0023] The technical effects brought about by the second to fourth aspects can be referred to the technical effects brought about by the different implementation methods in the first aspect above, and will not be repeated here. Attached Figure Description

[0024] Figure 1 A schematic diagram of a computer system architecture provided for an embodiment of this application;

[0025] Figure 2 A schematic diagram of a memory architecture provided for an embodiment of this application;

[0026] Figure 3 A schematic diagram of the circuit structure of a storage cell subarray provided for an embodiment of this application;

[0027] Figure 4 A schematic diagram of a circuit structure for a memory cell subarray and an inductive amplifier provided for an embodiment of this application;

[0028] Figure 5 A schematic diagram of a memory structure provided for an embodiment of this application;

[0029] Figure 6 A schematic diagram illustrating a data migration process in a memory provided for an embodiment of this application;

[0030] Figure 7 A schematic diagram of the structure of a memory provided for another embodiment of this application;

[0031] Figure 8 A schematic diagram of a data migration method provided for an embodiment of this application;

[0032] Figure 9 A schematic diagram illustrating a data migration method according to another embodiment of this application;

[0033] Figure 10 A schematic diagram of a data migration method provided in another embodiment of this application;

[0034] Figure 11 A schematic diagram of a data migration method provided in another embodiment of this application;

[0035] Figure 12 A schematic diagram of the structure of a data migration device provided for an embodiment of this application;

[0036] Figure 13 This is a schematic diagram of an integrated circuit structure provided for an embodiment of this application. Detailed Implementation

[0037] The following sections will discuss the fabrication and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided in this application can be implemented in a variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways of implementing and using this description and technology, and do not limit the scope of this application.

[0038] Unless otherwise defined, all technical terms used herein have the same meaning as commonly known to one of ordinary skill in the art.

[0039] Each circuit or other component may be described or referred to as "for" performing one or more tasks. In this context, "for" is used to imply a structure by indicating that the circuit / component includes a structure (e.g., a circuit system) that performs one or more tasks during operation. Therefore, even when the specified circuit / component is currently inoperable (e.g., not turned on), it can still be referred to as "for performing that task." Circuits / components used with the term "for" include hardware, such as circuits that perform operations.

[0040] The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. In this application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, in the embodiments of this application, the words "first," "second," etc., do not limit the quantity or order.

[0041] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0042] Figure 1 A schematic diagram of a computer system architecture provided for embodiments of this application. (As shown) Figure 1 As shown, the computer system 100 may include at least a processor 101, a memory controller 102, and a memory 103. Typically, the memory controller 102 may be integrated into the processor 101, and the memory 103 may be RAM. It should be noted that, in the computer system provided by the embodiments of this application, besides... Figure 1 In addition to the devices shown, the computer system 100 may also include communication interfaces and other devices such as disks as external storage, without limitation.

[0043] Processor 101 is the computing core and control unit of computer system 100. Processor 101 may include multiple cores 104. An operating system and other software programs are installed in processor 101, enabling processor 101 to access memory 103, cache, and disk. In embodiments of this application, core 104 in processor 101 may be a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor (DSP), or a neural network processor, or other application-specific integrated circuits (ASICs). Memory controller 102 is a bus circuit controller within computer system 100 that controls memory 103 and manages and plans data transfer between memory 103 and core 104. Data exchange can occur between memory 103 and core 104 through memory controller 102. Memory controller 102 may be a separate chip connected to core 104 via a system bus. Memory controller 102 may also be integrated into processor 101 or built into the northbridge. The embodiments of this application do not limit the specific location of the memory controller 102. In practical applications, the memory controller 102 can control the necessary logic to write data to or read data from the memory 103.

[0044] Memory 103 is the main memory of computer system 100. Memory 103 is connected to memory controller 102 via a double data rate (DDR) bus. Memory 103 is typically used to store various running software, input and output data, and information exchanged with external storage in the operating system. Dynamic random access memory (DRAM) is typically used as memory 103. Processor 101 can access memory 103 at high speed through memory controller 102, performing read and write operations on any memory cell in memory 103.

[0045] In the embodiments of this application, memory 103 is described as DRAM, which can also be referred to as DRAM 103. Data is stored in the memory cells (also referred to as DRAM cells, or MCs) of DRAM 103. In the embodiments of this application, a memory cell refers to the smallest memory cell used to store data. Typically, one memory cell can store 1 bit of data. DRAM uses the amount of charge stored in a capacitor to represent data 0 and 1. Due to leakage in the capacitor, if the charge in the capacitor is insufficient, the stored data will be corrupted. Therefore, the memory controller 102 refreshes the data in DRAM 103 every once in a while to prevent DRAM 103 from losing data. Furthermore, DRAM 103 is volatile; when the computer system 100 is powered off, the information in DRAM 103 will no longer be saved. In practical applications, the MCs in DRAM 103 are arranged into a matrix, which is called a memory cell subarray. Several memory cell subarrays form a bank, and the memory controller 102 can locate any bit in the bank using the corresponding row and column resolvers. Multiple banks can be combined to form a DRAM chip (also known as a memory chip), and multiple DRAM chips can be combined to form a rank. Multiple DRAM ranks can be integrated into a dual-inline-memory module (DIMM). For example, ... Figure 1 As shown, DRAM 103 may include multiple channels 105. Each channel 105 may include at least one rank, and each rank may include at least one bank. Each bank includes multiple memory cell subarrays. Those skilled in the art will understand that a rank refers to a memory chip connected to the same chip select signal. The memory controller 102 is capable of writing to chips within the same rank, and chips within the same rank share the same control signals. The memory controller 102 can access data in the memory cells within each channel of DRAM 103 via the memory bus.

[0046] In practical applications, memory cells are connected to word lines (WL) and bit lines (BL). Word lines connect multiple memory cells horizontally, while bit lines connect multiple memory cells vertically. Word lines enable memory cells, and bit lines charge the capacitors in each memory cell, thus using the amount of charge stored in the capacitors to represent data 0 and 1. It can be understood that when a bit line is high, the capacitor stores more charge, or has a larger charge level. When a bit line is low, the capacitor stores less charge, or has a smaller charge level. In one application, a larger charge in the capacitor can indicate that the stored data is "1," and a smaller charge can indicate that the stored data is "0." In another application, a larger charge in the capacitor can also indicate that the stored data is "0," and a smaller charge can indicate that the stored data is "1."

[0047] Reference Figure 2 As shown, the memory 103 may include a command decoder 110, control logic circuitry 120, memory cell subarray 130, and input / output circuitry 140. Specific embodiments are not limited to these and may include fewer or more components. The command decoder 110 can receive commands (CMD) from the memory controller 102 and can decode the received commands (CMD). For example, commands (CMD) may include write commands (WR), read commands (RD), active commands (ACT), and / or precharge commands (PRE).

[0048] The memory subarray 130 may include multiple memory cells MC. The multiple MCs may be connected to multiple word lines and multiple bit lines. Word lines may be connected to word line control circuitry (or word line resolvers), and bit lines may be connected to bit line control circuitry (or bit line resolvers). Control logic circuitry 120 may control components of memory 103 based on decoding results from command decoder 110. For example, if the decoding result of command decoder 110 indicates that the received command CMD is an activation command ACT, control logic circuitry 120 may control word line control circuitry to activate the word line corresponding to the row address (RA) received along with the activation command ACT. In this case, data stored in the memory cells MC connected to the activated word line may be configured (e.g., transferred, sent, output, etc.) via a sense amplifier (SA) to input / output circuitry 140. For example, if the decoding result of command decoder 110 indicates that the received command CMD is a read command RD, control logic circuit 120 can control input / output circuit 140 to output data from the bit line corresponding to the column address (CA) received along with the read command RD. If the decoding result of command decoder 110 indicates that the received command CMD is a write command WR, control logic circuit 120 can set the write data received from memory controller 102 to input / output circuit 140. Memory controller 102 can send a precharge command PRE to memory 103 for the purpose of deactivating and / or disabling active word lines. For example, if the decoding result of command decoder 110 indicates that the received command CMD is a precharge command PRE, control logic circuit 120 can control input / output circuit 140 and bit line control circuit to precharge the bit line. The basic principles of activation, read, write, and precharge operations have been briefly described above. It is understood that the activation, read, write, and precharge operations in the following scheme can at least be implemented using the methods described above.

[0049] Figure 3 Show Figure 2The circuit diagram of the memory cell subarray 130 is shown below. The memory cell subarray 130 may include a plurality of memory cells MC. Each memory cell MC may include an access transistor T and a storage capacitor C. The first terminal of the access transistor T of the memory cell MC is connected to one of the bit lines BL1 to BLm, and its second terminal is connected to the first terminal of the storage capacitor C. The gate of the access transistor T is connected to one of the word lines WL1 to WLn. The second terminal of the storage capacitor C may be connected to a voltage terminal. The voltage terminal may be connected to a voltage of a specific level (e.g., a desired voltage level) (e.g., ground voltage or half-supply voltage) via a source line (SL). In some embodiments, when any of the word lines WL1 to WLn are selected in response to an activation command ACT from the memory controller 102 and the selected word line is activated, data stored in the memory cell connected to the selected word line may be provided to the input / output circuit 140 via the plurality of bit lines BL1 to BLm and SA.

[0050] In addition, such as Figure 4 As shown, the positive input terminal BL and the negative input terminal of the sensing amplifier SA Two bit lines are connected to two adjacent memory cell subarrays, subarrayi and subarrayi+1, respectively. For example, BL1 in subarrayi is connected to the negative input of the sense amplifier SA1 in the i-th row. In subarray i+1, BL1 is connected to the positive input terminal BL of the sensing amplifier SAi in the i-th row. When the bit line WLi in any row of subarray i+1 is activated, the sensing amplifier SA reads from the memory cell connected to WLi in the memory cell subarray i+1 through the positive input terminal BL, or as... Figure 2 As shown, the input / output circuit 140 writes data to the memory cells via the corresponding BL1. Since the memory cells all have the same structure, in the following example, the memory cell subarray is simplified to... Figure 5 The simplified diagram showing the intersection of word lines and bit lines illustrates that there is a memory cell at each intersection of a word line and a bit line.

[0051] Based on the aforementioned memory, during data migration (such as...) Figure 5 , Figure 6As shown in the diagram, for example, it is necessary to migrate vectori on WLi in subarray i to subarrayi+1. Therefore, it is necessary to first activate WLi in subarrayi within bank_SRC, then read the vectori data a[1,2…m,n] on WLi sequentially, and write the data sequentially into subarrayi within another bank_INT for intermediate storage. Then, the data in bank_INT is read out and migrated to subarrayi+1 in bank_SRC. This not only places the data in two adjacent subarrays into the same subarray, but also prepares for subsequent bitwise logic operations. Based on this method, when data is migrated between adjacent subarrays within the same bank, if the data bit width is Y and the data bus bit width between different banks is X, then 4Y / X activation operations and 4Y / X precharge operations are required in the entire process. Therefore, the entire data transmission process is slow, energy-intensive, and inefficient.

[0052] To solve the aforementioned problems, a memory is provided, including several memory banks, as described above. Figure 7 As shown, the bank comprises: multiple subarrays of storage cells arranged in a column-oriented manner ( Figure 7 As shown in the diagram, subarrayi (subarray i - subarray i+3), each memory cell subarray includes memory cells distributed in an array. Memory cells in the same row are connected to the same word line, and memory cells in the same column are connected to the same bit line (the connection method between memory cells, word lines, and bit lines can be found in [reference]). Figure 3 , Figure 4 As shown); Figure 7 As shown, adjacent memory cell subarrays include row-spaced inductive amplifiers SA and switching units M; each inductive amplifier SA corresponds to one column of memory cells MC, and each switching unit M corresponds to another column of memory cells MC; the inductive amplifier SA has a positive input terminal BL and a negative input terminal BL. The bit lines of the first column of the memory cells of two adjacent memory cell subarrays are respectively connected; the two ends of the switch unit M are respectively connected to the bit lines of the second column of the memory cells of two adjacent memory cell subarrays; wherein, in the direction of the memory cells in the same column, the inductive amplifier SA and the switch unit M are spaced apart between the memory cell subarrays.

[0053] by Figure 7Taking two adjacent rows of memory cell subarrays, subarrayi and subarrayi+1, as an example, we can illustrate this. Between subarrayi and subarrayi+1, there is a row (the i-th row) of spaced-out inductive amplifiers SA and switching units M. Between adjacent memory cell subarrays, in every two adjacent columns of bit lines, one column of bit lines contains an inductive amplifier, and the other column contains a switching unit connected in series. For example, the inductive amplifier SA on the bit line is divided into two segments: one segment is connected to the positive input terminal BL of the inductive amplifier SA, and the other segment is connected to the negative input terminal of the inductive amplifier SA. Taking the inductive amplifier SA1 and the switching unit M2 in the i-th row as an example, the inductive amplifier SA1 divides the bit line BL1 into a segment of subarrayi+1 and a segment of subarrayi. Thus, the positive input terminal BL of the inductive amplifier SA1 is connected to the bit line BL1 of the storage unit MC in the first column of subarrayi+1; the negative input terminal of the inductive amplifier SA1... Bit line BL1 connects to the first column of the memory cell MC of subarray i. One end of the switching unit M2 connects to the bit line BL2 of the second column of the memory cell MC of subarray i+1; the other end of the switching unit M2 connects to the bit line BL2 of the second column of the memory cell MC of subarray i. In the direction of the memory cells in the same column as SA1, one end of the switching unit M1 located between subarray i+1 and subarray i+2 connects to the bit line BL1 of the first column of the memory cell MC of subarray i+1; the other end of the switching unit M1 connects to the bit line BL1 of the first column of the memory cell MC of subarray i+2. On the same column bit line, inductive amplifiers and switching units are alternately arranged between the memory cell subarrays. For example, in the direction of the bit line BL1 of the first column of the memory cell MC of each subarray, inductive amplifier SA1 is between subarray i and subarray i+1, switching unit M1 is between subarray i+1 and subarray i+2, and inductive amplifier SA2 is between subarray i+2 and subarray i+3.

[0054] In this way, when any switch unit is turned on, the SA connecting the two rows of memory cell subarrays can be turned on. For example, the positive input terminal BL of the first SA connected to a column of memory cells in memory cell subarray i+1 can be connected to the negative input terminal of the second SA connected to a column of memory cells in memory cell subarray i+2. When the first SA is turned on, after reading data from any storage cell in a column of storage cells in storage cell subarray i+1 through the positive input terminal BL of the first SA, the data read by the first SA can be transmitted to the second SA through the switching unit. Finally, the received data is written to any storage cell in a column of storage cells in storage cell subarray i+2 connected to the second SA through the second SA. This enables data migration between adjacent subarrays within the same bank without the need for migration between different banks, thus improving the speed of data transmission, reducing the energy consumption of data migration, and improving efficiency.

[0055] The control terminal of switch unit M is connected to a word line, such as... Figure 7 As shown, the control terminal of the switch unit in the i-th row is connected to the word line WL-iosi, and the control terminal of the switch unit in the (i+1)-th row is connected to the word line WL-iosi+1. When the switch unit is turned on by the control signal of the control terminal, it turns on the sense amplifiers of the previous row and the next row to transmit data between the sense amplifiers of the previous row and the next row. Furthermore, the control terminal of the switch unit can be connected to a word line control circuit via the word line, where the word line control circuit can be... Figure 2 The word line control circuit is shown in the figure. The word line control circuit is used to input control signals to the control terminal of the switching unit M.

[0056] like Figure 7 As shown, the switching unit M includes a switching transistor. The source and drain of the switching transistor are respectively connected to a column of bit lines of adjacent memory cell subarrays. For example, the source of the switching transistor M1 located between subarrayi+1 and subarrayi+2 is connected to the bit line BL1 of the first column of memory cell MC in subarrayi+1; the drain of the switching transistor M1 is connected to the bit line BL1 of the first column of memory cell MC in subarrayi+2. Alternatively, the drain of the switching transistor M1 is connected to the bit line BL1 of the first column of memory cell MC in subarrayi+1; the source of the switching transistor M1 is connected to the bit line BL1 of the first column of memory cell MC in subarrayi+2. The gate of the switching transistor M1 serves as a control terminal and is connected to the word line WL-iosi+1. In this scheme, the switching unit is mainly implemented using a switching transistor. Since the memory cell includes access transistors, the switching unit can also be implemented using transistors, which is convenient for fabrication using the same process technology.

[0057] In some examples, since the inductive amplifier SA is typically formed by connecting multiple transistors and the switching unit is typically formed by switching transistors, and the two are similar in manufacturing process, the switching unit M can be integrated into the inductive amplifier SA, so the inductive amplifier SA contains the switching unit M.

[0058] Based on the above Figure 7 The illustrated memory, an embodiment of this application provides a data migration method, referencing... Figure 8 As shown, the explanation is as follows:

[0059] S101. Read the data of the first storage cell of the first storage cell subarray through the first inductive amplifier, wherein the first end of the first inductive amplifier is connected to the first storage cell through the first bit line.

[0060] S102. The control switch unit is turned on to write the data of the first storage unit into the second inductive amplifier. The first end of the switch unit is connected to the first end of the first inductive amplifier through the first bit line, and the second end of the switch unit is connected to the second end of the second inductive amplifier through the second bit line.

[0061] S103. The data of the first storage cell is written into the second storage cell of the second storage cell subarray through the second sensing amplifier. The second end of the second sensing amplifier is connected to the second storage cell through the second bit line.

[0062] Wherein, the first terminal of the first inductive amplifier is the positive input terminal, and the second terminal of the second inductive amplifier is the negative input terminal; or the first terminal of the first inductive amplifier is the negative input terminal, and the second terminal of the second inductive amplifier is the positive input terminal.

[0063] In combination with the above Figure 3 , Figure 4 The memory shown includes memory cells connected to word lines. As described above, when the word lines connected to a memory cell are activated, data can be read from or written to the memory cell. Therefore, the first memory cell is also connected to a first word line; optionally, the first word line needs to be activated before step S101. The second memory cell is also connected to a second word line; optionally, the second word line needs to be activated before step S102. After step S103, the switching unit is turned off; the first bit line is pre-charged, and the second bit line is pre-charged.

[0064] Specifically, in combination Figure 9 , Figure 10 , Figure 11 The specific method for data migration between the odd and even columns of subarrayi+1 is explained below:

[0065] Taking the migration of data from the storage cells of the odd-numbered columns connected by word line WLi+1 in subarrayi+1 to subarrayi+2 as an example, the positive input BL of SA1 in the i-th row is connected to the word line BL1 of the first column storage cell in subarrayi+1, and the negative input of SA2 in the i+2-th row is... Connect the word line BL1 of the first column storage unit in subarray i+2. Connect one end of the switch unit M1 in row i+1 to the word line BL1 of the first column storage unit in subarray i+1, and connect the other end of the switch unit M1 to the word line BL1 of the first column storage unit in subarray i+2. The specific steps for data migration are as follows (see process details). Figure 10 ):

[0066] S201. Activate word line WLi+1 of subarray i+1. SA1 reads the data a1 of the storage cell at the position of the first column bit line BL1 on word line WLi+1 of subarray i+1 through the positive input terminal BL, and latches it.

[0067] For the other SAs in the i-th row, the operation is similar to that of SA1. In this way, each SA in the i-th row reads the data (a1, ..., n1, ...) of the storage cells in the odd-numbered column bit positions on the word line WLi+1 of subarrayi+1 at the same time.

[0068] S202. Enable the WL-isoi+1 signal in the (i+1)th row, control the switch unit M1 in the (i+1)th row to turn on, and pass the data a1 in SA1 through the negative input terminal of SA2 in the (i+2)th row. Write to SA2.

[0069] Among them, the other switch units M in the i+1th row will also be in the conducting state under the control of the WL-isoi+1 signal. For the other SAs in the i+2th row, their operation is similar to that of SA2. In this way, each SA in the i+2th row simultaneously writes the data (a1, ..., n1 ...) of the storage cells in the odd column bit positions on the word line WLi+1 of subarrayi+1.

[0070] S203. Activate word line WLi+2 of subarray i+2, and write the data a1 of SA2 in row i+2 into the storage unit at the first column bit line BL1 position on word line WLi+2 of subarray i+2.

[0071] For the other SAs in row i+2, the operation is similar to that of SA2. In this way, each SA in row i+2 simultaneously writes the data (a1, ..., n1, ...) into the storage cell at the odd column bit position on word line WLi+2 of subarray i+2.

[0072] S204. Invert the WL-isoi+1 signal in the (i+1)th row and turn off the switch unit M1 in the (i+1)th row.

[0073] Among them, the other switch units M in the i+1th position will also be in the off state under the control of the inverted WL-isoi+1 signal.

[0074] Finally, for the positive input terminal BL of each SA in the i-th row, and the negative input terminal of each SA in the (i+2)-th row... The connected bit lines are pre-charged.

[0075] Taking the migration of data from the even-numbered columns connected by word lines WLi+1 in subarrayi+1 to subarrayi as an example, the negative input terminal of SA3 in row i+1 is used as an example. Connect the word line BL2 of the second column storage unit in subarray i+1. Connect the positive input BL of SA4 in row i-1 to the word line BL2 of the second column storage unit in subarray i. Connect one end of the switch unit M2 in row i to the word line BL2 of the second column storage unit in subarray i+1, and connect the other end of the switch unit M2 to the word line BL2 of the second column storage unit in subarray i. The specific steps of data migration are as follows (see process details). Figure 11 ):

[0076] S301, activate word line WLi+1 of subarrayi+1, SA3 through negative input terminal Read the data b1 from the storage cell at the second column position on the word line WLi+1 of subarrayi+1 and latch it.

[0077] For the other SAs in row i+1, the operation is similar to that of SA3. In this way, each SA in row i+1 reads the data (b1, ..., m1, ...) of the storage cells in the even-numbered positions of the bit lines on the word line WL i+1 of subarray i+1.

[0078] S302, enable the WL-isoi signal in the i-th row, control the switch unit M2 in the i-th row to turn on, and write the data b1 in SA3 into SA4 through the positive input terminal BL of SA4 in the (i-1)-th row.

[0079] In addition, other switch units M in Sai will also be in the conducting state under the control of the WL-isoi signal. For the other SAs in the i-1th row, their operation is similar to that of SA4. In this way, each SA in the i-1th row simultaneously writes the data (b1, ..., m1...) of the storage cells in the even-numbered bit line positions on the word line WLi+1 of subarrayi+1.

[0080] S303. Activate the word line WLi of subarrayi and write the data b1 of SA4 in the (i-1)th row into the storage cell in the second column position of the word line WLi of subarrayi.

[0081] For the other SAs in the (i-1)th row, the operation is similar to that of SA4. Thus, each SA in the (i-1)th row simultaneously writes the data (b1, ..., m1, ...) into the storage cells at the even-numbered bit line positions on the word line WLi of subarrayi.

[0082] S304. Invert the WL-isoi signal in the i-th row and turn off the switch unit M2 in the i-th row.

[0083] In addition, the other switch units M in the i-th row will also be in the off state under the control of the inverted WL-isoi signal.

[0084] Finally, for the positive input terminal BL of each SA in the (i-1)th row, and the negative input terminal of each SA in the (i+1)th row... The connected bit lines are pre-charged.

[0085] After the above steps, data migration between adjacent memory cell subarrays can be successfully implemented in DRAM in-memory computing. In the existing DRAM structure, when data is migrated between adjacent subarrays within the same bank, if the data width is 512 bits and the data width between different banks is 128 bits, then 4 steps are required during the entire migration process. (512 / 128) activation operations and 4 (512 / 128) precharge operations. Assuming WL activation takes 35ns, precharge takes 15ns, and ignoring data read / write time, the current data migration scheme takes approximately 4 seconds. (512 / 128) (35+15)ns, or 400ns. However, the solution provided by the embodiments of this application only requires about 100ns (including the time spent on two activations and one pre-charging operation), which can bring about a 4-fold increase in data migration speed, thereby significantly reducing energy consumption and improving efficiency.

[0086] The foregoing mainly describes the solutions provided by the embodiments of this application from the perspective of method steps. It is understood that, in order to implement the above functions, a computer includes corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should readily recognize that, in conjunction with the modules and algorithm steps of the various examples described in the embodiments disclosed herein, this application can be implemented in a combination of hardware and computer software. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0087] This application embodiment can divide the data migration device into functional modules based on the above method example. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division; other division methods may be used in actual implementation.

[0088] When dividing each function into modules according to its corresponding function. Figure 12 A data migration apparatus, which can be a chip, is shown. The data migration apparatus 1000 includes:

[0089] The read control unit 1001 is used to read data from the first storage cell of the first storage cell subarray through the first inductive amplifier, wherein the first end of the first inductive amplifier is connected to the first storage cell through the first bit line.

[0090] A write control unit 1002 is used to control the switching unit to conduct, writing the data of the first storage unit into the second sensing amplifier. The first terminal of the switching unit is connected to the first terminal of the first sensing amplifier via the first bit line, and the second terminal of the switching unit is connected to the second terminal of the second sensing amplifier via the second bit line. The data of the first storage unit is written into the second storage unit of the second storage unit subarray via the second sensing amplifier, and the second terminal of the second sensing amplifier is connected to the second storage unit via the second bit line. The first terminal of the first sensing amplifier is a positive input terminal, and the second terminal of the second sensing amplifier is a negative input terminal; or the first terminal of the first sensing amplifier is a negative input terminal, and the second terminal of the second sensing amplifier is a positive input terminal.

[0091] Optionally, the first storage cell is also connected to a first word line and includes an activation unit 1003 for activating the first word line before reading data from the first storage cell of the first storage cell subarray via a first inductive amplifier.

[0092] Optionally, the second storage cell is also connected to a second word line and includes an activation unit 1003 for activating the second word line before writing the data of the first storage cell into the second storage cell subarray via the second inductive amplifier.

[0093] Optionally, the pre-charge unit 1004 is used to turn off the switching unit after the data of the first memory cell is written into the second memory cell of the second memory cell subarray through the second inductive amplifier; pre-charge the first bit line and pre-charge the second bit line.

[0094] All relevant content of each step involved in the above method embodiments can be referenced from the functional description of the corresponding functional module, and will not be repeated here.

[0095] For example, embodiments of this application also provide an integrated circuit, such as... Figure 13 As shown, the integrated circuit 1100 includes a memory interface 1101 and a memory controller 1102.

[0096] The memory interface 1101 is used for communication with other devices or equipment, such as a memory. The memory controller 1102 is used to read data from a first memory cell in a first memory cell subarray via a first inductive amplifier, wherein a first terminal of the first inductive amplifier is connected to the first memory cell via a first bit line; to control a switching unit to turn on, writing data from the first memory cell to a second inductive amplifier, wherein a first terminal of the switching unit is connected to the first terminal of the first inductive amplifier via the first bit line, and a second terminal of the switching unit is connected to the second terminal of the second inductive amplifier via a second bit line; and to write data from the first memory cell to a second memory cell in a second memory cell subarray via the second inductive amplifier, wherein a second terminal of the second inductive amplifier is connected to the second memory cell via a second bit line; wherein the first terminal of the first inductive amplifier is a positive input terminal, and the second terminal of the second inductive amplifier is a negative input terminal; or the first terminal of the first inductive amplifier is a negative input terminal, and the second terminal of the second inductive amplifier is a positive input terminal.

[0097] Optionally, the first storage cell is also connected to a first word line, and the memory controller 1102 is further configured to activate the first word line before reading data from the first storage cell of the first storage cell subarray via a first sensing amplifier.

[0098] Optionally, the second storage cell is also connected to a second word line, and the memory controller 1102 is further configured to activate the second word line before writing the data of the first storage cell into the second storage cell subarray via the second sensing amplifier.

[0099] Optionally, the memory controller 1102 is further configured to, after writing the data of the first memory cell into the second memory cell of the second memory cell subarray through the second sensing amplifier, turn off the switching unit; precharge the first bit line; and precharge the second bit line.

[0100] Based on this, this application embodiment also provides an electronic device, which includes the aforementioned integrated circuit and a memory. The integrated circuit includes a memory controller and a memory interface, wherein the memory is connected to the memory controller through the memory interface. Optionally, the electronic device can be different types of user equipment or terminal equipment such as the aforementioned computer system, mobile phone, tablet computer, wearable device, and vehicle-mounted device; the electronic device can also be a network device such as a base station. It should be noted that for specific descriptions regarding the memory in the electronic device, please refer to the descriptions of the memory in the above embodiments, and these descriptions will not be repeated here.

[0101] In another aspect of this application, a non-transitory computer-readable storage medium for use with a computer having software for creating integrated circuits is also provided. The computer-readable storage medium stores one or more computer-readable data structures having photomask data for manufacturing the memory provided in any of the above-provided figures.

[0102] The steps of the methods or algorithms described in conjunction with the disclosure of this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can reside in an ASIC.

[0103] Those skilled in the art will recognize that, in one or more of the examples above, the functions described in this application can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0104] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, include: A plurality of memory bank banks, wherein each bank comprises: a plurality of storage cell subarrays arranged in a column-oriented manner, each storage cell subarray comprising array-distributed storage cells, wherein storage cells located in the same row in the storage cell subarray are connected to the same word line, and storage cells located in the same column are connected to the same bit line; The adjacent memory cell subarrays include a row of spaced inductive amplifiers and switching units; between adjacent memory cell subarrays, in each pair of adjacent bit lines, an inductive amplifier is provided on one bit line and a switching unit is connected in series on the other bit line. In this configuration, on the same column line, the inductive amplifier and the switching unit are alternately arranged between the memory cell subarrays.

2. The memory according to claim 1, characterized in that, The bit line is divided into two segments by an inductive amplifier, one segment being connected to the positive input terminal of the inductive amplifier and the other segment being connected to the negative input terminal of the inductive amplifier.

3. The memory according to claim 1, characterized in that, The control terminal of the switching unit is connected to a word line. When the switching unit is turned on by the control signal of the control terminal, it turns on the inductive amplifier of the previous row and the inductive amplifier of the next row to transmit data between the inductive amplifier of the previous row and the inductive amplifier of the next row.

4. The memory according to claim 3, characterized in that, The switching unit includes a switching transistor, the source and drain of which are respectively connected to a row of bit lines of the adjacent memory cell subarray.

5. The memory according to claim 3, characterized in that, It also includes a word line control circuit, which is connected to the control terminal of the switching unit through the word line and is used to input control signals to the control terminal of the switching unit.

6. The memory according to any one of claims 1-5, characterized in that, The inductive amplifier includes the switching unit.

7. The memory according to any one of claims 1-5, characterized in that, The memory cell includes an access transistor and a storage capacitor, wherein one end of the storage capacitor is connected to the source line, the other end of the storage capacitor is connected to the first terminal of the access transistor, the second terminal of the access transistor is connected to the bit line, and the control terminal of the access transistor is connected to the word line.

8. A data migration method for a memory as described in any one of claims 1-7, characterized in that, Data of the first memory cell of the first memory cell subarray is read through the first sensing amplifier, wherein the first end of the first sensing amplifier is connected to the first memory cell through the first bit line; The control switch unit is turned on to write the data of the first storage unit into the second sensing amplifier. The first end of the switch unit is connected to the first end of the first sensing amplifier through the first bit line, and the second end of the switch unit is connected to the second end of the second sensing amplifier through the second bit line. The data of the first memory cell is written into the second memory cell of the second memory cell subarray through the second sensing amplifier, and the second end of the second sensing amplifier is connected to the second memory cell through the second bit line. Wherein, the first terminal of the first inductive amplifier is the positive input terminal, and the second terminal of the second inductive amplifier is the negative input terminal; or the first terminal of the first inductive amplifier is the negative input terminal, and the second terminal of the second inductive amplifier is the positive input terminal.

9. The method according to claim 8, characterized in that, The first storage cell is also connected to a first word line, and before reading the data of the first storage cell in the first storage cell subarray through the first inductive amplifier, it further includes: Activate the first character line.

10. The method according to claim 8, characterized in that, The second storage cell is also connected to a second word line. Before the data from the first storage cell is written into the second storage cell of the second storage cell subarray via the second sensing amplifier, the method further includes: Activate the second word line.

11. The method according to any one of claims 8-10, characterized in that, After writing the data from the first storage cell into the second storage cell of the second storage cell subarray via the second inductive amplifier, the method further includes: Turn off the switch unit; The first bit line is precharged, and the second bit line is precharged.

12. An integrated circuit, applied to a memory as described in any one of claims 1-7, characterized in that, This includes the memory controller and memory interface; The memory controller is configured to read data from a first memory cell in a first memory cell subarray via a first sensing amplifier, wherein a first terminal of the first sensing amplifier is connected to the first memory cell via a first bit line; control a switching unit to turn on, writing data from the first memory cell into a second sensing amplifier, wherein a first terminal of the switching unit is connected to a first terminal of the first sensing amplifier via the first bit line, and a second terminal of the switching unit is connected to a second terminal of the second sensing amplifier via a second bit line; and write data from the first memory cell into a second memory cell in a second memory cell subarray via the second sensing amplifier, wherein a second terminal of the second sensing amplifier is connected to the second memory cell via a second bit line; wherein the first terminal of the first sensing amplifier is a positive input terminal, and the second terminal of the second sensing amplifier is a negative input terminal; or the first terminal of the first sensing amplifier is a negative input terminal, and the second terminal of the second sensing amplifier is a positive input terminal.

13. The integrated circuit according to claim 12, characterized in that, The first storage cell is also connected to a first word line, and the memory controller is further configured to activate the first word line before reading data from the first storage cell of the first storage cell subarray via a first sensing amplifier.

14. The integrated circuit according to claim 12, characterized in that, The second storage cell is also connected to a second word line, and the memory controller is further configured to activate the second word line before writing the data of the first storage cell into the second storage cell subarray via the second sensing amplifier.

15. The integrated circuit according to any one of claims 12-14, characterized in that, The memory controller is further configured to turn off the switching unit after writing the data of the first memory cell into the second memory cell subarray through the second sensing amplifier; precharge the first bit line; and precharge the second bit line.

16. An electronic device, characterized in that, The integrated circuit includes the integrated circuit as described in any one of claims 12-15 and the memory as described in any one of claims 1-7, wherein the integrated circuit includes a memory controller and a memory interface, and wherein the memory is connected to the memory controller through the memory interface.

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