A method for failure analysis of an MMIC limiter chip

Abstract

The application relates to a MMIC limiter chip failure analysis method. The method comprises the following steps: scanning a MMIC limiter chip to be analyzed by using an electron microscope, determining the topographic damage position of the microwave integrated circuit; according to the positions of a plurality of PIN diodes in the MMIC limiter chip to be analyzed, the MMIC limiter chip to be analyzed is regionally segmented to obtain a plurality of test units; the I-V curve of the PIN diode on each test unit is acquired, whether the PIN diode is damaged is determined, and the active element damage point in the circuit is judged; according to the topographic scanning of the electron microscope, the passive element damage point is judged, and the active element damage point is judged according to the IV curve analysis of the PIN diode, so that the damage point of the limiter chip under high-power microwave radiation is positioned. By using the method, the MMIC limiter chip failure analysis is more convenient, accurate and low in cost, and meets the actual engineering application requirements.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for failure analysis of MMIC limiter chips. Background Technology

[0002] A microwave limiter is a self-conducting attenuator that utilizes the microwave characteristics of a PIN diode. The magnitude of the microwave signal passing through the diode controls whether the microwave signal is on or off. An ideal limiter should not attenuate the signal when it is low power, but as the input power increases, the attenuation increases when it exceeds a threshold level until the output power is maintained at a certain threshold value. The primary function of a limiter chip is to prevent high-power microwaves from damaging the signal receiving system. The core component of the limiter is the PIN diode, which directly determines several parameters of the limiter, including the limiting level, power capacity, and insertion loss. Studying the damage effects of PIN diodes under strong electromagnetic pulses can provide a theoretical basis for the design of subsequent electromagnetic protection chips. Current research on electromagnetic damage to semiconductor devices mainly focuses on theoretical aspects, including: 1. Obtaining peak leakage, flat-top leakage, and pulse power of PIN limiters using equivalent circuit models and simulation software; 2. Conducting theoretical analysis of the normalized absorption, load, and reflected power relationships with impedance of PIN limiters using ADS simulation software to obtain transient response models; 3. Investigating the effects of frequency and pulse width on PIN limiter damage at high power levels by solving semiconductor equations and considering internal device temperature and electric field effects. MMIC limiters contain multiple discrete components.

[0003] Investigating which component within a module is damaged during electromagnetic pulse testing is crucial for design guidance, yet current research in this area is limited. To study the impact of high-power electromagnetic pulse width on the device damage threshold, a traditional approach has been proposed: establishing an electromagnetic damage effect model for MMIC limiters using device physical simulation and verifying it experimentally. This method primarily utilizes time-domain reflectometry (TDR) to observe impedance discontinuities, using the change in the sampled step signal between two adjacent impedance discontinuities to locate the internal damage position of the limiter. The accuracy of this testing method depends on the resolution of the TDR system; for typical PCB materials (dielectric constant 4), the minimum resolvable physical gap is 2.5 mm. It is evident that this testing method is primarily applicable to PCB board limiter devices with larger dimensions (centimeter-level), but not to MMIC limiters with dimensions in the micrometer range. To analyze the damage mechanism of MMIC limiters, some researchers have observed the damage morphology of limiters under high-power pulse radiation, revealing the locations where MMIC limiters are prone to damage and the mechanism of interface damage. This method mainly uses focused ion beam (FIB) technology to perform nanofabrication on materials, creating a stepped profile at the questionable component location, and then using scanning electron microscopy to analyze the morphology of the MMIC limiter to determine the damage location of the limiter under high-power pulse radiation. However, this method has extremely high requirements for testing equipment and is costly. Summary of the Invention

[0004] Therefore, it is necessary to provide a failure analysis method for MMIC limiter chips to address the aforementioned technical problems.

[0005] A method for failure analysis of an MMIC limiter chip, the method comprising:

[0006] The pre-set failure analysis task is analyzed to obtain the MMIC limiter chip to be analyzed after being subjected to high-power microwave. The MMIC limiter chip to be analyzed includes multiple PIN diodes and passive components. The passive components include a planar spiral inductor, an overlapped capacitor, a power divider, a metallized via, and a ground.

[0007] The MMIC limiter chip to be analyzed is scanned using an electron microscope to obtain the circuit morphology of the MMIC limiter chip to be analyzed. Based on the circuit morphology, it is determined whether there is damage to the passive components on the integrated circuit of the MMIC limiter chip to be analyzed, and the damage result of the passive components is obtained.

[0008] Based on the integrated circuit structure of the MMIC limiter chip to be analyzed, the MMIC limiter chip to be analyzed is divided into regions, and the PIN diode is separated from other components and connecting lines to obtain multiple test units.

[0009] Obtain the IV curve of the PIN diode on each test unit. Based on the IV curve and the IV curve of the PIN diode under normal conditions, determine whether the PIN diode is damaged and obtain the damage result of the active component.

[0010] Based on the damage results of the passive components and the damage results of the active components, a failure analysis is performed on the MMIC limiter chip to be analyzed.

[0011] In one embodiment, the method further includes: when the passive component damage result is that a damaged passive component exists, obtaining the passive component damage point based on the position of the damaged passive component on the MMIC limiter chip integrated circuit to be analyzed; when the active component damage result is that a damaged PIN diode exists, obtaining the active component damage point based on the position of the damaged PIN diode on the MMIC limiter chip integrated circuit to be analyzed; and determining the damage point of the MMIC limiter chip to be analyzed based on the passive component damage point and the active component damage point.

[0012] In one embodiment, the method further includes: determining the probe points corresponding to each test unit based on the circuit structure of the MMIC limiter chip to be analyzed; performing IV curve testing using a semiconductor analyzer connected to the probe points at both ends of each test unit to obtain the IV curve test results corresponding to each test unit; determining the test unit to which the damaged area belongs based on the IV curve test results corresponding to each test unit; when the test unit to which the damaged area belongs includes at least two PIN diodes, dividing the test unit, obtaining the IV curve of each PIN diode after the area division, and determining whether the PIN diode is damaged based on the IV curve and the IV curve of each PIN diode under normal conditions to obtain the active component damage result.

[0013] In one embodiment, the method further includes: determining the probe point corresponding to each PIN diode on the test unit according to the circuit structure of the test unit to which the damaged area belongs; and using a semiconductor analyzer to access the probe points at both ends of the PIN diode after the area is segmented to perform IV curve testing to obtain the IV curve of each PIN diode.

[0014] In one embodiment, the method further includes: determining the positions of the plurality of PIN diodes in the MMIC limiter chip to be analyzed based on the manufacturing process of the MMIC limiter chip to be analyzed; and dividing the MMIC limiter chip to be analyzed into regions based on the positions of the plurality of PIN diodes in the MMIC limiter chip to be analyzed to obtain a plurality of test units.

[0015] In one embodiment, the method further includes: analyzing the process of the MMIC limiter chip under test, locating the distribution of the metal layer, setting probe points on the metal layer, and placing them at both ends of the PIN diode under test to avoid other damaging components affecting the test results.

[0016] In one embodiment, the method further includes: using laser cutting to divide the MMIC limiter chip to be analyzed and the test unit to which the damaged area belongs into regions, so as to separate other components and avoid other components from affecting the IV curve test.

[0017] In one embodiment, the method further includes: using high-precision laser cutting during region segmentation, and avoiding damage to the circuit during cutting to prevent damage points from affecting the IV curve test results; the damage point is a PIN diode.

[0018] In one embodiment, the MMIC limiter chip to be analyzed includes a radio frequency front-end limiter designed based on gallium arsenide microwave integrated circuit technology.

[0019] In one embodiment, the electron microscope further includes a super depth-of-field three-dimensional microscope.

[0020] The aforementioned MMIC limiter chip failure analysis method analyzes the morphological damage of the MMIC limiter chip to identify severely damaged passive components such as capacitors or inductors. Furthermore, it employs common voltage and current measurements to analyze the highly integrated limiter chip circuitry. Specifically, it measures the voltage-current characteristics of each active component's PIN diode, enabling more accurate location of the actual damage to the active components. By combining morphological damage analysis and PIN diode voltage-current characteristic analysis, MMIC limiter chip failure analysis is achieved. This invention, applied to micron-level limiter identification, can precisely locate damaged components in complex circuits, making MMIC limiter chip failure analysis more convenient, accurate, and cost-effective, and meeting the requirements of practical engineering applications. Attached Figure Description

[0021] Figure 1 This is a flowchart illustrating a failure analysis method for an MMIC limiter chip in one embodiment.

[0022] Figure 2 This is a schematic diagram of the IV curve test of a test unit in one embodiment;

[0023] Figure 3This is a schematic diagram comparing the IV curve of a test unit with the IV curve under normal conditions in one embodiment. (a) is a schematic diagram comparing the IV curve of test unit one with the IV curve under normal conditions, (b) is a schematic diagram comparing the IV curve of test unit two with the IV curve under normal conditions, (c) is a schematic diagram comparing the IV curve of test unit three with the IV curve under normal conditions, and (d) is a schematic diagram comparing the IV curve of test unit four with the IV curve under normal conditions.

[0024] Figure 4 This is a schematic diagram of the IV curve test of a single PIN diode in another embodiment. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0026] In one embodiment, such as Figure 1 As shown, a failure analysis method for an MMIC limiter chip is provided, including the following steps:

[0027] Step 102: Analyze the pre-set failure analysis task to obtain the MMIC limiter chip to be analyzed after being subjected to high-power microwave.

[0028] The MMIC limiter chip to be analyzed includes multiple PIN diodes and passive components, including a planar spiral inductor, overlapping capacitors, a power divider, metallized vias, and grounding. A limiter is a nonlinear microwave device whose impedance changes with the input signal and can be used in microwave switching. Specifically, when the voltage across the PIN diode is low, the PIN diode is in the off state, exhibiting high impedance, and the current through the PIN diode is very small. When the voltage across the PIN diode exceeds its threshold voltage, the PIN diode conducts, changing from high impedance to low impedance, and the current through the PIN diode increases exponentially. This unique voltage-current characteristic of the PIN diode is used to determine whether the PIN diode is damaged. In this embodiment of the invention, the MMIC limiter chip to be analyzed is an MMIC (Monolithic Microwave Integrated Circuit) limiter. Damage to the limiter under high-power microwave action includes three scenarios: first, severe damage to the input capacitor, with multiple breakdown morphologies on the capacitor surface, while the input diode damage is relatively minor; second, minor damage to the input capacitor, but severe damage to the input diode; and third, severe damage to both the input capacitor and the input diode. Since the PIN diode is the most important component in the MMIC limiter and determines the limiting performance, this invention proposes a combined SEM (scanning electron microscope) and IV testing method to analyze the failure of the limiter.

[0029] Step 104: Scan the MMIC limiter chip to be analyzed using an electron microscope to obtain the circuit morphology of the MMIC limiter chip to be analyzed. Based on the circuit morphology, determine whether there is damage to the passive components on the integrated circuit of the MMIC limiter chip to be analyzed, and obtain the damage results of the passive components.

[0030] An electron microscope, such as a super depth-of-field three-dimensional microscope, can be used to scan the MMIC limiter chip, analyze the overall circuit condition, and identify damaged components. Specifically, high-resolution imaging using an electron microscope can be used to observe the damage morphology of the MMIC circuit and determine whether passive components are damaged.

[0031] Step 106: Based on the integrated circuit structure of the MMIC limiter chip to be analyzed, the MMIC limiter chip to be analyzed is divided into regions, and the PIN diodes are separated from other components and connecting lines to obtain multiple test units.

[0032] The MMIC circuit is divided into regions using laser cutting to cut the circuit, thereby testing the DC-IV curve of the PIN diode in each test unit. Region division isolates the influence of other components on the IV curve test. When selecting test units, separating the PIN diode from other components and connections reduces the number of laser cutting points and avoids introducing other parasitic effects.

[0033] Step 108: Obtain the IV curve of the PIN diode on each test unit. Based on the IV curve and the IV curve of the PIN diode under normal conditions, determine whether the PIN diode is damaged and obtain the damage result of the active component.

[0034] The normal state refers to the state of the PIN diode without high-power microwave irradiation, and its test conditions are the same as those for PIN diodes subjected to high-power microwave irradiation. When obtaining the IV curve of the PIN diode in each test unit, a semiconductor analyzer is used to test the PIN diodes contained in the test unit via probes connected to both ends of the test unit. The probes are selected in conjunction with the MMIC process, and are positioned on the metal layer of the MMIC limiter. Accurate probe positioning avoids the influence of damage to other components on the test results.

[0035] Step 110: Perform failure analysis on the MMIC limiter chip to be analyzed based on the damage results of passive components and active components.

[0036] The damage locations of passive components were determined by morphological analysis, and the damage locations of active components were determined by PIN diode IV curve analysis. Based on the above analysis, the damage points of the MMIC limiter chip under high-power microwave irradiation were obtained.

[0037] In the aforementioned MMIC limiter chip failure analysis method, by analyzing the morphological damage of the MMIC limiter chip, severely damaged passive components such as capacitors or inductors can be identified. Furthermore, common voltage and current measurements are used to analyze the highly integrated limiter chip circuit; specifically, the voltage-current characteristics of each active component's PIN diode are measured, enabling more accurate location of the actual damage to the active components. Combining morphological damage analysis and PIN diode voltage-current characteristic analysis, MMIC limiter chip failure analysis is achieved. This invention, applied to micron-level limiter determination, can precisely locate specific damaged components in complex circuits, making MMIC limiter chip failure analysis more convenient, accurate, and low-cost, and meeting the requirements of practical engineering applications.

[0038] In one embodiment, the step of performing failure analysis on the MMIC limiter chip to be analyzed based on the damage results of passive components and active components includes: when the damage result of passive components indicates the presence of damaged passive components, obtaining the damage point of the passive components based on the location of the damaged passive components on the integrated circuit of the MMIC limiter chip to be analyzed; when the damage result of active components indicates the presence of damaged PIN diodes, obtaining the damage point of the active components based on the location of the damaged PIN diodes on the integrated circuit of the MMIC limiter chip to be analyzed; and determining the damage point of the MMIC limiter chip to be analyzed based on the damage points of passive components and active components. In this embodiment, an MMIC is a microwave circuit that fabricates active and passive devices on the same semiconductor substrate. The damage location of passive components is determined by combining the morphology and the damage location of active components is determined by analyzing the IV curve of the PIN diode, thus obtaining the damage point of the MMIC limiter chip to be analyzed.

[0039] In one embodiment, such as Figure 2 As shown, a schematic diagram of IV curve testing for a test unit is provided. The steps include: obtaining the IV curve of the PIN diode on each test unit; determining whether the PIN diode is damaged based on the IV curve and the IV curve of the PIN diode under normal conditions; determining the damage result of the active component based on the IV curve of the PIN diode and the IV curve of the PIN diode under normal conditions; determining the test unit to which the damaged area belongs based on the IV curve test result of each test unit; when the test unit to which the damaged area belongs includes at least two PIN diodes, dividing the test unit, obtaining the IV curve of each PIN diode after the area division, and determining whether the PIN diode is damaged based on the IV curve of each PIN diode under normal conditions to obtain the damage result of the active component.

[0040] In this embodiment, the MMIC process used in this invention is GaAs-MMIC manufacturing technology. This technology includes growing multilayer GaAs epitaxial layers using molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD), isolation processes, deep submicron "T"-type gate electrode manufacturing technology, source-drain ohmic contact technology, Au metallized electrodes and metal interconnect processes, back-side via grounding technology, air bridge technology, etc., integrating resistors, capacitors, inductors, interconnects, power dividers / power combiners, etc., onto the same chip. Multiple components such as inductors, capacitors, power dividers, and couplers are integrated within a 1mm*1mm space, resulting in high integration and complex circuitry. The inductors used are spiral inductors, which have high quality parameters, but their complex structure requires connecting the center coil to an external circuit, necessitating the use of an air bridge transverse structure. Furthermore, the MMIC design uses metallized via grounding, and the microstrip line also includes an electrolyte passivation layer and an isolation layer. Region segmentation is closely related to chip manufacturing processes. Correctly positioning components in a multi-layered structure and precisely cutting the circuit can reduce the impact on components and the overall circuit. Due to the small size of the MMIC limiter, region segmentation is used to improve testing accuracy. After region segmentation, the MMIC limiter circuit is divided into multiple relatively opposing test units. A semiconductor analyzer is used to apply a voltage from 0 to 3V across the PIN diode in the test unit, and the current flowing through the PIN diode is measured to obtain the IV curve of the PIN diode within the test unit.

[0041] In one embodiment, the process of the MMIC limiter chip under test is analyzed to locate the distribution of the metal layer. Probe points are then placed on the metal layer and positioned at both ends of the PIN diode under test to avoid other damaging components from affecting the test results.

[0042] In this embodiment, the MMIC limiter has different circuit designs depending on the manufacturing process. The selection of probe points is mainly based on the MMIC circuit configuration to determine suitable probe positions for accurate measurement of the voltage and current across the diode. Suitable probe points require analysis of the MMIC process and understanding of the structure of each layer. Probe points should be placed on metal layers, avoiding isolation layers. Before testing, the probes need to be calibrated to ensure accurate connection. MMIC processes are now at the micrometer or even nanometer level, demanding extremely high probe precision. Only accurate probe positioning can yield precise measurement results. The selection of probe point positions needs to isolate the influence of other components to avoid damage to the test results, and should be as close as possible to the structure of the PIN diode under test.

[0043] In one embodiment, based on the integrated circuit structure of the MMIC limiter chip to be analyzed, the MMIC limiter chip to be analyzed is divided into regions to separate the PIN diodes from other components and interconnections to obtain multiple test units. This includes: determining the positions of multiple PIN diodes in the MMIC limiter chip to be analyzed based on the manufacturing process of the MMIC limiter chip to be analyzed; and dividing the MMIC limiter chip to be analyzed into regions based on the positions of the multiple PIN diodes in the MMIC limiter chip to be analyzed to obtain multiple test units.

[0044] In this embodiment, laser cutting is used for segmentation. The key to unit cutting is to isolate the influence of other components on the IV curve test, while reducing the parasitic effects of laser cutting on the circuit. Since MMIC circuits are at the micron or even nanometer scale, even high-precision laser cutting can damage the circuit if not handled properly, and may even damage the diode, thus affecting the IV curve test results and consequently the judgment of the damage point. Therefore, the selection of test units needs to achieve the effect of testing the IV curve of PIN diodes while minimizing laser cutting points and avoiding the introduction of other parasitic effects.

[0045] like Figure 3 As shown, a schematic diagram comparing the IV curve of a test unit with that of a normal state is provided. (a) shows the comparison of the IV curve of test unit one with that of a normal state; (b) shows the comparison of the IV curve of test unit two with that of a normal state; (c) shows the comparison of the IV curve of test unit three with that of a normal state; and (d) shows the comparison of the IV curve of test unit four with that of a normal state. The PIN diodes of the four test units are tested with voltages ranging from 0 to 3V and current limiting of 0.1mA. The test results show that the IV characteristics of the PIN diodes at test unit one (position 1) and test unit two (position 2) change significantly after high-power pulse radiation. They exhibit high resistance when the voltage is below the turn-on voltage and a short circuit when the voltage is above the turn-on voltage. The IV characteristics of the PIN diodes can be used to determine the damaged area of ​​the MMIC limiter.

[0046] In one embodiment, such as Figure 4As shown, a schematic diagram of a single PIN diode IV curve test is provided. The steps of dividing the test unit and obtaining the IV curve of each PIN diode after the region division include: determining the probe point corresponding to each PIN diode on the test unit according to the circuit structure of the test unit to which the damaged region belongs; using a semiconductor analyzer to connect to the probe points at both ends of the PIN diode after the region division to perform IV curve testing, thereby obtaining the IV curve of each PIN diode.

[0047] In this embodiment, as Figure 2 The test unit shown includes two PIN diodes. If the IV curve of the PIN diodes within a test unit is abnormal, then that test unit contains a damaged area. Figure 4 As shown, by simply segmenting the test unit to which the damaged area belongs and performing IV curve testing on the PIN diode within that test unit, the specific damage point can be analyzed through the IV curve of the PIN diode. Figure 4 As can be seen from the newly added laser cutting points, the method of the present invention can cut the circuit as little as possible, which not only makes the failure analysis of the MMIC limiter chip simpler and faster, but also reduces the potential impact of cutting.

[0048] In one embodiment, the method further includes: using laser cutting to divide the MMIC limiter chip to be analyzed and the test unit to which the damaged area belongs into regions, so as to separate other components and avoid other components from affecting the IV curve test; when dividing the regions, high-precision laser cutting is used, and damage to the circuit is avoided during cutting, so as not to affect the IV curve test results; the damaged point is a PIN diode.

[0049] In this embodiment, laser cutting is used, which offers high-quality cutting. Laser cutting has the following advantages: the kerf is narrow, with parallel sides perpendicular to the surface, allowing for a dimensional accuracy of up to 0.05mm; the cut surface is smooth and aesthetically pleasing, with a surface roughness of only tens of micrometers, minimizing impact on circuit performance; after laser cutting, the heat-affected zone is very small, and the material properties near the kerf are almost unaffected; furthermore, workpiece deformation is minimal, cutting precision is high, and the kerf geometry is good, with a relatively regular rectangular cross-section.

[0050] In one embodiment, the MMIC limiter chip to be analyzed includes an RF front-end limiter designed based on gallium arsenide microwave integrated circuit technology.

[0051] In one embodiment, the electron microscope includes a super depth-of-field three-dimensional microscope.

[0052] It should be understood that, although Figure 1The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0053] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0054] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for failure analysis of an MMIC limiter chip, characterized in that, The method includes: The pre-set failure analysis task is analyzed to obtain the MMIC limiter chip to be analyzed after being subjected to high-power microwave. The MMIC limiter chip to be analyzed includes multiple PIN diodes and passive components. The passive components include a planar spiral inductor, an overlapped capacitor, a power divider, a metallized via, and a ground. The MMIC limiter chip to be analyzed is scanned using an electron microscope to obtain the circuit morphology of the MMIC limiter chip to be analyzed. Based on the circuit morphology, it is determined whether there is damage to the passive components on the integrated circuit of the MMIC limiter chip to be analyzed, and the damage result of the passive components is obtained. Based on the integrated circuit structure of the MMIC limiter chip to be analyzed, the MMIC limiter chip to be analyzed is divided into regions, and the PIN diode is separated from other components and connecting lines to obtain multiple test units. Obtain the IV curve of the PIN diode on each test unit. Based on the IV curve and the IV curve of the PIN diode under normal conditions, determine whether the PIN diode is damaged and obtain the damage result of the active component. Based on the damage results of the passive components and the damage results of the active components, a failure analysis is performed on the MMIC limiter chip to be analyzed.

2. The method according to claim 1, characterized in that, The steps for performing failure analysis on the MMIC limiter chip to be analyzed based on the damage results of the passive components and the damage results of the active components include: When the passive component damage result indicates the presence of a damaged passive component, the damage point of the passive component is obtained based on the location of the damaged passive component on the MMIC limiter chip integrated circuit to be analyzed. When the damage result of the active component is that there is a damaged PIN diode, the damage point of the active component is obtained according to the position of the damaged PIN diode on the MMIC limiter chip integrated circuit to be analyzed. The damage points of the MMIC limiter chip to be analyzed are determined based on the damage points of the passive components and the damage points of the active components.

3. The method according to claim 1, characterized in that, The step of obtaining the IV curve of the PIN diode on each test unit, and determining whether the PIN diode is damaged based on the IV curve and the IV curve of the PIN diode under normal conditions, to obtain the damage result of the active component, includes: Based on the circuit structure of the MMIC limiter chip to be analyzed, determine the probe points corresponding to each test unit; IV curve testing is performed by connecting the probe points at both ends of each test unit using a semiconductor analyzer to obtain the IV curve test results for each test unit. The test unit to which the damaged area belongs is determined based on the IV curve test results corresponding to each test unit; When the test unit to which the damaged area belongs includes at least two PIN diodes, the test unit is divided, and the IV curve of each PIN diode after the area division is obtained. Based on the IV curve and the IV curve of each PIN diode under normal conditions, it is determined whether the PIN diode is damaged, and the damage result of the active component is obtained.

4. The method according to claim 3, characterized in that, The step of dividing the test unit and obtaining the IV curve of each PIN diode after region segmentation includes: Based on the circuit structure of the test unit to which the damaged area belongs, determine the probe point corresponding to each PIN diode on the test unit; IV curve testing was performed on the probe points at both ends of the PIN diodes after the region was segmented using a semiconductor analyzer to obtain the IV curve of each PIN diode.

5. The method according to claim 1, characterized in that, The process involves dividing the MMIC limiter chip under analysis into regions based on its integrated circuit structure, separating the PIN diodes from other components and interconnections, and obtaining multiple test units, including: The positions of the plurality of PIN diodes in the MMIC limiter chip to be analyzed are determined according to the manufacturing process of the MMIC limiter chip to be analyzed. Based on the positions of the multiple PIN diodes in the MMIC limiter chip to be analyzed, the MMIC limiter chip to be analyzed is divided into regions to obtain multiple test units.

6. The method according to any one of claims 3 or 4, characterized in that, The method further includes: The process of the MMIC limiter chip under test is analyzed to locate the distribution of the metal layer. The probe points are set on the metal layer and at both ends of the PIN diode under test to avoid other damaged components from affecting the test results.

7. The method according to any one of claims 3-5, characterized in that, The method further includes: The MMIC limiter chip to be analyzed and the test unit to which the damaged area belongs are divided by laser cutting to separate other components and avoid other components from affecting the IV curve test.

8. The method according to claim 7, characterized in that, When performing region segmentation, high-precision laser cutting is used to avoid damaging the circuit during cutting, so as not to affect the IV curve test results due to damage points; the damage points are PIN diodes.

9. The method according to claim 1, characterized in that, The MMIC limiter chip to be analyzed includes a radio frequency front-end limiter designed based on gallium arsenide microwave integrated circuit technology.

10. The method according to claim 1, characterized in that, The electron microscope includes a super depth-of-field three-dimensional microscope.

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