Frequency control array transmitting system based on DDS and PLL

Abstract

The application discloses a frequency control array transmitting system based on DDS and PLL, which comprises a crystal oscillator source power division module, a DDS excitation ring-in mixed frequency phase-locked loop circuit module, a DDS local oscillator+phase-locked loop PLL2 circuit module, a phase-locked loop PLL1 circuit module, a ring-out mixed frequency power division circuit module and a FPGA control module. The application realizes that the 8-way reference carrier is 17GHz and the frequency offset of the adjacent two transmitting channels is 4MHz through the ring-in-ring-out mixed frequency phase-locked loop+DDS frequency synthesis and the crystal oscillator source power division module, and the frequency source circuit has good characteristics such as high frequency resolution and low phase noise.

Description

Technical Field

[0001] This invention belongs to the fields of radar and electronic warfare systems, specifically a radio frequency circuit for a frequency control array transmission system. Background Technology

[0002] Currently, phased arrays, widely used in radar, electronic warfare systems, radio astronomy, airport security, and even medicine, transmit the same signal in each element. Each element's output is connected to a phase shifter, which can change the direction of the transmitted beam. Adjusting the phase shifter allows for spatial scanning of the beam. Frequency-scanning antennas, on the other hand, achieve spatial beam scanning by changing the radar system's operating frequency. However, both phased arrays and frequency-scanning antennas have a drawback: within each scan snapshot, the beam direction is constant in the range direction, meaning the beam direction is independent of range. However, in some applications, such as range-dependent interference or clutter suppression, it is often desirable for the array beam to point at different ranges at the same angle within the same snapshot. This requires the transmitted beam direction to change with distance. Therefore, scholars both domestically and internationally have proposed a frequency diversity array where the transmitted beam radiation pattern is dependent on range, angle, and time; this is called a frequency-controlled array (FDA).

[0003] Compared to phased arrays, frequency-controlled arrays transmit beams that are distance-dependent, which brings the following advantages:

[0004] (1) The beam pointing can change with the distance, distinguishing targets from interference and clutter in the distance dimension, making radar signal processing more flexible;

[0005] (2) The integrated frequency control array's spatial, temporal, and frequency resources can simultaneously meet the tasks of radar moving target detection, anti-jamming, clutter control, and high-resolution radar imaging.

[0006] (3) The range-angle dependence of the frequency-controlled array transmit beam creates conditions for solving problems such as anti-main lobe interference, anti-range-related clutter, joint estimation and localization of target parameters.

[0007] Frequency-controlled arrays have broad application prospects, but research on them has mostly focused on radiation patterns or radar information processing, with very few public reports on their hardware implementation. The lack of simple and effective technical approaches to realize the many theoretical concepts of frequency diversity arrays will severely limit their future development. Summary of the Invention

[0008] To address the aforementioned technical deficiencies in the prior art, this invention proposes a radio frequency circuit for a frequency-controlled array transmission system.

[0009] The technical solution to achieve the purpose of this invention is as follows: a frequency-controlled array transmission system based on DDS and PLL, comprising a crystal oscillator power divider module, an FPGA control module, a DDS local oscillator + PLL2 circuit module, an 8-channel DDS excitation loop internal mixer PLL circuit module, a PLL1 circuit module, and an external mixer power amplifier circuit module. The crystal oscillator power divider module provides a 100MHz clock signal to the FPGA control module, the DDS local oscillator + PLL2 circuit module, the 8-channel DDS excitation loop internal mixer PLL circuit module, the PLL1 circuit module, and the external mixer power amplifier circuit module. The FPGA control module is connected to the DDS local oscillator + PLL2 circuit module and the 8-channel DDS excitation loop internal mixer PLL1 circuit module. The loop circuit module is connected to control the DDS local oscillator + PLL2 circuit module to output an 800MHz sine wave signal to the 8-channel DDS excitation loop internal mixer PLL circuit module. The link n of the 8-channel DDS excitation loop internal mixer PLL circuit module outputs an 8.2GHz + (n-1)·4MHz sine wave signal to the external mixer power amplifier circuit module, where n = 1 to 8. The PLL1 circuit module outputs 8 channels of 8.8GHz sine waves to the external mixer power amplifier circuit module. The external mixer power amplifier circuit module is used to output 8 channels of 17GHz + (n-1)·4MHz signals based on the sine wave signal output by the DDS excitation loop internal mixer PLL circuit module and each 8.8GHz sine wave signal output by the PLL1 circuit module.

[0010] Preferably, the crystal oscillator power divider module includes a 100MHz crystal oscillator, a clock buffer, and a resistor power divider structure. The 100MHz crystal oscillator provides a 100MHz clock signal output to the clock buffer input. Each port of the clock buffer is connected to the resistor power divider structure, which outputs 11 channels of 100MHz clock signals. These 11 clock signals are respectively transmitted to the inputs of the 8-channel DDS excitation loop internal mixer phase-locked loop module, the DDS local oscillator + phase-locked loop PLL2 circuit module, the PLL1 phase-locked loop module, and the FPGA module.

[0011] Preferably, the DDS local array + PLL2 circuit module includes a balun 1, a balun 2, a DDS chip, a bandpass filter, a power controller, a PLL chip, a microcontroller chip, and a 1-to-8 power divider. The input of balun 1 is connected to the 100MHz clock signal output of the crystal oscillator power divider module, and the output of balun 1 is connected to the clock signal input of the DDS chip. The DDS chip is controlled by an FPGA control module. The output of the DDS chip outputs a 25MHz sine wave signal, which enters balun 2. The output of balun 2 is connected to the bandpass filter, which is connected to the power controller. The power controller outputs a signal to the PLL chip. The PLL chip is controlled by the microcontroller chip to divide the frequency. The PLL chip outputs an 800MHz sine wave signal, which is input to the input of the 1-to-8 power divider. The 1-to-8 power divider outputs eight 800MHz sine waves to the mixing PLL circuit module within the DDS excitation loop via SMA connectors and coaxial cables.

[0012] Preferably, each of the 8-channel DDS excitation loop mixing phase-locked loop circuit modules includes a balun 3, a balun 4, a DDS chip, a phase detector, a microcontroller chip, a loop filter, a voltage-controlled oscillator, three power controllers, a mixer, a first bandpass filter, and a second bandpass filter. Balun 3 is connected to the 100MHz clock signal output of the crystal oscillator power divider module and to the clock signal input of the DDS chip. The DDS chip outputs a 25MHz+(n-1)·20kHz sine wave signal to balun 4. Balun 4 is connected to bandpass filter 1, which is connected to power controller 1. Power controller 1 is connected to the phase detector controlled by the microcontroller chip, and the phase detector is connected to the loop filter. The filter performs signal filtering, and the filtered signal is output to the voltage-controlled oscillator (VCO). The VCO outputs one 8.2GHz+(n-1)·4MHz sine wave signal as the output signal of the DDS excitation loop's internal mixer-PLL circuit module. The other signal is divided by 4 to obtain a 2.05GHz+(n-1)·1MHz (n=1~8) output signal, which is then output to power controller 2. The output signal of power controller 2, along with the 800MHz sine wave signal output from the DDS local array + PLL2 circuit module, is input to the mixer. The mixer output signal passes through bandpass filter 2, and the converted signal is input to power controller 3. Power controller 3 outputs a 1.25GHz+(n-1)·1MHz (n=1~8) signal to the phase detector chip. Finally, the output signals of each channel are the 8.2GHz+(n-1)·4MHz (n=1~8) sine waves output by the VCO, which are output to the external mixer-power amplifier module through SMA connectors and coaxial cables.

[0013] Preferably, the phase-locked loop (PLL1) module includes a phase detector, a VCO, a loop filter, and an 8-to-1 power divider. A 100MHz clock signal is input to the phase detector chip, the phase detector output signal is input to the loop filter, the loop filter chip output signal is input to the VCO, and the VCO outputs two 8.8GHz signals. One signal is output to the 8-to-1 power divider as the output signal of the PLL1 module, and the other signal is input to the phase detector chip as a phase detection signal.

[0014] Preferably, the mixing amplifier circuit includes a mixer, three power amplifiers, and two bandpass filters. The eight 8.2GHz+(n-1)·4MHz sine signals output from the eight-channel DDS excitation loop mixing phase-locked loop circuit module are fed to the intermediate frequency signal input terminal of each mixer as intermediate frequency signals. The 8.8GHz signal output from the phase-locked loop PLL1 module is input to power amplifier 4. After power amplification, it is used as the local oscillator signal and input to the mixer. The mixer output signal is input to bandpass filter 4, and the 17GHz+(n-1)·4MHz up-converted signal is input to power amplifier 5. After amplification, it is input to bandpass filter 5 to filter out noise and then input to power amplifier 6. After power amplifier 6, the final eight frequency source signals with a reference carrier of 17GHz and a frequency offset of 4MHz between two adjacent transmit channels are obtained.

[0015] Compared with the prior art, the significant advantages of this invention are:

[0016] 1. The scheme of in-loop and out-loop mixing phase-locked loop + DDS frequency synthesis realizes a frequency-controlled array transmission system with a small frequency offset (4MHz) in the Ku band.

[0017] 2. The modules are connected by SMA connectors and coaxial cables or DuPont wires and pin headers, making the overall system installation and debugging simple.

[0018] The objects and other advantages of the present invention can be realized and obtained by means of the structures particularly pointed out in the written description, claims and drawings. Attached Figure Description

[0019] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0020] Figure 1 This is a schematic diagram of the overall structure of the system of the present invention.

[0021] Figure 2 This is a schematic diagram of the crystal oscillator power divider module.

[0022] Figure 3 This is a schematic diagram of the DDS local array + phase-locked loop PLL2 circuit module structure.

[0023] Figure 4 This is a schematic diagram of the structure of a single-channel DDS excitation loop internal mixer phase-locked loop circuit module.

[0024] Figure 5 This is a schematic diagram of the phase-locked loop (PLL1) module.

[0025] Figure 6 This is a schematic diagram of the external ring mixer power amplifier module.

[0026] Figure 7 This is the spectrum of the output signal of the DDS local oscillator excitation phase-locked loop (PLL2) module.

[0027] Figure 8 This is the spectrum diagram of the second harmonic component of the output signal of the DDS local oscillator excitation phase-locked loop PLL2 module.

[0028] Figure 9 This is the spectrum diagram of the output signal of the in-loop mixer phase-locked loop module.

[0029] Figure 10 This is the spectrum diagram of the output signal (including harmonic components) of the in-loop mixer phase-locked loop module.

[0030] Figure 11 This is the spectrum diagram of the output signal of the phase-locked loop (PLL1) module.

[0031] Figure 12 This is the spectrum diagram of the output signal (including harmonic components) of the phase-locked loop (PLL1) module.

[0032] Figure 13 This is the spectrum diagram of the 17GHz single-transmit link output signal of the external ring mixer power amplifier module.

[0033] Figure 14 This is the spectrum diagram of the 17.016GHz single-transmit link output signal of the external ring mixer power amplifier module.

[0034] Figure 15 This is the spectrum diagram of the 17.028GHz single-transmit link output signal of the external ring mixer power amplifier module. Detailed Implementation

[0035] It is readily understood that, based on the technical solution of this invention, various embodiments of the invention can be conceived by those skilled in the art without altering the essential spirit of the invention. Therefore, the following detailed embodiments and accompanying drawings are merely illustrative examples of the technical solution of this invention and should not be considered as the entirety of the invention or as limitations or restrictions on the technical solution of this invention. Rather, these embodiments are provided to enable those skilled in the art to gain a more thorough understanding of the invention. Preferred embodiments of the invention are described below in conjunction with the accompanying drawings, which form part of this application and, together with the embodiments of the invention, serve to illustrate the innovative concept of the invention.

[0036] like Figures 1-6 As shown, a frequency-controlled array transmission system based on DDS and PLL includes a crystal oscillator power divider module, an FPGA control module, a DDS local oscillator + PLL2 circuit module, an 8-channel DDS excitation loop internal mixer PLL circuit module, a PLL1 circuit module, and an external mixer power amplifier circuit module. The crystal oscillator power divider module outputs a 100MHz clock signal, which is connected to the FPGA control module, the DDS local oscillator + PLL2 circuit module, the 8-channel DDS excitation loop internal mixer PLL circuit module, the PLL1 circuit module, and the external mixer power amplifier circuit module, respectively, to provide a 100MHz clock signal to these modules. Control module A is connected to the DDS local oscillator + PLL2 circuit module and the 8-channel DDS excitation loop internal mixer PLL circuit module. The DDS local oscillator + PLL2 circuit module outputs 8 channels of 800MHz sine waves, which are input to the 8-channel DDS excitation loop internal mixer PLL circuit modules. The nth channel of the 8-channel DDS excitation loop internal mixer PLL circuit module outputs an 8.2GHz + (n-1)·4MHz sine wave to the external mixer power amplifier circuit module. The PLL1 circuit module outputs 8 channels of 8.8GHz sine waves to the external mixer power amplifier circuit module. The external mixer power amplifier circuit module includes 8 mixer amplifier circuits, which output 8 channels of 17GHz + n·4MHz (n=1~8) signals.

[0037] In a further embodiment, the crystal oscillator power divider module includes a 100MHz crystal oscillator, a clock buffer, and a resistor power divider structure. The 100MHz crystal oscillator provides a 100MHz clock signal output to the clock buffer input. Each port of the clock buffer outputs to the resistor power divider structure to output 11 100MHz clock signals. These 11 clock signals are transmitted through SMA connectors and coaxial cables to the input terminals of the 8-channel DDS excitation loop internal mixer phase-locked loop module, the DDS local oscillator+ module, the PLL1 phase-locked loop module, and the FPGA module, respectively.

[0038] In a further embodiment, the DDS local array + PLL2 circuit module includes balun 1, balun 2, a DDS chip, a bandpass filter, a power controller, a PLL chip, a microcontroller chip, and a 1-to-8 power divider. The 100MHz clock signal output from the crystal oscillator power divider module is connected to balun 1. Balun 1 is connected to the clock signal input of the DDS chip controlled by the FPGA module. The DDS chip outputs a 25MHz sine wave signal to balun 2. Balun 2 is connected to the bandpass filter, which is connected to the power controller. The power controller outputs a signal to the PLL chip. The PLL chip's frequency divider is controlled by the microcontroller chip. Finally, the PLL chip outputs an 800MHz sine wave signal, which is input to the 1-to-8 power divider. The 1-to-8 power divider outputs eight 800MHz sine waves to the mixing PLL circuit module within the DDS excitation loop via SMA connectors and coaxial cables. Figures 7-8 As shown, the module outputs an 800MHz frequency signal with a power of -1.624dBm, a second harmonic suppression of approximately 35dBc, and high signal purity.

[0039] In a further embodiment, each of the eight DDS excitation loop mixing PLL circuit modules includes a balun 3, a balun 4, a DDS chip, a phase detector, a microcontroller chip, a loop filter, a voltage-controlled oscillator (VCO), three power controllers, a mixer, a first bandpass filter, and a second bandpass filter. One of the 100MHz clock signals output from the crystal oscillator module is input to the balun 3 of each DDS excitation loop mixing PLL circuit module. The balun 3 is connected to the clock signal input terminal of the DDS chip controlled by the FPGA module. The DDS chip outputs a 25MHz+(n-1)·20kHz (n=1~8) sine wave signal to the balun 4. The balun 4 is connected to the bandpass filter 1, which is connected to the power controller 1. The power controller 1 is connected to the phase detector controlled by the microcontroller chip as a phase detection signal. The phase detector is connected to the loop filter to filter the signal. The filtered signal is output to the voltage-controlled oscillator (VCO), which outputs an 8.2GHz+... A sinusoidal signal of (n-1)·4MHz (n=1~8) is used as the output signal of the DDS excitation loop internal mixer-PLL circuit module. Another path, after being divided by 4, yields a 2.05GHz+(n-1)·1MHz (n=1~8) output signal, which is then output to power controller 2. The output signal of power controller 2 serves as the intermediate frequency signal, and together with the 800MHz sinusoidal signal output from the DDS local array + PLL2 circuit module, it is used as the local oscillator signal and input to the mixer. The mixer output signal passes through bandpass filter 2, and the converted signal is input to power controller 3. Power controller 3 outputs a 1.25GHz+(n-1)·1MHz (n=1~8) signal to the phase detector chip. Finally, the output signals of each path are 8.2GHz+(n-1)·4MHz (n=1~8) sinusoidal signals output from the VCO, which are output to the external mixer-power amplifier module as intermediate frequency signals via SMA connectors and coaxial cables. Figures 9-10 As shown, the module outputs an 8.2GHz signal power of 12.84dBm, while the suppression levels of the first harmonic, third harmonic, and second harmonic can reach 30.5dBc, 35.4dBc, and 27dBc, respectively.

[0040] In a further embodiment, the FPGA control module includes an FPGA chip. Through the 100MHz clock signal output by the crystal oscillator power divider module, the FPGA chip serves as the control circuit chip for the 9 DDS chips in the 8-channel DDS excitation loop internal mixer phase-locked loop circuit module and the DDS local array + phase-locked loop PLL2 module. It provides control signals such as chip reset and mode selection for the DDS chips, controls the DDS chips to output a 25MHz sine wave signal, and transmits control commands through DuPont wires and header pins.

[0041] In a further embodiment, the phase-locked loop (PLL1) module includes a phase detector, a VCO, a loop filter, and an 8x1 power divider. A 100MHz clock signal is input to the phase detector chip, the phase detector output signal is input to the loop filter, the loop filter chip output signal is input to the VCO, and the VCO outputs two 8.8GHz signals. One signal is used as the output signal of the PLL1 module and output to the 8x1 power divider; the other signal is used as the phase detection signal and input to the phase detector chip. Finally, the PLL1 module outputs the 8.8GHz signal from the VCO, which is output to the external mixer power amplifier module via an SMA connector and a coaxial cable as the local oscillator signal. Figures 11-12 As shown, the module outputs an 8.8GHz signal power of 8.924dBm, and the first harmonic suppression level can reach 28.75dBc.

[0042] In a further embodiment, the external mixing power amplifier module comprises eight mixing amplifier circuits, each consisting of one mixer, three power amplifiers, and two bandpass filters. The eight 8.2GHz+(n-1)·4MHz sinusoidal signals output from the eight DDS excitation loop mixing phase-locked loop circuit modules are fed to the intermediate frequency (IF) input of each mixer as IF signals. The 8.8GHz signal output from the phase-locked loop (PLL1) module is input to power amplifier 4, amplified, and then used as the local oscillator signal input to the mixer. The mixer output signal is input to bandpass filter 4, where a 17GHz+(n-1)·4MHz (n=1~8) up-converted signal is input to power amplifier 5. After amplification, it is input to bandpass filter 5 to filter out noise, and then input to power amplifier 6. Power amplifier 6 then yields the final eight frequency source signals with a reference carrier of 17GHz and a frequency offset of 4MHz between adjacent transmit channels. Figures 13-15 As shown in the figure, the single-transmit link output signal spectrum at 17GHz, 17.016GHz, and 17.028GHz is used as a representative example. It can be seen that the transmit signal power of this module is around 12dBm.

[0043] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

[0044] It should be understood that, in order to simplify the present invention and help those skilled in the art understand its various aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes described in a single embodiment or with reference to a single figure. However, the present invention should not be construed as including all features in the exemplary embodiments as essential technical features of the claims of this patent.

[0045] It should be understood that the modules, units, components, etc., included in the device of one embodiment of the present invention can be adaptively changed to be placed in a device different from that embodiment. Different modules, units, or components included in the device of the embodiment can be combined into a single module, unit, or component, or they can be divided into multiple sub-modules, sub-units, or sub-components.

Claims

1. A frequency-controlled array transmission system based on DDS and PLL, characterized in that, The system includes a crystal oscillator power divider module, an FPGA control module, a DDS local oscillator + PLL2 circuit module, an 8-channel DDS excitation loop internal mixer PLL circuit module, a PLL1 circuit module, and an external mixer power amplifier circuit module. The crystal oscillator power divider module provides a 100MHz clock signal to the FPGA control module, the DDS local oscillator + PLL2 circuit module, the 8-channel DDS excitation loop internal mixer PLL1 circuit module, and the external mixer power amplifier circuit module. The FPGA control module is connected to the DDS local oscillator + PLL2 circuit module and the 8-channel DDS excitation loop internal mixer PLL circuit module to control the DDS local oscillator + PLL2 circuit module. The PLL2 circuit module outputs an 800MHz sine wave signal to an 8-channel DDS excitation loop internal mixer PLL circuit module. The link n of the 8-channel DDS excitation loop internal mixer PLL circuit module outputs an 8.2GHz + (n-1)·4MHz sine wave signal to the external mixer power amplifier circuit module, where n=1~8. The PLL1 circuit module outputs 8 channels of 8.8GHz sine waves to the external mixer power amplifier circuit module. The external mixer power amplifier circuit module is used to output 8 channels of 17GHz + (n-1)·4MHz signals based on the sine wave signal output by the DDS excitation loop internal mixer PLL circuit module and each 8.8GHz sine wave signal output by the PLL1 circuit module.

2. The frequency control array transmission system based on DDS and PLL according to claim 1, characterized in that, The crystal oscillator power divider module includes a 100MHz crystal oscillator, a clock buffer, and a resistor power divider structure. The 100MHz crystal oscillator provides a 100MHz clock signal output to the clock buffer input. Each port of the clock buffer is connected to the resistor power divider structure, which outputs 11 channels of 100MHz clock signals. These 11 clock signals are respectively transmitted to the inputs of the 8-channel DDS excitation loop internal mixer phase-locked loop circuit module, the DDS local oscillator + phase-locked loop PLL2 circuit module, the phase-locked loop PLL1 circuit module, and the FPGA control module.

3. The frequency control array transmission system based on DDS and PLL according to claim 1, characterized in that, The DDS local oscillator + phase-locked loop (PLL2) circuit module includes balun 1, balun 2, a DDS chip, a bandpass filter, a power controller, a PLL chip, a microcontroller chip, and a 1-to-8 power divider. The input of balun 1 is connected to the 100MHz clock signal output of the crystal oscillator power divider module, and the output of balun 1 is connected to the clock signal input of the DDS chip. The DDS chip is controlled by an FPGA control module, and its output output is a 25MHz sine wave signal, which enters balun 2. The output of balun 2 is connected to the bandpass filter, which is connected to the power controller. The power controller outputs a signal to the PLL chip, which is controlled by the microcontroller chip to divide the frequency. The PLL chip outputs an 800MHz sine wave signal, which is input to the 1-to-8 power divider. The 1-to-8 power divider outputs eight 800MHz sine waves to the mixing PLL circuit module within the DDS excitation loop via SMA connectors and coaxial cables.

4. The frequency control array transmission system based on DDS and PLL according to claim 1, characterized in that, The 8-channel DDS excitation loop mixing phase-locked loop circuit module includes, in each channel, a balun 3, a balun 4, a DDS chip, a phase detector, a microcontroller chip, a loop filter, a voltage-controlled oscillator (VCO), three power controllers, a mixer, a first bandpass filter, and a second bandpass filter. Balun 3 is connected to the 100MHz clock signal output of the crystal oscillator power divider module and to the clock signal input of the DDS chip. The DDS chip outputs a 25MHz + (n-1)·20kHz sine wave signal to balun 4. Balun 4 is connected to the first bandpass filter, which is connected to power controller 1. Power controller 1 is connected to the phase detector controlled by the microcontroller chip. The phase detector is connected to the loop filter to filter the signal. The filtered signal is output to the voltage-controlled oscillator (VCO). The oscillator VCO outputs one 8.2GHz+(n-1)·4MHz sine wave signal as the output signal of the DDS excitation loop internal mixer phase-locked loop circuit module. The other signal is divided by 4 to obtain a 2.05GHz+(n-1)·1MHz output signal, which is then output to power controller 2. The output signal of power controller 2 and the 800MHz sine wave signal output from the DDS local oscillator + phase-locked loop PLL2 circuit module are input to the mixer. The mixer output signal passes through the second bandpass filter, and the converted signal is input to power controller 3. Power controller 3 outputs a 1.25GHz+(n-1)·1MHz signal to the phase detector chip. Finally, the output signals of each channel are the 8.2GHz+(n-1)·4MHz sine wave signals output by the VCO, which are output to the external mixer power amplifier circuit module through the SMA connector and coaxial cable.

5. The frequency control array transmission system based on DDS and PLL according to claim 1, characterized in that, The phase-locked loop (PLL1) circuit module includes a phase detector, a VCO, a loop filter, and an 8-to-1 power divider. A 100MHz clock signal is input to the phase detector chip, the phase detector output signal is input to the loop filter, the loop filter chip output signal is input to the VCO, and the VCO outputs two 8.8GHz signals. One signal is used as the output signal of the PLL1 circuit module and output to the 8-to-1 power divider, while the other signal is used as a phase detection signal and input to the phase detector chip.

6. The frequency control array transmission system based on DDS and PLL according to claim 1, characterized in that, The external mixing power amplifier circuit module includes a mixer, three power amplifiers, and two bandpass filters. The eight 8.2GHz+(n-1)·4MHz sine signals output from the eight-channel DDS excitation loop internal mixing phase-locked loop circuit module are fed to the intermediate frequency signal input terminal of each mixer as intermediate frequency signals. The 8.8GHz signal output from the phase-locked loop PLL1 circuit module is input to power amplifier 4. After power amplification, it is used as the local oscillator signal and input to the mixer. The mixer output signal is input to bandpass filter 4, and the 17GHz+(n-1)·4MHz up-converted signal is input to power amplifier 5. After amplification, it is input to bandpass filter 5 to filter out noise and then input to power amplifier 6. After power amplifier 6, the final eight frequency source signals with a reference carrier of 17GHz and a frequency offset of 4MHz between two adjacent transmit channels are obtained.

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