Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a first area and a second area; the first area comprises a first sub-area and a second sub-area; a plurality of data lines are located in the first area and are divided into a plurality of first data lines and a plurality of second data lines; the plurality of first data lines are located in the first sub-area, the plurality of second data lines are located in the second sub-area, and the second sub-area is located on one side or both sides of the first sub-area; a plurality of wires are located in the second area, and the plurality of wires are divided into a plurality of first wires and a plurality of second wires; the first wires are connected with the first data lines in correspondence; the second wires are connected with the second data lines in correspondence; in at least part of the first wires, at least one second wire is inserted between two adjacent first wires; a peripheral circuit comprises a plurality of switch modules, the switch modules are connected with the data lines through the wires; the plurality of switch modules comprise at least two different types of switch modules; and the arrangement mode of the switch modules is determined according to the arrangement mode of the first wires and the second wires.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the continuous development of display technology, people have higher and higher requirements for display panels, especially the requirement that the frame of the display panel can be narrower and narrower. However, the fan-out wiring and various frame circuits need to be arranged in the frame of the display panel, and the existence of the fan-out wiring and the frame circuit limits the further reduction of the frame. SUMMARY

[0003] The present application provides a display panel and a display device to reduce the frame width of the display panel.

[0004] According to an aspect of the present application, a display panel is provided, comprising:

[0005] a first area and a second area at least partially surrounding the first area; the first area comprising a first sub-area and a second sub-area;

[0006] a plurality of data lines arranged in sequence in the first area, the plurality of data lines being divided into a plurality of first data lines and a plurality of second data lines; the plurality of first data lines being located in the first sub-area, and the plurality of second data lines being located in the second sub-area, the second sub-area being located on one side or both sides of the first sub-area;

[0007] a plurality of wiring lines arranged in sequence in the second area, the plurality of wiring lines being divided into a plurality of first wiring lines and a plurality of second wiring lines; the first wiring lines being connected to the first data lines in correspondence; the second wiring lines being connected to the second data lines in correspondence; in at least part of the first wiring lines, at least one second wiring line is inserted between two adjacent first wiring lines;

[0008] a peripheral circuit, the peripheral circuit comprising a plurality of switch modules, the switch modules being connected to the data lines through the wiring lines; the plurality of switch modules comprising at least two different types of switch modules; the arrangement mode of the switch modules being determined according to the arrangement mode of the first wiring lines and the second wiring lines.

[0009] Optionally, the first N data lines and the last M data lines in the data lines are the second data lines, and the first wiring lines and the second wiring lines are arranged in a preset rule; wherein N and M are both positive integers;

[0010] Preferably, the preset rule comprises: in at least part of the first wiring lines, b second wiring lines are inserted every a first wiring lines; wherein a and b are both positive integers;

[0011] Preferably, the preset rule further comprises that the connection mode of the plurality of second wires and the plurality of second data lines is forward connection or reverse connection.

[0012] Optionally, the display panel further comprises a plurality of pixel units, the pixel units comprising a plurality of sub-pixels; the data lines are connected with the plurality of sub-pixels; the types of the first data lines and the second data lines both comprise at least two types, and the colors and / or arrangement modes of the sub-pixels connected with different types of the data lines are different.

[0013] Optionally, the pixel unit comprises a first sub-pixel, a second sub-pixel and a third sub-pixel.

[0014] The types of the data lines comprise a first type of data line, a second type of data line and a third type of data line; wherein the sub-pixels connected with the first type of data line are the first sub-pixel and the second sub-pixel; the sub-pixels connected with the second type of data line are the first sub-pixel and the second sub-pixel; the arrangement order of the first sub-pixel and the second sub-pixel connected with the second type of data line is different from the arrangement order of the first sub-pixel and the second sub-pixel connected with the first type of data line; the sub-pixels connected with the third type of data line are all the third sub-pixel.

[0015] Preferably, the first sub-pixel is a blue sub-pixel, the second sub-pixel is a red sub-pixel, and the third sub-pixel is a green sub-pixel.

[0016] Preferably, the arrangement mode of the data lines comprises at least one of the following:

[0017] The data lines are arranged in a first arrangement mode, and the first arrangement mode is that the first type of data line, the third type of data line, the second type of data line and the third type of data line are sequentially arranged as a data line cycle unit along the row direction.

[0018] The data lines are arranged in a second arrangement mode, and the second arrangement mode is that the first type of data line, the third type of data line and the second type of data line are sequentially arranged as a data line cycle unit along the row direction.

[0019] Optionally, the types of the switch modules comprise a first type of switch module, a second type of switch module and a third type of switch module; wherein the first type of switch module is connected with the first type of data line, the second type of switch module is connected with the second type of data line, and the third type of switch module is connected with the third type of data line.

[0020] Preferably, the peripheral circuit is a pixel detection circuit; wherein the first type of switch module comprises a first transistor and a second transistor, a gate of the first transistor is connected to a first switch signal line, a first pole of the first transistor is connected to a first detection signal line, and a second pole of the first transistor is connected to the wire corresponding to the first type of data line; a gate of the second transistor is connected to a second switch signal line, a first pole of the second transistor is connected to a second detection signal line, and a second pole of the second transistor is connected to the wire corresponding to the first type of data line.

[0021] The second type of switch module comprises a third transistor and a fourth transistor, a gate of the third transistor is connected to the first switch signal line, a first pole of the third transistor is connected to the second detection signal line, and a second pole of the third transistor is connected to the wire corresponding to the second type of data line; a gate of the fourth transistor is connected to the second switch signal line, a first pole of the fourth transistor is connected to the first detection signal line, and a second pole of the fourth transistor is connected to the wire corresponding to the second type of data line.

[0022] The third type of switch module comprises a fifth transistor, a gate of the fifth transistor is connected to a third switch signal line, a first pole of the third transistor is connected to a third detection signal line, and a second pole of the third transistor is connected to the wire corresponding to the third type of data line.

[0023] Optionally, the pixel unit comprises: a first sub-pixel, a second sub-pixel, and a third sub-pixel.

[0024] The type of the data line comprises: a fourth type of data line, a fifth type of data line, and a sixth type of data line; wherein the sub-pixel connected with the fourth type of data line is the first sub-pixel; the sub-pixel connected with the fifth type of data line is the second sub-pixel; and the sub-pixel connected with the sixth type of data line is the third sub-pixel.

[0025] Preferably, the first sub-pixel is a blue sub-pixel, the second sub-pixel is a red sub-pixel, and the third sub-pixel is a green sub-pixel.

[0026] Preferably, the data line is arranged in a third arrangement mode, and the third arrangement mode is that the fourth type of data line, the fifth type of data line, and the sixth type of data line are sequentially arranged as a data line cycle unit along the row direction.

[0027] Optionally, the types of the switch modules comprise a fourth type of switch module, a fifth type of switch module and a sixth type of switch module; wherein the fourth type of switch module is connected with the fourth type of data line, the fifth type of switch module is connected with the fifth type of data line, and the sixth type of switch module is connected with the sixth type of data line.

[0028] Preferably, the peripheral circuit is a pixel detection circuit; wherein the fourth type of switch module comprises a sixth transistor, a gate of the sixth transistor is connected with a first switch signal line, a first pole of the sixth transistor is connected with a first detection signal line, and a second pole of the sixth transistor is connected with the wire corresponding to the fourth type of data line.

[0029] The fifth type of switch module comprises a seventh transistor, a gate of the seventh transistor is connected with a second switch signal line, a first pole of the seventh transistor is connected with a second detection signal line, and a second pole of the seventh transistor is connected with the wire corresponding to the fifth type of data line.

[0030] The sixth type of switch module comprises an eighth transistor, a gate of the eighth transistor is connected with a third switch signal line, a first pole of the eighth transistor is connected with a third detection signal line, and a second pole of the eighth transistor is connected with the wire corresponding to the sixth type of data line.

[0031] Optionally, at least part of the switch modules are arranged in cycles with a circuit cycle unit as a minimum cycle unit; wherein the number of the switch modules in the circuit cycle unit is associated with the arrangement mode of the first wire and the second wire.

[0032] Optionally, the data line comprises a plurality of data line cycle units arranged in sequence along a row direction, and each data line cycle unit comprises c data lines arranged in sequence along the row direction, wherein c is a positive integer greater than 1.

[0033] Each data line cycle unit comprises at least two types of data lines, and different types of the data lines are connected with different types of the switch modules.

[0034] The number of the switch modules in the circuit cycle unit is (a+b)*c; wherein in at least part of the first wires, b second wires are inserted into every a first wires, and a and b are positive integers.

[0035] Optionally, the peripheral circuit is a pixel detection circuit, the order of the switch modules corresponding to the first wire is a first type of order, the first type of order is associated with a pixel arrangement mode; and the order of the switch modules corresponding to the second wire is a second type of order, the second type of order is associated with the pixel arrangement and the arrangement mode of the first wire and the second wire.

[0036] In the circuit cycle unit, the arrangement of the (a+b)*c switch modules is interleaved arrangement of the first type of arrangement and the second type of arrangement.

[0037] Preferably, the pixel arrangement is the second pixel arrangement, a=1, b=1, c=3, the number of switch modules in the circuit cycle unit is six; the number of switch modules using the first type of arrangement and the number of switch modules using the second type of arrangement are both three; the minimum cycle unit of the peripheral circuit includes two first type of switch modules, two second type of switch modules and two third type of switch modules.

[0038] Alternatively, the pixel arrangement is the second pixel arrangement, a=3, b=1, c=3, the number of switch modules in the circuit cycle unit is twelve; the number of switch modules using the first type of arrangement is nine, the number of switch modules using the second type of arrangement is three; the minimum cycle unit of the peripheral circuit includes four first type of switch modules, four second type of switch modules and four third type of switch modules.

[0039] Alternatively, the pixel arrangement is the first pixel arrangement, a=1, b=1, c=4, the number of switch modules in the circuit cycle unit is eight; the number of switch modules using the first type of arrangement and the number of switch modules using the second type of arrangement are both four; the minimum cycle unit of the peripheral circuit includes two first type of switch modules, two second type of switch modules and four third type of switch modules.

[0040] Alternatively, the pixel arrangement is the first pixel arrangement, a=4, b=1, c=4, the number of switch modules in the circuit cycle unit is twenty; the number of switch modules using the first type of arrangement is sixteen, the number of switch modules using the second type of arrangement is four; the minimum cycle unit of the peripheral circuit includes five first type of switch modules, five second type of switch modules and ten third type of switch modules.

[0041] Optionally, the peripheral circuit is a multiplexing circuit, and the multiplexing manner of the peripheral circuit is 1:c.

[0042] Optionally, the arrangement of the switch module corresponding to the first wire is the first type of arrangement, the first type of arrangement is associated with the multiplexing manner of the multiplexing circuit; the arrangement of the switch module corresponding to the second wire is the second type of arrangement; the second type of arrangement is associated with the multiplexing manner of the multiplexing circuit and the arrangement manner of the first wire and the second wire.

[0043] The type of the data line includes a class C, and the circuit structure of the switch module has C types; in the circuit cycle unit, the sorting mode of the (a+b)*C switch modules is the first type sorting and the second type sorting interlaced sorting.

[0044] Preferably, a=1, b=1, c=2, the number of switch modules in the circuit cycle unit is four; the number of switch modules using the first type sorting and the number of switch modules using the second type sorting are both two.

[0045] Alternatively, a=3, b=1, c=2, the number of switch modules in the circuit cycle unit is eight; the number of switch modules using the first type sorting and the number of switch modules using the second type sorting are both four.

[0046] According to another aspect of the present application, a display device is provided, comprising a display panel as described in any embodiment of the present application.

[0047] The embodiment of the present application inserts the fan-out wires into the fan-out wires corresponding to the sequentially arranged data lines, vertically sets each fan-out wire as much as possible, reduces the angle of each fan-out wire in the frame area, and further compresses the frame width while ensuring that the adjacent fan-out wires do not short circuit and signal interference. That is, the embodiment of the present application reduces the frame by the disorderly arrangement of the fan-out wires. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0049] Figure 1 is a structural schematic diagram of a display panel in the prior art;

[0050] Figure 2 is a structural schematic diagram of another display panel in the prior art;

[0051] Figure 3 is a structural schematic diagram of a display panel provided by the embodiment of the present application;

[0052] Figure 4 is Figure 3 is an enlarged structural schematic diagram of the region BB in the middle;

[0053] Figure 5 is a structural schematic diagram of another display panel provided by the embodiment of the present application;

[0054] Figure 6 FIG. 4 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0055] Figure 7 FIG. 5 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0056] Figure 8 FIG. 6 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0057] Figure 9 FIG. 7 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0058] Figure 10 FIG. 8 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0059] Figure 11 FIG. 9 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0060] Figure 12 FIG. 10 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0061] Figure 13 FIG. 11 is a structural schematic diagram of another display panel according to an embodiment of the present application. DETAILED DESCRIPTION

[0062] In order to make the personnel in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by the personnel in the art without creative labor should belong to the protection scope of the present application.

[0063] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be exchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0064] As described in the background art, display panels have a problem of wide border width. The inventors have found that by changing the configuration of fan-out wiring and border circuits, the border width of the display panel can be further compressed, as described in detail below.

[0065] Figure 1 Schematic diagram of the structure of a display panel in the prior art. Figure 1 The display panel includes a first area AA and a second area NAA. For example, the first area AA is a display area, and a large number of sub-pixels ( Figure 1 The second area NAA is a frame area (not shown) and a plurality of data lines 10 extending along the column direction Y, the data lines 10 are used to provide data signals to the sub-pixels. Exemplarily, the second area is a frame area, and the second area NAA is arranged around the first area AA. Taking a rectangular display panel as an example, the second area NAA is divided into four areas, namely the upper frame, the lower frame, the left frame and the right frame. In particular, the width of the second area NAA where the wiring 20 and the peripheral circuit 30 are provided is relatively wide, which limits the further reduction of the display panel frame. The embodiment of the present invention improves the lower frame of the second area NAA to achieve further reduction of the display panel frame.

[0066] Specifically, the trace 20 is connected between the data line 10 and the peripheral circuit 30, and serves as a connecting trace between the data line 10 and the peripheral circuit 30. Therefore, under normal circumstances, the trace 20 corresponds to the data line 10 one by one. Figure 1 It can be seen that the wiring method of the existing routing 20 is fan-shaped, and the routing 20 can also be called a fan-out routing. This arrangement can achieve a one-to-one connection between the routing 20 and the data line 10. However, with the continuous improvement of the resolution of the display panel, the number of data lines 10 and routing 20 has further increased. In particular, there are more routings in the left and right rounded corners at the lower end of the first area AA, and the layout space of the routing 20 is limited, requiring a larger frame. In addition, setting a larger frame can leave enough distance between the obliquely arranged routings 20 to avoid line short circuits and signal interference. Therefore, the second area NAA needs to reserve a wider layout space for the routing 20, so that the width of the second area NAA is wider.

[0067] Figure 2 Schematic diagram of another display panel structure in the prior art. Figure 2 , in the row direction X, the trace 20 in the middle is Figure 1The layout of the middle routing 20 is the same. The routing 20 on both sides is wound to the middle in the second area NAA, and is wound to the corresponding data line 10 in the first area AA. For example, the first routing line 20 from left to right is led out by the peripheral circuit 30, extends to the upper left in the second area NAA, then extends to the right to the middle area, and then extends to the left from the middle of the first area AA, and is connected to the first data line 10 from left to right; the second routing line 20 from left to right is led out by the peripheral circuit 30, extends to the upper left in the second area NAA, then extends to the right to the middle area, and then extends to the left from the middle of the first area AA, and is connected to the second data line 10 from left to right; and so on. It can be seen from this that Figure 2 The layout of the traces 20 shown can avoid arranging the traces 20 in the left and right rounded corners at the lower end of the first area AA, and using the first area AA for arranging the traces 20 can reduce the border width to a certain extent.

[0068] However, the parts of each routing line 20 located in the second area NAA still need to be arranged diagonally, and in order to ensure sufficient distance between the diagonally arranged routing lines 20 to avoid line short circuits and signal interference, the second area NAA still needs to reserve wider routing space for the routing lines 20, thereby limiting the further reduction of the second area NAA.

[0069] In view of this, an embodiment of the present invention provides a display panel in which the wiring 20 and the peripheral circuit 30 are redesigned to further reduce the width of the second area NAA, as described in detail below.

[0070] Figure 3 A schematic structural diagram of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 4 yes Figure 3 Schematic diagram of the enlarged structure of the middle area BB. Figure 3 and Figure 4 , the display panel includes:

[0071] The first area AA and the second area NAA at least partially surrounding the first area AA; the first area AA includes a first sub-area AA1 and a second sub-area AA2.

[0072] A plurality of data lines 10 are located in the first area AA and arranged in sequence. The plurality of data lines 10 are divided into a plurality of first data lines 11 and a plurality of second data lines 12. The plurality of first data lines 11 are located in the first sub-area AA1, and the plurality of second data lines 12 are located in the second sub-area AA2. The second sub-area AA2 is located on one side or both sides of the first sub-area AA1. Figure 3 For example, the second sub-area AA2 is located on both sides of the first sub-area AA1.

[0073] A plurality of wires 20 arranged in sequence in the second area NAA, the plurality of wires 20 being divided into a plurality of first wires 21 and a plurality of second wires 22; the first wires 21 are connected to the first data lines 11 in correspondence; the second wires 22 are connected to the second data lines 12 in correspondence; in at least part of the first wires 21, at least one second wire 22 is inserted between two adjacent first wires 21.

[0074] A peripheral circuit 30, the peripheral circuit 30 comprising a plurality of switch modules (for example, switch module SW1, switch module SW2 and switch module SW3), the switch modules being connected to the data lines 10 through the wires 20; the switch modules comprising at least two different types of switch modules; the arrangement mode of the switch modules being determined according to the arrangement mode of the first wires 21 and the second wires 22. Wherein, the circuit structures of the different types of switch modules are different. The arrangement mode of the first wires 21 and the second wires 22 can also be expressed as the insertion mode of the second wires 22.

[0075] Exemplarily, along the row direction X, the data lines 10 arranged in sequence are defined as sequentially arranged, as shown in the following table. Figure 4 As shown in the table, the numbers of the data lines 10 are defined in sequence as data1, data2, data3, data4, data5, data6, data7, data8 and data9. Among them, the data lines numbered as data1, data2, data3 and data4 are the second data lines 12, and the data lines numbered as data5, data6, data7, data8 and data9 are the first data lines 11.

[0076] Along the row direction X, the wires 20 arranged in sequence are defined as sequentially arranged, and the numbers of the wires 20 are defined in sequence as F1, F2, F3, F4, F5, F6, F7, F8 and F9. Among them, the wires numbered as F1, F3, F5, F7 and F9 are the first wires 21, and the first wires 21 are connected to the first data lines 11 in correspondence. Specifically, the first wires numbered as F1, F3, F5, F7 and F9 are connected to the data lines numbered as data5, data6, data7, data8 and data9 in correspondence, respectively. The wires numbered as F2, F4, F6 and F8 are the second wires 22, and the second wires 22 are connected to the second data lines 12 in correspondence. Specifically, the second wires numbered as F2, F4, F6 and F8 are connected to the data lines numbered as data4, data3, data2 and data1 in correspondence, respectively.

[0077] Therefore, it can be seen that the wires numbered F1, F2, F3, F4, F5, F6, F7, F8 and F9 correspond to the connections of data5, data4, data6, data3, data7, data2, data8, data1 and data9, and the connection relationship between the data line 10 and the wire 20 presents the characteristic of disorder.

[0078] In combination Figure 3 And Figure 4 The advantage of such an arrangement is that the present embodiment makes the wires 20 as perpendicular as possible, reduces the angle of the wires 20 in the second area NAA, and thus can further reduce the frame width while ensuring that the adjacent wires 20 do not short circuit and signal interference. That is, the present embodiment reduces the frame width through the disorderly arrangement of the wires 20 and the data line 10. In addition, due to the shortening of the length of the wires 20, the on-wire capacitance and resistance of the wires can be reduced, thereby reducing the difference in capacitance and resistance between different wires and the abrupt change in capacitance and resistance between adjacent wires, and thus the problem of vertical stripes can be improved.

[0079] However, due to the disorderly arrangement of the wires 20 and the data line 10, if the signal output by the peripheral circuit 30 is not adjusted according to the disorderly arrangement, the display will have problems. Therefore, the present embodiment also limits the arrangement of the switch module in the peripheral circuit 30. The function of the switch module is to transmit the signal to the corresponding data line 10, so the arrangement of the switch module needs to correspond to the data line 10, and the corresponding mode is determined by the arrangement of the first wire 21 and the second wire 22. Therefore, the present embodiment determines the arrangement of the switch module according to the arrangement of the first wire 21 and the second wire 22, which can reduce the frame of the display panel while ensuring normal display.

[0080] On the basis of the above embodiments, the arrangement of the switch module is related to various factors, such as the type of the peripheral circuit 30, the arrangement of the first wire 21 and the second wire 22, and the pixel arrangement, etc. The following will specifically describe several arrangement modes, but not as a limitation of the present application.

[0081] Figure 5 Another structure diagram of a display panel provided by the present embodiment is shown. Referring to Figure 5 In an embodiment, the display panel further comprises a plurality of pixel units 40, the pixel unit 40 comprising a plurality of sub-pixels; the data line 10 is connected with the plurality of sub-pixels; the types of the first data line 11 and the second data line 12 both comprise at least two types, and the colors and / or arrangement modes of the sub-pixels connected with different types of data lines are different.

[0082] The plurality of pixel units 40 are arranged in an array along the row direction X and the column direction Y. For example, the pixel unit 40 includes a first sub-pixel B, a third sub-pixel G, a second sub-pixel R, and a third sub-pixel G arranged in sequence. The plurality of data lines 10 extend along the column direction Y, and the data lines 10 are connected to the sub-pixels arranged along the column direction Y.

[0083] by Figure 5 For example, the peripheral circuit 30 is a pixel detection circuit (Cell Test, CT circuit), and the switch control signal lines and detection signal lines connected by different types of switch modules are different. Exemplarily, the switch modules include a first type of switch module SW1, a second type of switch module SW2, and a third type of switch module SW3. The first type of switch module SW1 connects the first switch signal line D_SW1, the second switch signal line D_SW2, the first detection signal line D_B, and the second detection signal line D_R; the third type of switch module SW3 connects the third switch signal line D_SW3 and the third detection signal line D_G; the second type of switch module SW2 connects the first switch signal line D_SW1, the second switch signal line D_SW2, the first detection signal line D_B, and the second detection signal line D_R.

[0084] Figure 5 The arrangement of the switch modules shown is conventional, specifically, the first type switch module SW1, the third type switch module SW3, the second type switch module SW2, the third type switch module SW3, the first type switch module SW1, the third type switch module SW3, the second type switch module SW2, the third type switch module SW3, and the first type switch module SW1. The peripheral circuit 30 circulates in the order of the first type switch module SW1, the third type switch module SW3, the second type switch module SW2, and the third type switch module SW3.

[0085] However, the use of Figure 5 The test method of the detection circuit 30 shown in the figure may cause problems such as blue-green bright lines when detecting red images, red-green bright lines when detecting blue images, and red-blue bright lines when detecting green images, and the inability to debug white images. The specific reasons are:

[0086] The colors and / or arrangements of the sub-pixels connected by the data lines 10 are different. For example, the data lines 10 numbered as data1, data5 and data9 are of the same type, and sequentially connect the first sub-pixel B, the second sub-pixel R, the first sub-pixel B, the second sub-pixel R, the first sub-pixel B and the second sub-pixel R; the data lines 10 numbered as data2, data4, data6 and data8 are of the same type, and connect the third sub-pixel G; the data lines 10 numbered as data3 and data7 are of the same type, and sequentially connect the second sub-pixel R, the first sub-pixel B, the second sub-pixel R, the first sub-pixel B, the second sub-pixel R and the first sub-pixel B.

[0087] However, due to the insertion of the partial wires 20 into the wires 20 corresponding to the sequentially arranged data lines 10, the order of the data lines 10 connected to the sequentially arranged wires 20 is disordered. The order of the data lines 10 connected to the sequentially arranged wires 20 is disordered, which means that the numbers of the wires 20 are sequential, but the numbers of the data lines connected to the sequentially arranged wires 20 are non-sequential. For example, the wires 20 numbered as F1, F2, F3, F4, F5, F6, F7, F8 and F9 connect the data lines 10 numbered as data5, data4, data6, data3, data7, data2, data8, data1 and data9, respectively. Figure 5 For example, the wires 20 numbered as F1, F2, F3, F4, F5, F6, F7, F8 and F9 connect the data lines 10 numbered as data5, data4, data6, data3, data7, data2, data8, data1 and data9, respectively. Figure 5 When the peripheral circuit 30 shown in FIG. 6 is used for picture detection, the detection signal provided by the peripheral circuit 30 is still a sequentially arranged detection signal.

[0088] When the G picture is lit, all the third sub-pixels G in the display panel are lit. Correspondingly, the third switch signal line D_SW3 keeps the fifth transistor T5 open, the signal on the third detection signal line D_G is A1 potential, the third sub-pixel G emits light; the signals on the first switch signal line D_SW1 and the second switch signal line D_SW2 make the first transistor T1 and the second transistor T2 open at different times, and the signals on the first switch signal line D_SW1 and the second switch signal line D_SW2 make the third transistor T3 and the fourth transistor T4 open at different times, the signal on the first detection signal line D_B is B2 potential, and the first sub-pixel B does not emit light; the signal on the second detection signal line D_R is B3 potential, and the second sub-pixel R does not emit light.

[0089] If the B or R screen is illuminated, all first subpixels B or second subpixels R in the display panel are illuminated. Accordingly, the third switch signal line D_SW3 keeps the fifth transistor T5 normally on, and the signal on the third detection signal line D_G is at a potential of B1, preventing the third subpixel G from emitting light. The signals on the first and second switch signal lines D_SW1 and D_SW2 cause the first and second transistors T1 and T2 to be turned on in a time-sharing manner. Furthermore, the signals on the first and second switch signal lines D_SW1 and D_SW2 cause the third and fourth transistors T3 and T4 to be turned on in a time-sharing manner. Specifically, when the B screen is illuminated, the signal on the first detection signal line D_B is at a potential of A2, causing the first subpixel B to emit a certain brightness; the signal on the second detection signal line D_R is at a potential of B3, preventing the second subpixel R from emitting light. When the R screen is illuminated, the signal on the first detection signal line D_B is at a potential of B2, preventing the first subpixel B from emitting light; the signal on the second detection signal line D_R is at a potential of A3, preventing the second subpixel R from emitting light in a certain brightness.

[0090] by Figure 5 For example, to illuminate screen B, the first subpixel B in each row needs to be illuminated row by row. Specifically, when illuminating the first subpixel B in the first row, the first switch signal line D_SW1 provides an on signal, the second switch signal line D_SW2 provides an off signal, and the third switch signal line D_SW3 provides an on signal. As a result, the first transistor T1 is controlled to be on, the second transistor T2 is controlled to be off, the third transistor T3 is controlled to be on, the fourth transistor T4 is controlled to be off, and the fifth transistor T5 is controlled to be on. The signal on the third detection signal line D_G is at a potential of B1, the signal on the first detection signal line D_B is at a potential of A2, and the signal on the second detection signal line D_R is at a potential of B3. The detection signals transmitted on the traces 20 numbered F1, F2, F3, F4, F5, F6, F7, F8, and F9 are, in order, A2, B1, B3, B1, A2, B1, B3, B1, and A2. Among them, the routing line 20 numbered F5 transmits the A2 potential to the data line 10 numbered data7, lighting up the second sub-pixel R; the routing line 20 numbered F8 transmits the B1 potential to the data line 10 numbered data1, so that the first sub-pixel B that should have been lit is not lit.

[0091] Similarly, when lighting up sub-pixels in other rows, the second sub-pixel R and the third sub-pixel G may also be lit, resulting in the problem of some of the second and third sub-pixels being lit when detecting the first color image. That is, when detecting a red image, a blue-green bright line appears, when detecting a blue image, a red-green bright line appears, and when detecting a green image, a red-blue bright line appears. Similarly, when debugging a white image, the problem of some sub-pixels receiving detection signals that do not correspond to the sub-pixel color may also occur.

[0092] Due to the above problems, the step of picture detection can be abandoned in the process of manufacturing the mother board of the display panel. However, abandoning the picture detection can cause some defective display panels to be not detected in time.

[0093] Figure 6 Another structure of a display panel is provided in an embodiment of the present application. Referring to FIG. 2, the display panel comprises a plurality of switch modules 10 and a plurality of sub-pixels 20. Figure 6 In an embodiment of the present application, the arrangement of the switch modules 10 arranged in sequence along the row direction X matches the arrangement of the first and second wires 21 and 22. For example, the arrangement of the switch modules 10 is shown in FIG. 2. Figure 6 For example, in the arrangement of the sub-pixels shown in FIG. 2, when the first row of sub-pixels is lighted, the detection signals transmitted on the wires 20 numbered F1, F2, F3, F4, F5, F6, F7, F8 and F9 in sequence are A2 potential, B1 potential, B1 potential, B3 potential, B3 potential, B1 potential, B1 potential, A2 potential and A2 potential in sequence, so that all the first sub-pixels B in the first row of sub-pixels emit light, and all the second and third sub-pixels R and G do not emit light. Similarly, when the second row of sub-pixels is lighted, the detection signals transmitted on the wires 20 numbered F1, F2, F3, F4, F5, F6, F7, F8 and F9 in sequence are B3 potential, B1 potential, B1 potential, A2 potential, A2 potential, B1 potential, B1 potential, B3 potential and B3 potential in sequence, so that all the first sub-pixels B in the second row of sub-pixels emit light, and all the second and third sub-pixels R and G do not emit light.

[0094] From the perspective of the sub-pixels corresponding to a data line 10, the data line 10 numbered as data5 corresponds to connecting the first sub-pixel B and the second sub-pixel R, and the switch module arranged correspondingly can make the first sub-pixel B connected to the data line 10 emit light when detecting the B picture, and the second sub-pixel R does not emit light; can make the second sub-pixel R connected to the data line 10 emit light when detecting the R picture, and the first sub-pixel B does not emit light; and can make the first sub-pixel B and the second sub-pixel R connected to the data line 10 both not emit light when detecting the G picture. The data line 10 numbered as data4 corresponds to connecting a column of third sub-pixels G, and the switch module arranged correspondingly can make each third sub-pixel G connected to the data line 10 not emit light when detecting the B picture, can make each third sub-pixel G connected to the data line 10 not emit light when detecting the R picture, and can make the third sub-pixel G connected to the data line 10 emit light when detecting the G picture. The data line 10 numbered as data3 corresponds to connecting the second sub-pixel R and the first sub-pixel B, and the switch module arranged correspondingly can make the first sub-pixel B connected to the data line 10 emit light when detecting the B picture, and the second sub-pixel R does not emit light; can make the second sub-pixel R connected to the data line 10 emit light when detecting the R picture, and the first sub-pixel B does not emit light; and can make the first sub-pixel B and the second sub-pixel R connected to the data line 10 both not emit light when detecting the G picture. That is, when detecting the B picture, the detection signal received by each first sub-pixel B is the first detection signal provided by the first detection signal line D_B; when detecting the R picture, the detection signal received by each second sub-pixel R is the second detection signal provided by the second detection signal line D_R; and when detecting the third color picture, the detection signal received by each third sub-pixel G is the third detection signal provided by the third detection signal line D_G.

[0095] It can be seen that, by arranging the switch modules in the circuit structure in sequence, the arrangement mode of the first wire 21 and the second wire 22 is determined, the same detection signal is provided to the sub-pixels of the same color, the bright line problem in single-color picture detection is avoided, the single-color picture lighting and white picture debugging can be performed on the screen segment, the loss of the material in the later stage caused by the missed detection of the defective product in the previous stage is avoided, and the production cost is reduced.

[0096] In the above embodiments, there are various ways of inserting the second wire 22 into the first wire 21, and the arrangement mode of the peripheral circuit 30 is also different. The inventor has found that, if there is a rule in the arrangement mode of the first wire 21 and the second wire 22, the minimum cycle unit of the switch module can be arranged according to the arrangement mode of the first wire 21 and the second wire 22, so as to simplify the setting difficulty of the switch module.

[0097] In the following embodiments, first the several insertion modes of the second traces 22 are described, but not as a limitation to the present application.

[0098] In an embodiment of the present application, optionally, the first N data lines 10 and the last M data lines 10 are the second data lines 12, and the second traces 22 are inserted into the first traces 21 in a preset rule; wherein N and M are both positive integers. That is, the second sub-area AA2 is located on both sides of the first sub-area AA1, and the second sub-area AA2 on the left side of the first sub-area AA1 has N second data lines 12, and the second sub-area AA2 on the right side of the first sub-area AA1 has M second data lines 12. Preferably, N = M, and the second data lines 12 are symmetrically arranged to simplify the wiring difficulty. Referring to Figures 3-6 , for example, N = M = 4, that is, the first 4 data lines 10 and the last 4 data lines 10 are the second data lines 12. Specifically, the numbers of the first 4 second data lines 12 are data1, data2, data3 and data4 respectively, and the numbers of the corresponding second traces 22 are F8, F6, F4 and F2 respectively.

[0099] It should be noted that the values of N and M can be set as needed, for example, in actual application, N and M can be set as any value in 100-700.

[0100] In an embodiment of the present application, optionally, the preset rule comprises: in at least part of the first traces 21, every a first trace 21 is inserted with b second traces 22; wherein a and b are both positive integers. Referring to Figures 3-6 , for example, a = b = 1, the traces 20 numbered F1, F3, F5, F7 and F9 are the first traces 21, which are defined as sequentially arranged traces; and the traces 20 numbered F2, F4, F6 and F8 are the second traces 22. That is, one first trace 21 is inserted with one second trace 22.

[0101] In an embodiment of the present application, optionally, the preset rule further comprises: the connection mode of the plurality of second traces 22 and the second data lines 12 is forward connection or reverse connection. Referring to Figures 3-6 , for example, in reverse connection, the numbers of the second traces 22 are F2, F4, F6 and F8 respectively, and the numbers of the corresponding second data lines 12 are data4, data3, data2 and data1 respectively.

[0102] On the basis of the above embodiments, the classification mode of the data lines 10 and the classification mode of the peripheral circuit 30 are further described to obtain the circulation rule of the peripheral circuit 30.

[0103] In an embodiment of the present application, optionally, there are three types of the first data line 11 and the second data line 12, which are respectively a first type of data line, a second type of data line and a third type of data line. The sub-pixels connected with the first type of data line are the first sub-pixel B and the second sub-pixel R; the sub-pixels connected with the second type of data line are the first sub-pixel B and the second sub-pixel R; the arrangement order of the first sub-pixel B and the second sub-pixel R connected with the second type of data line is different from that of the first sub-pixel B and the second sub-pixel R connected with the first type of data line; and the sub-pixels connected with the third type of data line are all the third sub-pixel G. For example, the data lines 10 numbered as data1, data5 and data9 are the first type of data line, and the first sub-pixel B and the second sub-pixel R are arranged alternately; the data lines 10 numbered as data3 and data7 are the second type of data line, and the second sub-pixel R and the first sub-pixel B are arranged alternately; and the data lines 10 numbered as data2, data4, data6 and data8 are the third type of data line, and are all connected with the third sub-pixel G.

[0104] Continuing to refer to Figure 6 In an embodiment of the present application, the data lines 10 are arranged in a first arrangement mode, and the first arrangement mode is that the first type of data line, the third type of data line, the second type of data line and the third type of data line are arranged in sequence as a data line cycle unit along the row direction X. Optionally, the first sub-pixel B is a blue sub-pixel, the second sub-pixel R is a red sub-pixel, and the third sub-pixel G is a green sub-pixel. The pixel arrangement mode corresponding to the first arrangement mode is RGBG arrangement; wherein the arrangement mode of the sub-pixels in the pixel unit 40 is the first sub-pixel B, the third sub-pixel G, the second sub-pixel R and the third sub-pixel G; and the first sub-pixel B and the second sub-pixel R in the same column of sub-pixels are arranged alternately. For example, the group of data lines 10 numbered as data1, data2, data3 and data4 correspond to the pixel unit 40.

[0105] In an embodiment of the present application, optionally, there are three types of the data lines 10, and there are three types of the switch modules, which are respectively a first type of switch module SW1, a second type of switch module SW2 and a third type of switch module SW3; wherein the first type of switch module SW1 is connected with the first type of data line, the second type of switch module SW2 is connected with the second type of data line, and the third type of switch module SW3 is connected with the third type of data line. The present application classifies the switch modules in the peripheral circuit 30 according to the types of the data lines, which is beneficial to simplify the setting of the peripheral circuit 30.

[0106] Further, continuing to refer to Figure 6In an embodiment of the present application, the peripheral circuit 30 is a pixel detection circuit, i.e., a CT circuit. The first type of switch module SW1 includes a first transistor T1 and a second transistor T2. The gate of the first transistor T1 is connected to the first switch signal line D_SW1, the first electrode of the first transistor T1 is connected to the first detection signal line D_B, and the second electrode of the first transistor T1 is connected to the wire 20 connected to the first type of data line. The gate of the second transistor T2 is connected to the second switch signal line D_SW2, the first electrode of the second transistor T2 is connected to the second detection signal line D_R, and the second electrode of the second transistor T2 is electrically connected to the second electrode of the first transistor T1. For example, the first type of switch module SW1 is connected to the wires 20 numbered F1, F8, and F9.

[0107] The second type of switch module SW2 includes a third transistor T3 and a fourth transistor T4. The gate of the third transistor T3 is connected to the first switch signal line D_SW1, the first electrode of the third transistor T3 is connected to the second detection signal line D_R, and the second electrode of the third transistor T3 is connected to the wire 20 connected to the second type of data line. The gate of the fourth transistor T4 is connected to the second switch signal line D_SW2, the first electrode of the fourth transistor T4 is connected to the first detection signal line D_B, and the second electrode of the fourth transistor T4 is electrically connected to the second electrode of the third transistor T3. For example, the second type of switch module SW2 is connected to the wires 20 numbered F4 and F5.

[0108] The third type of switch module SW3 includes a fifth transistor T5. The gate of the fifth transistor T5 is connected to the third switch signal line D_SW3, the first electrode of the fifth transistor T5 is connected to the third detection signal line D_G, and the second electrode of the fifth transistor T5 is connected to the wire 20 connected to the third type of data line. For example, the third type of switch module SW3 is connected to the wires 20 numbered F2, F3, F6, and F7.

[0109] On the basis of the above-described embodiments, the arrangement of the switch modules in the peripheral circuit 30 is optionally cycled according to a certain rule, and the smallest cycle unit of the switch modules is defined as a circuit cycle unit. The data lines 10 are periodically arranged along the row direction X, and the data lines 10 include a plurality of data line cycle units arranged along the row direction X in sequence, each data line cycle unit including c data lines arranged along the row direction X in sequence, c being a positive integer greater than 1. Each data line cycle unit includes at least two types of data lines, and different types of data lines 10 are connected to different types of switch modules. The number of switch modules in a circuit cycle unit is (a+b)*c; wherein, in at least part of the first wires 21, b second wires 22 are inserted every a first wires 21, and a and b are positive integers. Still taking the example of the peripheral circuit 30 shown in FIG. 2, the peripheral circuit 30 includes a plurality of circuit cycle units arranged along the row direction X in sequence, each circuit cycle unit including a first type of switch module SW1, a second type of switch module SW2, and a third type of switch module SW3. Figure 6For example, a group of data lines 10 numbered as data1, data2, data3 and data4 is a data line circulation unit, and c=4. In the embodiment of the present application, the data line circulation unit corresponds to the pixel unit 40, and the number of data lines in the data line circulation unit is equal to the number of sub-pixels in the pixel unit. The embodiment of the present application provides a formula for the circulation rule of the pixel detection circuit, thereby reducing the design difficulty of the pixel detection circuit.

[0110] Further, the embodiment of the present application also limits the specific arrangement rule of the circuit circulation unit. That is, the order of the switch module corresponding to the first wire 21 is the first order, and the first order is associated with the pixel arrangement mode; the order of the switch module corresponding to the second wire 22 is the second order, and the second order is associated with the pixel arrangement mode and the rule of inserting the second wire 22 into the first wire. The first order is determined by the pixel arrangement mode, that is, the first order is the conventional order. For example, in the RGBG arrangement mode, the order of each data line 10 is the first data line, the third data line, the second data line and the third data line; correspondingly, the order of the switch module is the first switch module SW1, the third switch module SW3, the second switch module SW2 and the third switch module SW3. The second order is determined by the pixel arrangement and the arrangement mode of the first wire 21 and the second wire 22. For example, in the RGBG arrangement mode, the connection mode of the second wire 22 and the second data line 12 is the normal connection, and the arrangement mode of the second data line 12 is the first data line, the third data line, the second data line and the third data line; correspondingly, the order of the switch module corresponding to the second wire 22 is the first switch module SW1, the third switch module SW3, the second switch module SW2 and the third switch module SW3. For example, in the RGBG arrangement mode, the connection mode of the second wire 22 and the second data line 12 is the reverse connection, and the arrangement of the second data line 12 is the third data line, the second data line, the third data line and the first data line; correspondingly, the order of the switch module is the third switch module SW3, the second switch module SW2, the third switch module SW3 and the first switch module SW2.

[0111] Continuing to refer to Figure 6 In an embodiment of the present application, optionally, N=4, the first 4 data lines 10 are the second data line 12, a=1, b=1, c=4, the number of switch modules in the circuit circulation unit is 8, and the number of switch modules adopting the first order and the number of switch modules adopting the second order are both 4. The 8 switch modules include two first switch modules SW1, two second switch modules SW2 and four third switch modules SW3. Specifically, Table 1 is Figure 3The corresponding setting mode of each data line 10, trace 20, pixel arrangement and switch module in the display panel shown.

[0112] Table 1

[0113]

[0114] As can be seen from Table 1, since the first 8 traces 20 include the first trace 21 and the second trace 22, one second trace 22 is inserted in one first trace, therefore, the first 8 traces 20 correspond to 8 switch modules in disorder. Starting from the 9th trace 20, the minimum cycle unit of the corresponding switch module is the first type of sorting, including 4 switch modules, and the setting order of the 4 switch modules is: the first type of switch module SW1, the third type of switch module SW3, the second type of switch module SW2 and the third type of switch module SW3.

[0115] In the first 8 traces 20, the traces 20 numbered F1, F3, F5 and F7 are the first traces 21, and the sorting of the corresponding switch modules is the first type of sorting, that is, the first type of switch module SW1, the third type of switch module SW3, the second type of switch module SW2 and the third type of switch module SW3. The traces 20 numbered F2, F4, F6 and F8 are the second traces 22, and the sorting of the corresponding switch modules is the second type of sorting. And the connection mode of the second trace 22 and the second data line 12 in Table 1 is reverse connection, and the sorting of the corresponding switch modules is the third type of switch module SW3, the second type of switch module SW2, the third type of switch module SW3 and the first type of switch module SW1.

[0116] The setting order of the circuit cycle unit is that the first type of sorting and the second type of sorting are interleaved, that is, the first type of switch module SW1, the third type of switch module SW3, the third type of switch module SW3, the second type of switch module SW2, the second type of switch module SW2, the third type of switch module SW3, the third type of switch module SW3 and the first type of switch module SW1.

[0117] In another embodiment of the present application, optionally, as shown in Table 2, a=1, b=1, c=4, according to the formula (a+b)*c, the number of switch modules in the circuit cycle unit is 8, and the number of switch modules using the first type of sorting and the second type of sorting is 4. Different from Table 1, N=216, that is, the first 216 data lines 10 in the data line 10 are the second data line 12. Specifically, the difference between Table 2 and Table 1 is that the number of second data lines 12 and second traces 22 is larger, and the peripheral circuit 30 circulates with 8 switch modules as one circuit cycle unit.

[0118] Table 2

[0119]

[0120] As shown in Table 2, the disordered wires 20 are inserted into the ordered wires in a reverse order. Since the number of the disordered wires 20 is large, the circuit cycle unit with 8 switch modules as a group is arranged in the embodiment of the application, thereby reducing the design difficulty of the pixel detection circuit.

[0121] Figure 7 Another structure diagram of a display panel is provided in the embodiment of the application. In an embodiment of the application, optionally, in combination with Figure 7 and Table 3, N=4, the first 4 wires in the data line 10 are the second data line 12, a=1, b=1, c=4, according to the formula (a+b)*c, the number of the switch modules in the circuit cycle unit is 8, and the number of the switch modules adopting the first type of sorting and the switch modules adopting the second type of sorting is 4. Different from Table 1, the position of the second wire 22 inserted into the first wire 21 is different. In the foregoing embodiment, the first first wire 21 (F1) corresponds to the first type of data line (data5), and the first second wire 22 (F2) is inserted after the first first wire 21 (F1). In Table 3, the first first wire 21 (F2) corresponds to the first type of data line (data5), and the first second wire 22 (F1) is inserted before the first first wire 21 (F2). Figure 7

[0122] Table 3

[0123]

[0124]

[0125] As shown in Table 3, in the first 8 wires 20, the wires 20 numbered F2, F4, F6 and F8 are the first wires 21, and the sorting of the corresponding switch modules is the first type of sorting, that is, the first type of switch module SW1, the third type of switch module SW3, the second type of switch module SW2 and the third type of switch module SW3. The wires 20 numbered F1, F3, F5 and F7 are the second wires 22, the sorting of the corresponding switch modules is the second type of sorting, and the connection mode of the second wires 22 and the second data line 12 in Table 1 is reverse connection, and the sorting of the corresponding switch modules is the third type of switch module SW3, the second type of switch module SW2, the third type of switch module SW3 and the first type of switch module SW1.

[0126] The arrangement order of the circuit cycle unit is that the first type of sorting and the second type of sorting are interleaved, that is, the third type of switch module SW3, the first type of switch module SW1, the second type of switch module SW2, the third type of switch module SW3, the third type of switch module SW3, the second type of switch module SW2, the first type of switch module SW1 and the third type of switch module SW3.​

[0127] Therefore, when the insertion positions of the second wires 22 and the first wires 21 are different, the order of the switch modules will change. However, the setting mode of the number of switch modules in the circuit cycle unit, the first order and the second order provided by the embodiment of the present application is suitable for various insertion positions.

[0128] Figure 8 Another structure diagram of a display panel provided by the embodiment of the present application is shown in FIG. 6. In an embodiment of the present application, optionally, in combination with Figure 8 and Table 4, N=216, the first 216 lines in the data lines 10 are the second data lines 12, a=4, b=1, c=4, according to the formula (a+b)*c, the number of switch modules in the circuit cycle unit is 20. Specifically, the difference between Table 4 and Table 2 is that one second wire 22 is inserted into the four first wires 21, and the peripheral circuit 30 is cycled with 20 switch modules as one circuit cycle unit. The number of switch modules using the first order is 16, and the number of switch modules using the second order is 4. The 16 switch modules include 5 first order switch modules SW1, 5 second order switch modules SW2 and 10 third order switch modules SW3.

[0129] Table 4

[0130]

[0131]

[0132] As can be seen from Table 4, the connection mode of the second wire 22 and the second data line 12 is reverse connection, and since the number of the second wires 22 is large, the embodiment of the present application sets the circuit cycle unit with 20 switch modules as a group, thereby reducing the design difficulty of the pixel detection circuit. It can be further concluded that the order of the switch modules corresponding to the first wires 21 numbered F2-F5, F7-F10, F12-F15 and F17-F20 is the first order, i.e., the first order switch module SW1, the third order switch module SW3, the second order switch module SW2 and the third order switch module SW3. The order of the switch modules corresponding to the second wires 22 numbered F1, F6, F11 and F16 is the second order, i.e., the third order switch module SW3, the second order switch module SW2, the third order switch module SW3 and the first order switch module SW1.

[0133] Figure 9 Another structure diagram of a display panel provided by the embodiment of the present application is shown in FIG. 6. In an embodiment of the present application, optionally, in combination with Figure 9and Table 5, the data lines 10 are arranged in a second arrangement mode, and the second arrangement mode is that the first type data line, the third type data line and the second type data line are arranged in sequence as a data line cycle unit along the row direction X. Optionally, the first sub-pixel B is a blue sub-pixel, the second sub-pixel R is a red sub-pixel, and the third sub-pixel G is a green sub-pixel, and the pixel arrangement mode is a first type RBG arrangement. The arrangement mode of the sub-pixels in the pixel unit 40 is the first sub-pixel B, the third sub-pixel G and the second sub-pixel R; the first sub-pixel B and the second sub-pixel R in the same column of sub-pixels are arranged alternately; and the data lines connected with the pixel unit 40 include the first type data line, the third type data line and the second type data line. Illustratively, N = 216, the first 216 data lines 10 in the data lines 10 are the second data lines 12, the data lines numbered as data213, data216, data219 and data222 are the first type data lines, the data lines numbered as data214, data217, data220 and data223 are the third type data lines, and the data lines numbered as data215, data218, data221 and data224 are the second type data lines. The four groups of data lines 10 numbered as data213 to data215, data216 to data218, data219 to data221 and data222 to data224 correspond to the four pixel units 40 in the same row respectively.

[0134] wherein N = 216, the first 216 data lines 10 in the data lines 10 are the second data lines 12, a = 1, b = 1, and c = 3, according to the formula (a+b)*c, the number of the switch modules in the circuit cycle unit is 6, and the number of the switch modules adopting the first type sorting and the number of the switch modules adopting the second type sorting are both 3. The six switch modules include two first type switch modules SW1, two second type switch modules SW2 and two third type switch modules SW3. Specifically, Table 5 is Figure 9 the corresponding setting mode of each data line 10, the wire 20, the pixel arrangement and the switch module in the display panel shown in Table 5.

[0135] Table 5

[0136]

[0137]

[0138] As shown in Table 5, in the first 6 wirings 20, the wirings 20 numbered F1, F3 and F5 are the first wirings 21, and the corresponding switch modules are in the first type order, i.e., the third type switch module SW3, the second type switch module SW2 and the first type switch module SW1. The wirings 20 numbered F2, F4 and F6 are the second wirings 22, and the corresponding switch modules are in the second type order, and the second wirings 22 are connected to the second data lines 12 in the reverse order, and the corresponding switch modules are in the first type switch module SW1, the second type switch module SW2 and the third type switch module SW3.

[0139] The setting order of the circuit cycle units is the first type order and the second type order interlaced, i.e., the third type switch module SW3, the first type switch module SW1, the second type switch module SW2, the second type switch module SW2, the first type switch module SW1 and the third type switch module SW3.

[0140] Figure 10 Another structure schematic diagram of a display panel is provided in the embodiment of the present application. In one embodiment of the present application, optionally, in combination with Figure 10 and Table 6, and Figure 9 The difference is that a=3, b=1, c=3, according to the formula (a+b)*c, the number of switch modules in the circuit cycle unit is 12, the number of switch modules in the first type order is 9, and the number of switch modules in the second type order is 3. The 12 switch modules include four first type switch modules SW1, four second type switch modules SW2 and four third type switch modules SW3.

[0141] Table 6

[0142]

[0143]

[0144] As shown in Table 6, the second wirings 22 are connected to the second data lines 12 in the reverse order, and since the number of the second wirings 22 is large, the embodiment of the present application sets the circuit cycle unit with 12 switch modules as a group, thereby reducing the design difficulty of the pixel detection circuit. It can be further concluded that the wirings numbered F1-F3, F5-F7 and F9-F11 are the first wirings 21, and the corresponding switch modules are in the first type order, i.e., the first type switch module SW1, the third type switch module SW3 and the second type switch module SW2. The wirings 20 numbered F4, F8 and F12 are the second wirings 22, and the corresponding switch modules are in the second type order, i.e., the second type switch module SW2, the third type switch module SW3 and the first type switch module SW1.

[0145] Figure 11Another structural schematic diagram of a display panel is provided for an embodiment of the present application. In an embodiment of the present application, optionally, in combination with Figure 11 In combination with Table 7, the data lines 10 are arranged in a third arrangement, in which the fourth type of data line, the fifth type of data line, and the sixth type of data line are sequentially arranged as a data line cycle unit along the row direction X. Optionally, the first sub-pixel B is a blue sub-pixel, the second sub-pixel R is a red sub-pixel, and the third sub-pixel G is a green sub-pixel, and the pixel arrangement is a second type of RBG arrangement. Specifically, the sub-pixels in the same column are of the same color. The sub-pixels connected to the fourth type of data line are all first sub-pixels B; the sub-pixels connected to the fifth type of data line are all second sub-pixels R; and the sub-pixels connected to the sixth type of data line are all third sub-pixels G.

[0146] The data lines connected to the pixel units 40 include the fourth type of data line, the sixth type of data line, and the fifth type of data line. For example, the data lines numbered data213, data216, and data219 are the fourth type of data line, the data lines numbered data214, data217, and data220 are the sixth type of data line, and the data lines numbered data215 and data218 are the fifth type of data line. The two groups of data lines 10 numbered data213 to data215 and data216 to data218 correspond to two pixel units 40 in the same row, respectively.

[0147] The types of the switch modules include the fourth type of switch module SW4, the fifth type of switch module SW5, and the sixth type of switch module SW6. The fourth type of switch module SW4 is connected to the fourth type of data line, the fifth type of switch module SW5 is connected to the fifth type of data line, and the sixth type of switch module SW6 is connected to the sixth type of data line.

[0148] The fourth type of switch module SW4, the fifth type of switch module SW5, and the sixth type of switch module SW6 each include a transistor. The fourth type of switch module SW4 includes a sixth transistor T6, the gate of the sixth transistor T6 is connected to the first switch signal line D_SW1, the first electrode of the sixth transistor T6 is connected to the first detection signal line D_B, and the second electrode of the sixth transistor T6 is connected to the trace 20 corresponding to the fourth type of data line (for example, the data lines numbered data213, data216, and data219). For example, the fourth type of switch module SW4 is connected to the traces 20 numbered F2, F5, and F8.

[0149] The fifth type of switch module SW5 includes a seventh transistor T7, the gate of the seventh transistor T7 is connected to the second switch signal line D_SW2, the first electrode of the seventh transistor T7 is connected to the second detection signal line D_R, and the second electrode of the seventh transistor T7 is connected to the corresponding wire 20 of the fifth type of data line (for example, data lines numbered data215 and data218). For example, the fifth type of switch module SW5 is connected to the wires 20 numbered F3 and F4.

[0150] The sixth type of switch module SW6 includes an eighth transistor T8, the gate of the eighth transistor T8 is connected to the third switch signal line D_SW3, the first electrode of the eighth transistor T8 is connected to the third detection signal line D_G, and the second electrode of the eighth transistor T8 is connected to the corresponding wire 20 of the sixth type of data line (for example, data lines numbered data214, data217, and data220). For example, the sixth type of switch module SW6 is connected to the wires 20 numbered F1, F6, and F7.

[0151] Wherein, a=1, b=1, c=3, according to the formula (a+b)*c, the number of switch modules in the circuit cycle unit is 6, and the number of switch modules using the first type of sorting and the second type of sorting is 3. The 6 switch modules include two fourth type of switch modules SW4, two fifth type of switch modules SW5, and two sixth type of switch modules SW6. Specifically, Table 7 is Figure 11 The corresponding setting mode of each data line 10, wire 20, pixel arrangement, and switch module in the display panel shown.

[0152] Table 7

[0153]

[0154] As can be seen from Table 5, among the first 6 wires 20, the wires 20 numbered F1, F3, and F5 are the first wires 21, and the corresponding switch modules are sorted in the first type, i.e., the sixth type of switch module SW6, the fifth type of switch module SW5, and the fourth type of switch module SW4. The wires 20 numbered F2, F4, and F6 are the second wires 22, the corresponding switch modules are sorted in the second type, and the connection mode of the second wires 22 and the second data lines 12 is reverse connection, and the corresponding switch modules are sorted in the fourth type of switch module SW4, the fifth type of switch module SW5, and the sixth type of switch module SW6.

[0155] The setting order of the circuit cycle unit is that the first type of sorting and the second type of sorting are interleaved, i.e., the sixth type of switch module SW6, the fourth type of switch module SW4, the fifth type of switch module SW5, the fifth type of switch module SW5, the fourth type of switch module SW4, and the sixth type of switch module SW6.

[0156] It should be noted that in the above embodiments, only part of the pixel arrangement and the arrangement of the first and second wires 21 and 22 corresponding to the setting rule of the switch module are shown, which is not a limitation of the present application. In other embodiments, the pixel arrangement and the arrangement of the first and second wires 21 and 22 can be adjusted as needed, but the setting rule of the switch module is within the protection scope of the present application.

[0157] It should be further noted that in the above embodiments, the peripheral circuit 30 is taken as an example of a pixel detection circuit. In other embodiments, the peripheral circuit 30 can also be a multiplexing circuit (i.e., a demux circuit) or a detection multiplexing circuit. The multiplexing circuit is connected between the driving chip and the data line 10, and is used to provide a data signal from the driving chip to the data line 10 when the display panel is in normal use. The detection multiplexing circuit is connected between the detection device and the data line 10, and is located at the starting position of the data signal (lower than the driving chip in the plan view), and is used to detect the short-circuit defect in the array process after the array substrate is prepared and before evaporation, by providing a data signal from the detection device to the data line 10, and detecting the short-circuit defect in the array process by reading the data signal in the detection device.

[0158] Figure 12 Another structure diagram of a display panel is provided for the embodiments of the present application. In an embodiment of the present application, optionally, referring to Figure 12 , the demultiplexing mode of the peripheral circuit 30 is c1:c, where c is a positive integer. The demultiplexing mode 1:c means that the switch module has 1 input end and c output ends, and the switch module outputs the signal of the input end through the c output ends in time, i.e., one data signal is provided to c data lines 10 in time. Correspondingly, the types of data lines include c types, and the circuit structures of the switch module include c types. For example, c=2, one data signal is provided to two data lines 10 in the first time period and the second time period. The types of data lines include the seventh type and the eighth type, and the data signal is provided to the seventh type of data line in the first time period, and the data signal is provided to the eighth type of data line in the second time period. For example, the odd-numbered data lines 10 numbered as data1, data3, data5, data7 and data9 are the seventh type of data line; and the even-numbered data lines 10 numbered as data2, data4, data6 and data8 are the eighth type of data line.

[0159] The switch module includes a seventh switch module MUX1 connected with the seventh data line and an eighth switch module MUX2 connected with the eighth data line. Preferably, the seventh switch module MUX1 includes a ninth transistor T9, the gate of the ninth transistor T9 is connected with the seventh switch signal line D_Mux1, the first pole of the ninth transistor T9 is connected with the data input signal line, and the second pole of the ninth transistor T9 is connected with the corresponding wire 20. The eighth switch module MUX2 includes a tenth transistor T0, the gate of the tenth transistor T0 is connected with the eighth switch signal line D_Mux2, the first pole of the tenth transistor T0 is connected with the data input signal line, and the second pole of the tenth transistor T0 is connected with the corresponding wire 20.

[0160] In an embodiment of the present application, the data lines 10 are arranged periodically along the row direction X, the data lines 10 include a plurality of data line cycle units arranged along the row direction X in sequence, and each data line cycle unit includes c data lines arranged along the row direction X in sequence, where c is a positive integer greater than 1. Figure 12 The odd-numbered data lines numbered data1, data3, data5, data7, etc. are the seventh data lines, and the even-numbered data lines numbered data2, data4, data6, data8, etc. are the eighth data lines. A group of data lines 10 numbered data1 and data2 is a data line cycle unit, and c = 2 in this case.

[0161] Continuing to refer to Figure 12 The second wires 22 are inserted into the first wires 21 every a first wires 21, the de-multiplexing mode of the peripheral circuit 30 is 1:c, and the number of switch modules in the circuit cycle unit is (a+b)*c. In the embodiment of the present application, the data line cycle unit corresponds to the de-multiplexing mode of the peripheral circuit 30, and the number of data lines 10 in the data line cycle unit is equal to the number of output ends decomposed from one input end of the peripheral circuit 30. The embodiment of the present application provides a formula for the cycle rule of the multi-way de-multiplexing circuit, thereby reducing the design difficulty of the pixel detection circuit.

[0162] Further, the embodiment of the present application also limits the specific arrangement rule of the circuit cycle unit of the demultiplexing circuit. That is, the order of the switch module corresponding to the first wire 21 is the first order, the first order is associated with the demultiplexing mode of the demultiplexing circuit; the order of the switch module corresponding to the second wire 22 is the second order; the second order is associated with the demultiplexing mode of the demultiplexing circuit and the preset rule; c adjacent switch modules are connected to the same input signal end. Wherein, the first order is determined by the demultiplexing mode, that is, the first order is the conventional order. In the circuit cycle unit, the order of the (a+b)*c switch modules is the first order and the second order. Taking the 1:2 demultiplexing mode as an example, the order of each data line 10 is the seventh type of data line and the eighth type of data line arranged alternately; accordingly, the first order of the switch module is the seventh type of switch module MUX1 and the eighth type of switch module MUX2 arranged alternately. The second order is determined by the demultiplexing mode and the preset rule of the wire 20. Taking the 1:2 demultiplexing mode, the connection mode of the second wire 22 and the second data line 12 as the order connection as an example, the order of the second data line 12 connected to each second wire 22 is the seventh type of data line and the eighth type of data line arranged alternately; accordingly, the order of the switch module is the seventh type of switch module MUX1 and the eighth type of switch module MUX2 arranged alternately. Taking the 1:2 demultiplexing mode, the connection mode of the second wire 22 and the second data line 12 as the reverse connection as an example, the order of the second data line 12 connected to each second wire 22 is the eighth type of data line and the seventh type of data line arranged alternately; accordingly, the order of the switch module is the eighth type of switch module MUX2 and the seventh type of switch module MUX1 arranged alternately.

[0163] Continuing to refer to Figure 12 In an embodiment of the present application, optionally, a = 1, b = 1, c = 2, according to the formula (a+b)*c, the number of switch modules in the circuit cycle unit is 4; the number of switch modules using the first order and the number of switch modules using the second order are both 2c. That is, the minimum cycle unit of the peripheral circuit 30 includes two seventh type of switch modules MUX1 and two eighth type of switch modules MUX2. Specifically, Table 8 shows the corresponding setting mode of each data line 10, wire 20, pixel arrangement and switch module in the display panel. Figure 12 It should be noted that although the pixel arrangement mode is listed in Table 8, the setting mode of the switch module is irrelevant to the pixel arrangement mode.

[0164] Table 8

[0165]

[0166] In the first 4 wires 20, the wires 20 numbered F1 and F3 are the first wires 21, and the corresponding switch modules are sorted in the first type, i.e., the seventh type of switch module MUX1 and the eighth type of switch module MUX2. The wires 20 numbered F2 and F4 are the second wires 22, and the corresponding switch modules are sorted in the second type, and the connection mode of the second wires 22 and the second data lines 12 is reverse connection, and the corresponding switch modules are sorted in the eighth type of switch module MUX2 and the seventh type of switch module MUX1.

[0167] The setting order of the circuit cycle unit is that the first type and the second type are interleaved, i.e., the seventh type of switch module MUX1, the eighth type of switch module MUX2, the eighth type of switch module MUX2, and the seventh type of switch module MUX1. The seventh type of switch module MUX1 and the eighth type of switch module MUX2 that are adjacent to each other are connected to the same signal input end. Among them, for the multiplexing circuit, the signal input end is the pin of the driving chip; for the detection multiplexing circuit, the signal input end is the detection terminal connected to the detection equipment.

[0168] Figure 13 Another structure schematic diagram of a display panel is provided for the embodiment of the present application. In an embodiment of the present application, optionally, in combination with Figure 13 and Table 9, different from the foregoing embodiment, a=1, b=1, c=4, according to the formula (a+b)*c, the number of switch modules in the circuit cycle unit is 8. One data signal is provided to 4 data lines 10 in the first time period, the second time period, the third time period, and the fourth time period. The types of the data lines 10 include the seventh type of data line, the eighth type of data line, the ninth type of data line, and the tenth type of data line, and the sub-pixels connected with the seventh type of data line are lit in the first time period, the sub-pixels connected with the eighth type of data line are lit in the second time period, the sub-pixels connected with the ninth type of data line are lit in the third time period, and the sub-pixels connected with the tenth type of data line are lit in the fourth time period. For example, the data lines 10 numbered data1, data5, and data9, etc. 4n+1 are the seventh type of data line; the data lines 10 numbered data2 and data6, etc. 4n+2 are the eighth type of data line; the data lines 10 numbered data3 and data7, etc. 4n+3 are the ninth type of data line; and the data lines 10 numbered data4 and data8, etc. 4n+4 are the tenth type of data line, n is an integer.

[0169] The types of the switch modules include a seventh type of switch module MUX1, an eighth type of switch module MUX2, a ninth type of switch module MUX3, and a tenth type of switch module MUX4; the seventh type of switch module MUX1 is connected with the seventh type of data line, the eighth type of switch module MUX2 is connected with the eighth type of data line, the ninth type of switch module MUX3 is connected with the ninth type of data line, and the tenth type of switch module MUX4 is connected with the tenth type of data line. The seventh type of switch module MUX1 is controlled by a seventh switch signal line D_Mux1, the eighth type of switch module MUX2 is controlled by an eighth switch signal line D_Mux2, the ninth type of switch module MUX3 is controlled by a ninth switch signal line D_Mux3, and the tenth type of switch module MUX4 is controlled by a tenth switch signal line D_Mux4.

[0170] Further, a = 3, b = 1, and c = 2, and according to the formula (a + b) * c, the number of the switch modules in the circuit cycle unit is 8; the number of the switch modules adopting the first type of sorting and the number of the switch modules adopting the second type of sorting are both 4. That is, the minimum cycle unit of the frame circuit includes two seventh type of switch modules MUX1, two eighth type of switch modules MUX2, two ninth type of switch modules MUX3, and two tenth type of switch modules MUX4. Specifically, Table 9 is a corresponding setting mode of the data lines 10, the wires 20, the pixel arrangement, and the switch modules in the display panel shown in Table 8. Figure 13

[0171] Table 9

[0172]

[0173] In the first 8 wires 20, the wires 20 numbered F1, F3, F5, and F7 are the first wires 21, and the sorting of the corresponding switch modules is the first type of sorting, that is, the seventh type of switch module MUX1, the eighth type of switch module MUX2, the ninth type of switch module MUX3, and the tenth type of switch module MUX4. The wires 20 numbered F2, F4, F6, and F8 are the second wires 22, the sorting of the corresponding switch modules is the second type of sorting, and the preset rule is reverse connection, and the sorting of the corresponding switch modules is the tenth type of switch module MUX4, the ninth type of switch module MUX3, the eighth type of switch module MUX2, and the seventh type of switch module MUX1.

[0174] ​The setting sequence of the circuit loop unit is that the first type sorting and the second type sorting are interleaved, that is, the seventh type switch module MUX1, the tenth type switch module MUX4, the eighth type switch module MUX2, the ninth type switch module MUX3, the ninth type switch module MUX3, the eighth type switch module MUX2, the tenth type switch module MUX4 and the seventh type switch module MUX1. Four adjacent seventh type switch modules MUX1, eighth type switch modules MUX2, ninth type switch modules MUX3 and tenth type switch modules MUX4 are connected to the same signal input end. For the multiplexing and demultiplexing circuit, the signal input end is a pin of a driving chip; for the detection multiplexing circuit, the signal input end is a detection terminal connected to a detection device.

[0175] It should be noted that, in the Figure 12 , the transistors in the peripheral circuit 30 are longitudinally arranged, which is usually adopted by the multiplexing and demultiplexing circuit; in the Figure 13 , the transistors in the peripheral circuit 30 are transversely arranged, which is usually adopted by the detection multiplexing circuit. In actual application, adaptive adjustment can be made according to the wiring mode.

[0176] It should be further noted that the value of c can also be 3, 5, 6, 7, etc., which can be set as needed in actual application, as long as the loop mode of the bezel circuit provided in the embodiments of the present application is within the protection scope of the present application.

[0177] In summary, the embodiments of the present application further compress the bezel width by inserting the second wire 22 into the first wire 21, so that each wire 20 is arranged as vertically as possible, and the angle of each wire 20 in the second area NAA is reduced, thereby ensuring that the adjacent wires 20 do not short circuit and signal interference. That is, the embodiments of the present application reduce the bezel by arranging the first wire 21 and the second wire 22. Further, the embodiments of the present application match the circuit structure of the switch modules arranged in sequence with the arrangement mode of the first wire 21 and the second wire 22, so as to provide the same detection signal to the sub-pixels of the same color, thereby avoiding the bright line problem in monochrome picture detection, so that the monochrome picture can be lighted in the screen segment and the white picture can be debugged, thereby avoiding the loss of materials in the later stage caused by the missed detection of defective products in the previous stage, and further reducing the production cost.

[0178] The embodiments of the present application also provide a display device, which can be a mobile phone, a wearable device, a tablet computer, a computer, etc. The display device comprises the display panel provided in any of the embodiments of the present application, and the technical principles and effects are similar, which will not be described in detail.

[0179] It should be understood that the various forms of flow shown above can be used to reorder, add, or remove steps. For example, the steps recited in the present application can be performed in parallel, in series, or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, which are not limited herein.

[0180] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that: include: a first region and a second region at least partially surrounding the first region; the first region including a first sub-region and a second sub-region; a plurality of data lines located in the first area and arranged in sequence, the plurality of data lines being divided into a plurality of first data lines and a plurality of second data lines; the plurality of first data lines being located in the first sub-area, the plurality of second data lines being located in the second sub-area, and the second sub-area being located on one side or both sides of the first sub-area; A plurality of routing lines located in the second area and arranged in sequence, the plurality of routing lines being divided into a plurality of first routing lines and a plurality of second routing lines; the first routing lines being connected to the first data lines; the second routing lines being connected to the second data lines; and at least one second routing line being inserted between two adjacent first routing lines in at least some of the first routing lines; The peripheral circuit includes a plurality of switch modules, and the switch modules are connected to the data line through the routing line; the plurality of switch modules include at least two different types of switch modules; and the arrangement of the switch modules is determined according to the arrangement of the first routing line and the second routing line.

2. The display panel according to claim 1, wherein: The first N and last M of the data lines are the second data lines, and the first lines and the second lines are arranged according to a preset rule; wherein N and M are both positive integers.

3. The display panel according to claim 2, wherein The preset rule includes: in at least part of the first routing lines, inserting b second routing lines for every a first routing lines; wherein a and b are both positive integers.

4. The display panel according to claim 2, wherein: The preset rule further includes: the plurality of second routing lines and the plurality of second data lines are connected in a forward sequence or a reverse sequence.

5. The display panel according to claim 1, wherein: Also includes: A plurality of pixel units, each pixel unit including a plurality of sub-pixels; the data line is connected to the plurality of sub-pixels; the first data line and the second data line each include at least two types, and the sub-pixels connected to the different types of data lines have different colors and / or arrangements.

6. The display panel according to claim 5, wherein: The pixel unit includes: a first sub-pixel, a second sub-pixel and a third sub-pixel; The types of data lines include: first-category data lines, second-category data lines and third-category data lines; wherein the sub-pixels connected to the first-category data lines are the first sub-pixels and the second sub-pixels; the sub-pixels connected to the second-category data lines are the first sub-pixels and the second sub-pixels; the arrangement order of the first sub-pixels and the second sub-pixels connected to the second-category data lines is different from the arrangement order of the first sub-pixels and the second sub-pixels connected to the first-category data lines; the sub-pixels connected to the third-category data lines are all the third sub-pixels.

7. The display panel according to claim 6, wherein: The first sub-pixel is a blue sub-pixel, the second sub-pixel is a red sub-pixel, and the third sub-pixel is a green sub-pixel.

8. The display panel according to claim 6, wherein: The arrangement of the data lines includes at least one of the following: The data lines are arranged in a first arrangement, wherein the first arrangement is to sequentially arrange the first type of data lines, the third type of data lines, the second type of data lines, and the third type of data lines as a data line cycle unit along a row direction; The data lines are arranged in a second arrangement manner, wherein the first type of data lines, the third type of data lines and the second type of data lines are arranged in sequence along a row direction as a data line cycle unit.

9. The display panel according to claim 6, wherein: The types of the switch modules include: a first type switch module, a second type switch module and a third type switch module; wherein the first type switch module is connected to the first type data line, the second type switch module is connected to the second type data line, and the third type switch module is connected to the third type data line.

10. The display panel according to claim 9, wherein: The peripheral circuit is a pixel detection circuit; wherein the first type of switch module includes a first transistor and a second transistor, the gate of the first transistor is connected to a first switch signal line, the first electrode of the first transistor is connected to a first detection signal line, and the second electrode of the first transistor is connected to the routing line corresponding to the first type of data line; the gate of the second transistor is connected to a second switch signal line, the first electrode of the second transistor is connected to a second detection signal line, and the second electrode of the second transistor is connected to the routing line corresponding to the first type of data line; The second-type switch module includes a third transistor and a fourth transistor, wherein the gate of the third transistor is connected to the first switch signal line, the first electrode of the third transistor is connected to the second detection signal line, and the second electrode of the third transistor is connected to the routing line corresponding to the second-type data line; the gate of the fourth transistor is connected to the second switch signal line, the first electrode of the fourth transistor is connected to the first detection signal line, and the second electrode of the fourth transistor is connected to the routing line corresponding to the second-type data line; The third type switch module includes a fifth transistor, the gate of the fifth transistor is connected to the third switch signal line, the first electrode of the third transistor is connected to the third detection signal line, and the second electrode of the third transistor is connected to the routing line corresponding to the third type data line.

11. The display panel according to claim 5, wherein: The pixel unit includes: a first sub-pixel, a second sub-pixel and a third sub-pixel; The types of data lines include: fourth-category data lines, fifth-category data lines, and sixth-category data lines; wherein the sub-pixels connected to the fourth-category data lines are all the first sub-pixels; the sub-pixels connected to the fifth-category data lines are all the second sub-pixels; and the sub-pixels connected to the sixth-category data lines are all the third sub-pixels.

12. The display panel according to claim 11, wherein: The first sub-pixel is a blue sub-pixel, the second sub-pixel is a red sub-pixel, and the third sub-pixel is a green sub-pixel.

13. The display panel according to claim 11, wherein: The data lines are arranged in a third arrangement manner, wherein the fourth type of data lines, the fifth type of data lines, and the sixth type of data lines are arranged in sequence along a row direction as a data line cycle unit.

14. The display panel according to claim 11, wherein: The types of the switch modules include: a fourth-category switch module, a fifth-category switch module, and a sixth-category switch module; wherein the fourth-category switch module is connected to the fourth-category data line, the fifth-category switch module is connected to the fifth-category data line, and the sixth-category switch module is connected to the sixth-category data line.

15. The display panel according to claim 14, wherein: The peripheral circuit is a pixel detection circuit; wherein the fourth type of switch module includes a sixth transistor, the gate of the sixth transistor is connected to the first switch signal line, the first electrode of the sixth transistor is connected to the first detection signal line, and the second electrode of the sixth transistor is connected to the routing line corresponding to the fourth type of data line; The fifth type of switch module includes a seventh transistor, the gate of the seventh transistor is connected to the second switch signal line, the first electrode of the seventh transistor is connected to the second detection signal line, and the second electrode of the seventh transistor is connected to the routing line corresponding to the fifth type of data line; The sixth type of switch module includes an eighth transistor, the gate of the eighth transistor is connected to the third switch signal line, the first electrode of the eighth transistor is connected to the third detection signal line, and the second electrode of the eighth transistor is connected to the routing line corresponding to the sixth type of data line.

16. The display panel according to claim 1, wherein At least part of the switch modules are arranged in a cycle with a circuit cycle unit as the minimum cycle unit; wherein the number of switch modules in the circuit cycle unit is associated with the arrangement of the first routing line and the second routing line.

17. The display panel according to claim 16, wherein: The data line includes a plurality of data line circulation units sequentially arranged along a row direction, and the data line circulation unit includes c data lines sequentially arranged along a row direction, where c is a positive integer greater than 1; Each of the data line circulation units includes at least two types of data lines, and different types of data lines are connected to different types of switch modules; The number of switch modules in the circuit circulation unit is (a+b)*c; wherein, in at least part of the first routing lines, b second routing lines are inserted for every a first routing lines, and a and b are both positive integers.

18. The display panel according to claim 17, wherein: The peripheral circuit is a pixel detection circuit, the order of the switch modules corresponding to the first routing lines is a first order, and the first order is associated with the pixel arrangement; the order of the switch modules corresponding to the second routing lines is a second order, and the second order is associated with the pixel arrangement and the arrangement of the first routing lines and the second routing lines; In the circuit circulation unit, the (a+b)*c switch modules are arranged in an alternating manner of the first type of arrangement and the second type of arrangement.

19. The display panel according to claim 18, wherein: The pixel arrangement is the second pixel arrangement, a=1, b=1, c=3, the number of switch modules in the circuit circulation unit is six; the number of switch modules using the first type of sorting and the number of switch modules using the second type of sorting are both three; the minimum circulation unit of the peripheral circuit includes two first type switch modules, two second type switch modules, and two third type switch modules; Alternatively, the pixel arrangement is the second pixel arrangement, a=3, b=1, c=3, the number of switch modules in the circuit circulation unit is twelve; the number of switch modules using the first type of sorting is nine, and the number of switch modules using the second type of sorting is three; the minimum circulation unit of the peripheral circuit includes four first type switch modules, four second type switch modules, and four third type switch modules; Alternatively, the pixel arrangement is the first pixel arrangement, a=1, b=1, c=4, the number of switch modules in the circuit circulation unit is eight; the number of switch modules using the first type of arrangement and the number of switch modules using the second type of arrangement are both four; the minimum circulation unit of the peripheral circuit includes two first type switch modules, two second type switch modules, and four third type switch modules; Alternatively, the pixel arrangement is the first pixel arrangement, a=4, b=1, c=4, the number of switch modules in the circuit circulation unit is twenty; the number of switch modules using the first category sorting is sixteen, and the number of switch modules using the second category sorting is four; the minimum circulation unit of the peripheral circuit includes five first category switch modules, five second category switch modules and ten third category switch modules.

20. The display panel according to claim 17, wherein The peripheral circuit is a multiplexing demultiplexing circuit, and the demultiplexing mode of the peripheral circuit is 1:c.

21. The display panel according to claim 20, wherein: The order of the switch modules corresponding to the first routing lines is a first type of ordering, which is associated with a demultiplexing mode of the demultiplexing circuit; the order of the switch modules corresponding to the second routing lines is a second type of ordering, which is associated with the demultiplexing mode of the demultiplexing circuit and an arrangement mode of the first routing lines and the second routing lines; The types of the data lines include c types, and the circuit structures of the switch modules include c types; in the circuit circulation unit, the (a+b)*c switch modules are arranged in an alternating manner of the first type of arrangement and the second type of arrangement.

22. The display panel according to claim 21, wherein: a=1, b=1, c=2, the number of switch modules in the circuit circulation unit is four; the number of switch modules using the first type of sorting and the number of switch modules using the second type of sorting are both two; Alternatively, a=3, b=1, c=2, the number of switch modules in the circuit circulation unit is eight; the number of switch modules using the first type of sorting and the number of switch modules using the second type of sorting are both four.

23. A display device, characterized in that: include: A display panel as claimed in any one of claims 1 to 22.

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