Source driving circuit, display device, electronic device and driving chip

Abstract

The present disclosure relates to a source driving circuit, a display device, an electronic device and a driving chip, wherein the source driving circuit comprises: a bus data generating circuit and a pixel driving circuit; when the working mode of the bus data generating circuit is a pixel copying mode, the bus data generating circuit is used to generate a first pixel data group including at least two identical first pixel data by copying the first pixel data after acquiring the first pixel data, and output the first pixel data in the first pixel data group to the pixel driving circuit; wherein different first pixel data correspond to different pixel points in the input image; the pixel driving circuit is used to generate and output a driving signal to a pixel unit array circuit. The source driving circuit provided by the present disclosure can reduce the time for inputting the pixel data of the input image into the data transmission bus, as well as the power consumption, when the resolution of the input image is lower than the resolution of the display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display driving, and in particular to a source driving circuit, a display device, an electronic device and a driving chip. Background Art

[0002] In an existing display panel, if the resolution of an input image (i.e., an image input to the display panel) is smaller than the resolution of the display panel, each pixel data of the input image will be copied a certain number of times before the pixel data of the input image is input to the source driving circuit in the display panel, so that the number of copied pixel data is equal to the number of pixel points in the display panel, and the copied pixel data is input to the data transmission bus to achieve the purpose of driving each pixel unit in the display panel according to the pixel data of the input image. It can be seen that in the prior art, even if the resolution of the input image is smaller than the resolution of the display panel, the number of pixel data input to the data transmission bus will not decrease, thereby causing the time for the pixel data of the input image to be input to the data transmission bus, and the power consumption to remain unchanged.

[0003] In view of this, the present disclosure provides a source driving circuit to solve the problem that the resolution of the input image is reduced, the time for the pixel data of the input image to be input into the data transmission bus, and the power consumption remain unchanged. Summary of the invention

[0004] The present disclosure provides a source driving circuit for driving a pixel unit array circuit of a display panel, wherein the source driving circuit comprises: a bus data generating circuit and a pixel driving circuit; the bus data generating circuit is connected to the pixel unit array circuit through the pixel driving circuit; when the working mode of the bus data generating circuit is a pixel copy mode, the bus data generating circuit is used to sequentially obtain a plurality of first pixel data of an input image input in series, and when the first pixel data is obtained, by copying the first pixel data, a first pixel data group containing at least two identical first pixel data is generated, and the first pixel data in the first pixel data group is output in parallel to the pixel driving circuit; wherein different first pixel data correspond to different pixel points in the input image; when the working mode of the bus data generating circuit is a pixel copy mode, the pixel driving circuit is used to receive each first pixel data in the first pixel data group output by the bus data generating circuit; and generate and output a driving signal corresponding to each first pixel data in each first pixel data group to the pixel unit array circuit; wherein the driving signal corresponding to the first pixel data in the same first pixel data group is used to drive pixel units with continuous distribution positions in the pixel unit array circuit.

[0005] In a possible implementation, the bus data generation circuit includes: a data cache module and a parallel data generation module; the output end of the data cache module is connected to the input end of the parallel data generation module, and the output end of the parallel data generation module is connected to the input end of the pixel driving circuit; the data cache module is used to sequentially acquire and store each of the multiple first pixel data of the input image according to a first preset frequency; and sequentially output the multiple first pixel data of the input image to the parallel data generation module according to a second preset frequency; the parallel data generation module is used to, upon receiving the first pixel data output by the data cache module, copy the first pixel data to generate a first pixel data group containing at least two identical first pixel data, and output the first pixel data in the first pixel data group in parallel to the pixel driving circuit according to the second preset frequency; wherein the first preset frequency is a multiple of the second preset frequency.

[0006] In one possible embodiment, the pixel driving circuit includes: a shift register circuit, which is used to generate and sequentially output at least one enable signal according to a first clock signal; a latch circuit, whose input end is connected to the output end of the shift register circuit and the output end of the bus data generating circuit, and is used to store at least two first pixel data in a first pixel data group corresponding to the enable signal when the enable signal is received, and output at least two first pixel data in at least one stored first pixel data group to a driving signal generating circuit; a driving signal generating circuit, whose input end is connected to the output end of the latch circuit, and is used to generate and output a driving signal corresponding to each first pixel data in the first pixel data group to a pixel unit corresponding to each first pixel data in the first pixel data group according to the received at least two first pixel data in the first pixel data group and the correspondence between the first pixel data and the pixel unit.

[0007] In one possible implementation, the shift register circuit is also used to multiply the first clock signal to generate a second clock signal; based on each second timing pulse in the second clock signal, an enable signal corresponding to each second timing pulse is generated and output to the latch circuit, driving the latch circuit to receive at least two first pixel data in the first pixel data group corresponding to the enable signal until the latch circuit receives all the first pixel data of the input image; wherein the frequency of the second timing pulse is equal to the frequency of the input of the multiple pixel data of the input image to the bus data generation circuit.

[0008] In a possible implementation, when the working mode of the bus data generation circuit is not the pixel copy mode, the bus data generation circuit is used to sequentially acquire a plurality of first pixel data of the input image; divide a preset number of first pixel data of continuous input timing into a second pixel data group; for each second pixel data group, output in parallel at least two first pixel data in each second pixel data group to the pixel driving circuit; when the working mode of the bus data generation circuit is not the pixel copy mode, the pixel driving circuit is used to copy each first pixel data in each second pixel data group to obtain at least two third pixel data groups corresponding to each second pixel data group; generate and output a driving signal corresponding to each first pixel data in each third pixel data group to the pixel unit array circuit; wherein the first pixel data in the same third pixel data group corresponds to the first pixel data of the same pixel point of the input image, and the pixel units corresponding to the first pixel data of the input image are distributed in a continuous position.

[0009] In a possible implementation, the pixel driving circuit includes: a shift register circuit, for generating and outputting an enable signal corresponding to each first timing pulse in a first clock signal according to each first timing pulse in the first clock signal; a latch circuit, whose input end is connected to the output end of the shift register circuit, and whose output end is connected to a drive signal generating circuit, for storing at least two first pixel data in the second pixel data group corresponding to the enable signal when the enable signal is received; copying each first pixel data in each second pixel data group to obtain at least two third pixel data groups corresponding to each second pixel data group; outputting at least two first pixel data in at least one of the stored third pixel data groups to the drive signal generating circuit; a drive signal generating circuit, for receiving at least two first pixel data in the third pixel data group; generating and outputting a drive signal corresponding to each first pixel data in the third pixel data group to a pixel unit corresponding to each first pixel data in the first pixel data group according to at least two first pixel data in the received third pixel data group and the correspondence between the first pixel data and the pixel unit.

[0010] In a possible implementation, the latch circuit includes: a sampling latch module, a holding latch module and a channel selection module; when the channel selection module is connected between the bus data generation circuit and the sampling latch module, the input end of the channel selection module is connected to the output end of the bus data generation circuit through a plurality of first data transmission channels, and the output end thereof is connected to the input end of the sampling latch module through a plurality of second data transmission channels, so as to receive each first pixel data in the second pixel data group through the plurality of first data transmission channels; according to the correspondence between the first pixel data and the pixel unit, each first pixel data in the second pixel data group is output to the sampling latch module through the corresponding at least two second data transmission channels; wherein the number of the first data transmission channels is equal to the number of at least two first pixel data in each second pixel data group, and the number of the second data transmission channels is equal to the number of pixel units corresponding to at least two first pixel data in each second pixel data group; the output end of the sampling latch module is connected to the input end of the holding latch module through a plurality of third data transmission channels, and the input end thereof is connected to the shift register circuit, so as to receive the enable signal , receiving the first pixel data corresponding to the enable signal output by the channel selection module through the plurality of second data transmission channels, generating and storing each first pixel data in at least two third pixel data groups corresponding to the second pixel data group; determining the third data transmission channel corresponding to each first pixel data in the third pixel data group according to the second data transmission channel corresponding to each first pixel data; outputting each first pixel data in the third pixel data group to the holding latch module through the corresponding third data transmission channel; wherein the plurality of third data transmission channels correspond one-to-one to the plurality of second data transmission channels; the output end of the holding latch module is connected to the input end of the driving signal generating circuit through the plurality of fourth data transmission channels, for determining the fourth data transmission channel corresponding to each first pixel data in the third pixel data group according to the third data transmission channel corresponding to each first pixel data in the third pixel data group when receiving each first pixel data in the third pixel data group; outputting each first pixel data in the third pixel data group to the driving signal generating circuit through the corresponding fourth data transmission channel; wherein the plurality of fourth data transmission channels correspond one-to-one to the plurality of third data transmission channels.

[0011] In a possible implementation manner, the latch circuit includes: a sampling latch module, a holding latch module and a channel selection module; when the channel selection module is connected between the sampling latch module and the holding latch module, the input end of the sampling latch module is connected to the shift register circuit, and is connected to the output end of the bus data generation circuit through a plurality of first data transmission channels, and its output end is connected to the channel selection module through a plurality of second data transmission channels, and is used for receiving the enable signal through the plurality of first data transmission channels, and receiving the first pixel data in the second pixel data group corresponding to the enable signal, and outputting the first pixel data in the second pixel data group to the channel selection module through the corresponding second data transmission channels; wherein the number of the first data transmission channels is equal to the number of the second data transmission channels, and the number of the first pixel data in each of the second pixel data groups; the output end of the channel selection module is connected to the input end of the holding latch module through a plurality of third data transmission channels, and is used for receiving the second pixel data. each first pixel data in the data group; according to the corresponding relationship between the first pixel data and the pixel unit, each first pixel data in the second pixel data group is output to the holding latch module through the corresponding at least two third data transmission channels; wherein the number of the third data transmission channels is equal to the number of pixel units corresponding to at least two first pixel data in each of the second pixel data groups; the output end of the holding latch module is connected to the input end of the driving signal generating circuit through a plurality of fourth data transmission channels, and is used to generate and store each first pixel data in at least two third pixel data groups corresponding to the second pixel data group when receiving the first pixel data output by the channel selection module; according to the third data transmission channel corresponding to each first pixel data in the third pixel data group, the fourth data transmission channel corresponding to each first pixel data is determined; each first pixel data in the third pixel data group is output to the driving signal generating circuit through the corresponding fourth data transmission channel; wherein the plurality of fourth data transmission channels correspond one-to-one to the plurality of third data transmission channels.

[0012] In a possible implementation manner, the latch circuit includes: a sampling latch module, a holding latch module and a channel selection module; when the channel selection module is connected between the holding latch module and the drive signal generating circuit, the input end of the sampling latch module is connected to the shift register circuit, and is connected to the output end of the bus data generating circuit through a plurality of first data transmission channels, and its output end is connected to the holding latch module through a plurality of second data transmission channels, and is used for receiving, through a plurality of first data transmission channels, each first pixel data in the second pixel data corresponding to the enable signal, and outputting each first pixel data in the second pixel data group to the holding latch module through the corresponding second data transmission channel; wherein the number of the first data transmission channels is equal to the number of the second data transmission channels and the number of the first pixel data in each of the second pixel data groups; the output end of the holding latch module is connected to the channel selection circuit through a plurality of third data transmission channels. The input end of the channel selection module is connected to the input end of the driving signal generating circuit through multiple fourth data transmission channels, and is used to receive and store each first pixel data in the second pixel data group; according to the second data transmission channel corresponding to each first pixel data in the second pixel data group, the third data transmission channel corresponding to each first pixel data is determined; and each first pixel data in the second pixel data group is output to the channel selection module through the corresponding third data transmission channel; wherein the plurality of third data transmission channels correspond to the plurality of second data transmission channels one by one; the output end of the channel selection module is connected to the input end of the driving signal generating circuit through multiple fourth data transmission channels, and is used to receive each first pixel data in the second pixel data group; according to the corresponding relationship between the first pixel data and the pixel unit, each first pixel data in the second pixel data group is output to the driving signal generating circuit through the corresponding at least two fourth data transmission channels; wherein the number of fourth data transmission channels is equal to the number of pixel units corresponding to the at least two first pixel data in each second pixel data group.

[0013] In a possible implementation, when the enable signal includes a first enable signal and a second enable signal, the shift register circuit includes a first output end and a second output end; the sampling latch module includes a first sampling latch unit and a second sampling latch unit; the first output end of the shift register circuit is connected to the input end of the first sampling latch unit, and the second output end of the shift register circuit is connected to the input end of the second sampling latch unit; the shift register circuit is used to output the first enable signal to the first sampling latch unit through the first output end, and output the second enable signal to the second sampling latch unit through the second output end; the first sampling latch unit is used to receive the first pixel data corresponding to the odd-numbered first pixel data among the multiple first pixel data of the input image in the case of receiving the first enable signal; the second sampling latch unit is used to receive the first pixel data corresponding to the even-numbered first pixel data among the multiple first pixel data of the input image in the case of receiving the second enable signal.

[0014] According to another aspect of the present disclosure, a display device is further provided, comprising a plurality of display units and at least one source driving circuit as described above.

[0015] In a possible embodiment, the display unit includes a display panel, and the display panel includes at least one of a liquid crystal display panel, a micro light emitting diode display panel, a light emitting diode display panel, a mini light emitting diode display panel, a quantum dot light emitting diode display panel, an organic light emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel and a small pitch display panel.

[0016] According to another aspect of the present disclosure, an electronic device is further provided, comprising the display device described above.

[0017] According to another aspect of the present disclosure, a driver chip is further provided, the driver chip comprising the source driver circuit described above.

[0018] The source driving circuit provided by the present invention can, when the resolution of the input image is smaller than the resolution of the display panel, make the number of first pixel data of the input image serially input to the source driving circuit equal to the number of pixel points in the input image. The first pixel data of the input image is copied by the source driving circuit, thereby ensuring that when the resolution of the input image is smaller than the resolution of the display panel, the time required for inputting all pixel data of the input image into the source driving circuit and the power consumed can be reduced.

[0019] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0021] Figure 1 A schematic diagram of the circuit structure of a source driver circuit provided in an embodiment of the present disclosure.

[0022] Figure 2 It is a schematic diagram of the timing of data in a serial input line, data transmitted in a data bus, and N / m enable signals in the prior art.

[0023] Figure 3 A schematic diagram of the circuit structure of another source driving circuit provided in an embodiment of the present disclosure.

[0024] Figure 4 An embodiment of the present disclosure provides a schematic diagram of the timing of data in a serial input line, data transmitted in a data bus, and N / m enable signals.

[0025] Figure 5 A schematic diagram of the circuit structure of another source driving circuit provided in an embodiment of the present disclosure.

[0026] Figure 6 A schematic diagram of the timing of data in a serial input line, data transmitted in a data bus, N / 2m first enable signals, and N / 2m second enable signals provided in an embodiment of the present disclosure.

[0027] Figure 7 A schematic diagram of the circuit structure of another source driving circuit provided in an embodiment of the present disclosure.

[0028] Figure 8 A schematic diagram of the timing of data in a serial input line, data transmitted in a data bus, and N / m enable signals provided in an embodiment of the present disclosure.

[0029] Fig. 9 A schematic diagram of the circuit structure of a latch circuit provided in an embodiment of the present disclosure.

[0030] Fig.10 A schematic diagram of the circuit structure of another source driving circuit provided in an embodiment of the present disclosure.

[0031] Fig.11 A schematic diagram of the circuit structure of another latch circuit provided in an embodiment of the present disclosure.

[0032] Fig.12 A schematic diagram of the circuit structure of another source driving circuit provided in an embodiment of the present disclosure.

[0033] Fig.13 A schematic diagram of the circuit structure of another latch circuit provided in an embodiment of the present disclosure.

[0034] Fig.14 A schematic structural diagram of a display device provided by the present invention. DETAILED DESCRIPTION

[0035] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0036] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0037] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0038] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0039] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0040] See also Figure 1 as well as Figure 2 As shown, in the related art, the display panel includes a source driving circuit 1, a gate driving circuit 3 and a pixel unit array circuit 2. The output end of the source driving circuit 1 is connected to each column of pixel units in the pixel unit array circuit 2 through a plurality of source lines, and the gate driving circuit 3 is connected to each row of pixel units in the pixel unit array circuit 2 through a plurality of gate lines. The gate driving circuit 3 receives the driving signal output by the source driving circuit 1 by driving the pixel units in the pixel unit array circuit 2 row by row, so that the corresponding pixel units emit light. In the case where the gate driving circuit 3 drives the first row of pixel units in the pixel unit array circuit 2, the source driving circuit can output a driving signal A to the pixel units in the first row and the first column of the pixel unit array circuit 2 through the source line S1, output a driving signal B to the pixel units in the first row and the second column of the pixel unit array circuit 2 through the source line S2, output a driving signal C to the pixel units in the first row and the third column of the pixel unit array circuit 2 through the source line S3, and output a driving signal D to the pixel units in the first row and the fourth column of the pixel unit array circuit 2 through the source line S4. Wherein, each driving signal includes three driving sub-signals, and each driving sub-signal is used to drive a sub-pixel unit in the corresponding pixel unit. For example, driving signal A includes: driving sub-signal a1, driving sub-signal a2 and driving sub-signal a3, wherein driving sub-signal a1 is used to drive sub-pixel unit m1 in pixel unit M1 (i.e., pixel unit in the first row and first column in pixel unit array circuit 2), driving sub-signal a2 is used to drive sub-pixel unit m2 in pixel unit M1, and driving sub-signal a3 is used to drive sub-pixel unit m3 in pixel unit M1. It is worth noting that the pixel unit array circuit 2 includes a plurality of pixel units, each pixel unit corresponds to a pixel point of the image displayed by the display panel, and each pixel unit includes three colors of R (red), G (green), and B (blue), and the above sub-pixel units are responsible for displaying one color in the pixel unit. In other words, each driving sub-signal is used to drive a sub-pixel unit corresponding to a color in the corresponding pixel unit to emit light.

[0041] Continue reading Figure 1 as well as Figure 2As shown, in the related art, when the number of pixel units in the pixel unit array circuit 2 is N, and the number of pixel points of the input image of the input display panel is also N, taking the time length of each pixel data of the input image input to the source driving circuit 1 equal to T as an example, at this time, one pixel data of the input image corresponds to one pixel unit in the pixel unit array circuit 2, and different pixel data in the input image corresponds to different pixel units in the pixel unit array circuit 2. The time required for all pixel data (i.e., N pixel data) of the input image to be fully input to the source driving circuit 1 is equal to N*T. However, when the number of pixel points of the input image of the input display panel is N / 2, one pixel data of the input image corresponds to two adjacent pixel units in the pixel unit array circuit 2. At this time, in order to ensure that the source driving circuit 1 can drive the N pixel units in the pixel unit array circuit 2 according to the pixel data corresponding to the N / 2 pixel points of the input image (i.e., N / 2 pixel data), each pixel data of the input image will be copied once before the pixel data of the input image is input to the source driving circuit, and the number of pixel data of the input image after the copy is increased from N / 2 to N, so that different pixel data input to the source driving circuit correspond to different pixel units in the pixel unit array circuit 2. Similarly, taking the time length of each pixel data of the input image input to the source driving circuit 1 equal to T as an example, when the number of pixel data of the input image after the copy is N, the time required for all pixel data of the input image (i.e., N / 2 pixel data) to be fully input to the source driving circuit should be equal to N*T. It can be seen from this that in the existing display panel, even if the number of pixel points of the input image is less than the number of pixel units in the pixel unit array circuit of the display panel (i.e., the resolution of the input image is less than the resolution of the display panel), the time required for all pixel data of the input image to be input to the source driving circuit 1 and the power consumed are still the same as when the resolution of the input image is equal to the resolution of the display panel.

[0042] In view of this, see Figure 1 As shown, the present disclosure provides a source driving circuit, which can make the number of first pixel data of the input image serially input to the source driving circuit equal to the number of pixel points in the input image when the resolution of the input image is smaller than the resolution of the display panel. The first pixel data of the input image is copied by the source driving circuit, thereby ensuring that when the resolution of the input image is smaller than the resolution of the display panel, the time required for inputting all pixel data of the input image into the source driving circuit and the power consumed can be reduced.

[0043] For ease of understanding, specific numerical values ​​are used as an example here. When the resolution of the input image is half the resolution of the display panel, in the prior art, N / 2 first pixel data of the input image are copied once to generate N first pixel data, and then the N first pixel data are input into the source drive circuit. If the time required for each first pixel data to be input into the source drive circuit is equal to T, the total time required for the N / 2 first pixel data of the input image to be input into the source drive circuit is equal to N*T. In the present disclosure, the N / 2 first pixel data of the input image are directly input into the source drive circuit. Similarly, if the time required for each first pixel data to be input into the source drive circuit is equal to T, the total time required for the N / 2 first pixel data of the input image to be input into the source drive circuit is equal to (N / 2)*T. Therefore, the source drive circuit provided in the present disclosure can reduce the time required for all the first pixel data of the input image to be input into the source drive circuit, as well as the power consumed, when the resolution of the input image is less than the resolution of the display panel. In addition, it is worth noting that m in the accompanying drawings is used to indicate that the source driving circuit receives the first pixel data of m input images within the effective duration of each enable signal. The specific value of m is not limited in the present disclosure and can usually be selected as 2.

[0044] See also Figure 1 As shown, the source driving circuit 1 provided by the present disclosure is used to drive the pixel unit array circuit 2 of the display panel, and the source driving circuit 1 includes: a bus data generating circuit 11 and a pixel driving circuit 12. The bus data generating circuit 11 is connected to the pixel unit array circuit 2 through the pixel driving circuit 12.

[0045] Exemplarily, when the working mode of the bus data generating circuit 11 is the pixel copy mode, the bus data generating circuit 11 is used to sequentially obtain a plurality of first pixel data of the input image input in series, and when the first pixel data is obtained, by copying the first pixel data, generate a first pixel data group including at least two identical first pixel data, and output the first pixel data in the first pixel data group in parallel to the pixel driving circuit 12. For example: see Figure 4 As shown, the total number of first pixel data of the input image is N / 2, and the first pixel data of the input image is input to the bus data generation circuit 11 one by one through the serial input line. When the bus data generation circuit 11 receives the first pixel data RGB[1] (i.e., the first first pixel data input to the bus data generation circuit 11), the bus data generation circuit 11 copies the first pixel data RGB[1] once to obtain two first pixel data RGB[1]. The first pixel data group A (i.e., Figure 4The first pixel data group in the first pixel data group A is obtained by outputting the two first pixel data RGB[1] in the first pixel data group A in parallel to the pixel driving circuit 12. Similarly, when the bus data generating circuit 11 receives the first pixel data RGB[2] (i.e., the second first pixel data input to the bus data generating circuit), the bus data generating circuit 11 copies the first pixel data RGB[2] once to obtain two first pixel data RGB[2]. The first pixel data group B (i.e., Figure 4 ), and output the two first pixel data RGB[2] in the first pixel data group B in parallel to the pixel driving circuit 12, and so on, until the first pixel data groups corresponding to all the first pixel data of the input image are generated, that is, until the N / 2th first pixel data group is generated.

[0046] Exemplarily, different first pixel data correspond to different pixel points in the input image. Taking the input image as a 2*2 image as an example, the first pixel data RGB[1] may correspond to the pixel point in the first row and first column of the input image, the first pixel data RGB[2] may correspond to the pixel point in the first row and second column of the input image, the first pixel data RGB[3] may correspond to the pixel point in the second row and first column of the input image, and the first pixel data RGB[4] may correspond to the pixel point in the second row and second column of the input image.

[0047] Exemplarily, when the working mode of the bus data generating circuit 11 is the pixel copy mode, the pixel driving circuit 12 is used to receive each first pixel data in the first pixel data group output by the bus data generating circuit 11, and generate and output a driving signal corresponding to each first pixel data in each first pixel data group to the pixel unit array circuit 2. For example: when the bus data generating circuit 11 outputs the first pixel data group A to the pixel driving circuit 12, the pixel driving circuit 12 generates a driving signal to the pixel unit array circuit 2 according to one first pixel data RGB[1] in the first pixel data group A, and generates another driving signal to the pixel unit array circuit 2 according to another first pixel data RGB[1] in the first pixel data group A.

[0048] Exemplarily, the driving signals corresponding to the first pixel data in the same first pixel data group are used to drive the pixel units that are continuously distributed in the pixel unit array circuit 2. For example, when the number of first pixel data of the input image is equal to half the number of pixel units in the pixel unit array circuit 2, the two driving signals generated by the pixel driving circuit 12 according to the two first pixel data RGB[1] in the first pixel data group A can be used to drive the pixel units in the first row and the first column, and the pixel units in the first row and the second column in the pixel unit array circuit.

[0049] In one possible implementation, see Figure 3 as well as Figure 4 As shown, the bus data generation circuit 11 includes: a data cache module 111 and a parallel data generation module 112. The output end of the data cache module 111 is connected to the input end of the parallel data generation module 112, and the output end of the parallel data generation module 112 is connected to the input end of the pixel driving circuit 12.

[0050] Exemplarily, the data cache module 111 is used to sequentially acquire and store each of the multiple first pixel data of the input image according to a first preset frequency. The multiple first pixel data of the input image are sequentially output to the parallel data generation module 112 according to a second preset frequency. The parallel data generation module 112 is used to copy the first pixel data, generate a first pixel data group containing at least two identical first pixel data, and output the first pixel data in the first pixel data group to the pixel driving circuit 12 in parallel according to the second preset frequency, when receiving the first pixel data output by the data cache module 111. For example, taking the time required for each first pixel data of the input image to enter the data cache module 111 as T, and the number of the first pixel data of the input image is N / 2, and the number of pixel units in the pixel unit array circuit 2 is N as an example, the first preset frequency can be set to 1 / T, and the second preset frequency can be set to 1 / 2T, that is, the first preset frequency is twice the second preset frequency, and the data cache module 111 receives the first pixel data of the input image (i.e., RGB[1], RGB[2], RGB[3]...RGB[N / 2]) according to the first preset frequency, and stores the received first pixel data of the input image. At the same time, the first pixel data of the input image is output to the parallel data generation module 112 according to the second preset frequency. When the parallel data generation module 112 receives the first pixel data output by the data buffer module 111, taking the first pixel data RGB[1] as an example, the parallel data generation module 112 copies the first pixel data RGB[1] once to obtain two first pixel data RGB[1]. The first pixel data group A (i.e. Figure 4 The first pixel data group in the first pixel data group A), and the two first pixel data RGB[1] in the first pixel data group A are output in parallel to the pixel driving circuit 12.

[0051] Exemplarily, the first preset frequency is a multiple of the second preset frequency. For example, when the number of first pixel data of the input image is equal to half the number of pixel units in the pixel unit array circuit 2, the first preset frequency is twice the second preset frequency. The magnitude relationship between the first preset frequency and the second preset frequency can be determined according to actual conditions, and the present disclosure does not limit this.

[0052] In one possible implementation, see Figure 5 As shown, the pixel driving circuit 12 includes: a shift register circuit 121, a latch circuit 122 and a driving signal generating circuit 123. The input end of the latch circuit 122 is connected to the output end of the shift register circuit 121 and the output end of the bus data generating circuit 11, and the input end of the driving signal generating circuit 123 is connected to the output end of the latch circuit 122.

[0053] Exemplarily, the shift register circuit 121 is used to generate and sequentially output at least one enable signal according to the first clock signal. For example, the shift register circuit 121 can generate and output the enable signal NO[1] to the latch circuit 122 according to the first timing pulse A in the first clock signal, and generate and output the enable signal NO[2] to the latch circuit 122 according to the first timing pulse B in the first clock signal.

[0054] Exemplarily, the latch circuit 122 is used to store at least two first pixel data in the first pixel data group corresponding to the enable signal when receiving the enable signal, and output at least two first pixel data in the stored at least one first pixel data group to the drive signal generating circuit 123. For example: when the shift register circuit 121 outputs the enable signal NO[1], the latch circuit 122 receives the two first pixel data RGB[1] in the first pixel data group A output by the current bus data generating circuit 11; when the shift register circuit outputs the enable signal NO[2], the latch circuit 122 receives the two first pixel data RGB[2] in the first pixel data group B output by the current bus data generating circuit 11, and so on, until the latch circuit 122 latches all the first pixel data groups corresponding to the first pixel data of the input image into the interior. Here, an input image is taken as a 2*2 image, which includes 4 first pixel data. At this time, the input image corresponds to 4 first pixel data groups, namely the first pixel data group A to the first pixel data group D. When the latch circuit 122 latches the first pixel data in the first pixel data group A to the first pixel data group D, the first pixel data in the first pixel data group A to the first pixel data group D is output to the drive signal generating circuit 123.

[0055] Exemplarily, the driving signal generating circuit 123 is used to generate and output a driving signal corresponding to each first pixel data in the first pixel data group to a pixel unit corresponding to each first pixel data in the first pixel data group according to at least two first pixel data received in the first pixel data group and the correspondence between the first pixel data and the pixel unit. For example, when the latch circuit 122 outputs the first pixel data group A to the driving signal generating circuit 123, the driving signal generating circuit 123 generates a driving signal to the pixel unit array circuit according to one first pixel data RGB[1] in the first pixel data group A. And generates another driving signal to the pixel unit array circuit according to another first pixel data RGB[1] in the first pixel data group A. If the first pixel data RGB[1] corresponds to the pixel unit in the first row and the first column and the pixel unit in the first row and the second column in the pixel unit array circuit 2, the driving signal generating circuit 123 generates two driving signals according to the two first pixel units RGB[1] in the first pixel data group A, which are respectively used to drive the pixel unit in the first row and the first column and the pixel unit in the first row and the second column in the pixel unit array circuit 2.

[0056] In one possible implementation, see Figure 5 as well as Figure 6 As shown, the shift register circuit 121 is also used to multiply the first clock signal to generate a second clock signal, and according to each second timing pulse in the second clock signal, generate and output an enable signal corresponding to each second timing pulse to the latch circuit 122, and drive the latch circuit 122 to receive at least two first pixel data in the first pixel data group corresponding to the enable signal, until the latch circuit 122 receives all the first pixel data of the input image.

[0057] For example, see Figure 5 as well as Figure 6 As shown, the shift register circuit 121 multiplies the input first clock signal to obtain a second clock signal, generates and outputs an enable signal NO[1] to the latch circuit 122 according to the second timing pulse A in the second clock signal, generates and outputs an enable signal NO[2] to the latch circuit 122 according to the second timing pulse B in the second clock signal, and so on. The enable signal NO[1] is used to drive the latch circuit 122 to receive the first pixel data group A (i.e., Figure 6 The enable signal NO[2] is used to drive the latch circuit 122 to receive the first pixel data group B (i.e., the first pixel data group in the bus data generating circuit 11) outputted by the bus data generating circuit 11. Figure 6The latch circuit 122 receives the first pixel data in the N / 2th first pixel data group output by the bus data generating circuit 11, that is, until the latch circuit receives all the first pixel data of the input image.

[0058] Exemplarily, the frequency of the second timing pulse is equal to the frequency of the input bus data generating circuit 11 of the plurality of pixel data of the input image. For example, when the frequency of the pixel data of the input image input bus data generating circuit is 1 / T, the frequency of the second timing pulse is also 1 / T.

[0059] In one possible implementation, see Figure 8 As shown, when the working mode of the bus data generating circuit 11 is not the pixel copy mode, the bus data generating circuit 11 is used to sequentially obtain a plurality of first pixel data of the input image, divide a preset number of first pixel data with continuous input timing into a second pixel data group, and output at least two first pixel data in each second pixel data group to the pixel driving circuit 12 in parallel. For example: see Figure 7 as well as Figure 8 As shown, the bus data generation circuit 11 sequentially obtains the first pixel data RGB[1], the first pixel data RGB[2], the first pixel data RGB[3] ... the first pixel data RGB[N / 2] of the input image. When the preset number is 2, the bus data generation circuit 11 divides the first pixel data RGB[1] and the first pixel data RGB[2] into the second pixel data group A (i.e. Figure 8 In the case where the bus data generating circuit 11 generates the second pixel data group A, the first pixel data RGB[1] and the first pixel data RGB[2] in the second pixel data group A are output in parallel to the pixel driving circuit 12. Similarly, in the case where the bus data generating circuit 11 generates the second pixel data group B, the first pixel data RGB[3] and the first pixel data RGB[4] in the second pixel data group B are output in parallel to the pixel driving circuit 12, and so on, until the bus data generating circuit 11 outputs the first pixel data in the N / 4th second pixel data group to the pixel driving circuit 12.

[0060] Exemplarily, when the working mode of the bus data generating circuit 11 is not the pixel copy mode, the pixel driving circuit 12 is used to copy each first pixel data in each second pixel data group to obtain at least two third pixel data groups corresponding to each second pixel data group, and generate and output a driving signal corresponding to each first pixel data in each third pixel data group to the pixel unit array circuit 2. For example: when the pixel driving circuit 12 receives the first pixel data RGB[1] and the first pixel data RGB[2] in the second pixel data group A output by the bus data generating circuit 11, the pixel data driving circuit 12 copies the first pixel data RGB[1] once to obtain two first pixel data RGB[1], and copies the first pixel data RGB[2] once to obtain two first pixel data RGB[2], and uses the two first pixel data RGB[1] as the third pixel data group A, and uses the two first pixel data RGB[2] as the third pixel data group B, that is, at least two third pixel data groups corresponding to each second pixel data group are obtained. The pixel driving circuit 12 can generate two driving signals corresponding to the two first pixel data RGB[1] according to the third pixel data group A, and generate two driving signals corresponding to the two first pixel data RGB[2] according to the third pixel data group B.

[0061] Exemplarily, the first pixel data in the same third pixel data group corresponds to the first pixel data of the same pixel point in the input image, and the pixel units corresponding to at least two first pixel data in the third pixel data group are distributed in consecutive positions in the pixel unit array circuit. For example: the two first pixel data in the third pixel data group A are both two first pixel data RGB[1], that is, both correspond to the same pixel point in the input image. Similarly, the two first pixel data in the third pixel data group B are both two first pixel data RGB[2], that is, both correspond to the same pixel point in the input image. It can be seen from the above content that the first pixel data RGB[1] corresponds to the pixel unit in the first row and the first column in the pixel array circuit, and the pixel unit in the first row and the second column, that is, the pixel units corresponding to at least two first pixel data in the third pixel data group are distributed in consecutive positions in the pixel unit array circuit.

[0062] In one possible implementation, see Figures 7 to 13 As shown, the pixel driving circuit 12 includes: a shift register circuit 121, a latch circuit 122 and a driving signal generating circuit 123. The input end of the latch circuit 122 is connected to the output end of the shift register circuit 121, and the output end thereof is connected to the driving signal generating circuit.

[0063] Exemplarily, the shift register circuit 121 is used to generate and output an enable signal corresponding to each first timing pulse according to each first timing pulse in the first clock signal when the working mode of the bus data generating circuit 11 is not the pixel copy mode. For example, the shift register circuit 121 can generate and output an enable signal A to the latch circuit 122 according to the first timing pulse A in the first clock signal, and generate and output an enable signal B to the latch circuit 122 according to the first timing pulse B in the first clock signal. Figure 8 As shown, the enable signal A may include: a first enable signal NO[1] and a second enable signal NO[2], and the enable signal B may include: a first enable signal NO[3] and a second enable signal NO[4].

[0064] Exemplarily, the latch circuit 122 is used to store at least two first pixel data in the second pixel data group corresponding to the enable signal when receiving the enable signal, copy each first pixel data in each second pixel data group to obtain at least two third pixel data groups corresponding to each second pixel data group, and output at least two first pixel data in at least one third pixel data group to the drive signal generating circuit 123. For example: when the shift register circuit 121 outputs the enable signal A (which may include Figure 8 In the case where the first enable signal NO[1] and the second enable signal NO[2] are outputted from the current bus data generating circuit 11, the latch circuit 122 receives the first pixel data RGB[1] and the first pixel data RGB[2] in the second pixel data group A outputted from the current bus data generating circuit 11, that is, the latch circuit 122 receives the first pixel data RGB[1] according to the first enable signal NO[1], and receives the first pixel data RGB[2] according to the first enable signal NO[2]. When the shift register circuit 121 outputs the enable signal B (which may include Figure 8In the case of the first enable signal NO[3] and the second enable signal NO[4] in the input image, the latch circuit 122 receives the first pixel data RGB[3] and the first pixel data RGB[4] in the second pixel data group B output by the current bus data generating circuit, that is, the latch circuit 122 receives the first pixel data RGB[3] according to the first enable signal NO[3], and receives the first pixel data RGB[4] according to the first enable signal NO[4], and so on, until the latch circuit 122 latches all the second pixel data groups corresponding to the first pixel data of the input image into the internal part. At the same time, when the latch circuit 122 receives the first pixel data RGB[1] and the first pixel data RGB[2] in the second pixel data group A, the latch circuit 122 copies the first pixel data RGB[1] and the first pixel data RGB[2] in the second pixel data group A, respectively, to obtain two first pixel data RGB[1] and two first pixel data RGB[2], and uses the two first pixel data RGB[1] as the third pixel data group A, and uses the two first pixel data RGB[2] as the third pixel data group B. Here, the input image is a 2*2 image including four first pixel data as an example. At this time, the input image corresponds to two second pixel data groups and four third pixel data groups, namely, the third pixel data group A to the third pixel data group D. When the latch circuit 122 latches the first pixel data in the third pixel data group A to the third pixel data group D, the first pixel data in the third pixel data group A to the third pixel data group D is output to the driving signal generating circuit 123.

[0065] Exemplarily, the driving signal generating circuit 123 is used to receive at least two first pixel data in the third pixel data group, and based on the received at least two first pixel data in the third pixel data group and the correspondence between the first pixel data and the pixel unit, generate and output a driving signal corresponding to each first pixel data in the third pixel data group to the pixel unit corresponding to each first pixel data in the first pixel data group. For example, when the latch circuit 122 outputs the two first pixel data in the third pixel data group A and the third pixel data group B to the driving signal generating circuit 123, the driving signal generating circuit 123 generates two driving signals to the pixel unit array circuit according to the two first pixel data RGB[1] in the third pixel data group A, and generates two driving signals to the pixel unit array circuit 2 according to the two first pixel data RGB[2] in the third pixel data group B.

[0066] In one possible implementation, see Figure 7As shown, the latch circuit 122 includes: a sampling latch module 1221, a holding latch module 1222 and a channel selection module 1223. When the channel selection module 1223 is connected between the bus data generation circuit 11 and the sampling latch module 1221, the input end of the channel selection module 1223 is connected to the output end of the bus data generation circuit 11 through a plurality of first data transmission channels, and the output end of the channel selection module 1223 is connected to the input end of the sampling latch module 1221 through a plurality of second data transmission channels, so as to transmit the data through the plurality of first data transmission channels (corresponding to the sampling latch module 1221). Figure 7 n first data transmission channels, namely LA1 to LAn) receive each first pixel data in the second pixel data group, and transmit each first pixel data in the second pixel data group through at least two corresponding second data transmission channels (corresponding to Figure 7 The x second data transmission channels, namely LB1 to LBx) are output to the sampling latch module 1221.

[0067] Exemplarily, the number of the second data transmission channels may be twice or more than the number of the first data transmission channels, that is, x in the above text is greater than or equal to twice or more than n.

[0068] For example, taking the case where the resolution of the input image is 4*4, the resolution of the display panel is 8*4, and each second pixel data group includes two first pixel data, when the second pixel data group includes two first pixel data, if the channel selection module 1223 receives the first second pixel data group (i.e., the second pixel data group A), the channel selection module 1223 receives the first pixel data RGB[1] in the second pixel data group A through the first data transmission channel LA1, and receives the first pixel data RGB[2] in the second pixel data group A through the first data transmission channel LA2. And according to the corresponding relationship between each first pixel data of the input image and the pixel unit in the pixel unit array circuit 2, the first pixel data RGB[1] is output to the sampling latch module 1221 through the second data transmission channel LB1 and the second data transmission channel LB2, and the first pixel data RGB[2] is output to the sampling latch module 1221 through the second data transmission channel LB3 and the second data transmission channel LB4.

[0069] Exemplarily, the number of first data transmission channels is equal to the number of at least two first pixel data in each second pixel data group. The number of second data transmission channels is equal to the number of pixel units corresponding to at least two first pixel data in each second pixel data group. For example: if the above-mentioned second pixel data group includes two first pixel data, the number of first data transmission channels may be 2. When the resolution of the input image is half of the resolution of the display panel, each first pixel data in the input image corresponds to two adjacent pixel units in the pixel unit array circuit 2, and different first pixel data correspond to different pixel units in the pixel unit array circuit 2. At this time, the number of second data transmission channels is equal to the number of pixel units corresponding to the two first pixel data in each second pixel data group, that is, the number of second data transmission channels is equal to 4.

[0070] Exemplarily, the output end of the sampling latch module 1221 is transmitted through a plurality of third data transmission channels (corresponding to Figure 7 The x third data transmission channels in the sampling latch module 1221, namely, LC1 to LCx) are connected to the input end of the holding latch module 1222, and the input end thereof is connected to the shift register circuit 121. The sampling latch module 1221 is used to receive the first pixel data corresponding to the enable signal output by the channel selection module 1223 through the plurality of second data transmission channels, generate and store each first pixel data in at least two third pixel data groups corresponding to the second pixel data group, determine the third data transmission channel corresponding to each first pixel data according to the second data transmission channel corresponding to each first pixel data, and output each first pixel data in the third pixel data group to the holding latch module 1222 through the corresponding third data transmission channel. The plurality of third data transmission channels correspond one-to-one to the plurality of second data transmission channels.

[0071] Exemplarily, when the sampling latch module 1221 receives the first enable signal NO[1] in the enable signal A, the first pixel data corresponding to the first enable signal NO[1] output by the channel selection module 1223 is received through the second data transmission channel LB1 to the second data transmission channel LBx, that is, the two first pixel data in the first third pixel data group. When the sampling latch module 1221 receives the second enable signal NO[2] in the enable signal A, the first pixel data corresponding to the second enable signal NO[2] output by the channel selection module 1223 is received through the second data transmission channel LB1 to the second data transmission channel LBx, that is, the two first pixel data in the second third pixel data group. That is, at this time, the sampling latch module can receive the first pixel data in the two third pixel data groups generated by the channel selection module 1223 according to the second pixel data group A, that is, the two first pixel data RGB[1], and the two first pixel data RGB[2]. If two first pixel data RGB[1] are input to the sampling latch module 1221 through the second data transmission channel LB1 and the second data transmission channel LB2, and two first pixel data RGB[2] are input to the sampling latch module 1221 through the second data transmission channel LB3 and the second data transmission channel LB4, then the second data transmission channel corresponding to the first pixel data RGB[1] is the second data transmission channel LB1 and the second data transmission channel LB2, and the second data transmission channel corresponding to the first pixel data RGB[2] is the second data transmission channel LB3 and the second data transmission channel LB4. Since the second data transmission channel and the third data transmission channel are in a one-to-one correspondence, the first pixel data RGB[1] can be input to the holding latch module 1222 through the third data transmission channel LC1 and the third data transmission channel LC2, and the first pixel data RGB[2] can be input to the holding latch module 1222 through the third data transmission channel LC3 and the third data transmission channel LC4.

[0072] Exemplarily, the output end of the holding latch module 1222 is connected to the input end of the driving signal generating circuit 123 through a plurality of fourth data transmission channels. The holding latch module 1222 is used to determine the fourth data transmission channel corresponding to each first pixel data in the third pixel data group according to the third data transmission channel corresponding to each first pixel data in the third pixel data group when receiving each first pixel data in the third pixel data group, and output each first pixel data in the third pixel data group to the driving signal generating circuit 123 through the corresponding fourth data transmission channel. The plurality of fourth data transmission channels correspond one-to-one to the plurality of third data transmission channels.

[0073] Exemplarily, when the holding latch module 1222 receives the third pixel data group including two first pixel data RGB[1] and the third pixel data group B including two first pixel data RGB[2], since the first pixel data RGB[1] is input to the holding latch module 1222 through the third data transmission channel LC1 and the third data transmission channel LC2, the first pixel data RGB[2] is input to the holding latch module 1222 through the third data transmission channel LC3 and the third data transmission channel LC4, and the multiple fourth data transmission channels correspond one-to-one to the multiple third data transmission channels, the first pixel data RGB[1] can be output to the drive signal generating circuit 123 through the fourth data transmission channel LD1 and the fourth data transmission channel LD2, and the first pixel data RGB[2] can be output to the drive signal generating circuit 123 through the fourth data transmission channel LD3 and the fourth data transmission channel LD4.

[0074] For example, see Fig. 9As shown, each first pixel data includes three sub-pixel data, that is, the first pixel data RGB[1] includes sub-pixel data R[1], sub-pixel data G[1] and sub-pixel data B[1]. When each second data transmission channel, the third data transmission channel and the fourth data transmission channel can include three data transmission sub-channels, and each data transmission sub-channel is used to transmit one sub-pixel data of the corresponding first pixel data, the channel selection module 1223 outputs the first sub-pixel data R[1] in the first pixel data RGB[1] to the sampling latch module 1 through the sub-channel B1 in the first second data transmission channel and the sub-channel B4 in the second second data transmission channel. 221, outputs the first sub-pixel data G[1] in the first pixel data RGB[1] to the sampling latch module 1221 through the sub-channel B2 in the first second data transmission channel and the sub-channel B5 in the second second data transmission channel, and outputs the first sub-pixel data B[1] in the first pixel data RGB[1] to the sampling latch module 1221 through the sub-channel B3 in the first second data transmission channel and the sub-channel B6 in the second second data transmission channel, thereby outputting the first pixel data RGB[1] in the second pixel data A to the sampling latch module 1221. At this time, the sampling latch module 1221 receives the two first pixel data RGB[1]. At the same time, the channel selection module 1223 can output the first sub-pixel data R[2] in the first pixel data RGB[2] to the sampling latch module 1221 through the sub-channel B7 in the third second data transmission channel and the sub-channel B10 in the fourth second data transmission channel, output the first sub-pixel data G[2] in the first pixel data RGB[2] to the sampling latch module 1221 through the sub-channel B8 in the third second data transmission channel and the sub-channel B11 in the fourth second data transmission channel, and output the first sub-pixel data B[2] in the first pixel data RGB[2] to the sampling latch module 1221 through the sub-channel B9 in the third second data transmission channel and the sub-channel B12 in the fourth second data transmission channel, thereby outputting the first pixel data RGB[2] in the second pixel data A to the sampling latch module 1221. At this time, the sampling latch module 1221 receives two first pixel data RGB[2].

[0075] Exemplarily, when receiving two first pixel data RGB[1] and two first pixel data RGB[2], the sampling latch module 1221 may output the first sub-pixel data R[1] in the first pixel data RGB[1] to the holding latch module 1222 through the sub-channel C1 in the first third data transmission channel and the sub-channel C4 in the second third data transmission channel. The first sub-pixel data G[1] in the first pixel data RGB[1] is output to the holding latch module 1222 through the sub-channel C2 in the first third data transmission channel and the sub-channel C5 in the second third data transmission channel. The first sub-pixel data B[1] in the first pixel data RGB[1] is output to the holding latch module 1222 through the sub-channel C3 in the first third data transmission channel and the sub-channel C6 in the second third data transmission channel, thereby outputting the two first pixel data RGB[1] to the holding latch module 1222. At this time, the holding latch module 1222 receives the two first pixel data RGB[1]. At the same time, the sampling latch module 1221 can output the first sub-pixel data R[2] in the first pixel data RGB[2] to the holding latch module 1222 through the sub-channel C7 in the third third data transmission channel and the sub-channel C10 in the fourth third data transmission channel. The first sub-pixel data G[2] in the first pixel data RGB[2] is output to the holding latch module 1222 through the sub-channel C8 in the third third data transmission channel and the sub-channel C11 in the fourth third data transmission channel. The first sub-pixel data B[2] in the first pixel data RGB[2] is output to the holding latch module 1222 through the sub-channel C9 in the third third data transmission channel and the sub-channel C12 in the fourth third data transmission channel, thereby achieving the purpose of outputting the two first pixel data RGB[2] to the holding latch module 1222. At this time, the holding latch module 1222 receives the two first pixel data RGB[2].

[0076] Exemplarily, when receiving two first pixel data RGB[1] and two first pixel data RGB[2], the holding latch module 1222 may output the first sub-pixel data R[1] in the first pixel data RGB[1] to the driving signal generating circuit 123 through the sub-channel D1 in the first fourth data transmission channel and the sub-channel D4 in the second fourth data transmission channel. The first sub-pixel data G[1] in the first pixel data RGB[1] is output to the driving signal generating circuit 123 through the sub-channel D2 in the first fourth data transmission channel and the sub-channel D5 in the second fourth data transmission channel. The first sub-pixel data B[1] in the first pixel data RGB[1] is output to the driving signal generating circuit 123 through the sub-channel D3 in the first fourth data transmission channel and the sub-channel D6 in the second fourth data transmission channel, thereby outputting the two first pixel data RGB[1] to the driving signal generating circuit 123. At this time, the driving signal generating circuit 123 receives the two first pixel data RGB[1]. At the same time, the sampling latch module 1221 can output the first sub-pixel data R[2] in the first pixel data RGB[2] to the driving signal generating circuit 123 through the sub-channel D7 in the third fourth data transmission channel and the sub-channel D10 in the fourth fourth data transmission channel. The first sub-pixel data G[2] in the first pixel data RGB[2] is output to the driving signal generating circuit 123 through the sub-channel D8 in the third fourth data transmission channel and the sub-channel D11 in the fourth fourth data transmission channel. The first sub-pixel data B[2] in the first pixel data RGB[2] is output to the driving signal generating circuit 123 through the sub-channel D9 in the third fourth data transmission channel and the sub-channel D12 in the fourth fourth data transmission channel, thereby achieving the purpose of outputting the two first pixel data RGB[2] to the driving signal generating circuit 123. At this time, the driving signal generating circuit 123 receives the two first pixel data RGB[2].

[0077] In one possible implementation, see Figure 8 , Fig.10 as well as Fig.11 As shown, the latch circuit 122 includes: a sampling latch module 1221, a holding latch module 1222 and a channel selection module 1223. When the channel selection module 1223 is connected between the sampling latch module 1221 and the holding latch module 1222, the input end of the sampling latch module 1221 is connected to the shift register 121 circuit, and the sampling latch module 1221 is connected to the input end of the shift register 121 circuit through a plurality of first data transmission channels (corresponding to Fig.10 The n first data transmission channels, namely LA1 to LAn) in the bus data generation circuit 11 are connected to the output end of the bus data generation circuit 11, and the output end thereof is connected to the output end of the bus data generation circuit 11 through a plurality of second data transmission channels (corresponding to Fig.10n first data transmission channels, namely, LB1 to LBn) in the first pixel data group are connected to the channel selection module 1223, and are used to receive the first pixel data in the second pixel data group corresponding to the enable signal through the multiple first data transmission channels, and output the first pixel data in the second pixel data group to the channel selection module 1223 through the corresponding second data transmission channels. The number of the first data transmission channels is equal to the number of the second data transmission channels and the number of the first pixel data in each second pixel data group.

[0078] For example, taking the case where the resolution of the input image is 4*4, the resolution of the display panel is 8*4, and each second pixel data group includes two first pixel data, the sampling latch module 1221 receives the second pixel data group corresponding to the enable signal A (i.e., the second pixel data group A) through two first data transmission channels when receiving the first enable signal NO[1] and the second enable signal NO[2] in the enable signal A. The sampling latch module 1221 may receive the first first pixel data (e.g., the first pixel data RGB[1]) in the second pixel data group A according to the first enable signal NO[1] in the enable signal A, and receive the second first pixel data (e.g., the first pixel data RGB[2]) in the second pixel data group A according to the first enable signal NO[2] in the enable signal A. According to the correspondence between the first pixel data and the pixel unit (as shown above), the first pixel data RGB[1] in the second pixel data group A is output to the channel selection module through the second data transmission channel LB1, and the first pixel data RGB[2] in the second pixel data group A is output to the channel selection module 1223 through the second data transmission channel LB2.

[0079] Exemplarily, the output end of the channel selection module 1223 is transmitted through a plurality of third data transmission channels (corresponding to Fig.10 The x third data transmission channels, namely LC1 to LCx, in the second pixel data group are connected to the input end of the holding latch module 1222. The channel selection module 1223 is used to receive each first pixel data in the second pixel data group, and output each first pixel data in the second pixel data group to the holding latch module 1222 through the corresponding at least two third data transmission channels according to the corresponding relationship between the first pixel data and the pixel unit. The number of the third data transmission channels is equal to the number of pixel units corresponding to at least two first pixel data in each second pixel data group.

[0080] Exemplarily, when receiving the first pixel data RGB[1] and the first pixel data RGB[2] in the second pixel data group A, the channel selection module 1223 outputs the first pixel data RGB[1] in the second pixel data group to the holding latch module 1222 through the third data transmission channel LC1 and the third data transmission channel LC2 according to the correspondence between the first pixel data and the pixel unit, and outputs the first pixel data RGB[2] in the second pixel data group to the holding latch module 1222 through the third data transmission channel LC3 and the third data transmission channel LC4.

[0081] Exemplarily, the output end of the latch module 1222 is maintained through a plurality of fourth data transmission channels (corresponding to Fig.10 The x fourth data transmission channels, i.e., LD1 to LDx) in the channel selection module 1223 are connected to the input end of the driving signal generating circuit 123. The holding latch module 1222 is used to generate and store each first pixel data in at least two third pixel data groups corresponding to the second pixel data group after receiving the first pixel data output by the channel selection module 1223, determine the fourth data transmission channel corresponding to each first pixel data according to the third data transmission channel corresponding to each first pixel data in the third pixel data group, and output each first pixel data in the third pixel data group to the driving signal generating circuit 123 through the corresponding fourth data transmission channel. Among them, the plurality of fourth data transmission channels correspond to the plurality of third data transmission channels one by one.

[0082] Exemplarily, the holding latch module 1222 is used to, when receiving the two first pixel data RGB[1] and the two first pixel data RGB[2] output by the channel selection module 1223, use the two first pixel data RGB[1] as the third pixel data group A, and use the two first pixel data RGB[2] as the third pixel data group B. Since the first pixel data RGB[1] is input to the holding latch module 1222 through the third data transmission channel LC1 and the third data transmission channel LC2, the holding latch module 1222 outputs the two first pixel data RGB[1] to the driving signal generating circuit through the fourth data transmission channel LD1 and the fourth data transmission channel LD2. Since the first pixel data RGB[2] is input to the holding latch module 1222 through the third data transmission channel LC3 and the third data transmission channel LC4, the holding latch module 1222 outputs the two first pixel data RGB[2] to the driving signal generating circuit through the fourth data transmission channel LD3 and the fourth data transmission channel LD4.

[0083] For example, see Fig.11As shown, each first pixel data includes three sub-pixel data, that is, the first pixel data RGB[1] includes sub-pixel data R[1], sub-pixel data G[1] and sub-pixel data B[1]. When each second data transmission channel, the third data transmission channel and the fourth data transmission channel can include three data transmission sub-channels, and each data transmission sub-channel is used to transmit one sub-pixel data of the corresponding first pixel data, the sampling latch module 1221 outputs the first sub-pixel data R[1] in the first pixel data RGB[1] to the channel selection module 1223 through the sub-channel B1 in the first second data transmission channel. The first sub-pixel data G[1] in the first pixel data RGB[1] is output to the channel selection module 1223 through the sub-channel B2 in the first second data transmission channel. The first sub-pixel data B[1] in the first pixel data RGB[1] is output to the channel selection module 1223 through the sub-channel B3 in the first second data transmission channel. At this time, the channel selection module 1223 receives one first pixel data RGB[1]. At the same time, the sampling latch module 1221 outputs the first sub-pixel data R[2] in the first pixel data RGB[2] to the channel selection module 1223 through the sub-channel B4 in the second second data transmission channel. The first sub-pixel data G[2] in the first pixel data RGB[2] is output to the channel selection module 1223 through the sub-channel B5 in the second second data transmission channel. The first sub-pixel data B[2] in the first pixel data RGB[2] is output to the channel selection module 1223 through the sub-channel B6 in the second second data transmission channel. At this time, the channel selection module 1223 receives the first pixel data RGB[2].

[0084] Exemplarily, when the channel selection module 1223 receives the first pixel data RGB[1] and the first pixel data RGB[2] (i.e., the first pixel data in the second pixel data group A), the channel selection module 1223 may output the first sub-pixel data R[1] in the first pixel data RGB[1] to the holding latch module 1222 through the sub-channel C1 in the first third data transmission channel and the sub-channel C4 in the second third data transmission channel. The first sub-pixel data G[1] in the first pixel data RGB[1] may be output to the holding latch module 1222 through the sub-channel C2 in the first third data transmission channel and the sub-channel C5 in the second third data transmission channel. The first sub-pixel data B[1] in the first pixel data RGB[1] may be output to the holding latch module 1222 through the sub-channel C3 in the first third data transmission channel and the sub-channel C6 in the second third data transmission channel. Thus, the purpose of outputting the first pixel data RGB[1] in the second pixel data A to the holding latch module 1222 is achieved. At this time, the sampling latch module 1221 receives the two first pixel data RGB[1]. At the same time, the channel selection module 1223 can output the first sub-pixel data R[2] in the first pixel data RGB[2] to the holding latch module 1222 through the sub-channel C7 in the third third data transmission channel and the sub-channel C10 in the fourth third data transmission channel. The first sub-pixel data G[2] in the first pixel data RGB[2] can be output to the holding latch module 1222 through the sub-channel C8 in the third third data transmission channel and the sub-channel C11 in the fourth third data transmission channel. The first sub-pixel data B[2] in the first pixel data RGB[2] can be output to the holding latch module 1222 through the sub-channel C9 in the third third data transmission channel and the sub-channel C12 in the fourth third data transmission channel. Thereby, the purpose of outputting the first pixel data RGB[2] in the second pixel data A to the holding latch module 1222 is achieved. At this time, the sampling latch module 1221 receives two first pixel data RGB[2].

[0085] Exemplarily, when receiving two first pixel data RGB[1] and two first pixel data RGB[2], the holding latch module 1222 may output the first sub-pixel data R[1] in the first pixel data RGB[1] to the driving signal generating circuit 123 through the sub-channel D1 in the first fourth data transmission channel and the sub-channel D4 in the second fourth data transmission channel. The first sub-pixel data G[1] in the first pixel data RGB[1] is output to the driving signal generating circuit 123 through the sub-channel D2 in the first fourth data transmission channel and the sub-channel D5 in the second fourth data transmission channel. The first sub-pixel data B[1] in the first pixel data RGB[1] is output to the driving signal generating circuit 123 through the sub-channel D3 in the first fourth data transmission channel and the sub-channel D6 in the second fourth data transmission channel, thereby outputting the two first pixel data RGB[1] to the driving signal generating circuit 123. At this time, the driving signal generating circuit 123 receives the two first pixel data RGB[1]. At the same time, the sampling latch module 1221 can output the first sub-pixel data R[2] in the first pixel data RGB[2] to the driving signal generating circuit 123 through the sub-channel D7 in the third fourth data transmission channel and the sub-channel D10 in the fourth fourth data transmission channel. The first sub-pixel data G[2] in the first pixel data RGB[2] is output to the driving signal generating circuit 123 through the sub-channel D8 in the third fourth data transmission channel and the sub-channel D11 in the fourth fourth data transmission channel. The first sub-pixel data B[2] in the first pixel data RGB[2] is output to the driving signal generating circuit 123 through the sub-channel D9 in the third fourth data transmission channel and the sub-channel D12 in the fourth fourth data transmission channel, thereby achieving the purpose of outputting the two first pixel data RGB[2] to the driving signal generating circuit 123. At this time, the driving signal generating circuit 123 receives the two first pixel data RGB[2].

[0086] In one possible implementation, see Figure 8 , Fig.12 as well as Fig.13As shown, the latch circuit 122 includes: a sampling latch module 1221, a holding latch module 1222 and a channel selection module 1223. When the channel selection module 1223 is connected between the holding latch module 1222 and the driving signal generating circuit 123, the input end of the sampling latch module 1221 is connected to the shift register circuit 121, and is connected to the input end of the bus data generating circuit 11 through a plurality of first data transmission channels, and its output end is connected to the holding latch module 1222 through a plurality of second data transmission channels. The sampling latch module 1221 is used to receive each first pixel data in the second pixel data group corresponding to the enable signal through a plurality of first data transmission channels when receiving an enable signal, and output each first pixel data in the second pixel data group to the holding latch module 1222 through the corresponding second data transmission channel. Among them, the number of first data transmission channels is equal to the number of second data transmission channels and the number of first pixel data in each second pixel data group.

[0087] For example, taking the case where the resolution of the input image is 4*4, the resolution of the display panel is 8*4, and each second pixel data group includes two first pixel data, the sampling latch module 1221 is used to receive the first first pixel data (i.e., the first pixel data RGB[1]) in the second pixel data group A corresponding to the first enable signal NO[1] through the first data transmission channel LA1 when the first enable signal NO[1] in the enable signal A is received, and receive the second first pixel data (i.e., the first pixel data RGB[2]) in the second pixel data group A corresponding to the second enable signal NO[2] through the first data transmission channel LA2 when the second enable signal NO[2] in the enable signal A is received, and output the first pixel data RGB[1] in the second pixel data group A to the holding latch module 1222 through the second data transmission channel LB1, and output the first pixel data RGB[2] in the second pixel data group to the holding latch module 1222 through the second data transmission channel LB2.

[0088] Exemplarily, the output end of the holding latch module 1222 is connected to the input end of the channel selection module 1223 through multiple third data transmission channels. The holding latch module 1222 is used to receive and store each first pixel data in the second pixel data group, determine the third data transmission channel corresponding to each first pixel data according to the second data transmission channel corresponding to each first pixel data in the second pixel data group, and output each first pixel data of the second pixel data group to the channel selection module through the corresponding third data transmission channel. Among them, the multiple third data transmission channels correspond to the multiple second data transmission channels one by one.

[0089] Exemplarily, the holding latch module 1222 stores the first pixel data RGB[1] and the first pixel data RGB[2] when receiving the first pixel data RGB[1] and the first pixel data RGB[2] in the second pixel data group A. Since the first pixel data RGB[1] is input to the holding latch module 1222 through the second data transmission channel LB1, and the first pixel data RGB[2] is input to the holding latch module 1222 through the second data transmission channel LB2, the holding latch module 1222 outputs the first pixel data RGB[1] to the channel selection module 1223 through the third data transmission channel LC1, and outputs the first pixel data RGB[2] to the channel selection module 1223 through the third data transmission channel LC2.

[0090] Exemplarily, the output end of the channel selection module 1223 is connected to the input end of the driving signal generating circuit 123 through a plurality of fourth data transmission channels. The channel selection module 1223 is used to receive each first pixel data in the second pixel data group, and according to the correspondence between the first pixel data and the pixel unit, output each first pixel data in the second pixel data group to the driving signal generating circuit 123 through the corresponding at least two fourth data transmission channels. The number of the fourth data transmission channels is equal to the number of pixel units corresponding to the at least two first pixel data in each second pixel data group.

[0091] Exemplarily, when receiving each first pixel data in the second pixel data group A, the channel selection module 1223 inputs the first pixel data RGB[1] in the second pixel data group to the fourth data transmission channel LD1 and the fourth data transmission channel LD2, respectively, according to the correspondence between the first pixel data and the pixel unit, and outputs the two first pixel data RGB[1] to the drive signal generating circuit 123, and inputs the first pixel data RGB[2] in the second pixel data group to the fourth data transmission channel LD3 and the fourth data transmission channel LD4, respectively, and outputs the two first pixel data RGB[2] to the drive signal generating circuit 123.

[0092] For example, see Fig.13As shown, each first pixel data includes three sub-pixel data, that is, the first pixel data RGB[1] includes sub-pixel data R[1], sub-pixel data G[1] and sub-pixel data B[1]. When each second data transmission channel, the third data transmission channel and the fourth data transmission channel can include three data transmission sub-channels, and each data transmission sub-channel is used to transmit one sub-pixel data of the corresponding first pixel data, the sampling latch module 1221 outputs the first sub-pixel data R[1] in the first pixel data RGB[1] to the holding latch module 1222 through the sub-channel B1 in the first second data transmission channel. The first sub-pixel data G[1] in the first pixel data RGB[1] is output to the holding latch module 1222 through the sub-channel B2 in the first second data transmission channel. The first sub-pixel data B[1] in the first pixel data RGB[1] is output to the holding latch module 1222 through the sub-channel B3 in the first second data transmission channel. At this time, the holding latch module 1222 receives one first pixel data RGB[1]. At the same time, the sampling latch module 1221 outputs the first sub-pixel data R[2] in the first pixel data RGB[2] to the holding latch module 1222 through the sub-channel B4 in the second second data transmission channel. The first sub-pixel data G[2] in the first pixel data RGB[2] is output to the holding latch module 1222 through the sub-channel B5 in the second second data transmission channel. The first sub-pixel data B[2] in the first pixel data RGB[2] is output to the holding latch module 1222 through the sub-channel B6 in the second second data transmission channel. At this time, the holding latch module 1222 receives the first pixel data RGB[2].

[0093] Exemplarily, when the holding latch module 1222 receives the first pixel data RGB[1] and the first pixel data RGB[2] (i.e., the first pixel data in the second pixel data group A), the holding latch module 1222 may output the first sub-pixel data R[1] in the first pixel data RGB[1] to the channel selection module 1223 through the sub-channel C1 in the first third data transmission channel. The first sub-pixel data G[1] in the first pixel data RGB[1] is output to the channel selection module 1223 through the sub-channel C2 in the first third data transmission channel. The first sub-pixel data B[1] in the first pixel data RGB[1] is output to the channel selection module 1223 through the sub-channel C3 in the first third data transmission channel. At this time, the channel selection module 1223 receives the first pixel data RGB[1]. At the same time, the holding latch module 1222 may output the first sub-pixel data R[2] in the first pixel data RGB[2] to the channel selection module 1223 through the sub-channel C4 in the second third data transmission channel. The first sub-pixel data G[2] in the first pixel data RGB[2] is output to the channel selection module 1223 via the sub-channel C5 in the second third data transmission channel. The first sub-pixel data B[2] in the first pixel data RGB[2] is output to the channel selection module 1223 via the sub-channel C6 in the second third data transmission channel. At this time, the channel selection module 1223 receives the first pixel data RGB[2].

[0094] Exemplarily, when the channel selection module 1223 receives the first pixel data RGB[1] and the second pixel data RGB[2], the channel selection module 1223 outputs the first sub-pixel data R[1] in the first pixel data RGB[1] to the drive signal generating circuit 123 through the sub-channel D1 in the first fourth data transmission channel and the sub-channel D4 in the second fourth data transmission channel. The first sub-pixel data G[1] in the first pixel data RGB[1] can be output to the drive signal generating circuit 123 through the sub-channel D2 in the first fourth data transmission channel and the sub-channel D5 in the second fourth data transmission channel. The first sub-pixel data B[1] in the first pixel data RGB[1] can be output to the drive signal generating circuit 123 through the sub-channel D3 in the first fourth data transmission channel and the sub-channel D6 in the second fourth data transmission channel. Thus, the purpose of outputting the first pixel data RGB[1] in the second pixel data A to the holding latch module 1222 is achieved. At this time, the sampling latch module 1221 receives two first pixel data RGB[1]. At the same time, the channel selection module 1223 can output the first sub-pixel data R[2] in the first pixel data RGB[2] to the driving signal generating circuit 123 through the sub-channel D7 in the third fourth data transmission channel and the sub-channel D10 in the fourth third data transmission channel. The first sub-pixel data G[2] in the first pixel data RGB[2] can be output to the driving signal generating circuit 123 through the sub-channel D8 in the third fourth data transmission channel and the sub-channel D11 in the fourth fourth data transmission channel. The first sub-pixel data B[2] in the first pixel data RGB[2] can be output to the driving signal generating circuit 123 through the sub-channel D9 in the third third data transmission channel and the sub-channel D12 in the fourth fourth data transmission channel. Thus, the purpose of outputting the first pixel data RGB[2] in the second pixel data A to the driving signal generating circuit 123 is achieved. At this time, the driving signal generating circuit 123 receives two first pixel data RGB[2].

[0095] In one possible implementation, see Figure 8 As shown, when the enable signal includes the first enable signal and the second enable signal, the shift register circuit 121 includes a first output terminal and a second output terminal. The sampling latch module 1221 includes a first sampling latch unit and a second sampling latch unit. The first output terminal of the shift register circuit 121 is connected to the input terminal of the first sampling latch unit, and the second output terminal of the shift register circuit 121 is connected to the input terminal of the second sampling latch unit.

[0096] Exemplarily, the shift register circuit 121 is used to output a first enable signal to the first sampling latch unit through a first output terminal, and output a second enable signal to the second sampling latch unit through a second output terminal. The first sampling latch unit is used to receive the first pixel data corresponding to the odd-numbered first pixel data among the multiple first pixel data of the input image in the input first pixel data when the first enable signal is received. The second sampling latch unit is used to receive the first pixel data corresponding to the even-numbered first pixel data among the multiple first pixel data of the input image in the input first pixel data when the second enable signal is received.

[0097] Exemplarily, the shift register circuit outputs a first first enable signal to the first sampling latch unit, and the first sampling latch unit receives the first pixel data RGB[1] when receiving the first first enable signal. At the same time, the shift register circuit outputs a first second enable signal to the second sampling latch unit, and the second sampling latch unit receives the first pixel data RGB[2] when receiving the first second enable signal. The shift register circuit outputs a second first enable signal to the first sampling latch unit, and the first sampling latch unit receives the first pixel data RGB[3] when receiving the second first enable signal. At the same time, the shift register circuit outputs a second second enable signal to the second sampling latch unit, and the second sampling latch unit receives the first pixel data RGB[4] when receiving the second second enable signal, and so on, until all the first pixel data of the input image are input to the sampling latch module.

[0098] According to another aspect of the present disclosure, a display device is further provided, comprising a plurality of display units and at least one source driving circuit as described above.

[0099] Exemplarily, the display unit includes a display panel, and the display panel includes at least one of a liquid crystal display panel, a micro light emitting diode display panel, a light emitting diode display panel, a mini light emitting diode display panel, a quantum dot light emitting diode display panel, an organic light emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel and a small pitch display panel.

[0100] According to another aspect of the present disclosure, an electronic device is further provided, comprising the display device described above.

[0101] According to another aspect of the present disclosure, a driver chip is further provided, characterized in that the driver chip comprises the source driver circuit described above.

[0102] Exemplarily, the electronic devices in this embodiment include but are not limited to desktop computers, televisions, mobile devices with large screens such as mobile phones, tablet computers, and other common electronic devices that require multiple chips to be cascaded to achieve driving.

[0103] Exemplarily, the electronic device may also be a user equipment (UE), a mobile device, a user terminal, a terminal, a handheld device, a computing device or a vehicle-mounted device, etc. Exemplarily, some examples of terminals are: a display, a smart phone or a portable device, a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile Internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control (Industrial Control), a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid (Smart Grid), a wireless terminal in transportation safety (Transportation Safety), a wireless terminal in smart city (Smart City), a wireless terminal in smart home (Smart Home), a wireless terminal in Internet of Vehicles, etc. For example, the server may be a local server or a cloud server.

[0104] Fig.14 1 is a block diagram of an electronic device 1900 according to an embodiment of the present disclosure. For example, the electronic device 1900 may be provided as a server or a terminal device. Fig.14 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0105] The electronic device 1900 may also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output (I / O) interface 1958. The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™ or the like.

[0106] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0107] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the protection scope of the present invention. The protection scope of the present invention is determined by the appended claims.

[0108] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0109] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0110] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0111] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A source driving circuit for driving a pixel unit array circuit of a display panel, characterized in that: The source driving circuit includes: a bus data generating circuit and a pixel driving circuit; The bus data generation circuit is connected to the pixel unit array circuit through the pixel driving circuit; When the working mode of the bus data generating circuit is the pixel copy mode, the bus data generating circuit is used to sequentially obtain a plurality of first pixel data of the input image input in series, and when the first pixel data is obtained, generate a first pixel data group including at least two identical first pixel data by copying the first pixel data, and output the first pixel data in the first pixel data group to the pixel driving circuit in parallel; wherein different first pixel data correspond to different pixel points in the input image; When the working mode of the bus data generating circuit is the pixel copy mode, the pixel driving circuit is used to receive each first pixel data in the first pixel data group output by the bus data generating circuit; generate and output a driving signal corresponding to each first pixel data in each first pixel data group to the pixel unit array circuit; wherein the driving signal corresponding to the first pixel data in the same first pixel data group is used to drive the pixel units with consecutive distribution positions in the pixel unit array circuit; Wherein, the bus data generation circuit includes: a data cache module and a parallel data generation module; The output end of the data cache module is connected to the input end of the parallel data generation module, and the output end of the parallel data generation module is connected to the input end of the pixel driving circuit; The data cache module is used to sequentially acquire and store each first pixel data of a plurality of first pixel data of an input image according to a first preset frequency; sequentially output the plurality of first pixel data of the input image to the parallel data generation module according to a second preset frequency; the parallel data generation module is used to, upon receiving the first pixel data output by the data cache module, copy the first pixel data to generate a first pixel data group including at least two identical first pixel data, and output the first pixel data in the first pixel data group to the pixel driving circuit in parallel according to the second preset frequency; The first preset frequency is a multiple of the second preset frequency.

2. The source driving circuit according to claim 1, characterized in that: The pixel driving circuit comprises: A shift register circuit, used for generating and sequentially outputting at least one enable signal according to a first clock signal; a latch circuit, whose input end is connected to the output end of the shift register circuit and the output end of the bus data generating circuit, and is used for storing at least two first pixel data in the first pixel data group corresponding to the enable signal when receiving the enable signal; and outputting at least two first pixel data in at least one of the stored first pixel data groups to the drive signal generating circuit; A driving signal generating circuit, whose input end is connected to the output end of the latch circuit, is used to generate and output a driving signal corresponding to each first pixel data in the first pixel data group to a pixel unit corresponding to each first pixel data in the first pixel data group based on at least two first pixel data received in the first pixel data group and the correspondence between the first pixel data and the pixel unit.

3. The source driving circuit according to claim 2, characterized in that: The shift register circuit is further used for multiplying the frequency of the first clock signal to generate a second clock signal; according to each second timing pulse in the second clock signal, generating and outputting an enable signal corresponding to each second timing pulse to the latch circuit, driving the latch circuit to receive at least two first pixel data in the first pixel data group corresponding to the enable signal, until the latch circuit receives all the first pixel data of the input image; The frequency of the second timing pulse is equal to the frequency of inputting the plurality of pixel data of the input image into the bus data generating circuit.

4. The source driving circuit according to claim 1, characterized in that: When the working mode of the bus data generating circuit is not the pixel copy mode, the bus data generating circuit is used to sequentially acquire a plurality of first pixel data of the input image; and divide a preset number of first pixel data with continuous input timing into a second pixel data group; For each second pixel data group, outputting in parallel at least two first pixel data in each second pixel data group to the pixel driving circuit; When the working mode of the bus data generating circuit is not the pixel copy mode, the pixel driving circuit is used to copy each first pixel data in each second pixel data group to obtain at least two third pixel data groups corresponding to each second pixel data group; Generate and output a driving signal corresponding to each first pixel data in each third pixel data group to the pixel unit array circuit; wherein the first pixel data in the same third pixel data group corresponds to the first pixel data of the same pixel point of the input image, and the pixel units corresponding to the first pixel data of the input image are distributed in continuous positions.

5. The source driving circuit according to claim 4, characterized in that: The pixel driving circuit comprises: A shift register circuit, configured to generate and output an enable signal corresponding to each first timing pulse in the first clock signal according to each first timing pulse; a latch circuit, whose input end is connected to the output end of the shift register circuit, and whose output end is connected to the drive signal generating circuit, for storing at least two first pixel data in the second pixel data group corresponding to the enable signal when receiving the enable signal; copying each first pixel data in each second pixel data group to obtain at least two third pixel data groups corresponding to each second pixel data group; and outputting at least two first pixel data in at least one of the stored third pixel data groups to the drive signal generating circuit; A driving signal generating circuit is used to receive at least two first pixel data in the third pixel data group; based on the received at least two first pixel data in the third pixel data group and the correspondence between the first pixel data and the pixel unit, generate and output a driving signal corresponding to each first pixel data in the third pixel data group to a pixel unit corresponding to each first pixel data in the first pixel data group.

6. The source driving circuit according to claim 5, characterized in that: The latch circuit comprises: a sampling latch module, a holding latch module and a channel selection module; when the channel selection module is connected between the bus data generation circuit and the sampling latch module, The input end of the channel selection module is connected to the output end of the bus data generation circuit through a plurality of first data transmission channels, and the output end thereof is connected to the input end of the sampling latch module through a plurality of second data transmission channels, and is used for receiving each first pixel data in the second pixel data group through the plurality of first data transmission channels; and outputting each first pixel data in the second pixel data group to the sampling latch module through the corresponding at least two second data transmission channels according to the corresponding relationship between the first pixel data and the pixel unit; wherein the number of the first data transmission channels is equal to the number of the at least two first pixel data in each of the second pixel data groups, and the number of the second data transmission channels is equal to the number of the pixel units corresponding to the at least two first pixel data in each of the second pixel data groups; The output end of the sampling latch module is connected to the input end of the holding latch module through a plurality of third data transmission channels, and the input end thereof is connected to the shift register circuit, and is used for receiving the first pixel data corresponding to the enable signal output by the channel selection module through the plurality of second data transmission channels, generating and storing each first pixel data in at least two third pixel data groups corresponding to the second pixel data group; determining the third data transmission channel corresponding to each first pixel data in the third pixel data group according to the second data transmission channel corresponding to each first pixel data in the third pixel data group; and outputting each first pixel data in the third pixel data group to the holding latch module through the corresponding third data transmission channel; wherein the plurality of third data transmission channels correspond one-to-one to the plurality of second data transmission channels; The output end of the holding latch module is connected to the input end of the driving signal generating circuit through multiple fourth data transmission channels, and is used to determine the fourth data transmission channel corresponding to each first pixel data in the third pixel data group according to the third data transmission channel corresponding to each first pixel data in the third pixel data group when receiving each first pixel data in the third pixel data group; and output each first pixel data in the third pixel data group to the driving signal generating circuit through the corresponding fourth data transmission channel; wherein the multiple fourth data transmission channels correspond one-to-one to the multiple third data transmission channels.

7. The source driving circuit according to claim 5, characterized in that: The latch circuit comprises: a sampling latch module, a holding latch module and a channel selection module; when the channel selection module is connected between the sampling latch module and the holding latch module, The input end of the sampling latch module is connected to the shift register circuit, and is connected to the output end of the bus data generating circuit through a plurality of first data transmission channels, and the output end thereof is connected to the channel selection module through a plurality of second data transmission channels, and is used for receiving the enable signal through the plurality of first data transmission channels, receiving each first pixel data in the second pixel data group corresponding to the enable signal, and outputting each first pixel data in the second pixel data group to the channel selection module through the corresponding second data transmission channel; wherein the number of the first data transmission channels is equal to the number of the second data transmission channels, and the number of the first pixel data in each of the second pixel data groups; The output end of the channel selection module is connected to the input end of the holding latch module through a plurality of third data transmission channels, so as to receive each first pixel data in the second pixel data group; according to the correspondence between the first pixel data and the pixel unit, each first pixel data in the second pixel data group is output to the holding latch module through the corresponding at least two third data transmission channels; wherein the number of the third data transmission channels is equal to the number of pixel units corresponding to at least two first pixel data in each second pixel data group; The output end of the holding latch module is connected to the input end of the driving signal generating circuit through a plurality of fourth data transmission channels, and is used for generating and storing each first pixel data in at least two third pixel data groups corresponding to the second pixel data group when receiving the first pixel data output by the channel selection module; determining the fourth data transmission channel corresponding to each first pixel data according to the third data transmission channel corresponding to each first pixel data of the third pixel data group; and outputting each first pixel data in the third pixel data group to the driving signal generating circuit through the corresponding fourth data transmission channel; wherein the plurality of fourth data transmission channels correspond one-to-one to the plurality of third data transmission channels.

8. The source driving circuit according to claim 5, characterized in that: The latch circuit includes: a sampling latch module, a holding latch module and a channel selection module; when the channel selection module is connected between the holding latch module and the drive signal generating circuit, The input end of the sampling latch module is connected to the shift register circuit, and is connected to the output end of the bus data generating circuit through a plurality of first data transmission channels, and the output end thereof is connected to the holding latch module through a plurality of second data transmission channels, and is used for receiving the enable signal through the plurality of first data transmission channels, receiving each first pixel data in the second pixel data corresponding to the enable signal, and outputting each first pixel data in the second pixel data group to the holding latch module through the corresponding second data transmission channel; wherein the number of the first data transmission channels is equal to the number of the second data transmission channels, and the number of the first pixel data in each of the second pixel data groups; The output end of the holding latch module is connected to the input end of the channel selection module through a plurality of third data transmission channels, and is used for receiving and storing each first pixel data in the second pixel data group; determining the third data transmission channel corresponding to each first pixel data according to the second data transmission channel corresponding to each first pixel data in the second pixel data group; and outputting each first pixel data of the second pixel data group to the channel selection module through the corresponding third data transmission channel; wherein the plurality of third data transmission channels correspond one-to-one to the plurality of second data transmission channels; The output end of the channel selection module is connected to the input end of the driving signal generating circuit through multiple fourth data transmission channels, so as to receive each first pixel data in the second pixel data group; according to the corresponding relationship between the first pixel data and the pixel unit, each first pixel data in the second pixel data group is output to the driving signal generating circuit through the corresponding at least two fourth data transmission channels; wherein the number of fourth data transmission channels is equal to the number of pixel units corresponding to the at least two first pixel data in each second pixel data group.

9. The source driving circuit according to any one of claims 6 to 8, characterized in that: In the case where the enable signal includes a first enable signal and a second enable signal, the shift register circuit includes a first output terminal and a second output terminal; the sampling latch module includes a first sampling latch unit and a second sampling latch unit; The first output end of the shift register circuit is connected to the input end of the first sampling latch unit, and the second output end of the shift register circuit is connected to the input end of the second sampling latch unit; the shift register circuit is used to output the first enable signal to the first sampling latch unit through the first output end, and output the second enable signal to the second sampling latch unit through the second output end; The first sampling latch unit is used for receiving, in the case of receiving the first enable signal, first pixel data corresponding to an odd-numbered first pixel data among the plurality of first pixel data of the input image among the input first pixel data; The second sampling latch unit is used to receive first pixel data corresponding to an even-numbered first pixel data among a plurality of first pixel data of the input image in the case of receiving the second enable signal.

10. A display device, characterized in that: The display device comprises a plurality of display units and at least one source driving circuit according to claims 1-9.

11. The display device according to claim 10, characterized in that The display unit includes a display panel, and the display panel includes at least one of a liquid crystal display panel, a micro light emitting diode display panel, a light emitting diode display panel, a mini light emitting diode display panel, a quantum dot light emitting diode display panel, an organic light emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel and a small pitch display panel.

12. An electronic device, characterized in that: The electronic device comprises the display device according to claim 10 or 11.

13. A driver chip, characterized in that: The driver chip comprises the source driver circuit according to any one of claims 1 to 9.

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