Active element substrate
By employing an alternating arrangement of multiple insulating layers in the display panel, the problem of moisture entering the display panel is solved, effectively blocking moisture and improving the reliability of the display.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- AU OPTRONICS CORP
- Filing Date
- 2023-02-02
- Publication Date
- 2026-06-23
AI Technical Summary
Liquids or moisture can easily enter the display panel through the gap between the display panel and the splicing components, causing damage.
The active element adopts a multi-layer insulation structure, including a substrate, an active element layer, a first organic insulation layer, a first inorganic insulation layer, and a second organic insulation layer. The alternating arrangement of the first and second trenches prevents water vapor from entering the active element substrate.
It effectively blocks moisture from entering the active component substrate, preventing damage to the display panel and improving the reliability and resistance to moisture corrosion of the display.
Smart Images

Figure CN115863365B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to an active element substrate. Background Technology
[0002] With the rapid development of display technology, the market demand for large format displays (LFDs) is increasing. Currently, splicing technology is one of the main methods to realize large-format displays. Splicing technology combines multiple smaller display panels to form a large-format display. Compared to large-format display panels, smaller display panels have advantages such as higher yield rates and lower production costs.
[0003] In existing panel modules, small display panels are mostly fixed to splicing components, which are then assembled together to form a large display. However, when liquid is spilled on the display panel (e.g., during cleaning), liquid or moisture can easily enter the display panel through the gaps between the panel and the splicing components, causing damage. Therefore, there is an urgent need for a method to solve the aforementioned problem. Summary of the Invention
[0004] This invention provides an active element substrate that can reduce the problem of moisture intrusion.
[0005] At least one embodiment of the present invention provides an active element substrate. The active element substrate includes a substrate, an active element layer, a first organic insulating layer, a first inorganic insulating layer, and a second organic insulating layer. The substrate has an active region and a peripheral region. The active element layer is located on the substrate. The first organic insulating layer is located on the active element layer and has a first trench. The first trench is laterally located between the edge of the substrate and the active region. The first inorganic insulating layer is located above the first organic insulating layer and partially fills the first trench. The first inorganic insulating layer covers the sidewalls of the first trench. The second organic insulating layer is located above the first inorganic insulating layer and partially fills the first trench.
[0006] Based on the above, by setting the first organic insulating layer, the first inorganic insulating layer and the second organic insulating layer, water vapor can be blocked outside the first ditch. Attached Figure Description
[0007] Figure 1A This is a top view of an active element substrate according to an embodiment of the present invention.
[0008] Figure 1B It is along Figure 1A A schematic diagram of the cross sections of line A-A' and line B-B'.
[0009] Figures 2A to 2J yes Figure 1BA cross-sectional schematic diagram of the manufacturing method of the active component substrate.
[0010] Figure 3 This is a cross-sectional schematic diagram of an active element substrate according to an embodiment of the present invention.
[0011] Figure 4 This is a cross-sectional schematic diagram of an active element substrate according to an embodiment of the present invention.
[0012] Figure 5 This is a cross-sectional schematic diagram of an active element substrate according to an embodiment of the present invention.
[0013] Figure 6 This is a cross-sectional schematic diagram of an active element substrate according to an embodiment of the present invention.
[0014] Figure 7 This is a top view of an active element substrate according to an embodiment of the present invention.
[0015] Explanation of reference numerals in the attached figures:
[0016] 10, 20, 30, 40, 50: Active component substrate
[0017] 100: Substrate
[0018] 110: Active Component Layer
[0019] 111: Light-shielding layer
[0020] 112: Buffer layer
[0021] 113: Semiconductor Pattern
[0022] 114: Gate insulating layer
[0023] 115: Gate
[0024] 116: First source / drain
[0025] 117: Second source / drain
[0026] 118: Interlayer dielectric layer
[0027] 122: First inorganic capping layer
[0028] 124: First organic insulating layer
[0029] 132: First Inorganic Insulating Layer
[0030] 134: Second inorganic capping layer
[0031] 136: Second organic insulating layer
[0032] 142: Second inorganic insulating layer
[0033] 144: Third inorganic insulating layer
[0034] 152: Fourth Inorganic Insulation Layer
[0035] A-A',B-B': line
[0036] AA: Active Zone
[0037] CH1: First contact hole
[0038] CH2: Second contact hole
[0039] DR: Joint structure
[0040] M0: First conductive layer
[0041] M1: Second conductive layer
[0042] M2: Third conductive layer
[0043] M3: Fourth conductive layer
[0044] M4: Fifth conductive layer
[0045] M5: Sixth conductive layer
[0046] ND: Normal direction
[0047] PA: Surrounding Area
[0048] PH: Spacing
[0049] SL: Signal line
[0050] T: Active component
[0051] TH1: First through hole
[0052] TH2: Second through hole
[0053] TH3: Third through hole
[0054] TR1: First Ditch
[0055] TR2: Second Ditch
[0056] TR3: Third Ditch
[0057] W: Width Detailed Implementation
[0058] Figure 1A This is a top view of an active element substrate 10 according to an embodiment of the present invention. Figure 1B It is along Figure 1A Please refer to the cross-sectional diagrams of lines A-A' and B-B'. Figure 1A and Figure 1B The active element substrate 10 includes a substrate 100, an active element layer 110, a first organic insulating layer 124, a first inorganic insulating layer 132, and a second organic insulating layer 136. In this embodiment, the active element substrate 10 further includes a first inorganic capping layer 122, a second inorganic capping layer 134, a second inorganic insulating layer 142, and a third inorganic insulating layer 144.
[0059] The substrate 100 has an active region AA and a peripheral region PA. In this embodiment, the peripheral region PA surrounds the active region AA. The substrate 100 may be made of glass, quartz, organic polymer, or opaque / reflective materials (e.g., conductive materials, metals, wafers, ceramics, or other suitable materials) or other suitable materials.
[0060] The active element layer 110 is located on the substrate 100. In some embodiments, the active element layer 110 includes a first conductive layer M0, a buffer layer 112, a semiconductor pattern 113, a gate insulating layer 114, a second conductive layer M1, an interlayer dielectric layer 118, and a third conductive layer M2.
[0061] The first conductive layer M0 includes a light-shielding layer 111. A buffer layer 112 is located on the first conductive layer M0 and covers the light-shielding layer 111. A semiconductor pattern 113 is located on the buffer layer 111.
[0062] A gate insulating layer 114 is located on a semiconductor pattern 113. A second conductive layer M1 is located on the gate insulating layer 114. The second conductive layer M1 includes a gate 115, wherein the gate 115 overlaps the semiconductor pattern 113 in the normal direction ND of the top surface of the substrate 100.
[0063] An interlayer dielectric layer 118 is located on the second conductive layer M1 and the gate insulating layer 114. A third conductive layer M2 is located on the interlayer dielectric layer 118. The third conductive layer M2 includes a first source / drain 116 and a second source / drain 117. The first source / drain 116 and the second source / drain 117 are electrically connected to the semiconductor pattern 113. In this embodiment, the active element T is located in the active region AA and includes a gate 115, the semiconductor pattern 113, the first source / drain 116, and the second source / drain 117. In some embodiments, a plurality of active elements T arranged in an array are disposed on the active region AA, and each active element T is electrically connected to a corresponding signal line (not shown). In some embodiments, when the active element substrate 10 is applied to a display panel, the active element T is configured, for example, to control pixels. In this embodiment, the active element T is a top-gate thin-film transistor, but the invention is not limited thereto. In other embodiments, the active element T is a bottom-gate thin-film transistor, a dual-gate thin-film transistor, or other types of thin-film transistors.
[0064] In some embodiments, the materials of the first conductive layer M0, the second conductive layer M1, and the third conductive layer M2 include metals, but the invention is not limited thereto. In other embodiments, the first conductive layer M0, the second conductive layer M1, and the third conductive layer M2 may also use other conductive materials. For example, nitrides of metallic materials, oxides of metallic materials, oxynitrides of metallic materials, or other suitable materials, or stacked layers of metallic materials and other conductive materials.
[0065] In some embodiments, the semiconductor pattern 113 is a single-layer or multi-layer structure, comprising amorphous silicon, polycrystalline silicon, microcrystalline silicon, monocrystalline silicon, organic semiconductor materials, oxide semiconductor materials (e.g., indium zinc oxide, indium gallium zinc oxide, or other suitable materials, or combinations thereof), or other suitable materials or combinations thereof.
[0066] In some embodiments, the materials of the buffer layer 112, the gate insulating layer 114, and the interlayer dielectric layer 118 include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, organic insulating materials, or other suitable materials or combinations thereof.
[0067] A first inorganic capping layer 122 and a first organic insulating layer 124 are located above the active element layer 110, wherein the first inorganic capping layer 122 is located between the first organic insulating layer 124 and the active element layer 110. The first organic insulating layer 122 has one or more first contact holes CH1 located above the active region AA and a first trench TR1 located above the peripheral region PA. The first trench TR1 is laterally located between the edge of the substrate 100 and the active region AA. The first contact holes CH1 overlap a portion of the third conductive layer M2 (e.g., the second source / drain 117).
[0068] The first inorganic insulating layer 132 is located above the first organic insulating layer 124. The first inorganic insulating layer 132 partially fills the first trench TR1 and covers the sidewalls and bottom surface of the first trench TR1. In addition, the first inorganic insulating layer 132 also partially fills the first contact hole CH1 and covers the sidewalls of the first contact hole CH1. However, on the bottom surface of the first contact hole CH1, the first inorganic insulating layer 132 and the first inorganic covering layer 122 have a first through hole TH1.
[0069] The fourth conductive layer M3 is located on the first inorganic insulating layer 132, and a portion of the fourth conductive layer M3 is electrically connected to a portion of the third conductive layer M2 through the first contact hole CH1 and the first through hole TH1.
[0070] The second inorganic capping layer 134 and the second organic insulating layer 136 are located above the first inorganic insulating layer 132, wherein the second inorganic capping layer 134 is located between the first inorganic insulating layer 132 and the second organic insulating layer 136. In some embodiments, the fourth conductive layer M3 is located between the two inorganic capping layers 134 and the first inorganic insulating layer 132. The second inorganic capping layer 134 partially fills the first trench TR1 and covers the first inorganic insulating layer 132 in the first trench TR1. The second organic insulating layer 136 also partially fills the first trench TR1 and covers the second inorganic capping layer 134 in the first trench TR1.
[0071] The second organic insulating layer 136 is located above one or more second contact holes CH2 on the active region AA and above the peripheral region PA on the second trench TR2. The second trench TR2 is laterally located between the edge of the substrate 100 and the active region AA. The second trench TR2 does not overlap with the first trench TR1 in the normal direction ND of the surface of the substrate 100. In this embodiment, the second trench TR2 is laterally located between the first trench TR1 and the active region AA. In other words, in the horizontal direction, the second trench TR2 is closer to the active region AA than the first trench TR1. In other embodiments, the first trench TR1 is laterally located between the second trench TR2 and the active region AA. In other words, in other embodiments, the first trench TR1 is closer to the active region AA than the second trench TR2. The second contact hole CH2 overlaps with a portion of the fourth conductive layer M3.
[0072] The second inorganic insulating layer 142 is located above the second organic insulating layer 136. The second inorganic insulating layer 142 partially fills the second trench TR2 and covers the sidewalls and bottom surface of the second trench TR2. Furthermore, the second inorganic insulating layer 142 also partially fills the second contact hole CH2 and covers the sidewalls of the second contact hole CH2. However, on the bottom surface of the second contact hole CH2, the second inorganic insulating layer 142 and the second inorganic covering layer 134 have a second through-hole TH2.
[0073] The fifth conductive layer M4 is located on the second inorganic insulating layer 142, and a portion of the fifth conductive layer M4 is electrically connected to a portion of the fourth conductive layer M3 through the second contact hole CH2 and the second through hole TH2.
[0074] The third inorganic insulating layer 144 is located above the fifth conductive layer M4 and the second inorganic insulating layer 142. In some embodiments, the fourth conductive layer M3 is located between the third inorganic insulating layer 144 and the second inorganic insulating layer 142. The third inorganic insulating layer 144 partially fills the second trench TR2 and covers the second inorganic insulating layer 142 in the second trench TR2. The third inorganic insulating layer 144 has a third through-hole TH3 that overlaps a portion of the fourth conductive layer M3.
[0075] The sixth conductive layer M5 is located on the third inorganic insulating layer 144 and is electrically connected to a portion of the fifth conductive layer M4 through the third via TH3. In some embodiments, the sixth conductive layer M5 comprises, for example, copper, tungsten, nickel, or an alloy of the aforementioned metals or a combination of the aforementioned materials. In some embodiments, the sixth conductive layer M5 is adapted to connect a light-emitting element (e.g., a light-emitting diode). For example, the light-emitting element is electrically connected to the sixth conductive layer M5 via conductive adhesive, solder balls, or other materials.
[0076] In some embodiments, the materials of the first organic insulating layer 124 and the second organic insulating layer 136 include polymethyl methacrylate, epoxy resin, or other suitable materials or combinations thereof, and the first organic insulating layer 124 and the second organic insulating layer 136 may be cured photoresist materials. In some embodiments, the thickness of each of the first organic insulating layer 124 and the second organic insulating layer 136 is 1 micrometer to 8 micrometers. In some embodiments, the materials of the first inorganic insulating layer 132, the first inorganic capping layer 122, the second inorganic capping layer 134, the second inorganic insulating layer 142, and the third inorganic insulating layer 144 include silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials or combinations thereof. In some embodiments, the thickness of each of the first inorganic insulating layer 132, the first inorganic capping layer 122, the second inorganic capping layer 134, the second inorganic insulating layer 142, and the third inorganic insulating layer 144 is 500 angstroms to 3000 angstroms.
[0077] In this embodiment, the first channel TR1 of the first organic insulating layer 124 and the first inorganic insulating layer 132 within the first channel TR1 can prevent moisture from entering the first organic insulating layer 124 above the active area AA, thereby preventing moisture damage to the first organic insulating layer 124 above the active area AA and the formation of black spots. Furthermore, the second channel TR2 of the second organic insulating layer 136 and the second inorganic insulating layer 142 within the second channel TR2 can prevent moisture from entering the second organic insulating layer 136 above the active area AA, thereby preventing moisture damage to the second organic insulating layer 136 above the active area AA and the formation of black spots. Additionally, the first covering layer 134 in the first channel TR1 and the third inorganic insulating layer 144 in the second channel TR2 can further prevent moisture from entering the first organic insulating layer 124 and the second organic insulating layer 136 above the active area AA. Moreover, the staggered arrangement of the first channel TR1 and the second channel TR2 achieves dual protection, further enhancing the protection against moisture. In some embodiments, the width W of the first trench TR1 and the second trench TR2 is 3.0 micrometers to 50 micrometers, and the horizontal distance PH between the first trench TR1 and the second trench TR2 is 3.0 micrometers to 50 micrometers.
[0078] In some embodiments, the bonding structure DR is located between the first trench TR1 and the edge of the substrate 100. The bonding structure DR is configured for bonding with external circuitry. For example, the bonding structure DR is bonded to a chip, thin-film flip-chip package, or other circuit board via conductive adhesive, solder balls, or other conductive bonding elements. In this embodiment, the bonding structure DR is disposed inside the first trench TR1 and the second trench TR2, thereby preventing external moisture from damaging the bonding structure DR.
[0079] Figures 2A to 2J yes Figure 1B A cross-sectional schematic diagram of the manufacturing method of the active element substrate 10.
[0080] Please refer to Figure 2A An active element layer 110 is formed on the substrate 10. In some embodiments, the active element layer 110 extends from the active region AA into the peripheral region PA (see reference). Figure 1A ).
[0081] Please refer to Figure 2B A first inorganic capping layer 122 and a first organic insulating layer 124 are formed on the active element layer 110 by blanket deposition. In some embodiments, the method of forming the first inorganic capping layer 122 includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other suitable methods. In some embodiments, the method of forming the first organic insulating layer 124 includes spin coating, printing, spraying, or other suitable methods. In some embodiments, the first organic insulating layer 124 is a single-layer or multi-layer structure.
[0082] Please refer to Figure 2C A patterning process is performed on the first organic insulating layer 124 to form the first trench TR1 and the first contact hole CH1. For example, when the first organic insulating layer 124 is a photoresist material, a photolithography process is performed on the first organic insulating layer 124.
[0083] Please refer to Figure 2D A first inorganic insulating layer 132 is formed on the first organic insulating layer 124, and a patterning process is performed on the first inorganic insulating layer 132 and the first inorganic capping layer 122 to form a first through hole TH1 that exposes part of the third conductive layer M2 in the first inorganic insulating layer 132 and the first inorganic capping layer 122 on the bottom surface of the first contact hole CH1.
[0084] Please refer to Figure 2E A fourth conductive layer M3 is formed on the first inorganic insulating layer 132, and a portion of the fourth conductive layer M3 is filled into the first contact hole CH1 and the first through hole TH1 and electrically connected to a portion of the third conductive layer M2.
[0085] Please refer to Figure 2FA second inorganic capping layer 124 and a second organic insulating layer 136 are formed on the fourth conductive layer M3 and the first inorganic insulating layer 132 by blanket deposition. In some embodiments, the method for forming the second inorganic capping layer 124 includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other suitable methods. In some embodiments, the method for forming the second organic insulating layer 136 includes spin coating, printing, spraying, or other suitable methods. In some embodiments, the second organic insulating layer 136 is a single-layer or multi-layer structure.
[0086] Please refer to Figure 2G A patterning process is performed on the second organic insulating layer 136 to form the second trench TR2 and the second contact hole CH2. For example, when the second organic insulating layer 136 is a photoresist material, a photolithography process is performed on the second organic insulating layer 136.
[0087] Please refer to Figure 2H A second inorganic insulating layer 142 is formed on the second organic insulating layer 136, and a patterning process is performed on the second inorganic insulating layer 142 and the second inorganic capping layer 134 to form a second through hole TH2 that exposes part of the fourth conductive layer M3 in the second inorganic insulating layer 142 and the second inorganic capping layer 134 on the bottom surface of the second contact hole CH2.
[0088] Please refer to Figure 2I A fifth conductive layer M4 is formed on the second inorganic insulating layer 142, and a portion of the fifth conductive layer M4 is filled into the second contact hole CH2 and the second through hole TH2 and electrically connected to a portion of the fourth conductive layer M3.
[0089] Please refer to Figure 2J A third inorganic insulating layer 144 is formed on the fifth conductive layer M4, and a patterning process is performed on the third inorganic insulating layer 144 to form a third through hole TH3 that exposes part of the fifth conductive layer M4 in the third inorganic insulating layer 144.
[0090] Finally, please return to Figure 1B A sixth conductive layer M5 is formed on the third inorganic insulating layer 144. The sixth conductive layer M5 is partially filled into the third through-hole TH3 to be electrically connected to a portion of the fifth conductive layer M4.
[0091] Figure 3 This is a schematic cross-sectional view of an active element substrate 20 according to an embodiment of the present invention. It should be noted that... Figure 3 The embodiments follow Figure 1A and Figure 1B The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and they will not be repeated here.
[0092] Figure 3 Active component substrate 20 and Figure 1B The main difference between the active element substrate 10 and the active element substrate 20 is that the active element layer 110 of the active element substrate 20 also includes signal lines SL.
[0093] Please refer to Figure 3 In this embodiment, the third conductive layer M2 includes a signal line SL, a first source / drain 116, and a second source / drain 117. The signal line SL spans the bottom of the first trench TR1 and the bottom of the second trench TR2. In this embodiment, the first inorganic capping layer 122 directly covers the signal line SL so that the signal line SL is not exposed by the first trench TR1 during the process of forming the first trench TR1. In some embodiments, the bonding structure of the active element substrate 20 for bonding with external circuitry is disposed outside the first trench TR1 and the second trench TR2, and the signal line SL can electrically connect the bonding structure to the active element T on the active region AA.
[0094] Figure 4 This is a schematic cross-sectional view of an active element substrate 30 according to an embodiment of the present invention. It should be noted that... Figure 4 The embodiments follow Figure 1A and Figure 1B The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and they will not be repeated here.
[0095] Figure 4 Active component substrate 30 and Figure 1B The main difference between the active element substrate 10 and the active element substrate 30 is that the active element layer 110 of the active element substrate 30 also includes signal lines SL.
[0096] Please refer to Figure 4 In this embodiment, the second conductive layer M1 includes a signal line SL and a gate 115. The signal line SL spans the bottom of the first trench TR1 and the bottom of the second trench TR2. In this embodiment, the first inorganic capping layer 122 directly covers the signal line SL so that the signal line SL is not exposed by the first trench TR1 during the process of forming the first trench TR1. In some embodiments, the bonding structure of the active element substrate 20 for bonding with external circuitry is disposed outside the first trench TR1 and the second trench TR2, and the signal line SL can electrically connect the bonding structure to the active element T on the active region AA.
[0097] Figure 5 This is a schematic cross-sectional view of an active element substrate 40 according to an embodiment of the present invention. It should be noted that... Figure 5 The embodiments follow Figure 1A and Figure 1B The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and they will not be repeated here.
[0098] Figure 5 Active component substrate 40 and Figure 1B The main difference of the active element substrate 10 is that the active element layer 110 of the active element substrate 40 also includes a third organic insulating layer 146.
[0099] Please refer to Figure 5 A third organic insulating layer 146 is located above the third inorganic insulating layer 144 and partially fills the second trench TR2. The third organic insulating layer 146 has a third trench TR3. The third trench TR3 does not overlap with the second trench TR2 in the normal direction ND of the surface of the substrate 100. In some embodiments, the third trench TR3 overlaps with the first trench TR1 in the normal direction ND of the surface of the substrate 100, thereby saving trench layout space, but the invention is not limited thereto. In other embodiments, the third trench TR3 does not overlap with the first trench TR1 and the second trench TR2 in the normal direction ND.
[0100] The fourth inorganic insulating layer 152 is located above the third organic insulating layer 146. The fourth inorganic insulating layer 152 partially fills the second trench TR2 and covers the sidewalls and bottom surface of the second trench TR2.
[0101] Based on the above, the staggered arrangement of the first ditch TR1, the second ditch TR2, and the third ditch TR3 can achieve multiple layers of protection, further enhancing the protection against water vapor. In some embodiments, the width W of each of the first ditch TR1, the second ditch TR2, and the third ditch TR3 is 3.0 micrometers to 50 micrometers, and the horizontal distance PH between adjacent pairs of the first ditch TR1, the second ditch TR2, and the third ditch TR3 is 3.0 micrometers to 50 micrometers. In some embodiments, in the horizontal direction, the second ditch TR2 is closer to the active zone than the first ditch TR1 and the third ditch TR3, but this invention is not limited thereto. In other embodiments, in the horizontal direction, the first ditch TR1 and the third ditch TR3 are closer to the active zone than the second ditch TR2, but this invention is not limited thereto.
[0102] Figure 6 This is a schematic cross-sectional view of an active element substrate 40 according to an embodiment of the present invention. It should be noted that... Figure 6 The embodiments follow Figure 5The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and they will not be repeated here.
[0103] Figure 6 Active component substrate 50 and Figure 5 The main difference of the active element substrate 40 is that, in the active element substrate 50, the third trench TR3 is closer to the active region in the horizontal direction than the second trench TR2, and the second trench TR2 is closer to the active region than the first trench TR1.
[0104] Figure 7 This is a top view of an active element substrate 50 according to an embodiment of the present invention. It should be noted here that... Figure 7 The embodiments follow Figure 1A and Figure 1B The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and they will not be repeated here.
[0105] Figure 7 Active component substrate 60 and Figure 1A The main difference of the active element substrate 10 is that, in the active element substrate 60, a portion of the bonding structure DR disconnects the first trench TR1 from the second trench TR2.
[0106] Please refer to Figure 7 The connecting structure DR located on the upper side disconnects the first ditch TR1 from the second ditch TR2. In other words, part of the connecting structure DR is located on the extension path of the first ditch TR1 and the second ditch TR2.
Claims
1. An active element substrate, comprising: A substrate having an active region and a peripheral region surrounding the active region; An active component layer is located on the substrate; A first inorganic capping layer is located above the active element layer; A first organic insulating layer is located above the active element layer and the first inorganic cover layer, and has a first trench that is laterally located between the edge of the substrate and the active region. A first inorganic insulating layer is located above the first organic insulating layer, and partially fills the first trench, covers the sidewall of the first trench, and contacts the first inorganic covering layer; A second inorganic covering layer is located above the first inorganic insulating layer, wherein the second inorganic covering layer is partially filled into the first trench and covers the sidewalls and bottom of the first trench; A second organic insulating layer is located above the first inorganic insulating layer and partially fills the first trench, covering the sidewalls and bottom of the first trench. The second organic insulating layer has a second trench located above the first trench. The second trench does not overlap the first trench in a normal direction on the surface of the substrate. The second trench is laterally located between the first trench and the active region. The width W of the first trench and the second trench is 3.0 micrometers to 50 micrometers, and the horizontal spacing PH between the first trench and the second trench is 3.0 micrometers to 50 micrometers. The thickness of the first organic insulating layer and the second organic insulating layer is 1 micrometer to 8 micrometers. A second inorganic insulating layer is located above the second organic insulating layer and partially fills the second trench. The second inorganic insulating layer covers the sidewall of the second trench and contacts the second inorganic covering layer. A third inorganic insulating layer is located above the second inorganic insulating layer and partially fills the second trench, covering the sidewalls and bottom of the second trench. The thickness of the first inorganic insulating layer, the first inorganic covering layer, the second inorganic covering layer, the second inorganic insulating layer and the third inorganic insulating layer is 500 angstroms to 3000 angstroms. A third organic insulating layer is located above the third inorganic insulating layer and partially fills the second trench, covering the sidewalls and bottom of the second trench. The third organic insulating layer has a third trench located above the first trench and the second trench, and the third trench does not overlap with the second trench in the normal direction of the surface of the substrate. as well as A fourth inorganic insulating layer is located above the third organic insulating layer and partially fills the third trench. The fourth inorganic insulating layer covers the sidewall of the third trench and contacts the third inorganic insulating layer.
2. The active element substrate of claim 1, wherein the third trench overlaps the first trench in a normal direction on the surface of the substrate.
3. The active element substrate as claimed in claim 1, wherein the active element layer includes a signal line, and the signal line crosses the bottom of the first trench and the bottom of the second trench, and the first inorganic capping layer directly covers and contacts the signal line.
4. The active element substrate as described in claim 1, further comprising: A bonding structure is located between the first trench and the edge of the substrate.
5. The active element substrate as described in claim 1, further comprising: An upper connecting structure, wherein the upper connecting structure disconnects the first ditch from the second ditch and is disposed on the extension path of the first ditch and the second ditch; A lower side joining structure is provided on the inner side of the first ditch and the second ditch.