A graphics processing method and system for tile-based rendering mode

Abstract

The application discloses a kind of block rendering mode graphics processing method and system.The graphics processing system includes geometry processing system and fragment processing system;Geometry processing system is used to carry out geometry processing to primitive, and visible primitive is blocked to the multiple tiles M of screen visual space;Fragment processing system is used to render the multiple tiles M, and generate the rendering image of multiple tiles M;Fragment processing system includes post-processing module, and post-processing module is used to start the pixel filtering processing of the pixel in the first pixel set Pin0 of target tile M0 in the first time after the rendering image of target tile M0 is generated, before the rendering image of multiple tiles M is all generated.This application can effectively improve the processing efficiency of overall image pixel filtering, and will not produce additional pixel shading workload.

Description

Technical Field

[0001] This invention belongs to the field of image processing technology, and more specifically, relates to a block rendering mode graphics processing method and system. Background Technology

[0002] Computer graphics processing systems are used to process graphics data (including graph data and vertex data) for various computer graphics applications (such as computer games) and output rendered images produced through the rendering pipeline.

[0003] In graphics applications, 3D models are constructed by partitioning objects in a scene using primitives (including but not limited to triangles, lines, and points). These primitives are defined by vertices for their positions in 3D space, as well as lighting effects and shading properties. The geometric data of the primitives and vertices in the 3D model is sent to the computer graphics processing system (CGPU) as input data to the geometry processing stage during rendering. The CGPU performs geometric processing on the input primitives, including converting them to screen space and removing primitives that are not visible in screen space. After geometry processing, the primitive and vertex geometric data is sent to the fragment processing pipeline for rendering in the CGPU. As a result of the rendering process, the CGPU generates an output image of the 3D model, which is then displayed on a display unit (e.g., a display screen).

[0004] Existing computer graphics processing systems include tile-based rendering modes. In tile-based rendering, the screen is divided into multiple rectangular tiles. Primitives are geometrically processed and then classified into different tiles on the screen. Fragment processing is then performed separately within each tile to generate the rendered image. Because the rendered image in a tile-based computer graphics processing system is generated independently within each tile, and the filtering of pixels at the boundaries of each tile involves pixels in adjacent tiles, pixel filtering for each tile cannot be completed during the tile processing process. Instead, it must wait until all tiles have been rendered before pixel filtering is performed on the tiles, resulting in low efficiency. Summary of the Invention

[0005] In view of the above-mentioned defects or improvement needs of the existing technology, the present invention provides a block rendering mode graphics processing method and system, which can effectively improve the processing efficiency of overall image pixel filtering, and does not generate additional pixel coloring workload.

[0006] To achieve the above objectives, according to one aspect of the present invention, a graphics processing system is provided, including a geometry processing system and a fragment processing system; the geometry processing system is used to perform geometric processing on primitives and then divide the visible primitives into multiple patches M in the screen visual space; the fragment processing system is used to render the multiple patches M to generate rendered images of the multiple patches M, each patch M having a first pixel set Pin, a second pixel set Pb, and a third pixel set Ptile; wherein Pin = Ptile - Pb, and the third pixel set Ptile contains all the pixels of patch M; the fragment processing system includes a post-processing module, which is used to start pixel filtering processing on the pixels in the first pixel set Pin0 of the target patch M0 at a first time after the rendered image of the target patch M0 in the multiple patches M is generated and before all the rendered images of the multiple patches M are generated.

[0007] In some implementations, the post-processing module is also used to start pixel filtering processing on the pixels in the second pixel set Pb0 of the target pixel M0 at a second time after all the rendered images of the multiple pixels M have been generated.

[0008] In some embodiments, the post-processing module is further configured to, at a third time after the rendering image of the target tile M0 in the plurality of tiles M is generated but before all the rendering images of the plurality of tiles M are generated, begin to check the rendering status of the plurality of adjacent tiles MX of the target tile M0. When all the pixel information used to perform pixel filtering processing on the pixels in the second pixel set Pb0 of the target tile M0 in the plurality of adjacent tiles MX is generated, pixel filtering processing is performed on the pixels in the second pixel set Pb0 of the target tile M0; or, when all the pixel information used to perform pixel filtering processing on the subset of pixels in the second pixel set Pb0 of the target tile M0 in the plurality of adjacent tiles MX is generated, pixel filtering processing is performed on the subset of pixels in the second pixel set Pb0 of the target tile M0.

[0009] In some implementations, the post-processing module is further configured to start pixel filtering processing on the remaining pixels in the second pixel set Pb0 of the target patch M0 at a second time after all the rendered images of the multiple patches M have been generated; the remaining pixels are the pixels in the second pixel set Pb0 of the target patch M0 that did not undergo pixel filtering processing before all the rendered images of the multiple patches M were generated.

[0010] In some implementations, the post-processing module is also used to set a boundary mask and determine, based on the boundary mask, whether the pixels or a subset of pixels in the second pixel set Pb0 have undergone pixel filtering processing before all the rendered images of the multiple tiles M are generated.

[0011] In some implementations, each boundary of the map patch M is moved inward by k pixels, and the pixels in the resulting first rectangular region constitute the first pixel set Pin; a (2k+1)×(2k+1) filter kernel is used to perform pixel filtering processing on the pixels in the first pixel set Pin0 of the target map patch M0.

[0012] In some implementations, each patch M further has a fourth pixel set Ps, which is composed of pixels in the first remaining region after removing the second rectangular region from the rectangular region of patch M. The second rectangular region is obtained by moving each boundary of patch M inward by 2k pixels. The fragment processing system is used to store the fourth pixel set Ps of each patch M separately. The post-processing module is also used to obtain pixel color information in the second remaining region from the fourth pixel set PsX of multiple adjacent patches MX of the target patch M0. The second remaining region is the region after removing the rectangular region of the target patch M0 from the third rectangular region. The third rectangular region is obtained by moving each boundary of the target patch M0 outward by k pixels. The post-processing module is also used to perform pixel filtering processing on the pixels in the second pixel set Pb0 of the target patch M0 using a (2k+1)×(2k+1) filtering kernel based on the pixel color information in the fourth pixel set Ps0 of the target patch M0 and the pixel color information in the second remaining region.

[0013] In some implementations, the fragment processing system is used to calculate the pixel color address required for pixel filtering processing of pixels in the second pixel set Pb0 using a (2k+1)×(2k+1) filtering kernel, based on the tile index of the target tile M0, the tile indices of multiple adjacent tiles MX, and the pixel offset within the target tile M0.

[0014] In some implementations, the fragment processing system is used to store the pixel information in the fourth pixel set Ps as a whole, in units of tiles; and in the storage space corresponding to each tile M, to store the pixel information in the fourth pixel set Ps in the order of the top pixel, bottom pixel, left pixel and right pixel of the tile M.

[0015] In some implementations, the fragment processing system is used to store the pixel information of the first group of pixels at the top of the patch M in the fourth pixel set Ps column by column, the pixel information of the second group of pixels at the bottom of the patch M in the fourth pixel set Ps column by column, the pixel information of the third group of pixels on the left side of the patch M in the fourth pixel set Ps row by row, and the pixel information of the fourth group of pixels on the right side of the patch M in the fourth pixel set Ps row by row.

[0016] In some implementations, for a (2k+1)×(2k+1) filter kernel, the pixel color address of the fourth group of pixels to the right of target patch M0 in the fourth pixel set Ps0 of target patch M0 is:

[0017] Addr(x,y)=TileM0×uPs0+2×uPhori0+uPvert0+y×2k+(x-Pr0+2k-1),

[0018] Where x and y represent the horizontal and vertical coordinates of the pixel in the pixel coordinate system, respectively; TileM0 represents the tile index of the target tile M0; uPs0 represents the number of pixels in the fourth pixel set Ps0; uPhori0 represents the number of top or bottom pixels of the target tile M0 in the fourth pixel set Ps0; uPvert0 represents the number of left or right pixels of the target tile M0 in the fourth pixel set Ps0; and Pr0 represents the pixel offset of the right boundary of the target tile M0.

[0019] In some implementations, for a (2k+1)×(2k+1) filter kernel, the pixel color address of the third group of pixels to the left of target patch M0 in the fourth pixel set Ps0 of target patch M0 is:

[0020] Addr(x,y)=TileM0×uPs0+2×uPhori0+y×2k+x.

[0021] In some implementations, for a (2k+1)×(2k+1) filter kernel, the pixel color address of the first group of pixels at the top of the target patch M0 in the fourth pixel set Ps0 of the target patch M0 is:

[0022] Addr(x,y)=TileM0×uPs0+2k×x+(Pd0-y),

[0023] Where Pd0 represents the pixel offset of the top boundary of the target tile M0.

[0024] In some implementations, for a (2k+1)×(2k+1) filter kernel, the pixel color address of the second group of pixels at the bottom of the target patch M0 in the fourth pixel set Ps0 of the target patch M0 is:

[0025] Addr(x,y)=TileM0×uPs0+uPhori0+2k×x+(2k-1-y).

[0026] According to another aspect of the present invention, a graphics processing method is provided, characterized in that it includes: performing geometric processing on primitives, dividing the visible primitives into multiple patches M in the screen visual space; rendering the multiple patches M to generate rendered images of the multiple patches M; each patch M has a first pixel set Pin, a second pixel set Pb, and a third pixel set Ptile; wherein Pin = Ptile - Pb, and the third pixel set Ptile contains all the pixels of patch M; and, at a first time after the rendered image of a target patch M0 in the multiple patches M is generated but before all the rendered images of the multiple patches M are generated, starting pixel filtering processing on the pixels in the first pixel set Pin0 of the target patch M0.

[0027] In some implementations, the method further includes: at a second time after all the rendered images of the multiple tiles M have been generated, starting pixel filtering processing on the pixels in the second pixel set Pb0 of the target tile M0.

[0028] In some embodiments, the method further includes: after the rendering image of the target block M0 in the plurality of blocks M is generated and before all the rendering images of the plurality of blocks M are generated, starting to check the rendering status of the plurality of adjacent blocks MX of the target block M0; and when all the pixel information used to perform pixel filtering processing on the pixels in the second pixel set Pb0 of the target block M0 in the plurality of adjacent blocks MX is generated, performing pixel filtering processing on the pixels in the second pixel set Pb0 of the target block M0.

[0029] In some embodiments, the method further includes: after the rendering image of the target block M0 in the plurality of blocks M is generated and before all the rendering images of the plurality of blocks M are generated, starting to check the rendering status of the plurality of adjacent blocks MX of the target block M0; and when all the pixel information used to perform pixel filtering processing on the subset of pixels in the second pixel set Pb0 of the target block M0 in the plurality of adjacent blocks MX is generated, performing pixel filtering processing on the subset of pixels in the second pixel set Pb0 of the target block M0.

[0030] In some embodiments, the method further includes: at a second time after all the rendered images of the plurality of tiles M have been generated, starting pixel filtering processing on the remaining pixels in the second pixel set Pb0 of the target tile M0; the remaining pixels are the pixels in the second pixel set Pb0 of the target tile M0 that did not undergo pixel filtering processing before all the rendered images of the plurality of tiles M were generated.

[0031] In some implementations, the method further includes: setting a boundary mask, and determining, based on the boundary mask, whether the pixels or a subset of pixels in the second pixel set Pb0 have undergone pixel filtering processing before all the rendered images of the multiple tiles M are generated.

[0032] In some implementations, each boundary of the map patch M is moved inward by k pixels, and the pixels in the resulting first rectangular region constitute the first pixel set Pin; a (2k+1)×(2k+1) filter kernel is used to perform pixel filtering processing on the pixels in the first pixel set Pin0 of the target map patch M0.

[0033] In some implementations, each patch M further has a fourth pixel set Ps, which is composed of pixels in the first remaining region after removing the second rectangular region from the rectangular region of patch M. The second rectangular region is obtained by moving each boundary of patch M inward by 2k pixels. The method further includes: storing the fourth pixel set Ps of each patch M separately; obtaining pixel color information in the second remaining region from the fourth pixel set PsX of multiple adjacent patches MX of the target patch M0, where the second remaining region is the region after removing the rectangular region of the target patch M0 from the third rectangular region. The third rectangular region is obtained by moving each boundary of the target patch M0 outward by k pixels; and performing pixel filtering processing on the pixels in the second pixel set Pb0 of the target patch M0 using a (2k+1)×(2k+1) filtering kernel based on the pixel color information in the fourth pixel set Ps0 of the target patch M0 and the pixel color information in the second remaining region.

[0034] In some implementations, the method further includes: calculating the pixel color address required for pixel filtering processing of pixels in the second pixel set Pb0 using a (2k+1)×(2k+1) filter kernel, based on the tile index of the target tile M0, the tile indexes of multiple adjacent tiles MX, and the pixel offset within the target tile M0.

[0035] In some implementations, storing the fourth pixel set Ps for each tile M separately includes: storing the pixel information in the fourth pixel set Ps as a whole, on a tile-by-tile basis; and storing the pixel information in the fourth pixel set Ps in the storage space corresponding to each tile M in the order of the top pixel, bottom pixel, left pixel, and right pixel of the tile M.

[0036] In some implementations, storing the fourth pixel set Ps for each patch M separately further includes: storing the pixel information of the first group of pixels at the top of patch M in the fourth pixel set Ps column by column; storing the pixel information of the second group of pixels at the bottom of patch M in the fourth pixel set Ps column by column; storing the pixel information of the third group of pixels on the left side of patch M in the fourth pixel set Ps row by row; and storing the pixel information of the fourth group of pixels on the right side of patch M in the fourth pixel set Ps row by row.

[0037] In some implementations, for a (2k+1)×(2k+1) filter kernel, the pixel color address of the fourth group of pixels to the right of target patch M0 in the fourth pixel set Ps0 of target patch M0 is:

[0038] Addr(x,y)=TileM0×uPs0+2×uPhori0+uPvert0+y×2k+(x-Pr0+2k-1)

[0039] Where x and y represent the horizontal and vertical coordinates of the pixel in the pixel coordinate system, respectively; TileM0 represents the tile index of the target tile M0; uPs0 represents the number of pixels in the fourth pixel set Ps0; uPhori0 represents the number of top or bottom pixels of the target tile M0 in the fourth pixel set Ps0; uPvert0 represents the number of left or right pixels of the target tile M0 in the fourth pixel set Ps0; and Pr0 represents the pixel offset of the right boundary of the target tile M0.

[0040] In some implementations, for a (2k+1)×(2k+1) filter kernel, the pixel color address of the third group of pixels to the left of target patch M0 in the fourth pixel set Ps0 of target patch M0 is:

[0041] Addr(x,y)=TileM0×uPs0+2×uPhori0+y×2k+x.

[0042] In some implementations, for a (2k+1)×(2k+1) filter kernel, the pixel color address of the first group of pixels at the top of the target patch M0 in the fourth pixel set Ps0 of the target patch M0 is:

[0043] Addr(x,y)=TileM0×uPs0+2k×x+(Pd0-y)

[0044] Where Pd0 represents the pixel offset of the top boundary of the target tile M0.

[0045] In some implementations, for a (2k+1)×(2k+1) filter kernel, the pixel color address of the second group of pixels at the bottom of the target patch M0 in the fourth pixel set Ps0 of the target patch M0 is:

[0046] Addr(x,y)=TileM0×uPs0+uPhori0+2k×x+(2k-1-y).

[0047] According to another aspect of the present invention, an electronic device is provided, including the above-described graphics processing system; or, the electronic device includes: a processor; a memory communicatively connected to the processor; the memory storing instructions executable by the processor, the instructions being executed by the processor to enable the processor to perform the above-described method.

[0048] According to another aspect of the present invention, a computer-readable storage medium is provided, which stores computer instructions that, when executed by a processor, implement the above-described method.

[0049] In summary, compared with the prior art, the above-described technical solution conceived by this invention has the following beneficial effects: Introducing the concepts of internal pixel set, boundary pixel set, and separately stored pixel set into tile processing, and processing the internal pixel set and boundary pixel set separately, on the one hand, the filtering processing of pixels in the internal pixel set of the tile is initiated immediately after the tile's rendered image is generated, without waiting for all tiles to complete rendering, effectively improving the overall image pixel filtering processing efficiency, and without generating additional pixel coloring workload; on the other hand, storing all pixels required for filtering the pixels in the boundary pixel set separately, forming a separately stored pixel set, helps to quickly obtain the pixel color information of the separately stored pixel set from the storage space, improving the efficiency of filtering the pixels in the boundary pixel set. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of pixel filtering using a 3×3 pixel filter kernel;

[0051] Figure 2 This is a schematic diagram of the structure of the block rendering mode graphics processing system according to an embodiment of the present invention;

[0052] Figure 3 This is a schematic diagram of the pixel set of block M in an embodiment of the present invention;

[0053] Figure 4 This is a schematic diagram of the block structure of an embodiment of the present invention;

[0054] Figure 5 This is a schematic diagram illustrating the storage method of an independent storage pixel set according to an embodiment of the present invention;

[0055] Figure 6 This is a schematic diagram of the storage method of pixels in the horizontal direction of the independent storage pixel set block M according to an embodiment of the present invention;

[0056] Figure 7 This is a schematic diagram of the storage method of pixels in the vertical direction of the independently stored pixel set block M according to an embodiment of the present invention;

[0057] Figure 8 This is a structural block diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this application. Therefore, the drawings and description are considered exemplary in nature and not restrictive.

[0059] In computer graphics, image processing techniques can be applied to rendered images, such as bloom, depth of field, and super-resolution magnification, to enhance the visual effects of the rendering. These image processing algorithms typically involve sampling the pixel colors of the region surrounding a pixel.

[0060] For example, the filtered color G(x, y) obtained by passing the pixel (x, y) through a (2k+1)×(2k+1) filter kernel can be:

[0061]

[0062] Where k is a positive integer, x and y represent the horizontal and vertical coordinates of the pixel in the pixel coordinate system, u and v represent the offsets relative to the horizontal coordinate x and vertical coordinate y in the image coordinate system, u and v are both integers, f(x+u,y+v) represents the original pixel color at pixel (x+u,y+v) in the (2k+1)×(2k+1) filter kernel, and h(u,v) represents the weight factor of F(x+u,y+v).

[0063] Figure 1 A schematic diagram of pixel filtering using a 3×3 pixel filter kernel when k=1. The color of pixel (x, y) after passing through the 3×3 filter kernel can be... As can be seen, filtering a pixel (x, y) requires information from its 8 surrounding pixels. This means that when k = 1, the filtering kernel also needs to process 3×3–1 pixels surrounding the pixel. Similarly, when k = 2, the filtering kernel needs to process 5×5–1 pixels surrounding the pixel.

[0064] Because the rendered image in a tile-based rendering computer graphics processing system is generated separately for each tile, and the filtering of pixels at the boundaries of each tile involves pixels in adjacent tiles, the filtering of pixels at the tile boundaries cannot be completed during the tile processing process. Figure 1As shown, the filtering calculation of the original pixel color f(x, y) in patch M1 requires information of the original pixel colors f(x+1, y+1), f(x+1, y), and f(x+1, y-1) in the adjacent patch M2. Therefore, the filtering at the boundary pixel (x, y) of patch M1 cannot be completed during the processing of patch M1.

[0065] In an embodiment of the present invention, the image patch is divided into an internal pixel set and a boundary pixel set, and filtering processing is performed on the internal pixel set and the boundary pixel set respectively. The filtering processing of the internal pixel set can be started immediately after the rendered image of the image patch is generated, thus reducing the filtering workload after all image patches have been rendered.

[0066] like Figure 2 As shown, the block rendering mode graphics processing system of this invention includes a geometry processing system and a fragment processing system. The geometry processing system is used to construct primitives based on the input geometric data (e.g., vertex data), perform geometric processing on the primitives, divide the visible primitives into multiple blocks M in the screen visual space, and generate a block display list for each block M.

[0067] The geometry processing system further includes an input assembly module, a geometry processing pipeline, and a partitioning module. The input assembly module constructs primitives based on the input geometric data. The geometry processing pipeline processes the constructed primitives, removing those invisible in the screen's visual space and retaining only those visible. The partitioning module divides the visible primitives into multiple blocks M in the screen's visual space and generates a partitioned display list for each block M.

[0068] In some implementations, the tiled display list contains all primitives that at least partially overlap with tile M and thus need to be rendered in tile M; when a primitive is located in multiple tiles, the primitive will be included in the tiled display list of each tile in the screen visual space in which the primitive is located.

[0069] In some implementations, the screen visual space is divided into multiple tiles M, visible primitives are assigned to these tiles M, and a block display list is generated for each tile M. For example... Figure 3 As shown, for an N×N pixel patch M in the screen's visual space, segmentation can be achieved by checking whether the primitives are within, or at least partially within, the rectangular area defined by corner points D0, D1, D2, and D3. For example, primitive T0 partially overlaps with this rectangular area, and primitive T1 is located within this rectangular area; therefore, both primitives T0 and T1 are included in the segmented display list of patch M. Primitives T2 and T3 do not overlap with this rectangular area; therefore, neither primitives T2 nor T3 are included in the segmented display list of patch M.

[0070] The geometry processing pipeline further includes a geometry transformation module, a clipping and culling module, and a data receiving module. The geometry transformation module transforms the vertex data of the primitives constructed by the input assembly module into the screen's visual space. The clipping and culling module removes invisible primitives from the screen's visual space, retaining only the visible primitives, which are the primitives required for rendering the scene. The data receiving module receives and stores the primitive data of the visible primitives in the screen's visual space and the transformed vertex data.

[0071] In some embodiments, the geometry processing system includes a geometry processing pipeline to which primitives constructed by the input assembly module are sent and processed. In other embodiments, the geometry processing system includes multiple geometry processing pipelines to which primitives constructed by the input assembly module are distributed and processed by multiple downstream geometry processing pipelines respectively.

[0072] The graph data and converted vertex data in the data receiving module are written to the first memory of the storage module, and the block display list generated by the block module is written to the second memory of the storage module.

[0073] The fragment processing system is used to render multiple tiles M based on the block display list generated by the geometry processing system, producing rendered images of multiple tiles M. For example... Figure 2 As shown, the fragment processing system includes a block processing module, a rasterization module, a hidden face removal module, a pixel shading module, and a post-processing module. The block processing module reads the block display list generated by the geometry processing system from the second memory and sends the primitives required for rendering the blocks in the block display list to the rasterization module.

[0074] The rasterization module is used to read the required primitive data and converted vertex data of primitives referenced in the block display list from the first memory, and rasterize the primitives into visible pixels. In some embodiments, for a block M, the primitives are rasterized into visible pixels within block M.

[0075] The hidden face removal module performs depth testing on the visible pixels output by the rasterization module. Specifically, it compares the depth value of the visible pixels output by the rasterization module with the depth values ​​of previous primitive pixels stored in the depth buffer. If a primitive pixel output by the rasterization module is occluded by a previous primitive pixel, the depth test is considered to have failed, and the primitive pixel output by the rasterization module is removed. Otherwise, the primitive pixel output by the rasterization module is sent to the pixel shading module. In other words, the hidden face removal module removes pixels located behind other primitives at the same pixel position. In some implementations, the depth value of the previous primitive pixel is a preset value. In some implementations, the depth value of the previous primitive pixel is the depth value of a primitive pixel that previously passed the depth test.

[0076] To avoid frequent data exchange with external memory, in a tile-based rendering computer graphics system, the current depth value of each pixel is stored in an on-chip depth buffer. In some implementations, for a tile M, the current depth value of each pixel in a tile M with N×N pixels is stored in the on-chip depth buffer; that is, the size of the on-chip depth buffer used to store the current depth value is N×N pixels. It is understood that the size of the on-chip depth buffer can be set according to actual needs, and this invention does not limit it.

[0077] The pixel shading module is used to color the visible pixels output by the hidden face removal module to obtain the final color of the primitive pixel. In some implementations, the color information of the pixels in tile M is stored in an on-chip color buffer in a computer graphics processing system with tile rendering mode to avoid frequent data exchange with external memory, which would affect processing efficiency.

[0078] In some implementations, the pixel coloring module is used to color the pixels in the tile M.

[0079] In some implementations, the post-processing module is used to perform pixel filtering on the rendered image of tile M using a filtering kernel to obtain a filtered image.

[0080] In some implementations, the pixel (x, y) in patch M is filtered by a (2k+1)×(2k+1) filter kernel to obtain the filtered color. Where k is a positive integer, x and y represent the horizontal and vertical coordinates of the pixel in the pixel coordinate system, u and v represent the offsets relative to the horizontal coordinate x and vertical coordinate y in the image coordinate system, u and v are both integers, f(x+u,y+v) represents the original pixel color at pixel (x+u,y+v) in the (2k+1)×(2k+1) filter kernel, and h(u,v) represents the weight factor of F(x+u,y+v).

[0081] like Figure 3 As shown, patch M, with N×N pixels, is a rectangular region defined by corner points D0, D1, D2, and D3. Pixel filtering of patch M requires pixel information from surrounding patches, therefore pixels located in the boundary region of patch M cannot be processed directly within patch M.

[0082] In some implementations, the tile M is divided into an internal pixel set Pin (i.e., the first pixel set) and a boundary pixel set Pb (i.e., the second pixel set). The boundary pixel set Pb has the following relationship with the complete pixel set Ptile (i.e., the third pixel set) and the internal pixel set Pin:

[0083]

[0084] Pb = Ptile -- Pin

[0085] The complete pixel set Ptile contains all the pixels of tile M, and consists of N×N pixels contained in the rectangular area defined by corner points D0, D1, D2 and D3.

[0086] The internal pixel set Pin of tile M consists of pixels contained within a rectangular area defined by corner points D0′, D1′, D2′, and D3′. Pixel filtering can be performed on the pixels in the internal pixel set Pin using the pixel information from the complete pixel set Ptile of tile M, without needing pixel information from surrounding tiles outside of tile M.

[0087] In some implementations, each boundary of tile M is moved k pixels inwards to obtain a rectangular region (i.e., the first rectangular region) defined by corner points D0′, D1′, D2′, and D3′. Using the pixel information in the complete pixel set Ptile of tile M, a (2k+1)×(2k+1) filter kernel can be used to perform pixel filtering on the pixels in the internal pixel set Pin.

[0088] Since all the pixels required for pixel filtering using a (2k+1)×(2k+1) filter kernel in the internal pixel set Pin are within tile M, the filtering of pixels in the internal pixel set Pin can be performed directly after the pixel colors in tile M are generated, without waiting for all the rendered images of all tiles to be generated.

[0089] In some implementations, for any target map M0 among multiple map tiles M, pixel filtering processing can be started on the pixels in the internal pixel set Pin0 of the target map tile M0 at the first moment after the rendered image of the target map tile M0 is generated and before all the rendered images of the multiple map tiles M are generated.

[0090] In some implementations, the result of pixel filtering of the pixels in the internal pixel set Pin0 of the target patch M0 is directly written into the memory of the frame color buffer.

[0091] like Figure 3 As shown, the boundary pixel set Pb consists of pixels contained in the regions defined by corner points D0, D1, D2 and D3, as well as D0′, D1′, D2′ and D3′. That is, the boundary pixel set Pb consists of pixels contained in the region remaining after the first rectangular region is removed from the rectangular region of patch M.

[0092] In some implementations, the boundary pixel set Pb includes:

[0093] The first group of boundary pixels at the top of tile M consists of k rows and N columns of pixels;

[0094] The second group of boundary pixels at the bottom of tile M consists of k rows and N columns of pixels.

[0095] The third group of boundary pixels on the left side of tile M, which consists of k columns (N-2k) rows of pixels;

[0096] The fourth group of boundary pixels to the right of patch M consists of k columns (N-2k) rows of pixels.

[0097] In some implementations, the boundary pixel set Pb includes:

[0098] The first group of boundary pixels at the top of tile M consists of k rows (N-2k) of pixels;

[0099] The second group of boundary pixels at the bottom of tile M consists of k rows (N-2k) of pixels;

[0100] The third group of boundary pixels on the left side of tile M, which consists of k columns and N rows of pixels;

[0101] The fourth group of boundary pixels to the right of tile M consists of k columns and N rows of pixels.

[0102] Therefore, the number of pixels in the boundary pixel set Pb is:

[0103] uPb = 2k × N + 2k × (N - 2k)

[0104] For a 3x3 kernel when k=1 and a 32x32 pixel patch M when N=32, the number of pixels in the boundary pixel set Pb is:

[0105] uPb=2×32+2×(32-2)=124

[0106] Therefore, in a 32x32 pixel patch M, the number of pixels in the boundary pixel set Pb accounts for 12.1% of the total number of pixels in patch M.

[0107] For a 5x5 kernel when k=2 and a 32x32 pixel patch M when N=32, the number of pixels in the boundary pixel set Pb is:

[0108] uPb=4×32+4×(32-4)=240

[0109] Therefore, in a 32x32 pixel patch M, the number of pixels in the boundary pixel set Pb accounts for 23.44% of the total number of pixels in patch M.

[0110] Since the boundary pixel set Pb of patch M contains pixels that require pixel filtering using pixel information from neighboring patches outside of patch M, the pixels in the boundary pixel set Pb cannot be directly processed in patch M.

[0111] In some implementations, the pixel color information required for pixel filtering of pixels in the boundary pixel set Pb of patch M is stored separately.

[0112] like Figure 3 As shown in this embodiment of the invention, to perform pixel filtering with a (2k+1)×(2k+1) filter kernel on the k columns of boundary pixels located to the right of patch M in the boundary pixel set Pb, it is necessary to separately store the k columns of pixels located in adjacent patches to the right of the right boundary D1D2 of patch M, and the 2k columns of pixels located in patch M to the left of the right boundary D1D2. Similarly, to perform pixel filtering with a (2k+1)×(2k+1) filter kernel on the k columns of boundary pixels located to the left of patch M in the boundary pixel set Pb, it is necessary to separately store the k columns of pixels located in adjacent patches to the left of the left boundary D0D3 of patch M, and the 2k columns of pixels located in patch M to the right of the left boundary D0D3. To perform pixel filtering with a (2k+1)×(2k+1) kernel on the k rows of boundary pixels at the top of tile M in the boundary pixel set Pb, it is necessary to separately store the k rows of pixels above the top boundary D0D1 of tile M located in neighboring tiles, and the 2k rows of pixels below the top boundary D0D1 located in tile M. Similarly, to perform pixel filtering with a (2k+1)×(2k+1) kernel on the k rows of boundary pixels at the bottom of tile M in the boundary pixel set Pb, it is necessary to separately store the k rows of pixels below the bottom boundary D2D3 of tile M located in neighboring tiles, and the 2k rows of pixels above the bottom boundary D2D3 located in tile M.

[0113] In other words, when using a (2k+1)×(2k+1) filter kernel to filter the boundary pixels of a patch, the color information of the k neighboring pixels in each direction around that pixel is required. Therefore, in order to filter the pixels in the boundary pixel set Pb, the separately stored pixel color information should include not only the pixels in the boundary pixel set Pb, but also the color information of the k neighboring pixels in each direction around the boundary pixel.

[0114] by Figure 4For example, patch T(0,0) is surrounded by 8 patches. The pixel filtering process for any edge pixel of patch T(0,0) requires boundary pixels from 5 of the surrounding patches. Taking the top boundary pixel of patch T(0,0) as an example, its pixel filtering process requires boundary pixel information from patches T(-1,1), T(0,1), T(1,1), T(-1,0), and T(1,0). The pixel filtering process for the boundary pixel at the top corner of patch T(0,0) requires boundary pixels from 3 of the surrounding patches. Taking the top right boundary pixel of patch T(0,0) as an example, its pixel filtering process requires boundary pixel information from patches T(0,1), T(1,1), and T(1,0).

[0115] It can be seen that the first part of the pixels required for pixel filtering of the pixels in the boundary pixel set of patch M is contained in patch M, and the second part of the pixels required for pixel filtering of the pixels in the boundary pixel set of patch M is contained in the patch adjacent to patch M.

[0116] Specifically, such as Figure 3 As shown, pixel filtering with a (2k+1)×(2k+1) filter kernel is performed on the pixels in the boundary pixel set Pb of patch M. This requires using a third rectangular region to remove pixels from the region after the second rectangular region. The third rectangular region is the rectangular region D0″D1″D2″D3″ obtained by moving each boundary of patch M outward by k pixels. The second rectangular region is obtained by moving each boundary of patch M inward by 2k pixels.

[0117] Therefore, in some implementations, the individual stored pixel set Ps (i.e., the fourth pixel set) for each patch M includes 2k rows or 2k columns of pixels inside each boundary of patch M. That is, the individual stored pixel set Ps for patch M is composed of pixels in the first remaining region after removing the second rectangular region from the rectangular region of patch M. By utilizing the pixel color information in the individual stored pixel sets of multiple patches, the pixels in the boundary pixel sets of each patch can be filtered.

[0118] In some implementations, the pixels in the boundary pixel set Pb0 of the target patch M0 can be filtered based on the pixel color information in the separate stored pixel set Ps0 of the target patch M0 and the separate stored pixel set PsX of the multiple adjacent patches MX of the target patch M0.

[0119] In some implementations, pixel color information in the second remaining region is first obtained from the separate stored pixel sets PsX of multiple adjacent pixels MX of the target pixel M0. Then, based on the pixel color information in the fourth pixel set Ps0 of the target pixel M0 and the pixel color information in the second remaining region, a (2k+1)×(2k+1) filter kernel is used to perform pixel filtering processing on the pixels in the second pixel set Pb0 of the target pixel M0. The second remaining region is the region after removing the rectangular region of the target pixel M0 from the third rectangular region.

[0120] In some implementations, separate storage is achieved by allocating a separate storage space within the existing memory and storing the information in that separate storage space. In other implementations, separate storage is achieved by adding a new memory and storing the information in that new memory. In the pixel post-processing stage where pixels in the boundary pixel set Pb are subjected to pixel filtering, only the separately stored color information can be used, which helps to quickly retrieve the pixel color information of the separately stored pixel set from the storage space and improves the efficiency of filtering pixels in the boundary pixel set.

[0121] In some implementations, storing a separate pixel set Ps in a tile M having N×N pixels includes:

[0122] The first group of pixels at the top of tile M consists of 2k rows and N columns of pixels;

[0123] The second group of pixels at the bottom of tile M consists of 2k rows and N columns of pixels.

[0124] The third group of pixels to the left of tile M, which consists of 2k columns (N-4k rows) of pixels;

[0125] The fourth group of pixels to the right of patch M consists of 2k columns (N-4k) rows of pixels.

[0126] In other words, the number of pixels in the horizontal direction (top or bottom) of the pixel set patch M stored separately is uPhori = 2k × N, and the number of pixels in the vertical direction (left or right) of the pixel set patch M stored separately is uPvert = 2k × (N - 4k).

[0127] In some implementations, storing a separate pixel set Ps in a tile M having N×N pixels includes:

[0128] The first group of pixels at the top of tile M consists of 2k rows (N-4k columns) of pixels;

[0129] The second group of pixels at the bottom of tile M consists of 2k rows (N-4k columns) of pixels;

[0130] The third group of pixels to the left of tile M, which consists of 2k columns and N rows of pixels;

[0131] The fourth group of pixels to the right of patch M, which consists of 2k columns and N rows of pixels.

[0132] In other words, the number of pixels in the horizontal direction (top or bottom) of the pixel set patch M stored separately is uPhori = 2k × (N - 4k), and the number of pixels in the vertical direction (left or right) of the pixel set patch M stored separately is uPvert = 2k × N.

[0133] Therefore, the number of pixels in tile M that needs to be stored separately is:

[0134] uPs = 4k × N + 4k × (N - 4k)

[0135] For a 3x3 kernel when k=1 and a 32x32 pixel patch M when N=32, the number of pixels in the separate storage pixel set Ps of the patch boundary region is:

[0136] uPs=4×32+4×(32-4)=240

[0137] Therefore, in a 32x32 pixel tile M, the number of pixels stored in the pixel set Ps alone accounts for 23.44% of the total number of pixels.

[0138] For a 5x5 kernel with k=2 and a 32x32 pixel patch M with N=32, the number of pixels in the separate storage pixel set Ps of the patch boundary region is:

[0139] uPs=8×32+8×(32-8)=448

[0140] Therefore, in a 32x32 pixel tile M, the number of pixels in the separately stored pixel set Ps accounts for 43.75% of the total number of pixels.

[0141] The pixel color information required for the pixel filtering process using a (2k+1)×(2k+1) filter kernel on the boundary pixel set can be read from a separate memory or storage area by address calculation, which can be calculated based on the tile index and the pixel offset within the tile.

[0142] The storage method of the individual storage pixel set Ps in the memory according to the embodiments of the present invention is as follows: Figure 5 As shown, pixel information from the individual pixel sets of each tile M is stored as a whole, on a tile-by-tile basis.

[0143] In some implementations, pixel information from a single storage pixel set of a tile is stored as a whole, in the order of the tiles. For example, Figure 5 In this diagram, the pixel information of each individual pixel set in a map is treated as a whole and stored separately for each map in the order M0 to M4. It should be understood that each of the maps M0 to M4 represents a specific map M, and different labels are used for ease of distinction and understanding. Within the storage space corresponding to each map, the pixel information of that map's individual pixel set is stored in the order of top pixels, bottom pixels, left pixels, and right pixels.

[0144] Specifically, when performing pixel filtering on the fourth group of boundary pixels located on the right side of patch M in the boundary pixel set Pb of patch M using a (2k+1)×(2k+1) filter kernel, it is necessary to read the color information of 2k columns of pixels located on the left side of the right boundary of patch M within patch M from a separate storage space. Therefore, the color information of the 2k columns of pixels located on the left side of the right boundary of patch M within patch M should be stored at adjacent addresses in a separate storage space. This way, it is possible to obtain all the information required for pixel filtering from the storage space with the fewest read operations.

[0145] Similarly, the color information of the 2k columns of pixels located to the right of the left boundary of tile M and within tile M should also be stored at an adjacent address in a separate storage space; the color information of the 2k rows of pixels located below the top boundary of tile M and within tile M should also be stored at an adjacent address in a separate storage space; and the color information of the 2k rows of pixels located above the bottom boundary of tile M and within tile M should also be stored at an adjacent address in a separate storage space.

[0146] In some implementations, to improve memory access efficiency, the horizontal (top or bottom) pixels of the pixel cluster are stored column-by-column, such as... Figure 6 As shown, the color information of the pixels is first stored vertically at the starting position. When the color information of the pixels in the current column is completely stored, the pixel moves horizontally to the next column position and continues to store from the starting position of the next column position, and so on.

[0147] In some implementations, to improve memory access efficiency, the vertical (left or right) pixels of the pixel cluster are stored row by row, such as... Figure 7 As shown, the color information of the pixels is first stored horizontally at the starting position. When the color information of the pixels in the current row is completely stored, the process moves vertically to the next row position and continues to store from the starting position of the next row, and so on.

[0148] In some implementations, for a (2k+1)×(2k+1) filter kernel, the pixel color address of the fourth group of pixels to the right of patch M0 in the separate storage pixel set Ps0 of the target patch M0 is:

[0149] Addr(x,y)=TileM0×uPs0+2×uPhori0+uPvert0+y×2k+(x-Pr0+2k-1)

[0150] In some implementations, for a (2k+1)×(2k+1) filter kernel, the pixel color address of the third group of pixels to the left of patch M0 in the separate storage pixel set Ps0 of the target patch M0 is:

[0151] Addr(x,y)=TileM0×uPs0+2×uPhori0+y×2k+x.

[0152] In some implementations, for a (2k+1)×(2k+1) filter kernel, the pixel color address of the first group of pixels at the top of patch M0 in the separate storage pixel set Ps0 of the target patch M0 is:

[0153] Addr(x,y)=TileM0×uPs0+2k×x+(Pd0-y)

[0154] Where Pd0 represents the pixel offset of the top boundary of the target tile M0.

[0155] In some implementations, for a (2k+1)×(2k+1) filter kernel, the pixel color address of the second group of pixels at the bottom of patch M0 in the separate storage pixel set Ps0 of the target patch M0 is:

[0156] Addr(x,y)=TileM0×uPs0+uPhori0+2k×x+(2k-1-y).

[0157] Where x and y represent the horizontal and vertical coordinates of the pixel in the pixel coordinate system, respectively, TileM0 represents the tile index of the target tile M0, uPs0 represents the number of pixels in the fourth pixel set Ps0, uPhori0 represents the number of top or bottom pixels of the target tile M0 in the fourth pixel set Ps0, uPvert0 represents the number of left or right pixels of the target tile M0 in the fourth pixel set Ps0, Pr0 represents the pixel offset of the right boundary of the target tile M0, and Pd0 represents the pixel offset of the top boundary of the target tile M0.

[0158] like Figure 1 As shown, applying a 3×3 filter kernel to the right boundary pixel (x, y) of the current patch M1 to obtain the filtered color G(x, y) can be:

[0159]

[0160] Figure 1 The pixel color addresses of the pixels in column (x-1) and column x can be calculated using the following formula:

[0161] Addr(x,y)=TileM1×uPs1+2×uPhori1+uPvert1+y×2+(x-Pr1+1)

[0162] Figure 1 The pixel color address of the (x+1)th column pixel in the adjacent right-hand patch M2 can be calculated using the following formula:

[0163] Addr(x,y)=TileM2×uPs1+2×uPhori1+y×2+x

[0164] As mentioned earlier, when k=1 and N=32, the number of pixels in the individual storage pixel set Ps1 of patch M1 is uPs1=240. The number of horizontal (top or bottom) boundary pixels of patch M1 in the individual storage pixel set is calculated to be uPhori1=64, and the number of vertical (left or right) boundary pixels of patch M1 in the individual storage pixel set is uPvert1=56.

[0165] Given that the tile index of the target tile M1 is TileM1, the tile index of the adjacent tile M2 to its right is TileM2, and the pixel offset Pr1 = 31 of the right boundary of the target tile M1.

[0166] Figure 1 The pixel color address of the pixel in column (x-1) can be calculated as follows:

[0167] Addr(x-1,y)=TileM1×240+2×64+56+y×2+(x-1-31+1)=240TileM1+184+2y+(x-31)

[0168] Figure 1 The pixel color address of the pixel in column x can be calculated as follows:

[0169] Addr(x,y)=TileM1×240+2×64+56+y×2+(x-31+1)=240TileM1+184+2y+(x-30)

[0170] Figure 1 The pixel color address of the pixel in column (x+1) can be calculated as follows:

[0171] Addr(x+1,y)=TileM2×240+2×64+y×2+x+1=240TileM2+129+2y+x

[0172] In some implementations, pixel filtering is performed on the pixels in the boundary pixel set Pb0 of the target tile M0 at a second time after the pixel colors in all tiles have been generated.

[0173] To further improve the efficiency of pixel filtering for the boundary pixels of the target tile, in an embodiment of the present invention, after the rendering of the target tile is completed, pixel filtering is performed on the pixels in the internal pixel set of the target tile M0, and the rendering status of the adjacent tile MX of the target tile M0 is checked. If the rendering status of the adjacent tile meets the requirements, the pixels in the boundary pixel set of the target tile M0 are filtered in advance, without waiting for the rendering of all tiles to be completed.

[0174] In some implementations, after the rendered image of target tile M0 is generated but before all rendered images of multiple tiles M are generated, the rendering status of multiple adjacent tiles MX of target tile M0 is checked. When all pixel information used for pixel filtering of pixels in the boundary pixel set Pb0 of target tile M0 in the multiple adjacent tiles MX is generated, pixel filtering is performed on the pixels in the boundary pixel set Pb0 of target tile M0. That is, processing is performed on a per-pixel basis within the boundary pixel set Pb0.

[0175] In some implementations, after the rendered image of target tile M0 is generated but before all rendered images of multiple tiles M are generated, the rendering status of multiple adjacent tiles MX of target tile M0 is checked. When all pixel information used for pixel filtering of a subset of pixels in the boundary pixel set Pb0 of target tile M0 is generated in the multiple adjacent tiles MX, pixel filtering is performed on the subset of pixels in the boundary pixel set Pb0 of target tile M0. That is, processing is performed on a unit of pixel subsets consisting of a group of pixels in the boundary pixel set Pb0.

[0176] In some implementations, the subset of pixels in the boundary pixel set Pb0 is a first set of boundary pixels located at the top of the target tile M0, a second set of boundary pixels located at the bottom of the target tile M0, a third set of boundary pixels located to the left of the target tile M0, or a fourth set of boundary pixels located to the right of the target tile M0.

[0177] It should be understood that the aforementioned third time and the aforementioned first time may be the same time or different times, both of which are within the scope of protection of this application, and this application does not impose any restrictions on them.

[0178] In some implementations, at a second time after all the rendered images of the multiple tiles M have been generated, pixel filtering processing is started on the remaining pixels in the boundary pixel set Pb0 of the target tile M0; wherein, the remaining pixels are the pixels in the boundary pixel set Pb0 of the target tile M0 that did not undergo pixel filtering processing before all the rendered images of the multiple tiles M were generated.

[0179] As can be seen, through the above processing, pixel filtering can be performed on the boundary pixels of the target tile during the tile processing (i.e., when all tiles have not been fully rendered), without having to wait until all tiles have been rendered before performing this step, further reducing the workload of the later separate processing stage.

[0180] It should be understood that all four sets of boundary pixels of some target tiles may be processed during tile rendering, some sets of boundary pixels of some target tiles may be processed during tile rendering, and some target tiles may not meet the processing conditions for all four sets of boundary pixels, so no boundary pixels can be processed during tile rendering.

[0181] Furthermore, in some embodiments, a boundary mask is stored for each tile to indicate whether pixels or subsets of pixels in the tile boundary pixel set have undergone pixel filtering before all rendered images of multiple tiles M are generated. In some embodiments, a 4-bit boundary mask is stored for each tile to indicate whether the first group of boundary pixels at the top of the tile, the second group of boundary pixels at the bottom of the tile, the third group of boundary pixels on the left side of the tile, and the fourth group of boundary pixels on the right side of the tile boundary pixel set have undergone pixel filtering before all tiles are rendered. In some embodiments, after pixel filtering is performed on a subset of pixels in the boundary pixel set, boundary bits are set in the boundary mask accordingly. This allows the boundaries to be skipped in a separate stage of subsequent boundary pixel filtering, reducing the workload of separate processing stages.

[0182] like Figure 4As shown, during pixel filtering of the internal region (i.e., pixels within the internal pixel set Pin) of patch T(0,0), if the rendering of adjacent patches T(-1,1), T(0,1), T(1,1), T(-1,0), and T(1,0) has been completed and their boundary pixel information has been stored in separate memory and is available, then filtering of the first set of boundary pixels at the top of patch T(0,0) can begin. After processing, the boundary mask of the corresponding top boundary pixels in patch T(0,0) can be set to 1 to avoid filtering the first set of boundary pixels at the top of patch T(0,0) in a separate processing stage after all patches have been rendered, effectively improving the efficiency of filtering pixels in the boundary pixel set.

[0183] Figure 8 This is a structural block diagram of an electronic device according to an embodiment of this application. Embodiments of this application also provide an electronic device, such as... Figure 8 As shown, the electronic device includes at least one processor 801 and a memory 803 communicatively connected to the at least one processor 801. The memory 803 stores instructions executable by the at least one processor 801. The instructions are executed by the at least one processor 801. When the processor 801 executes the instructions, it implements the graphics processing method described in the above embodiments. The number of memories 803 and processors 801 can be one or more. This electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present application described and / or claimed herein.

[0184] The electronic device may also include a communication interface 805 for communicating with external devices and exchanging data. The devices are interconnected using different buses and can be mounted on a common motherboard or otherwise installed as needed. The processor 801 can process instructions executed within the electronic device, including instructions stored in or on memory to display graphical information of a graphical user interface (GUI) on an external input / output device (such as a display device coupled to the interface). In other embodiments, multiple processors and / or multiple buses can be used with multiple memories and multiple storage devices, if desired. Similarly, multiple electronic devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). The bus can be divided into address buses, data buses, control buses, etc. For ease of illustration, Figure 8 The symbol is represented by only one line, but this does not mean that there is only one bus or one type of bus.

[0185] Optionally, in a specific implementation, if the memory 803, the processor 801, and the communication interface 805 are integrated on a single chip, then the memory 803, the processor 801, and the communication interface 805 can communicate with each other through an internal interface.

[0186] It should be understood that the aforementioned processor can be a Central Processing Unit (CPU), or other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. General-purpose processors can be microprocessors or any conventional processor. It is worth noting that the processor can be a processor supporting Advanced Reduced Instruction Set Machines (ARM) architecture.

[0187] This application provides a computer-readable storage medium (such as the memory 803 described above) that stores computer instructions, which, when executed by a processor, implement the method provided in this application.

[0188] Optionally, memory 803 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function; the data storage area may store data created by the use of the electronic device according to the graphics processing method. Furthermore, memory 803 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory 803 may optionally include memory remotely located relative to processor 801, and these remote memories can be connected to the electronic device of the graphics processing method via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0189] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0190] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0191] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more (two or more) executable instructions for implementing a particular logical function or process. Furthermore, the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functionality involved.

[0192] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-included system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

[0193] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. All or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware, the program being stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiments.

[0194] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. This storage medium can be a read-only memory, a disk, or an optical disk, etc.

[0195] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A graphics processing system, characterized in that, Includes a geometry processing system and a fragment processing system; The geometric processing system is used to perform geometric processing on primitives and then divide the visible primitives into multiple blocks M in the screen visual space. The multiple image tiles M are obtained by dividing the screen visual space; The fragment processing system is used to render the plurality of image patches M, generating rendered images of the plurality of image patches M, each image patch M having a first pixel set. Second pixel set and the third pixel set ;in, First pixel set The internal pixel set of patch M, the second pixel set Let M be the boundary pixel set and the third pixel set. It contains all the pixels of tile M; The fragment processing system includes a post-processing module, which is used to start processing the first pixel set of the target patch M0 at a first moment after the rendered image of the target patch M0 in the plurality of patches M is generated and before all the rendered images of the plurality of patches M are generated. Perform pixel filtering on the pixels in the image; The post-processing module is also used to, at a second time after all the rendered images of the plurality of map tiles M have been generated, start processing the second pixel set of the target map tile M0. The pixels in the image are subjected to pixel filtering.

2. A graphics processing system, characterized in that, Includes a geometry processing system and a fragment processing system; The geometric processing system is used to perform geometric processing on primitives and then divide the visible primitives into multiple blocks M in the screen visual space. The multiple image tiles M are obtained by dividing the screen visual space; The fragment processing system is used to render the plurality of image patches M, generating rendered images of the plurality of image patches M, each image patch M having a first pixel set. Second pixel set and the third pixel set ;in, First pixel set The internal pixel set of patch M, the second pixel set Let M be the boundary pixel set and the third pixel set. It contains all the pixels of tile M; The fragment processing system includes a post-processing module, which is used to start processing the first pixel set of the target patch M0 at a first moment after the rendered image of the target patch M0 in the plurality of patches M is generated and before all the rendered images of the plurality of patches M are generated. Perform pixel filtering on the pixels in the image; The post-processing module is further configured to, in a third time after the rendering image of the target patch M0 in the plurality of patches M is generated but before all rendering images of the plurality of patches M are generated, begin to check the rendering status of the multiple adjacent patches MX of the target patch M0, and in the multiple adjacent patches MX, to process the second pixel set of the target patch M0. When all pixel information of the pixels in the target image M0 has been generated after pixel filtering, the second pixel set of the target image M0 is... Pixel filtering is performed on the pixels in the plurality of adjacent pixels MX; or, a second set of pixels is used to filter the target pixel M0. When all pixel information from the pixel subset of the target image M0 is generated after pixel filtering, the second pixel set of the target image M0 is... A subset of pixels is subjected to pixel filtering.

3. The graphics processing system as described in claim 2, characterized in that, The post-processing module is also used to, at a second time after all the rendered images of the plurality of map tiles M have been generated, start processing the second pixel set of the target map tile M0. The remaining pixels in the target image patch M0 are subjected to pixel filtering; the remaining pixels are the second pixel set of the target image patch M0. Pixels that failed to undergo pixel filtering before all rendered images of the multiple tiles M were generated.

4. The graphics processing system as described in claim 2, characterized in that, The post-processing module is also used to set a boundary mask and determine the second pixel set based on the boundary mask. Whether the pixels or subsets of pixels in the image have undergone pixel filtering before the entire rendered image of multiple tiles M is generated.

5. The graphics processing system as described in any one of claims 1 to 4, characterized in that, Move each boundary of tile M inward. k The pixels in the first rectangular region constitute the first pixel set. Enable Filter and verify the first pixel set of target patch M0 The pixels in the image are subjected to pixel filtering, where k is a positive integer.

6. The graphics processing system as described in claim 5, characterized in that, Each tile M also has a fourth pixel set. The fourth pixel set The first remaining region is formed by removing the second rectangular region from the rectangular region of patch M. The second rectangular region is formed by shifting each boundary of patch M inward by 2 pixels. k The fragment processing system is used to obtain the fourth pixel set of each patch M. Store the fourth pixel set separately. The pixel information in the image is stored as a whole, in units of tiles; The post-processing module is also used to obtain the fourth pixel set from multiple adjacent pixels MX of the target pixel M0. The pixel color information in the second remaining region is obtained. The second remaining region is the region after removing the rectangular region of the target patch M0 from the third rectangular region. The third rectangular region is obtained by moving each boundary of the target patch M0 outward. k 1 pixel is obtained; The post-processing module is further configured to use the fourth pixel set of the target patch M0. The pixel color information in the first region and the pixel color information in the second remaining region are used to determine the second pixel set of the target patch M0. Enable pixels in The filter kernel performs pixel filtering.

7. The graphics processing system as described in claim 6, characterized in that, The fragment processing system is used to calculate the value of the second pixel set based on the patch index of the target patch M0, the patch indices of the plurality of adjacent patches MX, and the pixel offset within the target patch M0. Enable pixels in The pixel color address required by the filter kernel for pixel filtering processing.

8. The graphics processing system as described in claim 6, characterized in that, The fragment processing system is used to store the fourth pixel set in the storage space corresponding to each patch M. The pixel information in the image is stored in the order of the top pixel, bottom pixel, left pixel, and right pixel of the image block M.

9. The graphics processing system as described in claim 8, characterized in that, The fragment processing system is used to store the fourth pixel set column by column. The pixel information of the first group of pixels at the top of the middle image block M is stored column by column for the fourth pixel set. The pixel information of the second group of pixels at the bottom of the middle image block M is stored line by line for the fourth pixel set. The pixel information of the third group of pixels on the left side of block M in the middle image, and the fourth pixel set stored line by line. The pixel information of the fourth group of pixels to the right of block M in the middle image.

10. The graphics processing system as described in claim 9, characterized in that, for Filter kernel, the fourth pixel set of the target patch M0 The pixel color address of the fourth group of pixels to the right of the target image block M0 is: ， Where x and y represent the x-coordinate and y-coordinate of the pixel in the pixel coordinate system, respectively. Indicates the tile index of the target tile M0. Represents the fourth pixel set The number of pixels in Represents the fourth pixel set The number of top or bottom pixels of the target tile M0. Represents the fourth pixel set The number of pixels to the left or right of the target pixel M0. This represents the pixel offset of the right boundary of the target tile M0.

11. The graphics processing system as described in claim 10, characterized in that, for Filter kernel, the fourth pixel set of the target patch M0 The pixel color address of the third group of pixels to the left of the target image block M0 is: 。 12. The graphics processing system as described in claim 10, characterized in that, for Filter kernel, the fourth pixel set of the target patch M0 The pixel color address of the first group of pixels at the top of the target block M0 is: ， in, This represents the pixel offset of the top boundary of the target tile M0.

13. The graphics processing system as described in claim 10, characterized in that, for Filter kernel, the fourth pixel set of the target patch M0 The pixel color address of the second group of pixels at the bottom of the target patch M0 is: 。 14. A graphics processing method, characterized in that, include: Divide the screen visual space into multiple tiles M; After geometric processing of the primitives, the visible primitives are divided into multiple blocks M in the screen visual space; The plurality of image tiles M are rendered to generate rendered images of the plurality of image tiles M; each image tile M has a first pixel set. Second pixel set and the third pixel set ;in, First pixel set The internal pixel set of patch M, the second pixel set Let M be the boundary pixel set and the third pixel set. It contains all the pixels of tile M; In the first instant after the rendered image of target patch M0 among the plurality of patches M is generated but before all rendered images of the plurality of patches M are generated, the first pixel set of target patch M0 is processed. Perform pixel filtering on the pixels in the image; At the second time after all the rendered images of the plurality of map tiles M have been generated, the second pixel set of the target map tile M0 is processed. The pixels in the image are subjected to pixel filtering.

15. A graphics processing method, characterized in that, include: Divide the screen visual space into multiple tiles M; After geometric processing of the primitives, the visible primitives are divided into multiple blocks M in the screen visual space; The plurality of image tiles M are rendered to generate rendered images of the plurality of image tiles M; each image tile M has a first pixel set. Second pixel set and the third pixel set ;in, First pixel set The internal pixel set of patch M, the second pixel set Let M be the boundary pixel set and the third pixel set. It contains all the pixels of tile M; In the first instant after the rendered image of target patch M0 among the plurality of patches M is generated but before all rendered images of the plurality of patches M are generated, the first pixel set of target patch M0 is processed. Perform pixel filtering on the pixels in the image; After the rendering image of the target tile M0 in the plurality of tiles M is generated, but before all the rendering images of the plurality of tiles M are generated, the rendering status of the multiple adjacent tiles MX of the target tile M0 is checked. The second pixel set used for the target patch M0 in the plurality of adjacent patches MX When all pixel information of the pixels in the target image M0 has been generated after pixel filtering, the second pixel set of the target image M0 is... Perform pixel filtering on the pixels in the image; or... The second pixel set used for the target patch M0 in the plurality of adjacent patches MX When all pixel information from the pixel subset of the target image M0 is generated after pixel filtering, the second pixel set of the target image M0 is... A subset of pixels is subjected to pixel filtering.

16. The graphics processing method as described in claim 15, characterized in that, The method further includes: at a second time after all the rendered images of the plurality of map tiles M have been generated, starting to process the second pixel set of the target map tile M0. The remaining pixels in the target image patch M0 are subjected to pixel filtering; the remaining pixels are the second pixel set of the target image patch M0. Pixels that failed to undergo pixel filtering before all rendered images of the multiple tiles M were generated.

17. The graphics processing method as described in claim 15, characterized in that, The method further includes: setting a boundary mask, and determining the second pixel set based on the boundary mask. Whether the pixels or subsets of pixels in the image have undergone pixel filtering before the entire rendered image of multiple tiles M is generated.

18. The graphics processing method according to any one of claims 14 to 17, characterized in that, Move each boundary of tile M inward. k The pixels in the first rectangular region constitute the first pixel set. Enable Filter and verify the first pixel set of target patch M0 The pixels in the image are subjected to pixel filtering, where k is a positive integer.

19. The graphics processing method as described in claim 18, characterized in that, Each tile M also has a fourth pixel set. The fourth pixel set The first remaining region is formed by removing the second rectangular region from the rectangular region of patch M. The second rectangular region is formed by shifting each boundary of patch M inward by 2 pixels. k 1 pixel is obtained; The method further includes: Store the fourth pixel set of each tile M separately. , set the fourth pixel The pixel information in the image is stored as a whole, in units of tiles; The fourth pixel set from multiple adjacent patches MX of the target patch M0 The pixel color information in the second remaining region is obtained. The second remaining region is the region after removing the rectangular region of the target patch M0 from the third rectangular region. The third rectangular region is obtained by moving each boundary of the target patch M0 outward. k 1 pixel is obtained; Based on the fourth pixel set of the target patch M0 The pixel color information in the first region and the pixel color information in the second remaining region are used to determine the second pixel set of the target patch M0. Enable pixels in The filter kernel performs pixel filtering.

20. An electronic device, characterized in that, Includes the graphics processing system according to any one of claims 1 to 13; Alternatively, the electronic device may include: processor; The memory is communicatively connected to the processor; The memory stores instructions that can be executed by the processor to enable the processor to perform the method of any one of claims 14 to 19.

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