An aes operation circuit and method

Abstract

The application discloses an AES operation circuit and method, and compared with the prior art, the application realizes the in-loop circulation of the AES algorithm through the pipeline technology, that is, part of the transformation of the next round can be realized in the transformation process of the current round, so that the number of clock cycles consumed by the AES encryption and decryption process is less, and the efficiency of data encryption and decryption is improved; in addition, since only the current key is stored, a large number of storage units are saved, so that the area of the AES operation circuit is greatly reduced, which is favorable for reducing the cost and improving the market competitiveness.

Description

Technical Field

[0001] This invention relates to the field of cryptographic circuit technology, specifically to an AES operation circuit and method. Background Technology

[0002] Advanced Encryption Standard (AES) is an encryption method widely used in general-purpose MCUs, especially cost-effective MCUs. These MCUs need to minimize the area of ​​each module while ensuring that the circuit can operate at the specified frequency, in order to control the cost of the MCU and improve its market competitiveness.

[0003] Traditional AES key processing circuits use registers or SRAM to pre-refresh the keys for each round before encryption and decryption, storing them sequentially in the memory. During subsequent encryption and decryption, the key for the current round is retrieved from the memory. For example, with 128-bit data and a 128-bit key, 11 rounds of encryption and decryption require 11 sets of 128-bit keys. Therefore, before encryption and decryption, the CPU sends a `key_start` signal to the AES module to perform key calculations and write the 11 round keys sequentially into the memory, consuming a total of 11 × 128 bits = 1408 bits of storage. Clearly, traditional AES key processing circuits require a large amount of storage, which is detrimental to cost reduction.

[0004] Furthermore, as an iterative encryption algorithm, AES requires a different number of rounds depending on the key length. Taking an AES encryption / decryption process with 128-bit data and a 128-bit key as an example, both encryption and decryption require 11 rounds of data processing (round 0 to round 10). Round 0 is called the initial round (or first round), rounds 1 to 9 are called intermediate rounds, and round 10 is called the final round. Except for the first round, each round receives data processed in the previous round and performs the computation. Traditional AES strictly follows the order of round transformations, making it impossible to segment operations within a round. This results in a high clock cycle consumption and low efficiency in the encryption / decryption process. Summary of the Invention

[0005] To address the aforementioned problems, this invention provides an AES operation circuit and method, which significantly reduces the area of ​​the key processing circuit and data encryption / decryption processing circuit, while improving the efficiency of data encryption / decryption and facilitating cost control. The specific technical solution of this invention is as follows:

[0006] An AES (Automatic Encryption and Decryption) processing circuit includes: a bus interface module for data interaction between a master and slave device; a FIFO (Fixed-Input Filter) module connected to the bus interface module for data buffering; a data flow control module connected to the FIFO module and a data encryption / decryption processing module for controlling data interaction between the FIFO module and the data encryption / decryption processing module; a data encryption / decryption processing module connected to the data flow control module for implementing data encryption / decryption using in-wheel pipeline technology; and a key processing module connected to the bus interface module and the data encryption / decryption processing module for providing the current key to the data encryption / decryption processing module; wherein the key processing module only stores the current key.

[0007] Compared with existing technologies, this technical solution implements the in-round loop of the AES algorithm through pipeline technology. That is, during the transformation of the current round, a partial transformation of the next round can be achieved, which reduces the number of clock cycles consumed by the AES encryption and decryption process and improves the efficiency of data encryption and decryption. In addition, since only the current key is stored, a large number of storage units are saved, which greatly reduces the area of ​​the AES operation circuit and helps to reduce costs.

[0008] Furthermore, the FIFO module includes an input buffer FIFO module and an output buffer FIFO module; wherein, the input buffer FIFO module is used to buffer the data to be encrypted or decrypted transmitted from the host by the bus interface module; and the output buffer FIFO module is used to buffer the encrypted or decrypted data transmitted from the data encryption / decryption processing module.

[0009] Further, the data encryption / decryption processing module includes: a first counter, used to count the number of clock cycles during the data encryption / decryption process and output the current sub-round number, resetting the current sub-round number to zero and recounting after a preset number of counts; a second counter, connected to the first counter, receiving the current sub-round number output by the first counter, used to count the number of pipeline rounds based on the current sub-round number; and a first-stage encryption / decryption circuit, connected to the second counter, used to perform a first-round XOR operation and a second-round S-box transformation / inverse S-box transformation and row shift transformation / inverse row shift transformation on the data to be encrypted / decrypted based on the number of pipeline rounds, the current sub-round number, and the AES direction; wherein, the AES direction includes the data encryption direction and the data decryption direction; the first round and the second round respectively represent AES... The data encryption and decryption rounds consist of an initial and intermediate round; a second-level encryption and decryption circuit, connected to the second counter and the first-level encryption and decryption circuit, which performs column-mixing transformation / inverse column-mixing transformation and XOR operation on the data output from the first-level encryption and decryption circuit in round N-1, and S-box transformation / inverse S-box transformation and row-shift transformation / inverse row-shift transformation in round N, based on the pipeline round number, the current sub-round number, and the AES direction; where N represents the AES data encryption and decryption round number, N is a positive integer greater than 2, and the maximum value of N is determined by the key length; and a third-level encryption and decryption circuit, connected to the second counter and the second-level encryption and decryption circuit, which performs XOR operation on the data output from the second-level encryption and decryption circuit based on the pipeline round number and the current sub-round number, and then outputs the encrypted and decrypted data. This technical solution implements the in-round loop of the AES algorithm through pipeline technology, that is, during the transformation process of the current round, a partial transformation of the next round can be achieved, which reduces the number of clock cycles consumed by the AES encryption and decryption process and improves the efficiency of data encryption and decryption.

[0010] Furthermore, the first counter counts the number of clock cycles each time it receives an AES module enable; after counting a preset number of times, the first counter generates a key refresh enable, and then resets the current sub-round count to zero and restarts the count. After counting a preset number of times, all bits of the current key have been transformed, and generating a key refresh enable can refresh the current key. At the same time, resetting the current sub-round count to zero allows the corresponding module to correctly select the corresponding bits of the refreshed current key.

[0011] Furthermore, the second counter counts the number of pipeline wheels once for every preset number of current sub-wheel counts received; when the number of pipeline wheels reaches the maximum value of N and the total number of clock cycles reaches the preset value, the second counter generates a valid encrypted / decrypted data flag signal.

[0012] Further, the first-stage encryption / decryption circuit includes: a first data selector, used to select the corresponding number of bits of the data to be encrypted / decrypted and the corresponding number of bits of the current key according to the current sub-round number, and output the result to a first XOR operation module; a first XOR operation module, connected to the first data selector, used to perform an XOR operation on the corresponding number of bits of the data to be encrypted / decrypted and the corresponding number of bits of the current key; a second data selector, connected to the second counter, used to select the XOR operation result of the corresponding round number according to the pipeline round number and output it to a first register; a first register, connected to the second data selector, used to store the data selected by the second data selector. If the pipeline round number reaches the maximum value of N and the total number of clock cycles reaches a preset value, the first register outputs the received data as encrypted / decrypted data; otherwise, the first register temporarily stores the received data until it is read by the next module; a third data selector, connected to the first register, used to select the corresponding number of bits of the XOR operation result in the first register according to the current sub-round number, and then transmit it to the S-box conversion module. An S-box transformation module, connected to the third data selector, is used to perform S-box transformation / inverse S-box transformation on the data output by the third data selector according to the AES direction; a data merging module, connected to the S-box transformation module, is used to merge the data output by the S-box transformation module; a row shift transformation module, connected to the data merging module, is used to perform row shift transformation / inverse row shift transformation on the merged data according to the AES direction; a fourth data selector, connected to the row shift transformation module, is used to select the corresponding bit length of the transformation result in the row shift transformation module according to the current sub-round number and output it to the next stage circuit; wherein, the data processing bit width of the first XOR operation module and the S-box transformation module is a first preset bit width, the data processing bit width of the row shift transformation module is a second preset bit width, the second preset bit width is an integer multiple of the first preset bit width, the storage space of the first register is a first preset value, the size of the first preset value is equal to the size of the second preset bit width, and the size of the corresponding bit length is equal to the size of the first preset bit width. This technical solution can perform XOR operations, S-box transformation / inverse S-box transformation, and row shift transformation / reverse row shift transformation on the data to be encrypted or decrypted in one round of pipeline, realizing the in-round loop of the AES algorithm and reducing the number of clock cycles consumed by the AES encryption and decryption process.

[0013] Furthermore, the data merging module includes a second register and a third register. The second register is connected to the S-box transformation module and is used to store the data output by the S-box transformation module. The third register is connected to both the S-box transformation module and the second register. When the storage space of the first register is insufficient, it receives the data output by the S-box transformation module and also receives the data in the first register, and then merges all the data. The storage space of the second register is a second preset value, and the storage space of the third register is a first preset value. The second preset value is less than the first preset value and is an integer multiple of the first preset bit width. This technical solution merges the data after S-box transformation / inverse S-box transformation, allowing the row shift transformation module to complete the row shift transformation / inverse row shift transformation of the data in one go, reducing the number of clock cycles consumed by the AES encryption and decryption process.

[0014] Further, the second-level encryption / decryption circuit includes: a column mixing transformation module connected to the fourth data selector, used to perform column mixing transformation / inverse column mixing transformation on the corresponding bits of the transformation result in the row shift transformation module according to the AES direction; a fifth data selector, used to select the corresponding bits of the current key according to the current sub-round number; a key inverse column mixing transformation module connected to the fifth data selector, used to perform inverse column mixing transformation on the corresponding bits of the current key output by the fifth data selector during data decryption; and a sixth data selector connected to the fifth data selector and the key inverse column mixing transformation module, used to select the corresponding bits of the fifth data selector according to the AES direction. The data output by the selector or the key inverse column hybrid transformation module is transmitted to the second XOR operation module; the second XOR operation module, connected to the sixth data selector and the column hybrid transformation module, is used to perform XOR operations on the data output by the column hybrid transformation module and the sixth data selector; the second-level encryption / decryption circuit also includes the second data selector, the first register, the third data selector, the S-box transformation module, the data merging module, the row shift transformation module, and the fourth data selector; wherein, the data processing bit width of the column hybrid transformation module, the key inverse column hybrid transformation module, and the second XOR operation module is a first preset bit width. This technical solution can realize column hybrid transformation / inverse column hybrid transformation, XOR operation, S-box transformation / inverse S-box transformation, and row shift transformation / inverse row shift transformation of the data to be encrypted / decrypted in one round of pipeline, realizing the in-round loop of the AES algorithm and reducing the number of clock cycles consumed by the AES encryption / decryption process.

[0015] Furthermore, the third-level encryption / decryption circuit includes: a seventh data selector, used to select the corresponding number of bits of the current key according to the current sub-round number; a third XOR operation module, connected to the seventh data selector and the fourth data selector, used to perform an XOR operation on the corresponding number of bits of the transformation result in the row shift transformation module and the corresponding number of bits of the current key; the third-level encryption / decryption circuit also includes a second data selector and the first register; wherein, the second data selector is connected to the first XOR operation module, the second XOR operation module and the third XOR operation module respectively; wherein, the data processing bit width of the third XOR operation module is a first preset bit width. Since the previous stage circuit has completed the S-box transformation / inverse S-box transformation and the row shift transformation / inverse row shift transformation, this technical solution only needs to implement the XOR operation, reducing the number of clock cycles consumed by the AES encryption / decryption process.

[0016] Furthermore, the first preset bit width is 32 bits, the second preset bit width and the first preset value are 128 bits, and the second preset value is 96 bits. This technical solution uses a 32-bit XOR operation module, an S-box transformation module, and a column hybrid transformation module with a data processing bit width of 32 bits instead of 64 bits (which requires two 32-bit components), which greatly reduces the area of ​​the data encryption and decryption processing module, helps control costs, and improves market competitiveness.

[0017] Furthermore, the key processing module includes: a key pre-refresh control state machine module, used to generate a key pre-refresh enable to control the key transformation module to perform key pre-refresh, and output a key pre-refresh completion interrupt signal after the key pre-refresh is completed; a first OR gate, connected to the key pre-refresh control state machine module, performing an OR operation on the key pre-refresh enable and the key refresh enable generated by the data encryption / decryption processing module; a key transformation module, connected to the first OR gate, used for key refresh to update the key in the key register; a data selector, connected to the key transformation module, selecting the corresponding key according to the data selection signal and transmitting it to the key register; and a key register, connected to the data selector, used to store the current key. This technical solution uses the key transformation module to refresh the key required in the encryption / decryption process, and updates the key in the key register with the refreshed key. Since only the current key is stored, a large number of storage units are saved, greatly reducing the area of ​​the key processing module and helping to reduce costs.

[0018] Furthermore, the key transformation module includes a forward key transformation module and a reverse key transformation module. The forward key transformation module, connected to the first OR gate, receives a key pre-refresh enable or a key refresh enable and performs one round of forward key transformation during the data encryption and key pre-refresh processes. The reverse key transformation module receives a key refresh enable and performs one round of reverse key transformation during the data decryption process. This allows the key to be refreshed back and forth within the same key register, saving unnecessary storage units.

[0019] Furthermore, the data selector includes an eighth data selector and a ninth data selector. The eighth data selector is connected to the key forward transformation module and the key inverse transformation module, and is used to receive the outputs of the key forward transformation module and the key inverse transformation module, and select the output of the key forward transformation module or the key inverse transformation module as the input of the ninth data selector according to the AES direction. The ninth data selector is connected to the eighth data selector and the bus interface module, and is used to receive the output of the eighth data selector and the initial key of the bus interface module, and select the output of the eighth selector or the initial key as the input of the key register according to the initial key configuration completion signal. The AES direction includes a data encryption direction and a data decryption direction.

[0020] Furthermore, the key processing module also includes a second OR gate, which is connected to the key pre-refresh control state machine module and the bus interface module. It is used to receive the initial key configuration completion signal from the bus interface module and the key pre-refresh completion interrupt signal output by the key pre-refresh control state machine module, and to perform an OR operation on the initial key configuration completion signal and the key pre-refresh completion interrupt signal to generate a key register write enable to control the writing of the key register.

[0021] Furthermore, the key pre-refresh control state machine module includes a state machine and a third counter; the state machine is used to control the third counter to count the number of pulses that enable key pre-refresh.

[0022] An AES operation method is provided, implemented through the AES operation circuit. The method includes: after acquiring the data to be encrypted or decrypted, the data encryption / decryption processing module encrypts or decrypts the data according to the AES direction using in-round pipeline technology; wherein, after each pipeline cycle, the data encryption / decryption processing module generates a key refresh enable, causing the key processing module to refresh the key and transmit it to the data encryption / decryption processing module for encryption / decryption; wherein the key processing module only stores the current key.

[0023] Compared with existing technologies, this technical solution implements the in-round loop of the AES algorithm through pipeline technology. That is, during the transformation of the current round, a partial transformation of the next round can be achieved, which reduces the number of clock cycles consumed by the AES encryption and decryption process and improves the efficiency of data encryption and decryption. In addition, since only the current key is stored, a large number of storage units are saved, which greatly reduces the area of ​​the AES operation circuit and helps to reduce costs.

[0024] Further, the in-round pipeline technology specifically includes: Step S1, according to the AES direction, the data encryption / decryption processing module performs a first round of XOR operation and a second round of S-box transformation / inverse S-box transformation and row shift transformation / inverse row shift transformation on the data to be encrypted / decrypted through the first-level encryption / decryption circuit; wherein, the AES direction includes the data encryption direction and the data decryption direction; the first round and the second round respectively represent the initial round and the intermediate round in the number of AES data encryption / decryption rounds; Step S2, the data encryption / decryption processing module performs a (N-1)th round of column hybrid transformation / inverse column hybrid transformation and XOR operation on the data output by the first-level encryption / decryption circuit through the second-level encryption / decryption circuit, and a Nth round of S-box transformation / inverse S-box transformation and row shift transformation / inverse row shift transformation; wherein, N represents the number of AES data encryption / decryption rounds, N is a positive integer and greater than 2, and the maximum value of N is determined by the key length; Step S3, the data encryption / decryption processing module performs an XOR operation on the data output by the second-level encryption / decryption circuit through the third-level encryption / decryption circuit, and then outputs the encrypted / decrypted data. This technical solution implements the AES algorithm through pipeline technology, which means that during the transformation of the current round, a partial transformation of the next round can be achieved, thus reducing the number of clock cycles consumed by the AES encryption and decryption process and improving the efficiency of data encryption and decryption.

[0025] Further, the method of step S1 specifically includes: Step S11, after the data encryption / decryption processing module receives the AES module enable, the first counter starts outputting the current sub-round number, then selects the number of bits of the first preset bit width corresponding to the data to be encrypted / decrypted and the current key for XOR operation, and then increments the current sub-round number by 1; wherein, the data to be encrypted / decrypted and the current key have the same data bit width, and are an integer multiple of the first preset bit width; Step S12, according to the AES direction, the data encryption / decryption processing module selects the number of bits of the first preset bit width corresponding to the data to be encrypted / decrypted and the current key for XOR operation, and simultaneously performs S-box transformation / inverse S-box transformation on the XOR operation result of the previous step, and then increments the current sub-round number by 1; Step S13, and so on, when the current sub-round number reaches a preset number, the data encryption / decryption processing module performs S-box transformation / inverse S-box transformation on the XOR operation result of the previous step according to the AES direction, and simultaneously performs row shift transformation / reverse row shift transformation on all the results after S-box transformation / inverse S-box transformation. This technical solution can perform XOR operations, S-box transformation / inverse S-box transformation, and row shift transformation / reverse row shift transformation on the data to be encrypted or decrypted in one round of pipeline, realizing the in-round loop of the AES algorithm and reducing the number of clock cycles consumed by the AES encryption and decryption process.

[0026] Furthermore, in step S13, before performing row shift / reverse row shift transformation on all data after S-box transformation / reverse S-box transformation according to the AES direction, the data encryption / decryption processing module transmits the result of each S-box transformation / reverse S-box transformation to the second register. When the current sub-round number reaches a preset number, the data encryption / decryption processing module transmits the result of the S-box transformation / reverse S-box transformation at this time, along with the result stored in the second register, to the third register for merging. Then, the merged data is transmitted to the row shift transformation module. This technical solution merges the data after S-box transformation / reverse S-box transformation, allowing the row shift transformation module to complete the row shift / reverse row shift transformation of the data in one go, reducing the number of clock cycles consumed by the AES encryption / decryption process.

[0027] Furthermore, when the current sub-round count reaches a preset number, the first counter generates a key refresh enable, which also causes the second counter to count the pipeline round count once. Then, the current sub-round count is reset to zero and recounted. After counting the preset number of times, all bits of the current key have been transformed, and generating a key refresh enable allows the current key to be refreshed. At the same time, recounting the current sub-round count to zero allows the corresponding module to correctly select the corresponding bits of the refreshed current key.

[0028] Further, the method of step S2 specifically includes: Step S21, based on the pipeline round number, the current sub-round number, and the AES direction, the data encryption / decryption processing module selects the number of bits corresponding to the first preset bit width in the result of the row shift transformation / reverse row shift transformation through the fourth data selector, performs column mixing transformation / reverse column mixing transformation, and then performs an XOR operation with the number of bits corresponding to the first preset bit width of the current key, and then increments the current sub-round number by 1; Step S22, the data encryption / decryption processing module selects the next corresponding number of bits of the first preset bit width in the result of the row shift transformation / reverse row shift transformation, performs column mixing transformation / reverse column mixing transformation, and then performs an XOR operation with the next corresponding number of bits of the first preset bit width of the current key, and simultaneously performs an XOR operation on the previous step's XOR operation. The calculation result undergoes S-box transformation / inverse S-box transformation, and then the current sub-round number is incremented by 1; Step S23, and so on, when the current sub-round number reaches a preset number, the data encryption and decryption processing module performs S-box transformation / inverse S-box transformation on the XOR operation result of the previous step according to the AES direction, and at the same time performs row shift transformation / reverse row shift transformation on all the results after S-box transformation / inverse S-box transformation; Step S24, after the first counter generates key refresh enable and the second counter counts the pipeline round number, the data encryption and decryption processing module resets the current sub-round number to zero and recounts, and then repeats steps S21 to S24 until the S-box transformation / inverse S-box transformation and row shift transformation / reverse row shift transformation of the Nth round are completed; where N is the maximum value. This technical solution can perform column hybrid transformation / inverse column hybrid transformation, XOR operation, S-box transformation / inverse S-box transformation, and row shift transformation / inverse row shift transformation on the data to be encrypted or decrypted in one round of pipeline, realizing the in-round loop of the AES algorithm and reducing the number of clock cycles consumed by the AES encryption and decryption process.

[0029] Furthermore, during the execution of step S2, if the AES direction is the data decryption direction, then before performing the XOR operation, the number of bits of the first preset bit width corresponding to the current key is first subjected to an inverse column mixing transformation.

[0030] Further, step S3 specifically includes: Step S31, based on the current sub-round number, the data encryption / decryption processing module selects the result of the row shift transformation / reverse row shift transformation and the number of bits corresponding to the first preset bit width of the current key through the fourth data selector, and performs an XOR operation, then increments the current sub-round number by 1; Step S32, and so on, after the data encryption / decryption processing module completes the XOR operation of the result of the row shift transformation / reverse row shift transformation and all bits of the current key, the first register outputs the encrypted / decrypted data. Since the previous stage circuit has already completed the S-box transformation / reverse S-box transformation and the row shift transformation / reverse row shift transformation, this technical solution only needs to implement the XOR operation, reducing the number of clock cycles consumed by the AES encryption / decryption process.

[0031] Furthermore, if the AES direction is the data encryption direction, the data encryption / decryption processing module receives the initial key as the current key, and after the first counter generates a key refresh enable, it receives the refreshed key as the current key, until the initial key is refreshed to the final key; if the AES direction is the data decryption direction, the data encryption / decryption processing module receives the final key as the current key, and after the first counter generates a key refresh enable, it receives the refreshed key as the current key, until the final key is refreshed to the initial key.

[0032] Furthermore, if the AES direction is for data encryption, the key processing module performs a forward key transformation, which means sequentially refreshing the initial key in the key register to the final key. If the AES direction is for data decryption, the key processing module performs a reverse key transformation, which means sequentially refreshing the final key in the key register to the initial key. Based on these forward and reverse key transformations, the key can be refreshed back and forth within the same key register, saving unnecessary storage units.

[0033] Furthermore, before the data encryption or decryption process begins, the key processing module updates the key in the key register to the initial key based on the AES module enable signal and the initial key configuration completion signal.

[0034] Furthermore, if the AES direction is the data decryption direction, then after refreshing the key in the key register to the initial key, the key processing module performs key pre-refresh according to the key pre-refresh enable; the key pre-refresh refers to performing a positive transformation on the key in the key register before the data decryption process, updating the key in the key register to the final key. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the AES data encryption and decryption process in existing technologies.

[0036] Figure 2 This is an embodiment of the AES operation circuit described in the present invention.

[0037] Figure 3 This is a data encryption / decryption processing module according to one embodiment of the present invention.

[0038] Figure 4 This is a key processing module according to one embodiment of the present invention.

[0039] Figure 5 This is a flowchart of a key processing method according to an embodiment of the present invention.

[0040] Figure 6 This is a flowchart of a data encryption / decryption processing method according to an embodiment of the present invention.

[0041] Figure 7 This is a data encryption pipeline design according to one embodiment of the present invention.

[0042] Figure 8 This is a data decryption pipeline design according to one embodiment of the present invention. Detailed Implementation

[0043] The technical solutions of the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. To further illustrate the embodiments, the present invention provides accompanying drawings. These drawings are part of the disclosure of the present invention, mainly used to illustrate the embodiments, and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments.

[0044] Unless otherwise defined, the technical or scientific terms used in this invention should be understood in their ordinary sense by one of ordinary skill in the art to which this application pertains. The terms "a," "an," "the," etc., used in this application do not indicate quantity limitation and may represent singular or plural. The terms "comprising," "including," "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion, such as: a process, method, system product, or device that includes a series of steps or modules is not limited to the listed steps or units, but may also include steps or modules not listed, or may also include other steps or units inherent to these processes, methods, products, or devices. The terms "first," "second," "third," etc., used in this application are merely used to distinguish similar correspondences and do not represent a specific ordering of objects.

[0045] In existing technologies, the AES data encryption and decryption process is as follows: Figure 1 As shown. Taking AES data encryption and decryption with 128-bit data and a 128-bit key as an example, the encryption process ( Figure 1 The left side shows the process from plain text to cipher text and the decryption process. Figure 1 The process from cipher text to plain text on the right side requires 11 rounds of data processing (round 0 to round 10).

[0046] During the encryption process, round 0 (called the initial round or first round) performs an XOR operation between the input data to be encrypted and the initial key KEY0. Rounds 1 through 9 are called intermediate rounds, totaling nine rounds. Each intermediate round performs four operations on the data processed in the previous round: SBOX transformation, SHIFT ROWS transformation, MIX COLUMNS transformation, and an XOR operation with the intermediate keys KEY1 through KEY9 respectively. Round 10 is called the final round, which performs an SBOX transformation, a SHIFT ROWS transformation, and an XOR operation with the final key KEY10 on the data processed in round 9. After round 10, the data encryption process ends.

[0047] During the decryption process, round 0 performs an XOR operation between the input data to be decrypted and the final key KEY10. In each intermediate round from round 1 to round 9, four operations are performed on the data processed in the previous round: INV SBOX transformation (inverse S-box transformation), INV SHIFT ROWS transformation (inverse row shift transformation), INV MIX COLUMNS transformation (inverse column hybrid transformation), and XOR operations with the intermediate keys INV_MIX_COLUMNS (KEY9~KEY1) after the INV MIX COLUMNS transformation. Round 10 performs INV SBOX transformation, INV SHIFT ROWS transformation, and XOR operations with the initial key KEY0 on the data processed in round 9. After round 10, the data decryption process ends.

[0048] Figure 1 The existing AES data encryption and decryption methods shown strictly follow the order of round transformations, making it impossible to segment operations within a round. This results in the encryption and decryption process requiring a large number of clock cycles, leading to low efficiency. Furthermore, the existing AES data encryption and decryption circuits use modules with a large data processing bit width, resulting in a large circuit area and increased costs. In addition, the existing AES key processing circuits store each key in a storage unit after each key refresh, requiring a large number of storage units, which also increases costs.

[0049] Therefore, embodiments of the present invention provide an AES operation circuit optimized in terms of circuit area and data encryption / decryption process, such as... Figure 2As shown, the computing circuit includes: a bus interface module for data interaction between the master and slave devices; a FIFO module connected to the bus interface module for data buffering; a data flow control module connected to the FIFO module and the data encryption / decryption processing module for controlling data interaction between the FIFO module and the data encryption / decryption processing module; a data encryption / decryption processing module connected to the data flow control module for implementing data encryption / decryption through in-wheel pipeline technology; and a key processing module connected to the bus interface module and the data encryption / decryption processing module for providing the current key to the data encryption / decryption processing module; wherein, the key processing module only stores the current key.

[0050] In one implementation, the FIFO module includes an input buffer FIFO module and an output buffer FIFO module. The input buffer FIFO module is used to buffer data to be encrypted or decrypted transmitted from the host by the bus interface module; the output buffer FIFO module is used to buffer encrypted or decrypted data transmitted from the data encryption / decryption processing module.

[0051] In one embodiment, the data encryption / decryption processing module includes: a first counter, a second counter, a first-level encryption / decryption circuit, a second-level encryption / decryption circuit, and a third-level encryption / decryption circuit.

[0052] like Figure 3 As shown, the first counter is used to count the number of clock cycles during the data encryption and decryption process and output the current sub-round number. After counting a preset number of times, the current sub-round number is reset to zero and the count restarts. It should be noted that the first counter counts the number of clock cycles once each time it receives an AES module enable signal configured by the CPU (or host), and after counting a preset number of times, it generates a key refresh enable signal and outputs it to... Figure 2 In the key processing module shown, the current key is refreshed, and then the current sub-round count is reset to zero and restarted. The current sub-round count indicates the current time point of the circuit in the current pipeline round, ensuring that the data selector, using the current sub-round count as the strobe signal, can correctly select the corresponding number of bits for the current key and / or the data to be encrypted / decrypted at that time. After the first counter counts a preset number of times, since all bits of the current key have been used in the calculation, the current sub-round count is reset to zero so that it can function again after the current key is refreshed.

[0053] like Figure 3As shown, the second counter, connected to the first counter, receives the current sub-round number output by the first counter and is used to count the number of pipeline rounds based on the current sub-round number. It should be noted that the second counter counts the number of pipeline rounds once for every preset number of current sub-round numbers received. The meaning of the pipeline round number differs from that of the traditional AES data encryption / decryption round number. For example, the first round of a traditional AES data encryption / decryption round only performs an XOR operation, while the first round of the pipeline in this invention not only performs the first round of the traditional AES data encryption / decryption round but also implements the S-box transformation / inverse S-box transformation and row shift transformation / inverse row shift transformation of the traditional AES data encryption / decryption round. That is, each pipeline round (except the last round) involves the operations of two rounds in the traditional AES data encryption / decryption method. The current sub-round number is a subdivision of a pipeline round; this invention plans corresponding data encryption / decryption operations for each clock cycle in a pipeline round. Additionally, when the number of pipeline rounds reaches its maximum value of N and the total number of clock cycles reaches a preset value, the second counter generates a valid encrypted / decrypted data flag signal and transmits it to... Figure 2 The data flow control module shown allows encrypted and decrypted data to be transmitted through the data flow control module.

[0054] As a preferred implementation, this invention employs a 32-bit XOR operation module, an S-box transformation module, and a column hybrid transformation module. Compared to traditional AES data encryption and decryption circuits, this invention eliminates the need for two 32-bit processing modules to form a 64-bit processing module, significantly reducing circuit area, which helps control costs and improves market competitiveness.

[0055] like Figure 3 As shown, the first-stage encryption / decryption circuit, connected to the second counter, is used to perform a first-round XOR operation on the data to be encrypted / decrypted based on the pipeline round number, the current sub-round number, and the AES direction, as well as a second-round S-box transformation / inverse S-box transformation and row shift transformation / reverse row shift transformation. The AES direction includes a data encryption direction and a data decryption direction. The first round and the second round represent the initial round and intermediate round in the AES data encryption / decryption rounds, respectively. It should be noted that the first-stage encryption / decryption circuit is used to implement the first round of pipelined operations. If the CPU is configured with the data encryption direction, it can be used to implement data encryption; if the CPU is configured with the data decryption direction, it can be used to implement data decryption.

[0056] The first-level encryption / decryption circuit includes:

[0057] The first data selector is used to select the corresponding number of bits in the data to be encrypted / decrypted and the corresponding number of bits in the current key according to the current sub-round number, and outputs the result to the first XOR operation module. Taking the AES data encryption / decryption process with 128 bits of data to be encrypted / decrypted and a 128-bit key as an example, since the main operation module of this invention uses a 32-bit data processing width, the 128 bits of data to be encrypted / decrypted and the current key need to be processed in four steps. The aforementioned current sub-round number is used to select the corresponding bits of the data to be encrypted / decrypted and the current key for operation. Specifically: when the current sub-round number is 0 (i.e., the first sub-round), the first data selector selects the [31:0] bits of the data to be encrypted / decrypted and the current key for XOR operation; when the current sub-round number is 1, it selects the [63:32] bits of the data to be encrypted / decrypted and the current key for XOR operation; when the current sub-round number is 2, it selects the [95:64] bits of the data to be encrypted / decrypted and the current key for XOR operation; when the current sub-round number is 3, it selects the [127:96] bits of the data to be encrypted / decrypted and the current key for XOR operation.

[0058] The first XOR operation module, connected to the first data selector, is used to perform an XOR operation on the corresponding number of bits in the data to be encrypted / decrypted and the corresponding number of bits in the current key.

[0059] The second data selector, connected to the second counter, is used to select the XOR operation result of the corresponding pipeline round number and output it to the first register. If the strobe signal is the first pipeline round, the result of the first XOR operation module is selected.

[0060] The first register, connected to the second data selector, is used to store the data selected by the second data selector. It should be noted that if the number of pipeline rounds reaches the maximum value of N and the total number of clock cycles reaches a preset value, it indicates that data encryption / decryption is complete. In this case, the first register will output the received data as encrypted / decrypted data. Otherwise, the first register will temporarily store the received data until it is read by the next module. The storage capacity of the first register is 128 bits, which is the same as the length of the data to be encrypted / decrypted.

[0061] The third data selector, connected to the first register, is used to select the corresponding bit of the XOR operation result in the first register according to the current sub-round number, and then transmit it to the S-box transformation module. Specifically, when the current sub-round number is 1 (the second sub-round), the [63:32] bits of the data to be encrypted / decrypted and the current key are undergoing an XOR operation, while the first register already stores the XOR operation result of the [31:0] bits of the data to be encrypted / decrypted and the current key. Therefore, when the current sub-round number is 1, the XOR operation result of the [31:0] bits when the current sub-round number is 0 is transmitted to the S-box transformation module for calculation. This process continues, with the S-box transformation / inverse S-box transformation of the previous sub-round occurring simultaneously during the XOR operation of the current sub-round.

[0062] The S-box transformation module, connected to the third data selector, performs S-box transformation / inverse S-box transformation on the data output by the third data selector according to the AES direction. If the AES direction is the data encryption direction, the S-box transformation is performed; if the AES direction is the data decryption direction, the inverse S-box transformation is performed.

[0063] A data merging module, connected to the S-box conversion module, is used to merge the data output by the S-box conversion module. The data merging module includes a second register and a third register, with the second register having a smaller storage space than the third register. The second register is 96 bits long and connected to the S-box conversion module, used to store the first 96 bits of data output by the S-box conversion module. The third register is 128 bits long and connected to both the S-box conversion module and the second register, used to receive the last 32 bits of data output by the S-box conversion module, as well as the data in the first register, and then merge all the data into a complete 128 bits. It is important to note that the data merging operation does not occupy any single clock cycle; after the S-box conversion module completes its data calculation, it transmits the data to the data merging module in real time.

[0064] The row shift transformation module, connected to the data merging module, is used to perform row shift transformation / reverse row shift transformation on the merged data according to the AES direction. The data processing bit width of the row shift transformation module is 128 bits. If the AES direction is the data encryption direction, a row shift transformation is performed; if the AES direction is the data decryption direction, a reverse row shift transformation is performed. It should be noted that when the current sub-round number is 4 (the 5th sub-round), the S-box transformation module is performing the final [127:96] bit calculation. In this sub-round, after the S-box transformation module completes the calculation, the data merging module merges the data in real time and then transmits it to the row shift transformation module to complete the row shift transformation / reverse row shift transformation. At this time, that is, in the 5th sub-round, the first-level encryption / decryption circuit completes the first pipeline round, the second counter increments the pipeline round number by 1, the first counter outputs the key refresh enable so that the key processing module refreshes the current key, and at the same time, the current sub-round number is reset to zero and recounted.

[0065] The fourth data selector, connected to the row shift transformation module, is used to select the corresponding number of bits in the transformation result from the row shift transformation module according to the current sub-round number and output it to the next stage circuit. The fourth data selector acts as a connection module for the next stage circuit; specifically, it acts as a connection module between the upper and lower pipelines, transmitting the result of the previous pipeline to the next pipeline for calculation. It should be noted that the current sub-round number is now zero.

[0066] like Figure 3 As shown, the second-stage encryption / decryption circuit, connected to the second counter and the first-stage encryption / decryption circuit, performs the following operations on the data output from the first-stage encryption / decryption circuit: N-1 round of column-mixing transformation / inverse column-mixing transformation and XOR operation; and N-round of S-box transformation / inverse S-box transformation and row-shift transformation / inverse row-shift transformation. Here, N represents the number of AES data encryption / decryption rounds, is a positive integer greater than 2, and its maximum value is determined by the key length. It is important to emphasize that N represents the number of rounds in the traditional AES data encryption / decryption method. When the key length is 128 bits, the maximum value of N is 11, meaning that data encryption and decryption require 11 rounds of transformation to complete. It should be noted that the second-stage encryption / decryption circuit is used to implement the pipeline from rounds 2 to 10, and can also perform both data encryption and decryption processes.

[0067] The second-level encryption / decryption circuit includes:

[0068] The column hybrid transformation module, connected to the fourth data selector, is used to perform column hybrid transformation / inverse column hybrid transformation on the corresponding number of bits of the transformation result in the row shift transformation module according to the AES direction.

[0069] The fifth data selector is used to select the corresponding number of bits for the current key based on the current sub-round number. It's important to note that the current key has been refreshed to the key from the second round of the sequence.

[0070] The key inverse mixing transformation module, connected to the fifth data selector, is used to perform an inverse mixing transformation on the corresponding bits of the current key output by the fifth data selector during data decryption. This module only functions during the data decryption process.

[0071] The sixth data selector, connected to the fifth data selector and the key inverse hybrid transformation module, is used to select the data output by the fifth data selector or the key inverse hybrid transformation module according to the AES direction and transmit it to the second XOR operation module. If the AES direction is the data encryption direction, the current key output by the fifth data selector is selected; if the AES direction is the data decryption direction, the transformed current key output by the key inverse hybrid transformation module is selected.

[0072] The second XOR operation module, connected to the sixth data selector and the column mixing transformation module, is used to perform XOR operations on the data output by the column mixing transformation module and the sixth data selector. This XOR operation module performs a sequential XOR operation from round 2 to round 10; that is, when the selection signal of the second data selector is 2-10, the data encryption / decryption processing module will select the second-level encryption / decryption circuit to execute the data encryption / decryption process.

[0073] It should be noted that the second-level encryption / decryption circuit also includes a second data selector, a first register, a third data selector, an S-box transformation module, a data merging module, a row shift transformation module, and a fourth data selector. The functions of these modules are consistent with those described in the first-level encryption / decryption circuit.

[0074] like Figure 3 As shown, the third-level encryption / decryption circuit, connected to the second counter and the second-level encryption / decryption circuit, performs an XOR operation on the data output by the second-level encryption / decryption circuit based on the pipeline round number and the current sub-round number, and then outputs the encrypted / decrypted data. The third-level encryption / decryption circuit is used to implement the final pipeline round; when N reaches its maximum value, the data encryption / decryption processing module switches from the second-level encryption / decryption circuit to the third-level encryption / decryption circuit.

[0075] The third-level encryption / decryption circuit includes:

[0076] The seventh data selector is used to select the corresponding number of bits in the current key based on the current sub-round number. At this point, the current key is the final key.

[0077] The third XOR operation module, connected to the seventh and fourth data selectors, performs an XOR operation between the corresponding bits of the transformation result from the row shift transformation module and the corresponding bits of the current key. In the final pipeline, no other operations are performed besides the XOR operation; therefore, the result of each XOR operation is stored in the first register. When all data has undergone the XOR operation, indicating that encryption and decryption have been completed, the first register outputs the data to the data flow control module, which then transmits it to the host via the bus interface module.

[0078] It should be noted that the third-level encryption / decryption circuit also includes the second data selector and the first register. The functions of the above modules are consistent with those described in the first-level encryption / decryption circuit. Specifically, the second data selector is connected to the first XOR operation module, the second XOR operation module, and the third XOR operation module, respectively.

[0079] Compared with existing technologies, the data encryption / decryption processing module described in this embodiment of the invention implements the AES algorithm's in-round loop through pipeline technology. This means that during the transformation process of the current round, a partial transformation of the next round can be performed, resulting in fewer clock cycles consumed in the AES encryption / decryption process and improved data encryption / decryption efficiency. Furthermore, this module uses a 32-bit XOR operation module, an S-box transformation module, and a column hybrid transformation module instead of a 64-bit module (which requires two 32-bit blocks), significantly reducing the area of ​​the data encryption / decryption processing module, which helps control costs and improves market competitiveness.

[0080] As one implementation method, such as Figure 4 As shown, the key processing circuit includes:

[0081] The key pre-refresh control state machine module is used to generate a key pre-refresh enable signal to control the key transformation module to perform key pre-refresh, and to output a key pre-refresh completion interrupt signal after the key pre-refresh is completed. The key pre-refresh control state machine module consists of a state machine and a counter. The state machine is a commonly used control center in digital circuits to perform specific operations, and it contains three states:

[0082] S0: Wait for the arrival of the pre-refresh signal configured by the CPU, and jump to S1 after the signal arrives;

[0083] S1: Send the key pre-refresh enable signal and control the third counter to count the number of pulses. When the number of key pre-refresh enable pulses reaches the preset value (taking the AES process with a data width of 128 bits and a key length of 128 bits as an example, 10 key pre-refresh enable pulses are required), stop sending the key pre-refresh enable signal and jump to S2;

[0084] S2: Issue a key pre-refresh completion interrupt signal, clear the count value of the third counter, and return to the S0 state. It should be noted that the key in the key register at this time is the final key, and the CPU input key pre-refresh start signal will only be received when the AES direction is configured as the data decryption direction.

[0085] The first OR gate, connected to the key pre-refresh control state machine module, performs an OR operation on the key pre-refresh enable and key refresh enable. The key refresh enable originates from the data encryption / decryption processing module, while the key pre-refresh enable originates from the key pre-refresh control state machine module.

[0086] The key transformation module includes a forward key transformation module and a reverse key transformation module. The forward key transformation module, connected to a first OR gate, receives a key pre-refresh enable or a key refresh enable and performs one round of forward key transformation during data encryption and key pre-refresh. The reverse key transformation module receives a key refresh enable and performs one round of reverse key transformation during data decryption. Both the forward and reverse key transformation modules consist of an S-box transformation module, an XOR operation module, and an rcon parameter transformation module. These modules are used to implement key operations and are existing technologies.

[0087] The data selector includes an eighth data selector and a ninth data selector. The eighth data selector is connected to the key forward transformation module and the key inverse transformation module. It receives the outputs of the key forward transformation module and the key inverse transformation module, and then selects the output of either the key forward transformation module or the key inverse transformation module as the input of the ninth data selector, depending on the AES direction. The ninth data selector is connected to the eighth data selector and receives the output of the eighth data selector and the initial key configured by the CPU. Then, based on the initial key configuration completion signal, it selects the output of the eighth selector or the initial key as the input of the key register. The AES direction includes a data encryption direction and a data decryption direction. Both the initial key and the initial key configuration completion signal are configured by the CPU. After the CPU configures the initial key, it generates an initial key configuration completion signal and notifies the key processing module to perform the corresponding operation via the bus interface module.

[0088] The key register, connected to the ninth data selector, stores the current key. Each time a refreshed key is obtained, the key register transmits it to the data encryption / decryption processing module for encryption or decryption. Additionally, the key forward transformation module and the key reverse transformation module also read the current key from the key register when they need to refresh the key.

[0089] The second OR gate, connected to the key pre-refresh control state machine module, receives the initial key configuration completion signal from the CPU and the key pre-refresh completion interrupt signal output by the key pre-refresh control state machine module. It then performs an OR operation on these two signals to generate a key register write enable, which controls the writing of the key register. When the second OR gate receives the initial key configuration completion signal, the key register write enable controls the key register to write the initial key configured by the CPU. When the second OR gate receives the key pre-refresh completion interrupt signal, the key register write enable controls the key register to write the final key output by the key forward transformation module.

[0090] Compared with existing technologies, this key processing module uses a key transformation module to refresh the key required in the encryption and decryption process, and updates the key in the key register with the refreshed key. Since only the current key is stored, a large number of storage units are saved, which greatly reduces the area of ​​the key processing module and helps to reduce costs.

[0091] This invention provides an AES operation method, implemented through the aforementioned AES operation circuit. The method includes: after acquiring the data to be encrypted or decrypted, the data encryption / decryption processing module encrypts or decrypts the data according to the AES direction using in-round pipeline technology; wherein, after each pipeline cycle, the data encryption / decryption processing module generates a key refresh enable, causing the key processing module to refresh the key and transmit it to the data encryption / decryption processing module for encryption / decryption; wherein, the key processing module only stores the current key.

[0092] Reference Figure 2 After the host transmits the data to be encrypted / decrypted to the bus interface module, it is buffered in the input buffer FIFO module and then transmitted to the data encryption / decryption processing module via the data flow control module for encryption / decryption. During this process, after each pipeline cycle, the data encryption / decryption processing module generates a key refresh enable, causing the key processing module to refresh the key required for the encryption / decryption process. After all pipeline cycles are completed, the data flow control module sends the encrypted / decrypted data to the output buffer FIFO module, and then the bus interface module transmits it back to the host. In addition to transmitting the encrypted / decrypted data, the bus interface module is also responsible for transmitting basic host configuration signals, including AES module enable, AES direction, initial key, initial key configuration complete signal, and key pre-refresh start signal. The above process is the basic flow of AES data encryption / decryption. The working methods of the key processing module and the data encryption / decryption processing module are described in detail below.

[0093] Since the data encryption and decryption process requires a key, the key processing method will be introduced first. (Refer to...) Figure 5This invention provides a key processing method, which includes: during data encryption or decryption, a key processing module refreshes the key in one round and updates the key in the key register with the key after each refresh, until the key refresh count reaches a preset number; wherein, the key register only stores the current key.

[0094] It should be noted that a refresh round refers to one round of forward key transformation or one round of reverse key transformation. Taking the AES encryption / decryption process with a data width of 128 bits and a key length of 128 bits as an example, encryption or decryption requires 10 key transformations from pipeline round 0 to pipeline round 10, resulting in 11 sets of keys from key0 to key10. Key0 is called the initial key, and key10 is called the final key. Assuming that encryption or decryption is currently in pipeline round 3, then key3 is called the current key, and this current key is stored in the key register. In this example, one round of key transformation (one round of forward key transformation or one round of reverse key transformation) includes 10 key transformations, and the following explanation will also use this as an example.

[0095] Before the data encryption or decryption process begins, the key processing module determines the AES module's operation based on the AES module's enable (AES operation circuit's enable). Figure 4 (Not shown in the image) and the initial key configuration completion signal, the key processing module updates the key in the key register to the initial key key0. The initial key key0 is directly configured by the CPU. When the AES module is enabled and the initial key configuration completion signal arrives, the key processing module updates the key in the key register to the initial key value key0.

[0096] After completing the preparations for encryption and decryption, the key processing module needs to determine whether an encryption or decryption process is currently underway to execute the corresponding method. If the AES direction of the key processing module is configured for data encryption, a forward key transformation is performed on the key, dynamically refreshing the value of the key register. The forward key transformation refers to sequentially refreshing the initial key to the final key, i.e., from key0 to key1, then to key2, and finally to key10. If the AES direction of the key processing module is configured for data decryption, a reverse key transformation is performed on the key, i.e., sequentially refreshing the final key to the initial key, i.e., from key10 to key9, then to key8, and finally to key0.

[0097] The transformation method of the key forward transformation is as follows:

[0098] w0_nxt = sbox[rot(w3)] ^ w0 ^ rcon;

[0099] w1_nxt = w1 ^ w0_nxt;

[0100] w2_nxt = w2 ^ w1_nxt;

[0101] w3_nxt = w3 ^ w2_nxt;

[0102] Among them, w0, w1, w2 and w3 form the key before the positive transformation. As mentioned above, each key from key0 to key10 is 128 bits of data, so w0, w1, w2 and w3 are all 32 bits, and w0[31:0]=key[127:96], w1[31:0]=key[95:64], w2[31:0]=key[63:32], w3[31:0]=key[31:0];

[0103] The sbox operation uses either a lookup table method or a transformation method; preferably, in this embodiment, the transformation method is used.

[0104] rot(w3) represents swapping the high 8 bits and low 24 bits of w3, i.e., rot(w3) = {w3[23:0], w3[31:24]};

[0105] The ^ symbol represents the XOR operation;

[0106] rcon is a variable parameter used to generate w0_nxt. The AES specification stipulates that 10 forward transformations are required during the encryption process, and rcon is as follows: 32'h100_0000, 32'h200_0000, 32'h400_0000, 32'h800_0000, 32'h1000_0000, 32'h2000_0000, 32'h4000_0000, 32'h8000_0000, 32'h1b00_0000, 32'h3600_0000;

[0107] w0_nxt, w1_nxt, w2_nxt and w3_nxt form the key key_nxt after the positive transformation, and w0_nxt[31:0]=key_nxt[127:96], w1_nxt[31:0]=key_nxt[95:64], w2_nxt[31:0]=key_nxt[63:32], w3_nxt[31:0]=key_nxt[31:0].

[0108] The inverse transform method is as follows:

[0109] w0_nxt = sbox[rot(w3 ^ w2)] ^ w0 ^ rcon;

[0110] w1_nxt = w1 ^ w0;

[0111] w2_nxt = w2 ^ w1;

[0112] w3_nxt = w3 ^ w2;

[0113] Among them, w0, w1, w2 and w3 form the key before the inverse transformation;

[0114] rcon is a variable parameter used to generate w0_nxt. The AES specification stipulates that 10 inverse transformations are required during the decryption process, and rcon is as follows: 32'h3600_0000, 32'h1b00_0000, 32'h8000_0000, 32'h4000_0000, 32'h2000_0000, 32'h1000_0000, 32'h1000_0000, 32'h400_0000, 32'h200_0000, 32'h100_0000.

[0115] By transforming the key in both directions, the key can be refreshed back and forth within the same key register, saving unnecessary storage units. The size of the key register is equal to the size of a single key; in this embodiment, the key register is 128 bits. It should be noted that after each key refresh, the key register transmits the latest key to the data encryption / decryption processing module for data encryption or decryption, and then waits for the key refresh enable function of the data encryption / decryption processing module to continue refreshing the key again, until the preset number of key refreshes is reached. The number of key refreshes is obtained by counting the key refresh enable by the third counter of the key pre-refresh control state machine module.

[0116] It should be noted that if the AES direction of the key processing module is configured for data decryption, after refreshing the key in the key register to the initial key, the key processing module performs key pre-refresh according to the key pre-refresh enable signal. Key pre-refresh refers to performing a forward transformation on the key before data decryption, updating the key in the key register to the final key; otherwise, the so-called inverse key transformation cannot be achieved. Preferably, during key pre-refresh, after completing a full forward transformation, the key in the key register is directly updated to the final key, without updating the key in the intermediate process. When the AES direction of the key processing module is configured for data encryption, key pre-refresh is not required.

[0117] During a key transformation round, the key is refreshed only when key refresh is enabled. For encryption, the key register is updated with the key after a forward transformation; for decryption, it is updated with the key after a reverse transformation. After each key transformation, it checks if the current refresh count has reached a preset number (e.g., 10 when the key length is 128 bits). If the preset number has been reached, it indicates that a complete round of data encryption or decryption and a complete round of forward or reverse key transformation have been completed, and the system returns to wait for the CPU to configure the initial key. If the current key refresh count has not reached the preset number, it waits for the key refresh enable from the data encryption / decryption processing module.

[0118] Compared with existing technologies, this AES key processing method only stores the current key during a key refresh process, thereby saving a large number of storage units and greatly reducing the area of ​​the key processing module, which helps to reduce costs.

[0119] Based on the above key processing method, embodiments of the present invention provide a data encryption and decryption processing method, such as... Figure 6 As shown, the method includes:

[0120] Step S1: According to the AES direction, the data encryption and decryption processing module performs a first round of XOR operation and a second round of S-box transformation / inverse S-box transformation and row shift transformation / inverse row shift transformation on the data to be encrypted and decrypted through the first-level encryption and decryption circuit; wherein, the AES direction includes the data encryption direction and the data decryption direction; the first round and the second round respectively represent the initial round and the intermediate round in the number of AES data encryption and decryption rounds.

[0121] As one implementation method, step S1 specifically includes:

[0122] In step S11, after the data encryption / decryption processing module receives the AES module enable, it causes the first counter to start outputting the current sub-round number. Then, it performs an XOR operation on the number of bits corresponding to the first preset bit width of the data to be encrypted / decrypted and the current key, and then increments the current sub-round number by 1. The data to be encrypted / decrypted and the current key have the same data bit width, which is an integer multiple of the first preset bit width. Taking the AES data encryption / decryption process with 128 bits of data to be encrypted / decrypted and a 128-bit key as an example, since the main processing module of this invention uses a 32-bit data processing bit width, the 128-bit data to be encrypted / decrypted and the current key need to be processed in four steps, meaning the first preset bit width is 32 bits.

[0123] Reference Figure 7The AES data encryption pipeline design, with a key length of 128 bits, requires 54 clock cycles (t0-t53) to complete data encryption, comprising 11 pipeline rounds (round0-round10). Each pipeline round (round0-round9) consumes 5 clock cycles, and round10 consumes 4 clock cycles. The first-stage encryption / decryption circuit executes the first pipeline round (round0).

[0124] Step S11 corresponds to time t0 (at which point the current sub-round number is 0, indicating the first sub-round of pipeline round 0). The [31:0] bits of the data to be encrypted are XORed with the [31:0] bits of the initial key. Then, the first counter counts once, and the current sub-round number becomes 1. The initial key, KEY0, is directly configured by the CPU.

[0125] In step S12, according to the AES direction, the data encryption and decryption processing module selects the number of bits of the first preset bit width corresponding to the data to be encrypted and decrypted and the current key to perform an XOR operation. At the same time, the XOR operation result of the previous step is subjected to S-box transformation / inverse S-box transformation, and then the current sub-round number is incremented by 1.

[0126] Reference Figure 7 Step S12 corresponds to time t1, where the [63:32] bits of the data to be encrypted are XORed with the [63:32] bits of the initial key, and the XOR result at time t0 is transformed by an S-box, and then the current sub-round number becomes 2.

[0127] Step S13, and so on, when the current sub-round number reaches the preset number of times, the data encryption and decryption processing module performs S-box transformation / inverse S-box transformation on the XOR operation result of the previous step according to the AES direction, and at the same time performs row shift transformation / reverse row shift transformation on all the results after S-box transformation / inverse S-box transformation.

[0128] Reference Figure 7 At time t2, the [95:64] bits of the data to be encrypted are XORed with the [95:64] bits of the initial key, and the XOR result at time t1 is subjected to an S-box transformation. Then the current sub-round number becomes 3.

[0129] At time t3, the [127:96] bits of the data to be encrypted are XORed with the [127:96] bits of the initial key, and the XOR result at time t2 is transformed by an S-box. Then the number of the current sub-round becomes 4.

[0130] At time t4, the XOR operation result of t3 is subjected to an S-box transformation, and the S-box transformation results from t1 to t4 are subjected to a row shift transformation. At this time, the first pipeline round 0 ends, the first counter generates a key refresh enable to refresh the initial key KEY0 as the intermediate key KEY1, and the second counter counts the pipeline round number once, entering the second pipeline round 1, and then the current sub-round number is reset to zero and recounted. After the pipeline round 0 ends, that is, after time t4, the traditional AES data encryption process round 0 (the XOR operation between the data to be encrypted and the initial key) is completed, as are the S-box transformation and row shift transformation in round 1.

[0131] In one implementation, step S13, before performing row shift transformation / reverse row shift transformation on all S-box transformed / inverse S-box transformed data according to the AES direction, further includes: the data encryption / decryption processing module transmits the result of each S-box transformed / inverse S-box transformed data to the second register; when the current sub-round number reaches a preset number, the data encryption / decryption processing module transmits the result of the S-box transformed / inverse S-box transformed data at this time and the result stored in the second register together to the third register for merging, and then transmits the merged data to the row shift transformation module.

[0132] Step S2: The data encryption / decryption processing module performs the (N-1)th round of column hybrid transformation / inverse column hybrid transformation and XOR operation, as well as the Nth round of S-box transformation / inverse S-box transformation and row shift transformation / inverse row shift transformation on the data output by the first-level encryption / decryption circuit through the second-level encryption / decryption circuit; where N represents the number of AES data encryption / decryption rounds, N is a positive integer and greater than 2, and the maximum value of N is determined by the key length.

[0133] As one implementation method, step S2 specifically includes:

[0134] Step S21: Based on the pipeline round number, the current sub-round number, and the AES direction, the data encryption / decryption processing module selects the number of bits corresponding to the first preset bit width in the result of the row shift transformation / reverse row shift transformation through the fourth data selector, performs column mixing transformation / reverse column mixing transformation, and then performs an XOR operation with the number of bits corresponding to the first preset bit width of the current key. Subsequently, the current sub-round number is incremented by 1.

[0135] Reference Figure 7Step S21 corresponds to time t5 (at this time, the current number of child rounds is 0, indicating the first child round of pipeline round 1). The [31:0] bits of the row shift transformation result at time t4 are subjected to column mixing transformation, and then XORed with the [31:0] bits of the intermediate key KEY1. Then the current number of child rounds becomes 1.

[0136] In step S22, the data encryption / decryption processing module selects the number of bits of the first preset bit width corresponding to the next row shift transformation / inverse row shift transformation result, performs column hybrid transformation / inverse column hybrid transformation, and then performs an XOR operation with the number of bits of the first preset bit width corresponding to the current key. At the same time, it performs S-box transformation / inverse S-box transformation on the XOR operation result of the previous step, and then increments the current sub-round number by 1.

[0137] Reference Figure 7 Step S22 corresponds to time t6. The [63:32] bits of the row shift transformation result at time t4 are subjected to column mixing transformation, and then XORed with the [63:32] bits of the intermediate key KEY1. The XOR result at time t5 is subjected to S-box transformation, and then the current sub-round number becomes 2.

[0138] Step S23, and so on, when the current sub-round number reaches the preset number of times, the data encryption and decryption processing module performs S-box transformation / inverse S-box transformation on the XOR operation result of the previous step according to the AES direction, and at the same time performs row shift transformation / reverse row shift transformation on all the results after S-box transformation / inverse S-box transformation.

[0139] Reference Figure 7 At time t7, the [95:64] bits of the row shift transformation result at time t4 are subjected to column mixing transformation, and then XORed with the [95:64] bits of the intermediate key KEY1. The XOR result at time t6 is subjected to S-box transformation, and then the current sub-round number becomes 3.

[0140] At time t8, perform column mixing transformation on the [127:96] bits of the row shift transformation result at time t4, then perform XOR operation with the [127:96] bits of the intermediate key KEY1, and perform S-box transformation on the XOR operation result at time t7. Then the current sub-round number becomes 4.

[0141] At time t9, the XOR result from time t8 undergoes an S-box transformation, and the S-box transformation results from time t6 to t9 undergo a row shift transformation. At this point, the second pipeline round 1 ends. The first counter generates a key refresh enable, using the refreshed intermediate key KEY1 as the intermediate key KEY2. Simultaneously, the second counter counts the pipeline round number once, entering the third pipeline round 2. Then, the current sub-round number is reset to zero and recounted. After pipeline round 1 ends, i.e., after time t9, the column mixing transformation and XOR operation of round 1 in the traditional AES data encryption process are completed, as are the S-box transformation and row shift transformation in round 2.

[0142] Step S24: After the first counter generates a key refresh enable and the second counter counts the pipeline rounds, the data encryption / decryption processing module resets the current sub-round count to zero and recounts. Then, steps S21 to S24 are repeated until the Nth round of S-box transformation / inverse S-box transformation and row shift transformation / inverse row shift transformation is completed; where N takes the maximum value.

[0143] Reference Figure 7 The execution flow of pipeline rounds 2-9 is the same as that of pipeline round 1, and will not be repeated here. After pipeline round 9 ends, i.e., after time t49, the column mixing transformation and XOR operation of round 9 in the traditional AES encryption process are completed, as are the S-box transformation and row shift transformation in round 10. It should be noted that after time t49, the 11th pipeline round 10 begins, and the key is refreshed to the final key KEY10 at this time.

[0144] Step S3: The data encryption / decryption processing module performs an XOR operation on the data output by the second-level encryption / decryption circuit through the third-level encryption / decryption circuit, and then outputs the encrypted / decrypted data.

[0145] As one implementation method, step S3 specifically includes:

[0146] Step S31: Based on the current sub-round number, the data encryption / decryption processing module selects the result of the row shift transformation / reverse row shift transformation and the number of bits of the first preset bit width corresponding to the current key through the fourth data selector and performs an XOR operation, and then increments the current sub-round number by 1.

[0147] Reference Figure 7Step S31 corresponds to time t50 (at this time, the current number of child rounds is 0, indicating the first child round of pipeline round 10). The [31:0] bits of the row shift transformation result at time t49 are XORed with the [31:0] bits of the final key KEY10, and then the current number of child rounds becomes 1.

[0148] Step S32, and so on, after the data encryption / decryption processing module completes the XOR operation of the result of the row shift transformation / reverse row shift transformation and all bits of the current key, the first register outputs the encrypted / decrypted data.

[0149] Reference Figure 7 At time t51, the [63:32] bits of the row shift transformation result at time t49 are XORed with the [63:32] bits of the final key KEY10; at time t52, the [95:64] bits of the row shift transformation result at time t49 are XORed with the [95:64] bits of the final key KEY10; at time t53, the [127:96] bits of the row shift transformation result at time t49 are XORed with the [127:96] bits of the final key KEY10. At this point, pipeline round 10 ends, meaning the encryption process is complete after time t53, and the first register outputs the encrypted data.

[0150] It should be noted that before the pipeline begins, if the AES direction is for data encryption, the data encryption / decryption processing module receives the initial key as the current key. After the first counter generates a key refresh enable, it receives the refreshed key as the current key, continuing until the initial key is refreshed to the final key. If the AES direction is for data decryption, the data encryption / decryption processing module receives the final key as the current key. After the first counter generates a key refresh enable, it receives the refreshed key as the current key, continuing until the final key is refreshed to the initial key.

[0151] As another embodiment, refer to Figure 8 The AES data decryption pipeline design, still taking a 128-bit AES data encryption / decryption process with a 128-bit key as an example, requires 54 clock cycles to complete decryption, comprising 11 pipeline rounds. The specific AES data decryption pipeline is as follows:

[0152] At time t0, perform an XOR operation between the [31:0] bits of the data to be decrypted and the [31:0] bits of the final key KEY10;

[0153] At time t1, perform an XOR operation on the [63:32] bits of the data to be decrypted and the [63:32] bits of the final key KEY10, and perform an inverse S-box transformation on the XOR operation result at time t0;

[0154] At time t2, perform an XOR operation on the [95:64] bits of the data to be decrypted and the [95:64] bits of the final key KEY10, and perform an inverse S-box transformation on the XOR operation result at time t1;

[0155] At time t3, perform an XOR operation on the [127:96] bits of the data to be decrypted and the [127:96] bits of the final key KEY10, and perform an inverse S-box transformation on the XOR result at time t2;

[0156] At time t4, the XOR operation result from time t3 is subjected to an inverse S-box transformation, and the inverse S-box transformations from time t1 to t4 are subjected to an inverse shift transformation. At this point, the first round of pipeline round 0 ends. After time t4, the traditional AES data decryption process round 0 (XOR operation between the data to be decrypted and the final key KEY10) is completed, as are the inverse S-box transformation and inverse shift transformation in round 1.

[0157] The next step is the second round (pipeline round 1) of the AES data decryption pipeline. The process is similar to the AES data encryption pipeline described above, but with an additional step of performing an inverse column mixing transformation on the current key (excluding the final and initial keys), as follows:

[0158] At time t5, the [31:0] bits of the reverse shift transformation result at time t4 are subjected to an inverse column hybrid transformation, and then an XOR operation is performed between them and the [31:0] bits of the inverse column hybrid transformation KEY9.

[0159] At time t6, the [63:32] bits of the reverse shift transformation result at time t4 are subjected to an inverse column hybrid transformation, and then an XOR operation is performed on them with the [63:32] bits of the inverse column hybrid transformation KEY9. Finally, the XOR operation result at time t5 is subjected to an inverse S-box transformation.

[0160] At time t7, the [95:64] bits of the reverse shift transformation result at time t4 are subjected to an inverse column hybrid transformation, and then an XOR operation is performed on them with the [95:64] bits of the inverse column hybrid transformation result KEY9. Finally, an inverse S-box transformation is performed on the XOR operation result at time t6.

[0161] At time t8, the [127:96] bits of the reverse shift transformation result at time t4 are subjected to an inverse column hybrid transformation, and then an XOR operation is performed on them with the KEY9[127:96] bits after the inverse column hybrid transformation. Finally, the XOR operation result at time t7 is subjected to an inverse S-box transformation.

[0162] At time t9, the XOR result from time t8 is subjected to an inverse S-box transformation, and the inverse S-box transformation results from time t6 to t9 are subjected to an inverse row shift transformation. After pipeline round 1 ends, i.e., after time t9, the inverse column hybrid transformation and XOR operation in round 1 of the traditional AES data decryption process are completed, and the inverse S-box transformation and inverse row shift transformation in round 2 are completed. The execution flow of pipeline round 2 to pipeline round 9 is the same as that of pipeline round 1. After pipeline round 9 ends, i.e., after time t49, the inverse column hybrid transformation and XOR operation in round 9 of the traditional AES data decryption process are completed, and the inverse S-box transformation and inverse row shift transformation in round 10 are completed.

[0163] At time t50, perform an XOR operation between the [31:0] bits of the reverse shift transformation result at time t49 and the [31:0] bits of the initial key KEY0;

[0164] At time t51, perform an XOR operation between the [63:32] bits of the reverse shift transformation result at time t49 and the [63:32] bits of the initial key KEY0;

[0165] At time t52, perform an XOR operation between the [95:64] bits of the reverse shift transformation result at time t49 and the [95:64] bits of the initial key KEY0;

[0166] At time t53, the [127:96] bits of the reverse shift transformation result at time t49 are XORed with the [127:96] bits of the initial key KEY0. After pipeline round 10 ends, i.e. after time t53, the decryption process is complete, and the first register outputs the decrypted data.

[0167] Compared with the prior art, the data encryption and decryption processing method described in this embodiment of the invention realizes the in-round loop of the AES algorithm through pipeline technology. That is, during the transformation process of the current round, a partial transformation of the next round can be realized, which reduces the number of clock cycles consumed by the AES encryption and decryption process and improves the efficiency of data encryption and decryption.

[0168] Furthermore, in the description of this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0169] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. These programs can be stored in computer-readable storage media (such as ROM, RAM, magnetic disks, or optical disks, and other media capable of storing program code). When executed, the program performs the steps of the above-described method embodiments.

[0170] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An AES (Automatic Encoding and Strategy) operational circuit, characterized in that, The arithmetic circuit includes: The bus interface module is used for data interaction between the master and slave devices. The FIFO module, connected to the bus interface module, is used for data buffering. The data flow control module, connected to the FIFO module and the data encryption / decryption processing module, is used to control the data interaction between the FIFO module and the data encryption / decryption processing module. The data encryption / decryption processing module is connected to the data flow control module and implements data encryption / decryption through in-wheel pipeline technology. The key processing module, connected to the bus interface module and the data encryption / decryption processing module, is used to provide the current key to the data encryption / decryption processing module. The key processing module only stores the current key; The data encryption / decryption processing module includes: The first counter is used to count the number of clock cycles during the data encryption and decryption process and output the current sub-wheel number. After each preset number of counts, the current sub-wheel number is reset to zero and the count is restarted. The second counter is connected to the first counter and receives the current sub-wheel count output by the first counter. It is used to count the number of conveyor wheels based on the current sub-wheel count. The first-stage encryption / decryption circuit, connected to the second counter, is used to perform a first-round XOR operation on the data to be encrypted / decrypted based on the pipeline round number, the current sub-round number, and the AES direction, as well as a second-round S-box transformation / inverse S-box transformation and row shift transformation / reverse row shift transformation; wherein, the AES direction includes the data encryption direction and the data decryption direction; the first round and the second round respectively represent the initial round and the intermediate round in the AES data encryption / decryption rounds; The second-level encryption / decryption circuit, connected to the second counter and the first-level encryption / decryption circuit, is used to perform column mixing transformation / inverse column mixing transformation and XOR operation on the data output by the first-level encryption / decryption circuit in the (N-1)th round, as well as S-box transformation / inverse S-box transformation and row shift transformation / inverse row shift transformation in the Nth round, based on the pipeline round number, the current sub-round number, and the AES direction; where N represents the AES data encryption / decryption round number, N is a positive integer greater than 2, and the maximum value of N is determined by the key length; The third-level encryption / decryption circuit is connected to the second counter and the second-level encryption / decryption circuit. It is used to perform an XOR operation on the data output by the second-level encryption / decryption circuit according to the number of pipeline wheels and the current number of sub-wheels, and then output the encrypted / decrypted data. The key processing module includes: The key pre-refresh control state machine module is used to generate key pre-refresh enable to control the key transformation module to perform key pre-refresh, and outputs a key pre-refresh completion interrupt signal after the key pre-refresh is completed. The first OR gate is connected to the key pre-refresh control state machine module and performs an OR operation on the key pre-refresh enable and the key refresh enable generated by the data encryption and decryption processing module. A key transformation module, connected to the first OR gate, is used for key refresh to update the key in the key register; The data selector, connected to the key transformation module, selects the corresponding key based on the data selection signal and transmits it to the key register. The key register, connected to the data selector, is used to store the current key; Specifically, if the AES direction is the data encryption direction, the data encryption / decryption processing module receives the initial key as the current key, and after the first counter generates the key refresh enable, it receives the refreshed key as the current key, until the initial key is refreshed to the final key; if the AES direction is the data decryption direction, the data encryption / decryption processing module receives the final key as the current key, and after the first counter generates the key refresh enable, it receives the refreshed key as the current key, until the final key is refreshed to the initial key.

2. The AES operation circuit according to claim 1, characterized in that, The FIFO module includes an input buffer FIFO module and an output buffer FIFO module; wherein... The input buffer FIFO module is used to buffer the data to be encrypted or decrypted transmitted from the host by the bus interface module; The output buffer FIFO module is used to buffer encrypted and decrypted data transmitted from the data encryption and decryption processing module.

3. The AES operation circuit according to claim 1, characterized in that, The first counter counts the number of clock cycles once each time it receives an AES module enable; after counting a preset number of times, the first counter generates a key refresh enable, and then resets the current sub-round count to zero and starts counting again.

4. The AES operation circuit according to claim 3, characterized in that, The second counter counts the number of pipeline wheels once for every preset number of current sub-wheel counts received; when the number of pipeline wheels reaches the maximum value of N and the total number of clock cycles reaches the preset value, the second counter generates a valid encrypted / decrypted data flag signal.

5. The AES operation circuit according to claim 4, characterized in that, The first-level encryption / decryption circuit includes: The first data selector is used to select the corresponding number of bits of the data to be encrypted / decrypted and the corresponding number of bits of the current key according to the current sub-round number, and outputs the result to the first XOR operation module; The first XOR operation module is connected to the first data selector and is used to perform an XOR operation on the corresponding number of bits of the data to be encrypted / decrypted and the corresponding number of bits of the current key. The second data selector, connected to the second counter, is used to select the XOR operation result of the corresponding number of pipeline rounds and output it to the first register. The first register, connected to the second data selector, is used to store the data selected by the second data selector. If the number of pipeline rounds reaches the maximum value of N and the total number of clock cycles reaches the preset value, the first register will output the received data as encrypted and decrypted data; otherwise, the first register will temporarily store the received data until it is read by the next module. The third data selector, connected to the first register, is used to select the corresponding bit of the XOR operation result in the first register according to the current sub-round number, and then transmit it to the S-box conversion module; The S-box transformation module is connected to the third data selector and is used to perform S-box transformation / inverse S-box transformation on the data output by the third data selector according to the AES direction. A data merging module, connected to the S-box transformation module, is used to merge the data output by the S-box transformation module; The row shift transformation module, connected to the data merging module, is used to perform row shift transformation / reverse row shift transformation on the merged data according to the AES direction; The fourth data selector, connected to the row shift transformation module, is used to select the corresponding number of bits of the transformation result in the row shift transformation module according to the current number of sub-wheels and output it to the next stage circuit. Wherein, the data processing bit width of the first XOR operation module and the S-box transformation module is a first preset bit width, the data processing bit width of the row shift transformation module is a second preset bit width, the second preset bit width is an integer multiple of the first preset bit width, the storage space of the first register is a first preset value, the size of the first preset value is equal to the size of the second preset bit width, and the size of the corresponding bit is equal to the size of the first preset bit width.

6. The AES operation circuit according to claim 5, characterized in that, The data merging module includes a second register and a third register, wherein, The second register is connected to the S-box conversion module and is used to store the data output by the S-box conversion module; The third register is connected to the S-box conversion module and the second register respectively. It is used to receive the data output by the S-box conversion module when the storage space of the first register is insufficient, and also to receive the data in the first register, and then merge all the data. Wherein, the storage space of the second register is a second preset value, the storage space of the third register is a first preset value, the second preset value is less than the first preset value, and the second preset value is an integer multiple of the first preset bit width.

7. The AES operation circuit according to claim 5, characterized in that, The second-level encryption / decryption circuit includes: The column hybrid transformation module, connected to the fourth data selector, is used to perform column hybrid transformation / inverse column hybrid transformation on the corresponding number of bits of the transformation result in the row shift transformation module according to the AES direction; The fifth data selector is used to select the corresponding number of bits in the current key based on the current sub-round number; The key inverse mixing transformation module, connected to the fifth data selector, is used to perform an inverse mixing transformation on the corresponding bits of the current key output by the fifth data selector during data decryption. The sixth data selector, connected to the fifth data selector and the key inverse hybrid transformation module, is used to select the data output by the fifth data selector or the key inverse hybrid transformation module according to the AES direction and transmit it to the second XOR operation module; The second XOR operation module is connected to the sixth data selector and the column mixing transformation module, and is used to perform XOR operation on the data output by the column mixing transformation module and the sixth data selector; The second-level encryption / decryption circuit also includes a second data selector, a first register, a third data selector, an S-box conversion module, a data merging module, a row shift conversion module, and a fourth data selector; The data processing bit width of the column mixing transformation module, the key inverse column mixing transformation module, and the second XOR operation module is a first preset bit width.

8. The AES operation circuit according to claim 7, characterized in that, The third-level encryption / decryption circuit includes: The seventh data selector is used to select the corresponding number of bits in the current key based on the current sub-round number; The third XOR operation module, connected to the seventh data selector and the fourth data selector, is used to perform an XOR operation on the corresponding number of bits of the transformation result in the row shift transformation module and the corresponding number of bits of the current key. The third-level encryption / decryption circuit further includes a second data selector and a first register; wherein the second data selector is connected to the first XOR operation module, the second XOR operation module and the third XOR operation module respectively; The data processing bit width of the third XOR operation module is the first preset bit width.

9. An AES operation circuit according to claim 5, characterized in that, The first preset bit width is 32 bits, the second preset bit width and the first preset value are 128 bits, and the second preset value is 96 bits.

10. An AES operation circuit according to claim 9, characterized in that, The key transformation module includes a forward key transformation module and a reverse key transformation module, wherein... The key forward transformation module, connected to the first OR gate, is used to receive key pre-refresh enable or key refresh enable, and to perform one round of key forward transformation during the data encryption process and the key pre-refresh process. The key inverse transformation module is used to receive the key refresh enable so as to perform a key inverse transformation during the data decryption process.

11. The AES operation circuit according to claim 10, characterized in that, The data selector includes an eighth data selector and a ninth data selector, wherein, The eighth data selector is connected to the key forward transformation module and the key inverse transformation module. It is used to receive the output of the key forward transformation module and the output of the key inverse transformation module, and select the output of the key forward transformation module or the key inverse transformation module as the input of the ninth data selector according to the AES direction. The ninth data selector, connected to the eighth data selector and the bus interface module, is used to receive the output of the eighth data selector and the initial key of the bus interface module, and select the output of the eighth selector or the initial key as the input of the key register according to the configuration completion signal of the initial key. The AES direction includes a data encryption direction and a data decryption direction.

12. An AES operation circuit according to claim 9, characterized in that, The key processing module further includes a second OR gate, which is connected to the key pre-refresh control state machine module and the bus interface module. It is used to receive the initial key configuration completion signal from the bus interface module and the key pre-refresh completion interrupt signal output by the key pre-refresh control state machine module, and to perform an OR operation on the initial key configuration completion signal and the key pre-refresh completion interrupt signal to generate a key register write enable to control the writing of the key register.

13. The AES operation circuit according to claim 9, characterized in that, The key pre-refresh control state machine module includes a state machine and a third counter; the state machine is used to control the third counter to count the number of pulses that enable key pre-refresh.

14. An AES operation method, characterized in that, This method is implemented using the AES operation circuit according to any one of claims 1 to 13, and the method includes: After acquiring the data to be encrypted or decrypted, the data encryption / decryption processing module encrypts or decrypts the data using in-round pipeline technology according to the AES direction. During each pipeline round, the data encryption / decryption processing module generates a key refresh enable, which causes the key processing module to refresh the key and transmit it to the data encryption / decryption processing module for encryption / decryption. The key processing module only stores the current key. Specifically, the in-wheel assembly line technology includes: Step S1: According to the AES direction, the data encryption / decryption processing module performs a first round of XOR operation and a second round of S-box transformation / inverse S-box transformation and row shift transformation / inverse row shift transformation on the data to be encrypted / decrypted through the first-level encryption / decryption circuit; wherein, the AES direction includes a data encryption direction and a data decryption direction; the first round and the second round respectively represent the initial round and the intermediate round in the number of AES data encryption / decryption rounds; Step S2: The data encryption / decryption processing module performs the (N-1)th round of column mixing transformation / inverse column mixing transformation and XOR operation, as well as the Nth round of S-box transformation / inverse S-box transformation and row shift transformation / inverse row shift transformation on the data output by the first-level encryption / decryption circuit through the second-level encryption / decryption circuit; where N represents the number of AES data encryption / decryption rounds, N is a positive integer and greater than 2, and the maximum value of N is determined by the key length; Step S3: The data encryption / decryption processing module performs an XOR operation on the data output by the second-level encryption / decryption circuit through the third-level encryption / decryption circuit, and then outputs the encrypted / decrypted data.

15. The AES operation method according to claim 14, characterized in that, The method in step S1 specifically includes: Step S11: After the data encryption / decryption processing module receives the AES module enable, it causes the first counter to start outputting the current sub-round number, and then selects the number of bits of the first preset bit width corresponding to the data to be encrypted / decrypted and the current key to perform an XOR operation, and then increments the current sub-round number by 1; wherein, the data to be encrypted / decrypted and the current key have the same data bit width and are integer multiples of the first preset bit width; Step S12: According to the AES direction, the data encryption and decryption processing module selects the number of bits of the first preset bit width corresponding to the data to be encrypted and decrypted and the current key to perform an XOR operation. At the same time, the XOR operation result of the previous step is subjected to S-box transformation / inverse S-box transformation. Then the current sub-round number is incremented by 1. Step S13, and so on, when the current sub-round number reaches the preset number of times, the data encryption and decryption processing module performs S-box transformation / inverse S-box transformation on the XOR operation result of the previous step according to the AES direction, and at the same time performs row shift transformation / reverse row shift transformation on all the results after S-box transformation / inverse S-box transformation.

16. The AES operation method according to claim 15, characterized in that, In step S13, before performing row shift transformation / reverse row shift transformation on all S-box transformed / inverse S-box transformed data according to the AES direction, the following is also included: The data encryption and decryption processing module transmits the result of each S-box transformation / inverse S-box transformation to the second register. When the current sub-round number reaches the preset number, the data encryption and decryption processing module transmits the result of the S-box transformation / inverse S-box transformation at this time and the result stored in the second register together to the third register for merging, and then transmits the merged data to the row shift transformation module.

17. The AES operation method according to claim 16, characterized in that, When the current number of sub-rounds reaches a preset number, the first counter generates a key refresh enable and transmits it to the key processing module. At the same time, the second counter counts the pipeline rounds once, and then the current number of sub-rounds is reset to zero and recounted.

18. The AES operation method according to claim 17, characterized in that, The method in step S2 specifically includes: Step S21: Based on the pipeline round number, the current sub-round number, and the AES direction, the data encryption and decryption processing module selects the number of bits corresponding to the first preset bit width in the result of the row shift transformation / reverse row shift transformation through the fourth data selector, performs column mixing transformation / reverse column mixing transformation, and then performs an XOR operation with the number of bits corresponding to the first preset bit width of the current key. Subsequently, the current sub-round number is incremented by 1. Step S22: The data encryption and decryption processing module selects the number of bits of the next corresponding first preset bit width in the result of row shift transformation / inverse row shift transformation, performs column mixing transformation / inverse column mixing transformation, and then performs an XOR operation with the number of bits of the next corresponding first preset bit width of the current key. At the same time, it performs S-box transformation / inverse S-box transformation on the XOR operation result of the previous step, and then increments the current sub-round number by 1. Step S23, and so on, when the current number of sub-rounds reaches the preset number of times, the data encryption and decryption processing module performs S-box transformation / inverse S-box transformation on the XOR operation result of the previous step according to the AES direction, and performs row shift transformation / reverse row shift transformation on all the results after S-box transformation / inverse S-box transformation. Step S24: After the first counter generates a key refresh enable and the second counter counts the pipeline rounds, the data encryption / decryption processing module resets the current sub-round count to zero and recounts. Then, steps S21 to S24 are repeated until the Nth round of S-box transformation / inverse S-box transformation and row shift transformation / inverse row shift transformation is completed; where N takes the maximum value.

19. The AES operation method according to claim 18, characterized in that, During step S2, if the AES direction is the data decryption direction, before performing the XOR operation, the number of bits of the first preset bit width corresponding to the current key is first subjected to an inverse column mixing transformation.

20. The AES operation method according to claim 18, characterized in that, The method in step S3 specifically includes: Step S31: Based on the current sub-round number, the data encryption / decryption processing module selects the result of the row shift transformation / reverse row shift transformation and the number of bits of the first preset bit width corresponding to the current key through the fourth data selector and performs an XOR operation, and then increments the current sub-round number by 1; Step S32, and so on, after the data encryption / decryption processing module completes the XOR operation of the result of the row shift transformation / reverse row shift transformation and all bits of the current key, the first register outputs the encrypted / decrypted data.

21. The AES operation method according to claim 20, characterized in that, If the AES direction is for data encryption, the key processing module performs a forward key transformation on the key, which means sequentially refreshing the initial key in the key register to the final key; if the AES direction is for data decryption, the key processing module performs a reverse key transformation on the key, which means sequentially refreshing the final key in the key register to the initial key.

22. The AES operation method according to claim 21, characterized in that, Before the data encryption or decryption process begins, the key processing module updates the key in the key register to the initial key based on the AES module enable signal and the initial key configuration completion signal.

23. The AES operation method according to claim 22, characterized in that, If the AES direction is the data decryption direction, then after refreshing the key in the key register to the initial key, the key processing module performs key pre-refresh according to the key pre-refresh enable; the key pre-refresh refers to performing a positive transformation on the key in the key register before the data decryption process, updating the key in the key register to the final key.

Images