Hardware implementation method and hardware implementation device of montgomery algorithm

Abstract

Provided are a hardware implementation method and a hardware implementation device of a Montgomery algorithm. A REDC operation of the Montgomery algorithm includes a first multiplication operation, a second multiplication operation, a third multiplication operation, a fourth multiplication operation, and a subtraction operation, the third multiplication operation depends on a result of the second multiplication operation, a clock cycle for the REDC operation includes a first clock cycle for multiplication operation and a second clock cycle for subtraction operation, the hardware implementation method includes: replacing the second clock cycle with an additional clock cycle for multiplication operation by adjusting a calculation flow of the REDC operation; performing the first multiplication operation, the second multiplication operation, and the third multiplication operation by a first multiplier, wherein the first multiplication operation includes a first multiplier and a second multiplier; and performing the fourth multiplication operation by a second multiplier. The hardware implementation method can save multiplier resources without reducing hardware performance.

Description

Technical Field

[0001] This disclosure relates to the field of optimization technology for hardware implementation of algorithms, and more specifically, to a hardware implementation method and hardware implementation device for the Montgomery algorithm. Background Technology

[0002] In typical hardware implementations of the Montgomery algorithm, multiplication requires a separate multiplier, while subtraction requires an adder or other logical combinations. Since multiplication is far more complex than addition, multipliers consume significantly more resources than adders. However, in dedicated hardware acceleration circuits, whether ASICs or FPGAs, the number of on-chip resources is limited, and the number of on-chip multipliers is often far less than the number of adders. Therefore, the quantity and efficiency of on-chip multiplier resources directly determine the computing power provided by a Montgomery-based hardware accelerator. Thus, conserving multiplier resources is of significant practical importance in the hardware implementation of the Montgomery algorithm. However, existing solutions often fail to save sufficient multiplier resources or even reduce the performance of Montgomery-based hardware accelerators. Summary of the Invention

[0003] This disclosure proposes a hardware implementation method and hardware implementation device for the Montgomery algorithm, which can at least solve the above-mentioned problems, or may not solve the above-mentioned problems.

[0004] According to one aspect of this disclosure, a hardware implementation method for the Montgomery algorithm is provided, wherein the REDC operation of the Montgomery algorithm includes a first multiplication operation, a second multiplication operation, a third multiplication operation, a fourth multiplication operation, and a subtraction operation, wherein the third multiplication operation depends on the result of the second multiplication operation, and the clock cycle for the REDC operation includes a first clock cycle for the multiplication operation and a second clock cycle for the subtraction operation. The hardware implementation method includes: replacing the second clock cycle with an additional clock cycle for the multiplication operation by adjusting the calculation flow of the REDC operation; executing the first multiplication operation, the second multiplication operation, and the third multiplication operation through a first multiplier, wherein the first multiplication operation includes a first multiplier and a second multiplier; and executing the fourth multiplication operation through a second multiplier, wherein executing the first multiplication operation, the second multiplication operation, and the third multiplication operation through the first multiplier includes: using the first multiplier, in the first clock cycle and the additional clock cycle, The first, second, and third multiplication operations are executed in a time-sharing manner, wherein the execution of the first, second, and third multiplication operations in a time-sharing manner during a first clock cycle and an additional clock cycle includes: inputting the original input stream of the first multiplier into a register to obtain a delayed input stream of the first multiplier, wherein the delayed input stream lags behind the original input stream by one clock cycle; inputting the original input stream and the delayed input stream into a data selector; switching the original input stream and the delayed input stream to input one of the original input stream and the delayed input stream into the first multiplier, such that based on the clock cycle in which the delayed input stream lags behind the original input stream and the additional clock cycle, a one-clock-cycle switching interval is reserved each time the original input stream and the delayed input stream are switched; the first multiplier performs the second multiplication operation or the third multiplication operation during the switching interval, and performs the first multiplication operation in the remaining clock cycles.

[0005] Optionally, the first multiplication operation includes a first number of first multipliers and a second number of second multipliers, and any one of the calculation cycles of each REDC operation includes: the first number of clock cycles for performing the first multiplication operation, a clock cycle for performing the second multiplication operation, and a clock cycle for performing the third multiplication operation, wherein the switching between the original input stream and the delayed input stream includes: switching the original input stream and the delayed input stream twice in each calculation cycle, such that each calculation cycle includes two switching intervals, wherein one switching interval is used to perform the second multiplication operation, and the other switching interval is used to perform the third multiplication operation, and the switching interval for performing the third multiplication operation lags behind the switching interval for performing the second multiplication operation by at least a predetermined number of clock cycles.

[0006] Optionally, switching the original input stream and the delayed input stream includes: switching the original input stream and the delayed input stream based on an input selection signal and the data selector, wherein the input selection signal includes an original signal and a delayed signal, wherein the original signal is used to cause the data selector to select the original input stream as the input of the first multiplier, and the delayed signal is used to cause the data selector to select the delayed input stream as the input of the first multiplier.

[0007] Optionally, the original input stream includes an additional first multiplier twice the number of additional clock cycles of the second quantity, wherein the original input stream includes two adjacent additional first multipliers at the end of each data cycle.

[0008] Optionally, the switching interval includes a first switching interval when switching from the original input stream to the delayed input stream and a second switching interval when switching from the delayed input stream to the original input stream.

[0009] Optionally, the step of performing the second multiplication operation or the third multiplication operation through the first multiplier during the switching interval, and performing the first multiplication operation in the remaining clock cycles, includes: cyclically executing the following steps until the REDC operation ends: performing a first multiplication operation based on the original input stream through the first multiplier; switching the original input stream and the delayed input stream when the first multiplier has performed the first multiplication operation for a predetermined number of clock cycles; performing a third multiplication operation through the first multiplier during the first switching interval; performing a first multiplication operation based on the delayed input stream through the first multiplier; switching the original input stream and the delayed input stream when the first multiplier has performed the first multiplication operation for a first number and a predetermined number of clock cycles of the difference between the first and predetermined number of clock cycles; and performing a second multiplication operation through the first multiplier during the second switching interval.

[0010] Optionally, the step of performing the second multiplication operation or the third multiplication operation through the first multiplier during the switching interval and performing the first multiplication operation in the remaining clock cycles further includes: performing the second multiplication operation for two clock cycles and the third multiplication operation for one clock cycle through the first multiplier before performing the first multiplication operation through the first multiplier, so that the subsequent multiplication operations are performed in an orderly manner.

[0011] According to another aspect of this disclosure, a hardware implementation apparatus for the Montgomery algorithm is provided, wherein the REDC operation of the Montgomery algorithm includes a first multiplication operation, a second multiplication operation, a third multiplication operation, a fourth multiplication operation, and a subtraction operation, wherein the third multiplication operation depends on the result of the second multiplication operation, and the clock cycle for the REDC operation includes a first clock cycle for the multiplication operation and a second clock cycle for the subtraction operation. The hardware implementation apparatus includes: an operation substitution unit configured to substitute the second clock cycle for an additional clock cycle for the multiplication operation by adjusting the calculation flow of the REDC operation; and a first multiplication unit configured to execute the first multiplication operation, the second multiplication operation, and the third multiplication operation through a first multiplier, wherein the first multiplication operation includes a first multiplier and a second multiplier, wherein the first multiplication operation is executed time-divisionally in the first clock cycle and the additional clock cycle. The second and third multiplication operations are performed, wherein the original input stream of the first multiplier is input to a register to obtain a delayed input stream of the first multiplier, wherein the delayed input stream lags behind the original input stream by one clock cycle, wherein the original input stream and the delayed input stream are input to a data selector to switch between the original input stream and the delayed input stream, so that one of the original input stream and the delayed input stream is input to the first multiplier, such that based on the clock cycle in which the delayed input stream lags behind the original input stream and the additional clock cycle, a switching interval of one clock cycle is reserved each time the original input stream and the delayed input stream are switched, and the second multiplication operation or the third multiplication operation is performed by the first multiplier during the switching interval, and the first multiplication operation is performed in the remaining clock cycles; the second multiplication unit is configured to perform the fourth multiplication operation through the second multiplier.

[0012] Optionally, the first multiplication operation includes a first number of first multipliers and a second number of second multipliers, and any one of the calculation cycles of each REDC operation includes: the first number of clock cycles for performing the first multiplication operation, a clock cycle for performing the second multiplication operation, and a clock cycle for performing the third multiplication operation, wherein the first multiplication unit is configured to switch the original input stream and the delayed input stream twice in each calculation cycle, such that each calculation cycle includes two switching intervals, wherein one switching interval is used to perform the second multiplication operation, and the other switching interval is used to perform the third multiplication operation, and the switching interval for performing the third multiplication operation lags behind the switching interval for performing the second multiplication operation by at least a predetermined number of clock cycles.

[0013] Optionally, the first multiplication unit is configured to switch between the original input stream and the delayed input stream based on an input selection signal and the data selector, wherein the input selection signal includes an original signal and a delayed signal, wherein the original signal is used to cause the data selector to select the original input stream as the input of the first multiplier, and the delayed signal is used to cause the data selector to select the delayed input stream as the input of the first multiplier.

[0014] Optionally, the original input stream includes an additional first multiplier twice the number of additional clock cycles of the second quantity, wherein the original input stream includes two adjacent additional first multipliers at the end of each data cycle.

[0015] Optionally, the switching interval includes a first switching interval when switching from the original input stream to the delayed input stream and a second switching interval when switching from the delayed input stream to the original input stream.

[0016] Optionally, the first multiplication unit is configured to: cyclically execute the following steps until the REDC operation ends: perform a first multiplication operation based on the original input stream using the first multiplier; switch the original input stream and the delayed input stream when the first multiplier has performed the first multiplication operation for a predetermined number of clock cycles; perform a third multiplication operation using the first multiplier during the first switching interval; perform a first multiplication operation based on the delayed input stream using the first multiplier; switch the original input stream and the delayed input stream when the first multiplier has performed the first multiplication operation for a first number of clock cycles equal to the difference between the first and predetermined number of clock cycles; and perform a second multiplication operation using the first multiplier during the second switching interval.

[0017] Optionally, the first multiplication unit is configured to perform a second multiplication operation for two clock cycles and a third multiplication operation for one clock cycle before performing the first multiplication operation through the first multiplier, thereby ensuring that subsequent multiplication operations are performed in an orderly manner.

[0018] According to another aspect of this disclosure, a system is provided that includes at least one computing device and at least one storage device for storing instructions, wherein the instructions, when executed by the at least one computing device, cause the at least one computing device to perform a Montgomery hardware implementation method according to this disclosure.

[0019] According to another aspect of this disclosure, a computer-readable storage medium for storing instructions is provided, wherein when the instructions are executed by at least one computing device, the at least one computing device causes the at least one computing device to perform a hardware implementation method of Montgomery according to this disclosure.

[0020] The hardware implementation method and hardware implementation apparatus of the Montgomery algorithm according to the exemplary embodiments of the present disclosure can improve the efficiency of multiplier usage without affecting the overall acceleration performance of the REDC computing unit, thereby reducing the number of multipliers used in a computing unit of a Montgomery algorithm REDC operation to 2, and thus greatly improving the performance of the hardware accelerator based on the Montgomery algorithm. Attached Figure Description

[0021] These and / or other aspects and advantages of this disclosure will become clearer and more readily understood from the following description of the embodiments, taken in conjunction with the accompanying drawings, wherein:

[0022] Figure 1 This is a schematic diagram illustrating the hardware implementation of the REDC operation of the Montgomery algorithm before optimization;

[0023] Figure 2 This is a flowchart illustrating a hardware implementation method of the Montgomery algorithm according to an exemplary embodiment of the present disclosure;

[0024] Figure 3a , Figure 3b , Figure 3c This illustrates the execution of X according to an exemplary embodiment of the present disclosure. j ·Y i A diagram illustrating the clock cycle of a multiplier;

[0025] Figure 4 This is a dedicated circuit diagram illustrating a hardware implementation of the Montgomery algorithm according to an exemplary embodiment of the present disclosure.

[0026] Figure 5 This is a block diagram illustrating a hardware implementation apparatus for the Montgomery algorithm according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0027] The following description, provided with reference to the accompanying drawings, is intended to aid in a full understanding of embodiments of the present disclosure as defined by the claims and their equivalents. Various specific details are included to aid understanding, but these details are to be considered exemplary only. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Furthermore, for clarity and brevity, descriptions of well-known functions and structures are omitted.

[0028] It should be noted that the phrase "at least one of several items" in this disclosure refers to three parallel cases: "any one of the several items", "a combination of any number of the several items", and "all of the several items". For example, "including at least one of A and B" includes the following three parallel cases: (1) including A; (2) including B; (3) including A and B. As another example, "performing at least one of step one and step two" indicates the following three parallel cases: (1) performing step one; (2) performing step two; (3) performing both step one and step two.

[0029] In recent years, big data and artificial intelligence technologies have developed rapidly, and more and more related applications have been widely implemented in people's daily production and lives. However, with the booming development of big data, various data breaches have also occurred frequently, and people's demand for data security and data privacy has become increasingly urgent. At the same time, countries around the world have successively enacted legislation to regulate data privacy protection, making privacy protection a decisive legal factor in the implementation of big data and artificial intelligence technologies.

[0030] Federated learning, a novel technology proposed in 2016, is a recent hot topic in artificial intelligence and privacy protection. Unlike traditional distributed machine learning systems that primarily focus on performance improvements during model training, federated learning aims to balance data protection and application within distributed machine learning systems. Common federated learning systems typically involve two or more participants collaborating to perform joint machine learning on their data without disclosing their own. To achieve the privacy requirement of data sharing without disclosure, a common technique is to perform homomorphic encryption on the data itself. Homomorphic encryption is a special form of encryption that allows specific algebraic operations to be performed on the encrypted ciphertext, and the decrypted result is identical to the result of performing the same operation on the plaintext. This special cryptographic property allows machine learning systems using homomorphic encryption to both complete machine learning training tasks and protect data privacy.

[0031] The Paillier encryption system is a widely used homomorphic encryption system. Based on the difficult problem of composite residues, the Paillier encryption algorithm satisfies additive homomorphism, meaning that the multiplication of ciphertext equals the addition of plaintext. The Paillier encryption algorithm uses a large number of large integer modular exponentiation operations in its encryption and decryption operations. Since these modular exponentiation operations can have operands as long as 2048 or 4096 bits, they require a significant amount of computational power. Even with optimizations using the industry-standard Montgomery algorithm, these large integer modular exponentiation operations often account for more than 90% of the computation time in the Paillier encryption and decryption calculations.

[0032] Due to the difficulty in further reducing the computation time of these large integer modular exponentiation operations on CPUs, and in pursuit of higher performance and lower power consumption, the industry has proposed many heterogeneous hardware acceleration implementations based on the Montgomery algorithm in recent years. These hardware acceleration solutions often use dedicated hardware such as ASICs or FPGAs as a foundation, and can specifically optimize and improve the computing power of large integer modular exponentiation operations in homomorphic encryption systems.

[0033] In the design of dedicated hardware acceleration circuits, resource utilization is one of the most important factors affecting the computational performance of the acceleration circuit. This is because the number of on-chip resources available for both ASIC and FPGA chips is not infinitely large. In the hardware implementation of the Montgomery algorithm, an essential resource is the on-chip integer multiplier, which is responsible for calculating the numerous multiplication operations involved in modular exponentiation. The quantity and efficiency of on-chip integer multiplier resources often directly determine the computing power that a Montgomery algorithm-based hardware accelerator can provide.

[0034] Montgomery's algorithm is a commonly used optimization algorithm in modular exponentiation. The overall process of modular exponentiation using Montgomery's algorithm can be summarized in the following three steps: Step 1, convert the base in the modular exponentiation to Montgomery notation; Step 2, perform the exponentiation operation on the converted base in Montgomery notation; Step 3, convert the calculation result back to Montgomery notation to obtain the final result. Now, we define a custom operation called REDC (Montgomery Reduction) for modular exponentiation a. e mod n, as described above, all three steps can be achieved through a combination of REDC operations. Here, the calculation process of step 1 can be expressed as REDC((a mod N)(R 2 The calculation process in step 2 includes REDC(aR·bR), and the calculation process in step 3 can be expressed as REDC(aR mod N).

[0035] All major computational steps in the Montgomery algorithm can be performed using REDC operations. A typical REDC operation includes four multiplication operations and one subtraction operation. The four multiplication operations are X... j ·Y i q i ·N j 、X0·Y i and P·β i A subtraction operation is SN; here, j∈[0, m) and i∈[0, n).

[0036] Figure 1This is a schematic diagram illustrating the hardware implementation of the REDC operation of the Montgomery algorithm before optimization.

[0037] Reference Figure 1 For the hardware implementation of the REDC operation of the unoptimized Montgomery algorithm, X in the four multiplication operations... j ·Y i and q i ·N j The calculation needs to be performed in each clock cycle; X0·Y i and P·β i This requires calculation every m clock cycles, and because P·β i The calculation depends on X0·Y i The calculation result is X0·Y i With P·β i A time interval of k clock cycles is required between them. It is evident that the hardware implementation of the REDC operation in the unoptimized Montgomery algorithm requires 4 multipliers per REDC operation unit. It should be noted that all multipliers in the diagram are pipelined multipliers. That is, these multipliers can accept a new set of inputs in each clock cycle, but each multiplier requires d clock cycles to produce the corresponding multiplication result; here, there exists a quantitative relationship where d ≤ k, thus X0·Y i With P·β i They operate in an orderly manner.

[0038] In typical hardware implementations of the Montgomery algorithm, multiplication operations are implemented using separate multipliers, and subtraction operations are implemented using adders or other logical combinations. Since multipliers consume significantly more resources than adders, and the number of adders that can be implemented in a device is often much greater than the number of multipliers, the exemplary embodiments of this disclosure primarily focus on reducing the use of multiplier resources in the hardware implementation of the REDC operation of the Montgomery algorithm.

[0039] For the four multiplication operations included in REDC operations, existing hardware implementations often employ the following three solutions. These three solutions and their respective shortcomings will be briefly described below.

[0040] Existing Solution 1: Make X0·Y i and P·β i Two multiplication operations share one multiplier.

[0041] Due to X0·Y i and P·β i The two multiplication operations do not need to be calculated in every clock cycle, but only once every m clock cycles. Therefore, the existing scheme 1 utilizes this computational characteristic of the Montgomery algorithm, and by scheduling the input and output, makes X0·Y iand P·β i These two multiplication operations can be performed using a single multiplier. By sharing a single multiplier, existing scheme 1 reduces the number of multiplier resources used in the hardware implementation from four to three, i.e., by X j ·Y i and q i ·N j Each has its own multiplier, and X0·Y i and P·β i Then they share a single multiplier.

[0042] Existing Solution 2: Make X0·Y i Reuse X j ·Y i The calculated results.

[0043] As can be seen from the formula, since the range of values ​​for i includes 0, and the range of values ​​for j is [0, m), therefore X j ·Y i The calculation also includes X0·Y i That is, in the Montgomery algorithm, X0·Y i Actually, it's X j ·Y i This is a specific computational example. By utilizing this property, X can be temporarily stored. j ·Y i The calculation of individual cases avoids repeated calculations of X0·Y. i This achieves the goal of reducing multiplier resources. However, due to X0·Y i The computation timeline is much earlier than X. j ·Y i The calculation example in the example is to avoid waiting for X0·Y in subsequent calculations. i The problem with the result requires adjustment of X0·Y. i The calculation order, advance X0·Y i The calculation is performed, and the result is temporarily stored to obtain the correct result. This is achieved through X0·Y i With X j ·Y i By reusing the computation results, the existing scheme 2 can also reduce the number of multipliers used in the hardware implementation from 4 to 3, i.e., by X j ·Y i q i ·N j With P·β i Each has its own multiplier.

[0044] Existing Solution 3: Based on existing Solution 2, make q i ·N j With P·β iThey share a single multiplier.

[0045] In the hardware implementation of the Montgomery algorithm, due to P·β i The calculation does not need to be performed in every clock cycle, so the P·β calculation in the existing scheme 2 can also be achieved by scheduling the input and output. i The exclusive multiplier and q i ·N j The computational multipliers that were previously exclusive are now shared. However, due to q... i ·N j The calculation depends on P·β i The calculation results show that simply sharing multipliers increases computation cycles and leads to data dependency waiting, ultimately causing pipeline stalls and requiring more clock cycles to complete the computation. Existing solution 3, through more scheduling sharing, can complete the computation using only 2 multipliers, but due to the increased computation clock cycles, although it saves multiplier resources, it also reduces the performance of hardware accelerators based on the Montgomery algorithm.

[0046] This disclosure aims to improve the efficiency of the multiplier without compromising performance by optimizing the hardware accelerator architecture based on the Montgomery algorithm through techniques such as operation substitution, input / output scheduling, and creating and selecting additional data streams. Specifically, by applying operation substitution, the clock cycles of the subtraction operations in the later stages of the REDC operation in the Montgomery algorithm are replaced with additional clock cycles from the earlier multiplication operations. This adds 2n ​​additional clock cycles to the earlier multiplication operations without affecting the overall acceleration performance. Based on the computational characteristics of the Montgomery algorithm, X of these additional clock cycles is utilized... j ·Y i The property that at least one multiplier in a multiplication operation is zero can be used to complete X0·Y by effectively scheduling inputs and outputs and utilizing these 2n extra clock cycles. i and P·β i The calculation. Simultaneously, an additional X is created through the register. j The input stream is switched between two data streams via a data selector, thereby enabling X to... j ·Y i Multiplication operations can be performed continuously while satisfying X0·Y i With P·β i The condition that k clock cycles are required between operations. By employing the above-mentioned techniques, this disclosure improves the efficiency of multipliers without affecting performance, reducing the number of multipliers required for a single REDC computation unit to 2, thus greatly improving the computing power of hardware accelerators based on the Montgomery algorithm.

[0047] The following reference Figures 2 to 5The present disclosure provides a detailed description of a hardware implementation method and hardware implementation apparatus for the Montgomery algorithm according to exemplary embodiments thereof.

[0048] The REDC operation of Montgomery's algorithm can include first multiplication, second multiplication, third multiplication, fourth multiplication, and subtraction. Here, the first multiplication operation can be X. j ·Y i The second multiplication operation can be X0·Y i The third multiplication operation can be P·β i The fourth multiplication operation can be q i ·N j The subtraction operation can be SN. The third multiplication operation can depend on the result of the second multiplication operation. Here, the second and third multiplication operations can be spaced apart by a predetermined number of clock cycles. Specifically, the predetermined number can be k, and the value of k can be set by those skilled in the art according to the actual situation. In addition, the clock cycle used for REDC operation can include a first clock cycle for multiplication operation and a second clock cycle for subtraction operation. Here, the first clock cycle is in the early stage of REDC operation, and the second clock cycle is in the later stage of REDC operation. See below for reference. Figure 2 A detailed description is provided of a hardware implementation method of the Montgomery algorithm according to exemplary embodiments of the present disclosure.

[0049] Figure 2 This is a flowchart illustrating a hardware implementation method of the Montgomery algorithm according to an exemplary embodiment of the present disclosure.

[0050] Reference Figure 2 In step S201, the second clock cycle can be replaced with an additional clock cycle for multiplication by adjusting the computation flow of the REDC operation. This disclosure does not limit the computational substitution method used to adjust the computation flow of the REDC operation; any possible computational substitution method can be used to implement step S201. For example, the computational substitution method proposed by author Hachez in the paper "Montgomery Exponentiation with no Final Subtractions: Improved Results" can be used.

[0051] Figure 3a , Figure 3b , Figure 3c This illustrates the execution of X according to an exemplary embodiment of the present disclosure. j ·Y i A diagram illustrating the clock cycle of a multiplier.

[0052] Reference Figure 3aAs an example, clock cycles 129, 130, 259, and 260 represent the additional clock cycles obtained after the substitution. Here, as shown by clock cycles 129 and 130, and clock cycles 259 and 260, the 2n additional clock cycles are grouped into pairs. Through the operational substitution method described above, the clock cycles used for subtraction in the later stages of the REDC operation can be removed, and 2n additional clock cycles are introduced into the multiplication operation in the earlier stages of the REDC operation. Simultaneously, through the operational substitution method described above, X is executed for these 2n additional clock cycles. j ·Y i The multiplier (hereinafter referred to as multiplier X) j ·Y i One of the inputs (i.e., input stream X) j The value of X is fixed at zero. Since the multiplier performs multiplication, if one input is zero, its output will also be zero. However, this is not the only possibility; other operational substitution methods can be used to make X in the extra clock cycle zero. j It is not zero. That is, during these 2n additional clock cycles, the multiplier X can be omitted. j ·Y i To execute X j ·Y i The computational operation, thus making the multiplier X j ·Y i Used for other calculations.

[0053] Therefore, return to the reference. Figure 2 In step 202, a first multiplication operation, a second multiplication operation, and a third multiplication operation can be performed by the first multiplier. Here, the first multiplication operation may include a first multiplier and a second multiplier.

[0054] According to an exemplary embodiment of this disclosure, the first multiplier may be a multiplier X as described above. j ·Y i The first multiplier can be X j And the second multiplier can be Y i Furthermore, the values ​​of i and j can be j∈[0, m) and i∈[0, n). Specifically, the first multiplication operation may include a first number of first multipliers and a second number of second multipliers, where the first number may be m and the second number may be n, and the values ​​of m and n may be determined by those skilled in the art based on the actual calculation situation. Further, any one of the calculation cycles in each REDC operation may include: a first number of clock cycles for performing the first multiplication operation, a clock cycle for performing the second multiplication operation, and a clock cycle for performing the third multiplication operation.

[0055] Furthermore, the first multiplication operation, the second multiplication operation, and the third multiplication operation can be performed in a time-sharing manner within the first clock cycle and the additional clock cycles via the first multiplier. Here, for the first multiplication operation, the original input stream includes an additional first multiplier twice the number of additional clock cycles. Specifically, the original input stream includes two adjacent additional first multipliers at the end of each data cycle. More specifically, the additional first multipliers may, but are not limited to, be zero.

[0056] Next, refer to Figure 3b By utilizing multiplier X j ·Y i X in the extra clock cycle j This property of fixing X0·Y to zero can be used to... i and P·β i The calculation is incorporated into these 2n additional clock cycles. However, due to X0·Y i With P·β i There needs to be a k-clock cycle interval between them, and the 2n additional clock cycles introduced by the permutation operation are grouped into adjacent pairs of two clock cycles each. Therefore, if we simply use X0·Y i and P·β i The calculation introduced into an extra clock cycle will cause multiplier X to... j ·Y i Generating kn wait clock cycles will actually reduce the computational performance of the hardware implementation of the REDC operation in the Montgomery algorithm.

[0057] Therefore, according to an exemplary embodiment of this disclosure, the original input stream of the first multiplier can be input into a register to obtain a delayed input stream of the first multiplier. Here, the delayed input stream lags behind the original input stream by one clock cycle. Specifically, the original input stream can be X j The input stream, and the delayed input stream can be X, which is delayed by one clock cycle. j The input stream.

[0058] Furthermore, the original input stream and the delayed input stream can be input to a data selector to switch between the original input stream and the delayed input stream, so that one of the original input stream and the delayed input stream is input to the first multiplier. Based on the clock cycle of the delayed input stream lagging behind the original input stream and the additional clock cycle, a switching interval of one clock cycle is reserved each time the original input stream and the delayed input stream are switched. The first multiplier performs a second multiplication operation or a third multiplication operation during the switching interval, and performs a first multiplication operation during the remaining clock cycles.

[0059] According to exemplary embodiments of this disclosure, the original input stream and the delayed input stream can be switched based on an input selection signal and a data selector. Here, the input selection signal may include an original signal and a delayed signal. Specifically, the original signal is used to cause the data selector to select the original input stream as the input of the first multiplier, and the delayed signal is used to cause the data selector to select the delayed input stream as the input of the first multiplier. By using the delayed input stream and the input selection signal, the data scheduling of the REDC operation of the Montgomery algorithm can be optimized.

[0060] The following reference Figure 4 A detailed description of a dedicated circuit diagram for a hardware implementation of the Montgomery algorithm according to exemplary embodiments of the present disclosure is provided, showing how the X0·Y algorithm can be solved using the illustrated dedicated circuit. i and P·β i The problems caused by the calculation interval.

[0061] Figure 4 This is a dedicated circuit diagram illustrating a hardware implementation of the Montgomery algorithm according to an exemplary embodiment of the present disclosure.

[0062] Reference Figure 4 It can be used in multiplier X j ·Y i A dedicated circuit is set at the input terminal of the multiplier X, and the multiplier X is used by the dedicated circuit. j ·Y i ZhongX j The input stream is controlled. Specifically, an additional X stream can be created using registers. j The input stream, in which, for any given clock cycle, the data in the new input stream is the same as the original X. j The data presented in the input stream in the previous clock cycle, that is, the data in the new input stream is more than the original X. j The input stream lags behind by one clock cycle. Based on this, a data selector can be used to select the appropriate input stream according to the input selection signal generated by the scheduling circuit, thereby switching between the two input streams.

[0063] According to an exemplary embodiment of this disclosure, the original input stream and the delayed input stream can be switched twice within each computation cycle, such that each computation cycle includes two switching intervals. Here, one switching interval is used to perform a second multiplication operation, and the other switching interval is used to perform a third multiplication operation. The switching interval for performing the third multiplication operation lags behind the switching interval for performing the second multiplication operation by at least a predetermined number of clock cycles, to satisfy X0·Y i With P·β i The condition that there must be a k-clock cycle interval between them.

[0064] According to an exemplary embodiment of this disclosure, the switching interval may include a first switching interval when switching from the original input stream to the delayed input stream and a second switching interval when switching from the delayed input stream to the original input stream.

[0065] According to an exemplary embodiment of this disclosure, the following steps can be performed cyclically until the REDC operation ends: A first multiplication operation is performed using a first multiplier based on the original input stream; when the first multiplier has performed the first multiplication operation for a predetermined number of clock cycles, the original input stream and the delayed input stream are switched; a third multiplication operation is performed using the first multiplier at a first switching interval; a first multiplication operation is performed using the first multiplier based on the delayed input stream; when the first multiplier has performed the first multiplication operation for a difference of a first number and a predetermined number of clock cycles, the original input stream and the delayed input stream are switched; a second multiplication operation is performed using the first multiplier at a second switching interval. Referring below... Figure 3c The present disclosure describes in detail the steps of performing a second multiplication operation or a third multiplication operation by a first multiplier during a switching interval and performing a first multiplication operation during the remaining clock cycles, according to exemplary embodiments of the present disclosure.

[0066] Reference Figure 3c For multiplier X j ·Y i X0·Y i With P·β i The calculation is incorporated into 2n switching intervals. Specifically, the multiplier X... j ·Y i X can be executed first using the raw input stream. j ·Y i The calculation, when multiplier X j ·Y i When a calculation is performed for k clock cycles using the raw input stream, the multiplier X can be... j ·Y i The input is switched from the original input stream to a delayed input stream, and the multiplier X... j ·Y i P·β can be executed within one clock cycle of the switching interval. i The calculation is performed, and then starting from the next clock cycle of the switching interval, the multiplier X... j ·Y i X can be executed using a delayed input stream. j ·Y i The calculation, when multiplier X j ·Y i When a calculation is performed for mk clock cycles using a delayed input stream, the multiplier X can be... j ·Y i The input is switched from a delayed input stream to a raw input stream, and the multiplier X...j ·Y i X0·Y can be executed within one clock cycle of the switching interval. i The calculation is performed, and then starting from the next clock cycle of the switching interval, the multiplier X... j ·Y i X can be executed using the raw input stream j ·Y i The calculation is repeated in this way until the REDC operation ends.

[0067] More specifically, such as Figure 3c The clock cycle diagram shown assumes that k is 31 and m is 128. Multiplier X j ·Y i First, X is executed using the raw input stream from clock cycle 1 to clock cycle 31. j ·Y i The calculation; then the multiplier X j ·Y i The input is switched from the original input stream to a delayed input stream, and the multiplier X... j ·Y i P·β is executed during the switching interval of 32 clock cycles. i The calculation; then the multiplier X j ·Y i X is executed using a delayed input stream from clock cycle 33 to clock cycle 129. j ·Y i The calculation; then the multiplier X j ·Y i The input is switched from a delayed input stream to a raw input stream, and the multiplier X... j ·Y i Execute X0·Y during the switching interval of 130 clock cycles. i The calculation; then the multiplier X j ·Y i X is executed using the raw input stream from clock cycle 131 to clock cycle 161. j ·Y i The calculation is repeated until the REDC operation ends.

[0068] Therefore, it can be seen that, through the dedicated circuit described above, X can be... j ·Y i While multiplication operations are performed continuously, ensure that X0·Y i With P·β i There must be at least k clock cycles between them.

[0069] According to exemplary embodiments of this disclosure, a second multiplication operation lasting two clock cycles and a third multiplication operation lasting one clock cycle may be performed by the first multiplier before the first multiplication operation is performed by the first multiplier, thereby ensuring that subsequent multiplication operations are performed in an orderly manner. As an example, such as... Figure 3c The clock cycle demonstration diagram shown allows the second multiplication operation X0·Y0, the third multiplication operation P·β0, and the second multiplication operation X1·Y0 to be executed sequentially by the first multiplier before clock cycle 1, thus ensuring that subsequent multiplication operations proceed in an orderly manner.

[0070] Return to reference Figure 2 In step S203, the fourth multiplication operation can be performed by the second multiplier. This disclosure does not limit the execution order of steps S202 and S203. For example, steps S202 and S203 can be executed simultaneously, sequentially, or in reverse order within the calculation cycle of the REDC operation of the Montgomery algorithm. Specifically, the execution order of the multiplication operations described above can be, but is not limited to, performing the second multiplication operation first, then the third multiplication operation, followed by the fourth multiplication operation and the first multiplication operation.

[0071] The hardware implementation method of the Montgomery algorithm according to the exemplary embodiments of this disclosure can improve the efficiency of multiplier usage without affecting the overall acceleration performance, thereby reducing the number of multipliers used in a computational unit of a Montgomery algorithm REDC operation to two, and thus greatly improving the performance of hardware accelerators based on the Montgomery algorithm.

[0072] Figure 5 This is a block diagram illustrating a hardware implementation apparatus for the Montgomery algorithm according to an exemplary embodiment of the present disclosure.

[0073] Reference Figure 5 The hardware implementation apparatus 500 of the Montgomery algorithm according to an exemplary embodiment of the present disclosure may include an operation permutation unit 501, a first multiplication unit 502, and a second multiplication unit 503.

[0074] The operation substitution unit 501 can replace the second clock cycle with an additional clock cycle for multiplication operations by adjusting the calculation process of the REDC operation.

[0075] The first multiplication unit 502 can perform a first multiplication operation, a second multiplication operation, and a third multiplication operation through the first multiplier. Here, the first multiplication operation may include a first multiplier and a second multiplier.

[0076] According to an exemplary embodiment of this disclosure, the first multiplication operation may include a first number of first multipliers and a second number of second multipliers, where the first number may be m, the second number may be n, and the values ​​of m and n may be determined by those skilled in the art based on the actual calculation situation. Further, any one of the calculation cycles in each REDC operation may include: a first number of clock cycles for performing the first multiplication operation, a clock cycle for performing the second multiplication operation, and a clock cycle for performing the third multiplication operation.

[0077] According to an exemplary embodiment of this disclosure, the first multiplication unit 502 can perform a first multiplication operation, a second multiplication operation, and a third multiplication operation in a time-sharing manner during a first clock cycle and additional clock cycles via a first multiplier. Here, for the first multiplication operation, the original input stream includes an additional first multiplier twice the number of additional clock cycles. Specifically, the original input stream includes two adjacent additional first multipliers at the end of each data cycle.

[0078] According to an exemplary embodiment of this disclosure, the first multiplication unit 502 can input the original input stream of the first multiplier into a register to obtain a delayed input stream of the first multiplier. Here, the delayed input stream lags behind the original input stream by one clock cycle.

[0079] According to an exemplary embodiment of this disclosure, the first multiplication unit 502 can input the original input stream and the delayed input stream into a data selector to switch between the original input stream and the delayed input stream, so as to input one of the original input stream and the delayed input stream into the first multiplier. Based on the clock cycle in which the delayed input stream lags behind the original input stream and the additional clock cycle, a switching interval of one clock cycle is reserved each time the original input stream and the delayed input stream are switched. The first multiplier performs a second multiplication operation or a third multiplication operation during the switching interval, and performs a first multiplication operation during the remaining clock cycles.

[0080] According to an exemplary embodiment of this disclosure, the first multiplication unit 502 can switch between a raw input stream and a delayed input stream based on an input selection signal and a data selector. Here, the input selection signal may include a raw signal and a delayed signal. Specifically, the raw signal is used to cause the data selector to select the raw input stream as the input of the first multiplier, and the delayed signal is used to cause the data selector to select the delayed input stream as the input of the first multiplier.

[0081] According to an exemplary embodiment of this disclosure, the first multiplication unit 502 may switch between the original input stream and the delayed input stream twice in each calculation cycle, such that each calculation cycle includes two switching intervals. Here, one switching interval is used to perform a second multiplication operation, and the other switching interval is used to perform a third multiplication operation, and the switching interval for performing the third multiplication operation lags behind the switching interval for performing the second multiplication operation by at least a predetermined number of clock cycles. Further, the switching interval may include a first switching interval when switching from the original input stream to the delayed input stream and a second switching interval when switching from the delayed input stream to the original input stream.

[0082] According to an exemplary embodiment of this disclosure, the first multiplication unit 502 may cyclically execute the following steps until the REDC operation ends: performing a first multiplication operation based on the original input stream using a first multiplier; switching between the original input stream and the delayed input stream when the first multiplier has performed the first multiplication operation for a predetermined number of clock cycles; performing a third multiplication operation using the first multiplier at a first switching interval; performing a first multiplication operation based on the delayed input stream using the first multiplier; switching between the original input stream and the delayed input stream when the first multiplier has performed the first multiplication operation for a difference of a first number and a predetermined number of clock cycles; and performing a second multiplication operation using the first multiplier at a second switching interval.

[0083] According to an exemplary embodiment of this disclosure, the first multiplication unit 502 may perform a second multiplication operation for two clock cycles and a third multiplication operation for one clock cycle before performing the first multiplication operation through the first multiplier, thereby enabling subsequent multiplication operations to proceed in an orderly manner.

[0084] The second multiplication unit 503 can perform the fourth multiplication operation through the second multiplier.

[0085] The hardware implementation method and hardware implementation apparatus of the Montgomery algorithm according to the exemplary embodiments of the present disclosure can improve the efficiency of multiplier usage without affecting the overall acceleration performance, thereby reducing the number of multipliers used in a computational unit of a Montgomery algorithm REDC operation to two, and thus greatly improving the performance of hardware accelerators based on the Montgomery algorithm.

[0086] The above has been referred to Figures 1 to 5 A hardware implementation method and hardware implementation apparatus for the Montgomery algorithm according to exemplary embodiments of the present disclosure are described.

[0087] Figure 5The individual units in the hardware implementation of the Montgomery algorithm shown can be configured as software, hardware, firmware, or any combination thereof to perform specific functions. For example, each unit may correspond to a dedicated integrated circuit, pure software code, or a module combining software and hardware. Furthermore, one or more functions implemented by each unit can also be uniformly executed by components in a physical entity device (e.g., a processor, client, or server).

[0088] In addition, refer to Figure 2 The hardware implementation method of the described Montgomery algorithm can be implemented by a program (or instructions) recorded on a computer-readable storage medium. For example, according to an exemplary embodiment of the present disclosure, a computer-readable storage medium storing instructions may be provided, wherein when the instructions are executed by at least one computing device, the at least one computing device causes the at least one computing device to perform the hardware implementation method of the Montgomery algorithm according to the present disclosure.

[0089] The computer program in the aforementioned computer-readable storage medium can run in an environment deployed in computer devices such as clients, hosts, agent devices, and servers. It should be noted that the computer program can also be used to perform additional steps beyond those described above, or to perform more specific processing while performing the above steps. The details of these additional steps and further processing are already described in the reference... Figure 2 The relevant methods were mentioned in the description of the process, so they will not be repeated here to avoid repetition.

[0090] It should be noted that each unit in the hardware implementation apparatus of the Montgomery algorithm according to the exemplary embodiments of the present disclosure can rely entirely on the operation of the computer program to realize the corresponding function. That is, each unit corresponds to each step in the functional architecture of the computer program, so that the entire system is called through a special software package (e.g., a lib library) to realize the corresponding function.

[0091] on the other hand, Figure 5 The units shown can also be implemented using hardware, software, firmware, middleware, microcode, or any combination thereof. When implemented in software, firmware, middleware, or microcode, the program code or code segment used to perform the corresponding operation can be stored in a computer-readable medium such as a storage medium, so that the processor can perform the corresponding operation by reading and running the corresponding program code or code segment.

[0092] For example, exemplary embodiments of this disclosure can also be implemented as a computing device including a storage component and a processor, wherein the storage component stores a set of computer-executable instructions, and when the set of computer-executable instructions is executed by the processor, a hardware implementation method of the Montgomery algorithm according to exemplary embodiments of this disclosure is executed.

[0093] Specifically, the computing device can be deployed on a server or client, or on node devices in a distributed network environment. Furthermore, the computing device can be a PC, tablet, personal digital assistant, smartphone, web application, or other device capable of executing the aforementioned set of instructions.

[0094] Here, the computing device is not necessarily a single computing device, but can be any collection of devices or circuits capable of executing the aforementioned instructions (or instruction sets) individually or in combination. The computing device can also be part of an integrated control system or system manager, or can be configured to interconnect with a portable electronic device locally or remotely (e.g., via wireless transmission) through an interface.

[0095] In a computing device, a processor may include a central processing unit (CPU), a graphics processing unit (GPU), a programmable logic device, a dedicated processor system, a microcontroller, or a microprocessor. By way of example and not limitation, a processor may also include an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, etc.

[0096] Some operations described in the hardware implementation method of the Montgomery algorithm according to exemplary embodiments of this disclosure can be implemented in software, some operations can be implemented in hardware, and these operations can also be implemented in a combination of software and hardware.

[0097] The processor can execute instructions or code stored in one of the storage components, which can also store data. Instructions and data can also be sent and received over a network via a network interface device, which can employ any known transport protocol.

[0098] Storage components can be integrated with the processor, for example, by placing RAM or flash memory within an integrated circuit microprocessor. Alternatively, storage components can include separate devices, such as external disk drives, storage arrays, or other storage devices that can be used by any database system. Storage components and the processor can be operatively coupled, or can communicate with each other, for example, via I / O ports, network connections, etc., enabling the processor to read files stored in the storage component.

[0099] In addition, the computing device may include a video display (such as a liquid crystal display) and a user interaction interface (such as a keyboard, mouse, touch input device, etc.). All components of the computing device may be interconnected via a bus and / or network.

[0100] The hardware implementation method of the Montgomery algorithm according to exemplary embodiments of this disclosure can be described as various interconnected or coupled functional blocks or functional diagrams. However, these functional blocks or functional diagrams can be equally integrated into a single logic device or operate according to non-precise boundaries.

[0101] Therefore, refer to Figure 2 The hardware implementation of the described Montgomery algorithm can be achieved through a system comprising at least one computing device and at least one storage device for storing instructions.

[0102] According to an exemplary embodiment of the present disclosure, at least one computing device is a computing device for executing a hardware implementation method of the Montgomery algorithm according to an exemplary embodiment of the present disclosure, and a storage device stores a set of computer-executable instructions. When the set of computer-executable instructions is executed by the at least one computing device, the method for executing the reference algorithm is... Figure 2 The hardware implementation method of the described Montgomery algorithm.

[0103] The foregoing has described various exemplary embodiments of this disclosure. It should be understood that the foregoing description is exemplary only and not exhaustive, and this disclosure is not limited to the disclosed exemplary embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A hardware implementation method for the Montgomery algorithm, wherein, The REDC operation of the Montgomery algorithm includes a first multiplication operation, a second multiplication operation, a third multiplication operation, a fourth multiplication operation, and a subtraction operation. The third multiplication operation depends on the result of the second multiplication operation. The clock cycle for the REDC operation includes a first clock cycle for the multiplication operation and a second clock cycle for the subtraction operation. The hardware implementation method includes: By adjusting the calculation process of the REDC operation, the second clock cycle is replaced with an additional clock cycle for the multiplication operation; The first multiplication operation, the second multiplication operation, and the third multiplication operation are performed by the first multiplier, wherein the first multiplication operation includes a first multiplier and a second multiplier; The fourth multiplication operation is performed by the second multiplier. The execution of the first multiplication operation, the second multiplication operation, and the third multiplication operation through the first multiplier includes: The first multiplier performs the first multiplication operation, the second multiplication operation, and the third multiplication operation in a time-sharing manner during the first clock cycle and an additional clock cycle. The step of performing the first multiplication operation, the second multiplication operation, and the third multiplication operation in a time-sharing manner during the first clock cycle and the additional clock cycle includes: The original input stream of the first multiplier is input into a register to obtain a delayed input stream of the first multiplier, wherein the delayed input stream lags behind the original input stream by one clock cycle. The original input stream and the delayed input stream are input to a data selector to switch between the original input stream and the delayed input stream, so that one of the original input stream and the delayed input stream is input to the first multiplier. Based on the clock cycle of the delayed input stream lagging behind the original input stream and the additional clock cycle, a switching interval of one clock cycle is reserved each time the original input stream and the delayed input stream are switched. The first multiplier performs the second multiplication operation or the third multiplication operation during the switching interval, and performs the first multiplication operation during the remaining clock cycles.

2. The hardware implementation method as described in claim 1, wherein, The first multiplication operation includes a first number of first multipliers and a second number of second multipliers, and any one of the calculation cycles of each REDC operation includes: the first number of clock cycles for performing the first multiplication operation, one clock cycle for performing the second multiplication operation, and one clock cycle for performing the third multiplication operation. The switching between the original input stream and the delayed input stream includes: The original input stream and the delayed input stream are switched twice within each calculation cycle, such that each calculation cycle includes two switching intervals, wherein one switching interval is used to perform the second multiplication operation and the other switching interval is used to perform the third multiplication operation, and the switching interval for performing the third multiplication operation lags behind the switching interval for performing the second multiplication operation by at least a predetermined number of clock cycles.

3. The hardware implementation method as described in claim 2, wherein, The switching between the original input stream and the delayed input stream includes: Based on the input selection signal and the data selector, the original input stream and the delayed input stream are switched, wherein the input selection signal includes an original signal and a delayed signal. The original signal is used to cause the data selector to select the original input stream as the input of the first multiplier. The delay signal is used to cause the data selector to select the delayed input stream as the input of the first multiplier.

4. The hardware implementation method as described in claim 2, wherein, The original input stream includes an additional first multiplier twice the number of additional clock cycles of the second quantity, wherein the original input stream includes two adjacent additional first multipliers at the end of each data cycle.

5. The hardware implementation method as described in claim 4, wherein, The switching interval includes a first switching interval when switching from the original input stream to the delayed input stream and a second switching interval when switching from the delayed input stream to the original input stream.

6. The hardware implementation method as described in claim 5, wherein, The step of performing the second multiplication operation or the third multiplication operation through the first multiplier during the switching interval, and performing the first multiplication operation in the remaining clock cycles, includes: The following steps are repeated until the REDC operation is completed: Based on the original input stream, a first multiplication operation is performed by the first multiplier; When the first multiplier performs the first multiplication operation for a predetermined number of clock cycles, the original input stream and the delayed input stream are switched. The third multiplication operation is performed by the first multiplier during the first switching interval; Based on the delayed input stream, a first multiplication operation is performed by the first multiplier; When the first multiplier performs a first multiplication operation for a number of clock cycles that is the difference between the first number and the predetermined number, the original input stream and the delayed input stream are switched. The second multiplication operation is performed by the first multiplier during the second switching interval.

7. The hardware implementation method as described in claim 6, wherein, The step of performing the second multiplication operation or the third multiplication operation through the first multiplier during the switching interval, and performing the first multiplication operation during the remaining clock cycles, further includes: Before performing the first multiplication operation through the first multiplier, the second multiplication operation is performed for two clock cycles and the third multiplication operation is performed for one clock cycle through the first multiplier, so that the subsequent multiplication operations are performed in an orderly manner.

8. A hardware implementation device for the Montgomery algorithm, wherein, The REDC operation of the Montgomery algorithm includes a first multiplication operation, a second multiplication operation, a third multiplication operation, a fourth multiplication operation, and a subtraction operation. The third multiplication operation depends on the result of the second multiplication operation. The clock cycle for the REDC operation includes a first clock cycle for the multiplication operation and a second clock cycle for the subtraction operation. The hardware implementation device includes: The operation substitution unit is configured to replace the second clock cycle with an additional clock cycle for multiplication operations by adjusting the calculation flow of the REDC operation. A first multiplication unit is configured to perform a first multiplication operation, a second multiplication operation, and a third multiplication operation via a first multiplier. The first multiplication operation includes a first multiplier and a second multiplier. The first, second, and third multiplication operations are performed time-divisionally within a first clock cycle and an additional clock cycle. The original input stream of the first multiplier is input to a register to obtain a delayed input stream of the first multiplier. The delayed input stream lags behind the original input stream by one clock cycle. The original input stream and the delayed input stream are input to a data selector to switch between them, allowing one of them to be input to the first multiplier. Based on the clock cycle in which the delayed input stream lags behind the original input stream and the additional clock cycle, a one-clock-cycle switching interval is reserved each time the original input stream and the delayed input stream are switched. The first multiplier performs either the second or third multiplication operation during this switching interval and performs the first multiplication operation in the remaining clock cycles. The second multiplication unit is configured to perform the fourth multiplication operation via the second multiplier.

9. The hardware implementation apparatus as described in claim 8, wherein, The first multiplication operation includes a first number of first multipliers and a second number of second multipliers, and any one of the calculation cycles of each REDC operation includes: the first number of clock cycles for performing the first multiplication operation, one clock cycle for performing the second multiplication operation, and one clock cycle for performing the third multiplication operation. The first multiplication unit is configured as follows: The original input stream and the delayed input stream are switched twice within each calculation cycle, such that each calculation cycle includes two switching intervals, wherein one switching interval is used to perform the second multiplication operation and the other switching interval is used to perform the third multiplication operation, and the switching interval for performing the third multiplication operation lags behind the switching interval for performing the second multiplication operation by at least a predetermined number of clock cycles.

10. The hardware implementation apparatus as described in claim 9, wherein, The first multiplication unit is configured as follows: Based on the input selection signal and the data selector, the original input stream and the delayed input stream are switched, wherein the input selection signal includes an original signal and a delayed signal. The original signal is used to cause the data selector to select the original input stream as the input of the first multiplier. The delay signal is used to cause the data selector to select the delayed input stream as the input of the first multiplier.

11. The hardware implementation apparatus as described in claim 9, wherein, The original input stream includes an additional first multiplier twice the number of additional clock cycles of the second quantity, wherein the original input stream includes two adjacent additional first multipliers at the end of each data cycle.

12. The hardware implementation apparatus as described in claim 11, wherein, The switching interval includes a first switching interval when switching from the original input stream to the delayed input stream and a second switching interval when switching from the delayed input stream to the original input stream.

13. The hardware implementation apparatus as described in claim 12, wherein, The first multiplication unit is configured as follows: The following steps are repeated until the REDC operation is completed: Based on the original input stream, a first multiplication operation is performed by the first multiplier; When the first multiplier performs the first multiplication operation for a predetermined number of clock cycles, the original input stream and the delayed input stream are switched. The third multiplication operation is performed by the first multiplier during the first switching interval; Based on the delayed input stream, a first multiplication operation is performed through the first multiplier; When the first multiplier performs a first multiplication operation for a first number of clock cycles that is the difference between the first number and the predetermined number, the original input stream and the delayed input stream are switched. The second multiplication operation is performed by the first multiplier during the second switching interval.

14. The hardware implementation apparatus as described in claim 13, wherein, The first multiplication unit is configured as follows: Before performing the first multiplication operation through the first multiplier, the second multiplication operation is performed for two clock cycles and the third multiplication operation is performed for one clock cycle through the first multiplier, so that the subsequent multiplication operations are performed in an orderly manner.

15. A system comprising at least one computing device and at least one storage device for storing instructions, wherein, When the instructions are executed by the at least one computing device, they cause the at least one computing device to perform the Montgomery hardware implementation method as described in any one of claims 1 to 7.

16. A computer-readable storage medium for storing instructions, wherein, When the instructions are executed by at least one computing device, they cause the at least one computing device to perform the Montgomery hardware implementation method as described in any one of claims 1 to 7.

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