Display device

Abstract

A display device according to embodiments of this disclosure may include: a display panel; a data driver configured to drive by dividing a driving period into an active period and a blank period, and applying a stop voltage during the blank period; and a controller configured to: change the driving frequency in frames according to an input image, and operate the frame as a refresh frame for writing data voltage according to the driving frequency, or operate by dividing the frame into refresh frames and hold frames, wherein the voltage level of the stop voltage changes according to the driving frequency. Therefore, stripe defects can be prevented and the uniformity of the display panel can be improved by reducing the non-uniformity of the stop voltage, thereby improving image quality.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0130006, filed on September 30, 2021, which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] Embodiments of this disclosure relate to display devices, and more specifically, to display devices capable of improving uniformity degradation caused by non-uniformity such as flicker and stains. Background Technology

[0004] Display devices that display various information on a screen are a crucial technology in the information and communication age, and are evolving towards thinner, lighter, more portable, and higher-performance designs. Therefore, display devices that can be manufactured in a lightweight and thin form have become a focus of attention. Display devices using self-emissive elements are advantageous in terms of power consumption due to their low-voltage operation, and also offer excellent high-speed response, high luminous efficiency, viewing angle, and contrast ratio, and are being researched as next-generation display devices. Display devices realize images through multiple sub-pixels arranged in a matrix. Each of the multiple sub-pixels includes a light-emitting device and pixel circuitry, such as multiple transistors independently driving the light-emitting device.

[0005] Specific examples of such flat panel displays can include liquid crystal displays (LCDs), quantum dot displays (QDs), field emission displays (FEDs), and organic light-emitting diode (OLED) displays. OLED displays do not require a separate light source and are highly regarded as a means of compact devices and vivid color display. OLED displays use organic light-emitting diodes (OLEDs) to emit light themselves and have advantages such as fast response time, high contrast, high luminous efficiency, high brightness, and wide viewing angle.

[0006] Organic light-emitting diode (OLED) display devices, including OLEDs, offer various advantages because they display images based on light generated from light-emitting devices within pixels. However, uniformity defects can arise due to non-uniformity such as flicker and smudges caused by coupling between internal lines of pixels during driving or by the operating conditions of the driving signal. This can be a factor reducing satisfaction with the image quality of the display device.

[0007] Therefore, various driving techniques have been developed to address image anomalies, and to improve image quality, it is necessary to improve operational performance by controlling the driving conditions of pixels. Summary of the Invention

[0008] The purpose of embodiments of this disclosure is to provide a display device capable of improving flicker and uniformity degradation by controlling the driving voltage conditions of pixel circuits.

[0009] In one aspect of this disclosure, a display device is provided, comprising: a display panel including a plurality of pixels connected to data lines and gate lines; a data driver configured to: drive by dividing a driving period into an active period for applying a data voltage to the data lines and a blank period for which no data voltage is applied, and applying a parking voltage during the blank period; a gate driver configured to apply a scan signal to the gate lines; and a controller configured to: drive by changing a driving frequency in units of frames according to an input image, and operate the frame as a refresh frame for writing the data voltage according to the driving frequency, or operate by dividing the frame into refresh frames and holding frames for holding the data voltage written in the refresh frames, wherein the voltage level of the parking voltage can be changed according to the driving frequency.

[0010] In another aspect of this disclosure, a display device is provided, comprising: a data driver configured to provide a data voltage during an active period and a stop voltage during a blank period; and a controller configured to operate a frame as a refresh frame for writing the data voltage and / or a hold frame for holding the data voltage written in the refresh frame, depending on a drive frequency, wherein the stop voltage has different voltage levels in the refresh frame and the hold frame.

[0011] In addition to the technical issues mentioned above, other features and advantages of this disclosure may be described below, or will be clearly understood by those skilled in the art based on such description.

[0012] According to embodiments of this disclosure, stripe defects can be prevented and the uniformity of the display panel can be improved by reducing the non-uniformity of the stop voltage, thereby improving image quality.

[0013] The effects of this disclosure are not limited to those exemplified above, and may include many other effects. Attached Figure Description

[0014] Figure 1 This is a block diagram of a display device according to an embodiment of the present disclosure.

[0015] Figures 2A to 2C This is a circuit diagram showing the pixel circuitry of a display device according to an embodiment of the present disclosure.

[0016] Figure 3A and Figure 3B This is a diagram illustrating the driving of pixel circuits in a display device for explaining embodiments of the present disclosure.

[0017] Figure 4 The operation of a scan signal of a frame in a display device according to an embodiment of the present disclosure is shown.

[0018] Figure 5 The data voltage and stop voltage in a display device according to an embodiment of the present disclosure are shown.

[0019] Figure 6A and Figure 6B A refresh frame and a hold frame according to the refresh rate are shown in a display device according to an embodiment of the present disclosure.

[0020] Figure 7A and Figure 7B The stop voltages for refresh frames and hold frames in a display device according to an embodiment of the present disclosure are shown. Detailed Implementation

[0021] The advantages, features, and methods of this disclosure will become apparent from the following detailed description of the embodiments, taken in conjunction with the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below, but will be implemented in various different forms. These embodiments are provided merely to illustrate that the disclosure of this specification is complete and to fully inform those skilled in the art of the scope of the invention, and the specification will be defined by the scope of the claims.

[0022] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings for illustrating the embodiments in this specification are exemplary, and the embodiments in this specification are not limited to those shown. Furthermore, when describing embodiments, if it is determined that a detailed description of the relevant known art might unnecessarily obscure the essential points of the embodiment, its detailed description will be omitted.

[0023] In this specification, the terms “comprising,” “having,” “constituting,” “including,” etc., are used, and unless “only” is used, they should be understood to mean that other parts or elements can be added. When elements are expressed in the singular, unless otherwise expressly stated, they should be understood to include, and contain, the plural.

[0024] In addition, when interpreting elements, even if there is no separate explicit description, they should be interpreted as including the range of error.

[0025] In descriptions relating to spatial relationships, such as when the terms “on top of,” “above,” “above,” “below,” “under,” “below,” “below,” “near,” “close to,” or “adjacent” are used to describe the positional relationship between two elements, the positional relationship should be interpreted as one or more elements also being “placed” between these elements, unless terms such as “directly” or “only” are used.

[0026] When describing temporal relationships, such as when the temporal relationship is described as "after", "following", "next", "then", "before", it can include discontinuous cases unless "immediately following" or "directly" is used.

[0027] When terms such as "first," "second," etc., are used herein to describe various elements or components, it should be understood that these elements or components are not limited thereto. These terms are used only herein to distinguish one element from other elements. Therefore, in the technical concept of this disclosure, the first element mentioned below can be a second element.

[0028] The term "at least one" should be understood to include all possible combinations of one or more related elements. For example, "at least one of the first element, the second element, and the third element" could mean all combinations of two or more of the first, second, and third elements, as well as each of the first, second, or third elements.

[0029] Features of each embodiment in this specification can be combined or coupled in part or in whole with each other, and can be technically linked or operated in various ways. Furthermore, each embodiment can be implemented independently of each other, or can be implemented together in a related relationship.

[0030] In the following description, embodiments of the display device according to this disclosure will be described with reference to the accompanying drawings. When adding reference numerals to components in each drawing, the same components will be represented by the same reference numerals as much as possible, even if they are indicated in different drawings. Furthermore, since the proportions of the components shown in the drawings may differ from the actual proportions for ease of description, the proportions shown in the drawings are not limited thereto.

[0031] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0032] Figure 1 This is a block diagram of a display device according to an embodiment of the present disclosure.

[0033] Reference Figure 1The display device 10 may include: a display panel 100 including a plurality of pixels; a gate driver 300 that provides a gate signal to each of the plurality of pixels; a data driver 400 that provides a data signal to each of the plurality of pixels; a light emission signal generator 500 for providing a light emission signal to each of the plurality of pixels; and a controller 200.

[0034] The controller 200 can process externally input RGB image data according to the size and resolution of the display panel 100, and provide the processed image data to the data driver 400. The controller 200 can use externally input synchronization signals SYNC, such as a dot clock signal CLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync, to generate multiple gate control signals GCS, data control signals DCS, and light emission control signals ECS. The generated multiple gate control signals GCS, data control signals DCS, and light emission control signals ECS can be provided to the gate driver 300, the data driver 400, and the light emission signal generator 500 to control the gate driver 300, the data driver 400, and the light emission signal generator 500 respectively.

[0035] Depending on the device to which the controller is installed, the controller 200 can be configured in conjunction with various processors such as microprocessors, mobile processors, application processors, etc.

[0036] The controller 200 can generate signals that allow pixels to be driven at various refresh rates. That is, the controller 200 can generate drive-related signals that allow pixels to be driven in a variable refresh rate (VRR) mode, or to switch between a first refresh rate and a second refresh rate. For example, the controller 200 can simply change the speed of a clock signal, generate a synchronization signal to generate horizontal or vertical spacing, or drive the gate driver 300 using a masking method to drive pixels at various refresh rates.

[0037] Each of multiple pixels P can be driven within a single frame by a combination of refresh frames and hold frames, depending on the refresh rate.

[0038] For example, if the refresh rate is driven at 120Hz, only the refresh frame can be driven, and if the refresh rate is driven at 10Hz, the refresh frame and the hold frame can be driven alternately. That is, within a frame, one refresh frame and multiple hold frames are configured as a group and can be driven repeatedly.

[0039] Additionally, the controller 200 can generate various signals for driving the pixel at a first refresh rate, and specifically, when driving the pixel at the first refresh rate, the controller 200 can generate a light emission control signal ECS so that the light emission signal generator 500 generates a light emission signal EM(n) with a first duty cycle. Thereafter, the controller 200 can operate to drive the pixel at a second refresh rate, and can generate various signals for driving the pixel at the second refresh rate. Specifically, when driving the pixel at the second refresh rate, the controller can generate a light emission control signal ECS such that the light emission signal generator 500 generates a light emission signal EM(n) with a second duty cycle different from the first duty cycle.

[0040] The gate driver 300 can provide the scan signal SC to the gate line GL according to the gate control signal GCS provided from the controller 200. Although Figure 1 The gate driver 300 is shown to be spaced apart from one side of the display panel 100, but the number and arrangement of the gate drivers 300 are not limited thereto. That is, the gate drivers 300 can be disposed on one or both sides of the display panel 100 using the gate in-plane (GIP) method.

[0041] The data driver 400 converts image data RGB into data voltage Vdata according to the data control signal DCS provided from the controller 200, and provides the converted data voltage Vdata to the pixels through the data line DL.

[0042] In the display panel 100, multiple gate lines GL, multiple light-emitting lines EL, and multiple data lines DL can intersect each other, and each of the multiple pixels can be connected to the gate lines GL, light-emitting lines EL, and data lines DL. Specifically, a pixel receives a gate signal from the gate driver 300 via the gate line GL, a data signal from the data driver 400 via the data line DL, a light-emitting signal EM(n) via the light-emitting line EL, and various power signals via power lines. Here, the gate line GL provides a scan signal SC, the light-emitting line EL provides the light-emitting signal EM(n), and the data line DL provides a data voltage Vdata. However, according to various embodiments, the gate line GL may include multiple scan signal lines, and the data line DL may additionally include multiple power lines VL. Furthermore, the light-emitting line EL may include multiple light-emitting signal lines. In addition, a pixel receives a high potential voltage or a first power voltage ELVDD and a low potential voltage or a second power voltage ELVSS. Additionally, a first bias voltage V1 and a second bias voltage V2 can be provided via one or more power lines VL.

[0043] Additionally, each pixel includes a light-emitting device (ELD) and a pixel circuit for controlling the driving of the ELD. Here, the ELD includes an anode, a cathode, and an organic light-emitting layer between the anode and cathode. The pixel circuit includes multiple switching devices, driving switching devices, and a capacitor. Here, the switching devices can be composed of TFTs, and in the pixel circuit, the driving TFT controls the amount of current supplied to the ELD based on the difference between the data voltage charged in the capacitor and a reference voltage, thereby adjusting the amount of light emitted by the ELD. Furthermore, the multiple switching TFTs receive a scan signal SC provided through the gate line GL and a light emission signal EM(n) provided through the light emission line EL to charge the capacitor with the data voltage Vdata.

[0044] The display device 10 according to embodiments of this disclosure may include a gate driver 300, a data driver 400, a light-emitting signal generator 500 for driving a display panel 100 including a plurality of pixels, and a controller 200 for controlling the gate driver 300, the data driver 400, and the light-emitting signal generator 500. Here, the light-emitting signal generator 500 may be configured to adjust the duty cycle of the light-emitting signal EM(n). For example, the light-emitting signal generator 500 may include a shift register and a latch for adjusting the duty cycle of the light-emitting signal EM(n). When the pixel circuit is driven at a first refresh rate according to the light-emitting control signal ECS generated by the controller 200, the light-emitting signal generator 500 may generate a light-emitting signal having a first duty cycle and provide the light-emitting signal to the pixel circuit. When the pixel circuit is driven at a second refresh rate, the light-emitting signal generator 500 may be configured to generate a light-emitting signal having a second duty cycle different from the first duty cycle and provide it to the pixel circuit.

[0045] Figures 2A to 2C This is a circuit diagram showing the pixel circuitry of a display device according to an embodiment of the present disclosure.

[0046] Figures 2A to 2C The pixel circuit shown is merely an example for illustration and is not limited thereto. Any pixel circuit can have a structure capable of controlling the light emission of the light-emitting device ELD by applying a light emission signal EM(n). For example, the pixel circuit may include an additional scan signal, a switching TFT connected thereto, and a switching TFT to which an additional initialization voltage is applied, and the connection relationships between the switching devices or the connection positions of the capacitors may be configured differently. That is, if the light emission of the light-emitting device ELD is controlled according to the change in the duty cycle of the light emission signal EM(n), and the light emission can be controlled according to the refresh rate, pixel circuits with various structures can be used. For example, various pixel circuits such as 3T1C, 4T1C, 6T1C, 7T1C, and 7T2C can be used. In the following description, for ease of description, the following will be described including... Figures 2A to 2C A display device with a 7T1C pixel circuit.

[0047] Reference Figure 2A Each of the plurality of pixels P may include a pixel circuit and a light-emitting device ELD connected to the pixel circuit, the pixel circuit including a driving transistor DT.

[0048] The pixel circuit can drive the light-emitting device ELD by controlling the drive current Id flowing through it. The pixel circuit may include a drive transistor DT, first transistors T1 through sixth transistors T6, and a storage capacitor C. ST Transistor DT and each of T1 through T6 may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode.

[0049] Transistor DT and each of T1 through T6 can be a PMOS transistor or an NMOS transistor. Figure 2A and Figure 2B In this implementation, the first transistor T1 is an NMOS transistor, while the other transistors DT and T2 to T6 are PMOS transistors. Additionally, in... Figure 2C In this embodiment, the first transistor T1 is also configured as a PMOS transistor.

[0050] In the following description, the case where the first transistor T1 is an NMOS transistor and the remaining transistors DT, T2 through T6 are PMOS transistors will be exemplarily described. Therefore, the first transistor T1 is turned on by applying a logic high voltage, and the other transistors DT, T2 through T6 are turned on by applying a logic low voltage.

[0051] According to the example, the first transistor T1 constituting the pixel circuit can be used as a compensation transistor, the second transistor T2 can be used as a data supply transistor, the third transistor T3 and the fourth transistor T4 can be used as light-emitting control transistors, and the fifth transistor T5 and the sixth transistor T6 can be used as bias transistors.

[0052] The light-emitting device (ELD) may include a pixel electrode (or anode electrode) and a cathode electrode. The pixel electrode of the light-emitting device (ELD) may be connected to a fifth node N5, and the cathode electrode may be connected to a second power voltage ELVSS.

[0053] The driving transistor DT may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode connected to the first node N1. The driving transistor DT may be based on the voltage of the first node N1 (or stored in the capacitor C described later). STThe data voltage in the middle provides a driving current Id to the light-emitting device ELD.

[0054] The first transistor T1 may include a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a gate electrode for receiving the first scan signal SC1(n). The first transistor T1 may be turned on in response to the first scan signal SC1(n) and may transmit a data signal Vdata to the first node N1. The first transistor T1 may be connected as a diode between the first node N1 and the third node N3 to sample the threshold voltage Vth of the driving transistor DT. The first transistor T1 may be a compensation transistor.

[0055] Capacitor C ST It can be connected or formed between the first node N1 and the fourth node N4. Capacitor C ST It can store or retain the provided data signal Vdata.

[0056] The second transistor T2 has a first electrode connected to the data line DL (or receiving the data signal Vdata), a second electrode connected to the second node N2, and a gate electrode for receiving the third scan signal SC3(n). The second transistor T2 can be turned on in response to the third scan signal SC3(n) and can transmit the data signal Vdata to the second node N2. The second transistor T2 can be a data supply transistor.

[0057] The third transistor T3 and the fourth transistor T4 (or the first light-emitting control transistor and the second light-emitting control transistor) can be connected between the first power voltage ELVDD and the light-emitting device ELD, and can form the current movement path through which the driving current Id generated by the driving transistor DT flows.

[0058] The third transistor T3 may include a first electrode connected to the fourth node N4 to receive the first power voltage ELVDD, a second electrode connected to the second node N2, and a gate electrode for receiving the light emission signal EM(n).

[0059] Similarly, the fourth transistor T4 may include a first electrode connected to the third node N3, a second electrode connected to the fifth node N5 (or the pixel electrode of the light-emitting device ELD), and a gate electrode for receiving the light-emitting signal EM(n).

[0060] The third transistor T3 and the fourth transistor T4 can be turned on in response to the light emission signal EM(n), and in this case, the drive current Id is provided to the light emission device ELD, and the light emission device ELD can emit light with a brightness corresponding to the drive current Id.

[0061] The fifth transistor T5 may include a first electrode connected to the third node N3, a second electrode receiving a first bias voltage V1, and a gate electrode receiving a second scan signal SC2(n).

[0062] The sixth transistor T6 may include a first electrode connected to the fifth node N5, a second electrode receiving a second bias voltage V2, and a gate electrode receiving a second scan signal SC2(n). Figure 2A In this configuration, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 are configured to jointly receive the second scan signal SC2(n). However, this disclosure is not limited thereto, and as such... Figure 2B and Figure 2C As shown, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 can be configured to receive separate scan signals SC2_a(n) and SC2_b(n) for independent control.

[0063] The sixth transistor T6 may include a first electrode connected to the fifth node N5, a second electrode connected to the second bias voltage V2, and a gate electrode for receiving the second scan signal SC2(n). The sixth transistor T6 can be turned on in response to the second scan signal SC2(n) before (or after) the light-emitting device ELD emits light, and the pixel electrode (or anode electrode) of the light-emitting device ELD can be initialized using the second bias voltage V2. The light-emitting device ELD may have a parasitic capacitor formed between the pixel electrode and the cathode electrode. Furthermore, the parasitic capacitor is charged while the light-emitting device ELD emits light, allowing the pixel electrode of the light-emitting device ELD to have a specific voltage. Therefore, by applying the second bias voltage V2 to the pixel electrode of the light-emitting device ELD using the sixth transistor T6, the amount of charge accumulated in the light-emitting device ELD can be initialized.

[0064] Figure 3 is used for illustration. Figures 2A to 2C The diagram shows the driving mechanism of the pixel circuit in the display device.

[0065] Referring to Figure 3, each of the plurality of pixels P can initialize the voltage charged or held in the pixel circuit. Specifically, the effects of the data voltage Vdata and drive voltage VDD stored in the previous frame can be removed. Therefore, each of the plurality of pixels P can display an image corresponding to the new data voltage Vdata.

[0066] The operation of a pixel circuit may include at least one initialization period, a sampling period, and an emission period, but this is just an example and is not necessarily limited to this order.

[0067] In the following text, reference will be made to Figure 3A and Figure 3BThe process of driving the pixel circuit for each initialization period, sampling period, and emission period is described in detail.

[0068] Figure 3A This shows the signals applied to the pixel circuitry during frame refresh. Figure 3A In this context, I represents the initialization period. The initialization period I is used to initialize the voltage at the gate electrode of the driving transistor DT.

[0069] During the initialization period, the first scan signal SC1(n) is a logic high voltage, and the first transistor T1 is turned on. The second scan signal SC2(n) is a logic low voltage, and the fifth transistor T5 and the sixth transistor T6 are turned on. When the first transistor T1 and the fifth transistor T5 are turned on, the gate electrode of the driving transistor DT connected to the first node N1 is initialized to the first bias voltage V1. Additionally, when the sixth transistor T6 is turned on, the pixel electrode (or anode electrode) of the light-emitting device ELD is initialized to the second bias voltage V2. However, as described above, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 can be configured to be controlled independently by receiving separate scan signals. That is, it is not always necessary to apply bias voltages to both the gate electrode of the driving transistor DT and the pixel electrode of the light-emitting device ELD simultaneously during the initialization period.

[0070] exist Figure 3A In this diagram, S represents the sampling period. During the sampling period, a logic low voltage is input to the third scan signal SC3(n), and the second transistor T2 is turned on. When the second transistor T2 is turned on, the current frame's Vdata voltage is applied to the drain electrode of the driving transistor DT, connected to the second node N2. The first transistor T1 remains on. Since the driving transistor DT is in a diode-connected state when the first transistor T1 is on, the voltage at the gate electrode of the driving transistor DT connected to the first node N1 becomes Vdata - |Vth|. That is, the first transistor T1 can be diode-connected between the first node N1 and the third node N3 to sample the threshold voltage Vth of the driving transistor DT.

[0071] exist Figure 3A In this context, E represents the emission period. The emission period is the time during which the light-emitting device (ELD) emits light using a drive current corresponding to the data voltage sampled after the desampling threshold voltage Vth.

[0072] During the light-emitting period, the light-emitting signal EM(n) is at a logic low voltage, and the third transistor T3 and the fourth transistor T4 are turned on.

[0073] When the third transistor T3 is turned on, the first power voltage ELVDD connected to the fourth node N4 is applied to the drain electrode of the driving transistor DT connected to the second node N2 through the third transistor T3. The driving current Id provided by the driving transistor DT to the light-emitting device ELD through the fourth transistor T4 is independent of the threshold voltage Vth of the driving transistor DT, thus compensating for the threshold voltage Vth of the driving transistor DT.

[0074] Figure 3B The signal applied to the pixel circuitry during frame holding is shown. Figure 3B In this context, R represents the reset period. The reset period R is the time period used to reset the voltage of the pixel electrode (or anode electrode) of the light-emitting device (ELD). During the hold frame, the first scan signal SC1(n) is fixed at a logic low voltage, while the third scan signal SC3(n) is fixed at a logic high voltage.

[0075] During the reset period, the second scan signal SC2(n) is at logic low, and the sixth transistor T6 is turned on. When the sixth transistor T6 is turned on, the pixel electrode (or anode electrode) of the light-emitting device ELD is initialized to the second bias voltage V2.

[0076] exist Figure 3B In this context, E represents the light emission period, and during the light emission period E of the hold frame, the light emission device ELD can emit light through a drive current corresponding to the data voltage sampled in the refresh frame.

[0077] Figure 4 The operation of a scan signal of a frame in a display device according to an embodiment of the present disclosure is shown.

[0078] Reference Figure 4 Each of the multiple pixels P is driven at a constant frequency and can be driven in a variable refresh rate (VRR) mode. In the variable refresh rate mode, when high-speed driving is required, the refresh rate used to update the data voltage Vdata is increased to operate the pixel circuitry, or when low-speed driving or low power consumption is required, the refresh rate is decreased to operate the pixel circuitry.

[0079] Each of multiple pixels P can be driven within a single frame by a combination of refresh frames and hold frames, depending on the refresh rate.

[0080] During low-speed driving, refresh frames and hold frames are driven alternately, and in hold frames, the pixel electrodes of the light-emitting device ELD are periodically initialized by the sixth transistor T6 of the pixel circuit, thereby reducing the hysteresis characteristics of the driving transistor DT.

[0081] In this case, the second scan signal SC2 provided from the gate driver 300 to drive the sixth transistor T6 can be driven at a frequency twice that provided from the controller 200 to the display panel 100.

[0082] For example, if the refresh rate is 120Hz, the drive frequency can operate at 120Hz, and the second scan signal SC2 used to turn on the TFT can operate at 240Hz. That is, since the second scan signal SC2 is driven at twice the drive frequency, the sixth transistor T6 is turned on more often, and the fifth node N5 is initialized more frequently, thereby improving the performance of the drive transistor DT.

[0083] Figure 5 The data voltage and stop voltage in a display device according to an embodiment of the present disclosure are shown.

[0084] Reference Figure 5 The period during which the data voltage Vdata is applied can be an active period, while the period during which no data voltage Vdata is applied can be a blank period. A refresh frame can be included during the active period, and both refresh frames and hold frames can be included during the blank period.

[0085] When the data line DL is in a floating state during the idle period, the adjacent first node N1 and second node N2 may be affected by coupling, which may cause flickering.

[0086] Therefore, for drives in variable refresh rate (VRR) modes, a stop voltage Vpark can be applied during the blank period after the data voltage Vdata is applied to the data line DL and before the data voltage Vdata of the next frame is applied.

[0087] In the case of applying a stop voltage Vpark at a specific voltage level, since the flicker performance of all gray levels needs to be controlled by a single stop voltage Vpark, non-uniformity such as blemishes in a specific gray level may be identified based on the relationship between the data voltage Vdata and the stop voltage Vpark. The resulting non-uniformity, such as blemishes, can be termed stop voltage non-uniformity (Vpark non-uniformity).

[0088] Furthermore, when a stop voltage Vpark of a specific voltage level is applied during the blank period, multiple pixels located in the central portion of the display panel 100 can operate because the second scan signal SC2, which is sequentially applied to the gate line GL, operates at twice the drive frequency, causing the sixth transistor T6 to be turned on. Therefore, coupling occurs between the data line DL and the fifth node N5, which may result in uneven stop voltage (Vpark non-uniformity) in the central region of the display panel 100, thereby reducing uniformity.

[0089] Depending on the voltage level of the stop voltage Vpark, stop voltage non-uniformity is more sensitive to low gray levels, and the light-emitting device ELD may emit light unnecessarily.

[0090] In other words, since the required stop voltage Vpark level varies depending on the brightness, an appropriate stop voltage Vpark needs to be applied to reduce flickering and stop voltage inhomogeneity (Vpark inhomogeneity).

[0091] Figure 6A and Figure 6B The refresh frame and hold frame according to the refresh rate are shown in a display device according to an embodiment of the present disclosure.

[0092] Reference Figure 6A and Figure 6B If the refresh rate is 120Hz, a frame can consist entirely of refresh frames, and if the refresh rate is 10Hz, a frame can consist of refresh frames and hold frames.

[0093] The refresh frame and hold frame are each 1 / 120 of a second (=8.33ms), and when the refresh rate is 120Hz, a set time period only includes the refresh frame, so a set time period is 1 / 120s (=8.33ms). When the refresh rate is 10Hz, a set time period is 1 / 10 of a second (=0.1s).

[0094] exist Figure 6A and Figure 6B In the process, a data voltage Vdata can be applied during the active period, and the active period can be the sampling period S of the refresh frame. During the blank period when no data voltage Vdata is applied, a stop voltage Vpark is applied. In this case, the stop voltage Vpark is determined as the voltage level that minimizes flicker during the hold frame. When the voltage difference between the data voltage Vdata and the stop voltage Vpark increases, the stop voltage non-uniformity becomes more pronounced. Therefore, due to the brightness variations that occur when repeating the data voltage Vdata and the stop voltage Vpark in a 120Hz refresh rate drive that only includes refresh frames, dark and bright stripe defects are identified. For example, this dark and bright stripe defect can be reduced by changing the voltage level of the stop voltage according to the drive frequency, thereby improving the uniformity of the display panel 100 and improving image quality. The following will refer to... Figure 7A and Figure 7B A specific example of changing the voltage level of the stop voltage according to the drive frequency is described; however, this disclosure is not limited thereto, and the voltage level of the stop voltage can be changed in other ways according to the drive frequency as needed.

[0095] Figure 7A and Figure 7B The stop voltages for refresh frames and hold frames in a display device according to an embodiment of the present disclosure are shown.

[0096] Reference Figure 7A and Figure 7B In order to reduce the unevenness of the stop voltage generated in the central part of the display panel 100 when driven at low brightness, the stop voltage Vpark can be set to have different voltage levels in refresh frames and hold frames.

[0097] Specifically, in the refresh frame, the voltage level of the optimal stop voltage Vpark_a can be set to reduce the voltage difference between the data voltage Vdata and the stop voltage Vpark, thereby improving stop voltage unevenness. Additionally, in the hold frame, the optimal stop voltage Vpark_b can be set to a voltage level designed to reduce flicker.

[0098] exist Figure 7A In a 120Hz refresh rate drive that only includes refresh frames, if the voltage difference between the data voltage Vdata and the stop voltage Vpark is set to be small, the visibility of brightness changes can be relatively reduced.

[0099] Therefore, in the refresh frame, taking into account the visual evaluation and the data voltage Vdata of each frequency band in multiple frequency bands, the optimal stop voltage Vpark_a can be set to the same voltage level as the data voltage Vdata of the low grayscale level.

[0100] First, the level of voltage non-uniformity at the stop voltage is assessed visually to determine the appropriate voltage level range for the optimal stop voltage Vpark_a. Then, the level of voltage non-uniformity at the stop voltage is assessed again for each frequency band to arrive at the optimal stop voltage Vpark_a.

[0101] In this case, the stop voltage Vpark can be changed and applied according to the process conditions and driving conditions. However, since the stop voltage is not uniformly identified in low-brightness areas, the stop voltage can preferably be set to the low grayscale data voltage Vdata. That is, in the refresh frame, the optimal stop voltage Vpark_a can be set to a data voltage Vdata of 15 grayscale levels or less.

[0102] exist Figure 7B In the context of driving at a 10Hz refresh rate that includes both refresh frames and hold frames, the stop voltage Vpark can have different voltage levels in refresh frames and hold frames.

[0103] In a refresh frame, the optimal stop voltage Vpark_a can be set to a data voltage Vdata of 15 gray levels or less, in the same way as a 120Hz refresh rate drive.

[0104] During the hold frame, only the stop voltage Vpark is applied, not the data voltage Vdata. Therefore, the optimal stop voltage Vpark_b can be set to a voltage level that reduces flicker. Since the display panel 100 is most susceptible to flicker when driven at a refresh rate of 10Hz, the optimal stop voltage Vpark_b is preferably derived based on a refresh rate of 10Hz.

[0105] If the same stop voltage Vpark is applied to both the refresh and hold frames, the luminance ratio due to the uneven stop voltage is approximately 26%. On the other hand, if optimal stop voltages Vpark_a and Vpark_b with different voltage levels are applied to the refresh and hold frames, respectively, the stripe defects can be improved and the luminance ratio can be reduced to approximately 7%.

[0106] Therefore, defects such as uneven stop voltage and flickering can be reduced by using optimal stop voltages Vpark_a and Vpark_b with different voltage levels in the refresh frame and hold frame, respectively.

[0107] In addition, by reducing the unevenness of the stop voltage, the uniformity of the display panel 100 can be improved, and the image quality can be improved.

[0108] The display device according to the embodiments of this specification can be described as follows.

[0109] A display device according to embodiments of the present disclosure may include: a display panel including a plurality of pixels connected to data lines and gate lines; a data driver configured to drive by dividing a driving period into an active period in which a data voltage is applied to the data lines and a blank period in which no data voltage is applied, and to apply a stop voltage during the blank period; a gate driver configured to apply a scan signal to the gate lines; and a controller configured to change the driving frequency in frames according to an input image, and to operate by dividing the frames into refresh frames or hold frames for writing data voltage, wherein the data voltage written in the refresh frame is held during the hold frame, and wherein the voltage level of the stop voltage can be changed according to the driving frequency.

[0110] The controller can be controlled based on a drive frequency that varies in frames according to the input image, such that a frame consists of one or more refresh frames, or a frame consists of one or more refresh frames and one or more hold frames (or is divided into one or more refresh frames and one or more hold frames). Here, a refresh frame can refer to a period (interval) during which data voltage is written, and a hold frame can refer to a period (interval) during which the data voltage written in the refresh frame is held.

[0111] In a display device according to an embodiment of the present disclosure, the stop voltage may have different voltage levels in the refresh frame and the hold frame.

[0112] In a display device according to an embodiment of the present disclosure, the stop voltage may be a first stop voltage Vpark_a having the same voltage level as the data voltage of the low grayscale level in a refresh frame.

[0113] In a display device according to an embodiment of the present disclosure, the first stop voltage Vpark_a may be a data voltage of 15 gray levels or less.

[0114] In a display device according to an embodiment of the present disclosure, the stop voltage may be a second stop voltage Vpark_b having a voltage level for reducing flicker in the hold frame.

[0115] In a display device according to an embodiment of the present disclosure, a second stop voltage Vpark_b can be derived based on a 10Hz refresh rate.

[0116] In a display device according to an embodiment of the present disclosure, the controller can change the driving frequency according to the refresh rate, and the gate driver can apply a scan signal with a frequency higher than the driving frequency.

[0117] In a display device according to an embodiment of the present disclosure, the frequency of the scanning signal may be twice the driving frequency.

[0118] A display device according to an embodiment of the present disclosure may include: a data driver configured to provide a data voltage during an active period and a stop voltage during a blank period; and a controller configured to operate a frame as a refresh frame for writing the data voltage and / or a hold frame for holding the data voltage written in the refresh frame, depending on a drive frequency, wherein the stop voltage has different voltage levels in the refresh frame and the hold frame.

[0119] The features, structures, effects, etc., described in the examples above in this disclosure are included in at least one embodiment of this disclosure, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc., shown in at least one example of this disclosure can be combined or modified by those skilled in the art relative to other examples. Therefore, content related to these combinations and modifications should be interpreted as being included within the scope of this disclosure.

[0120] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the invention is not necessarily limited to these embodiments, and various modifications can be made without departing from the spirit of the invention. Therefore, the embodiments disclosed in this disclosure are not intended to limit the spirit of the invention, but are illustrative by way of example, and the scope of the spirit of the invention is not limited by these embodiments. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive. The scope of protection of the invention should be interpreted by the appended claims, and all technical concepts within the scope of the claims should be interpreted as being included within the scope of the invention.

Claims

1. A display device, comprising: The display panel includes a plurality of pixels connected to data lines and gate lines; A data driver configured to drive by dividing the driving period into an active period in which a data voltage is applied to the data line and a blank period in which no data voltage is applied, and to apply a stop voltage during the blank period; A gate driver configured to apply a scan signal to the gate line; as well as A controller configured to: change the drive frequency in frames based on the input image, and operate the frame as a refresh frame for writing the data voltage according to the drive frequency, or operate by dividing the frame into refresh frames and hold frames, wherein the data voltage written in the refresh frame is held during the hold frame. Wherein, the voltage level of the stop voltage varies according to the driving frequency, and The pause voltage has different voltage levels in the refresh frame and the hold frame.

2. The display device according to claim 1, wherein, The stop voltage in the refresh frame is a first stop voltage having the same voltage level as the data voltage at the low grayscale level.

3. The display device according to claim 2, wherein, The first stop voltage is a data voltage of 15 gray levels or less.

4. The display device according to claim 1, wherein, The stop voltage in the hold frame is a second stop voltage with a voltage level for reducing flicker.

5. The display device according to claim 4, wherein, The second stop voltage is derived based on a 10Hz refresh rate.

6. The display device according to claim 1, wherein, The controller changes the drive frequency according to the refresh rate, and the gate driver applies a scan signal with a frequency higher than the drive frequency.

7. The display device according to claim 6, wherein, The frequency of the scanning signal is twice the driving frequency.

8. A display device, comprising: A data driver configured to provide a data voltage during an active period and a stop voltage during a quiet period; as well as The controller is configured to operate according to a drive frequency to treat frames as refresh frames for writing the data voltage and / or hold frames for holding the data voltage written in the refresh frames. The pause voltage has different voltage levels in the refresh frame and the hold frame.

9. The display device according to claim 8, wherein, The stop voltage in the refresh frame is a first stop voltage having the same voltage level as the data voltage of the low grayscale level, and The stop voltage in the hold frame is a second stop voltage with a voltage level for reducing flicker.

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