Display panel and methods for testing the display panel

Abstract

This application relates to display panels and methods for testing display panels. The method for testing a display panel includes: applying a test voltage to each of the data lines; applying a gate signal to each of the gate lines; measuring a sense voltage applied through pixel circuitry to one end of the light-emitting unit of each pixel in response to the gate signal and the test voltage; and determining, based on the sense voltage, whether the light-emitting elements within the light-emitting unit of each pixel are effectively connected in series.

Description

Technical Field

[0001] This disclosure relates to a display panel and a testing method thereof. Background Technology

[0002] With increasing interest in information display and growing demand for portable information media, the need for and commercialization of display devices has become a focus. Summary of the Invention

[0003] Technical issues

[0004] The embodiments of this disclosure provide a testing method for a display panel, which can determine whether the light-emitting elements are properly aligned or effectively aligned within the pixels of the display panel.

[0005] Embodiments of this disclosure provide a display panel capable of determining whether the light-emitting elements are effectively aligned for each pixel.

[0006] Technical solutions

[0007] The method for testing a display panel according to embodiments of the present disclosure can test a display panel. The display panel may include pixels electrically connected to gate lines and data lines, and each pixel may include a pixel circuit and a light-emitting unit. The pixel circuit is electrically connected to a corresponding gate line and a corresponding data line, and the light-emitting unit includes one end electrically connected to the pixel circuit. The method for testing the display panel may include: applying a test voltage to each of the data lines; applying a gate signal to each of the gate lines; measuring a sense voltage applied by the pixel circuit to one end of the light-emitting unit in each pixel in response to the gate signal and the test voltage; and determining, based on the sense voltage, whether the light-emitting elements in the light-emitting unit of each pixel are effectively connected in series.

[0008] In an implementation, the test voltage may be greater than the reference voltage, and the reference voltage may be equal to the voltage difference between the total operating voltage of the series-connected light-emitting elements and the operating voltage of one of the light-emitting elements.

[0009] In this implementation, the test voltage may be less than or equal to the total operating voltage of the light-emitting element.

[0010] In an implementation, determining whether the light-emitting elements are effectively connected in series may include: determining that all the light-emitting elements are effectively aligned when the sensed voltage is greater than the reference voltage.

[0011] In an implementation, determining whether the light-emitting elements are effectively connected in series may include: determining that at least one of the light-emitting elements is ineffectively aligned when the sensed voltage is less than or equal to the reference voltage.

[0012] In an embodiment, the method may further include: determining that at least one of the light-emitting elements is short-circuited when the sensed voltage is less than or equal to a reference voltage; and physically opening at least one of the light-emitting elements by a repair process.

[0013] In one implementation, applying a test voltage to each of the data lines may include: applying a test voltage to a first pad; and sequentially applying the test voltage to at least a portion of the data lines via a first demultiplexer electrically connected between the first pad and the data lines.

[0014] In one implementation, the first demultiplexer may include a sub-demultiplexer, and applying the test voltage sequentially to at least a portion of the data lines may include simultaneously applying the test voltage to a portion of the data lines via the sub-demultiplexer.

[0015] In one implementation, applying a gate signal to each of the gate lines may include: applying a gate signal to a second pad; and sequentially applying the gate signal to the gate line via a second demultiplexer electrically connected between the second pad and the gate line.

[0016] In one implementation, sequentially applying gate signals to gate lines may include sequentially applying gate signals to gate lines while simultaneously applying a test voltage to one of the data lines.

[0017] In an implementation, the gate line may include a scan line and a sensing scan line, and the display panel may further include sensing lines. The pixel circuitry may include a sensing transistor electrically connected between one end of the light-emitting unit and a corresponding one of the sensing lines. The sensing transistor includes a gate electrode electrically connected to a corresponding one of the sensing scan lines, and a gate signal may be simultaneously applied to one of the scan lines and one of the sensing scan lines by a second demultiplexer.

[0018] In one implementation, the first demultiplexer can sequentially connect at least a portion of the sensing lines to the third pad.

[0019] In one embodiment, measuring the sense voltage may include: applying a test voltage to the gate electrode of a driving transistor in a pixel circuit in response to a gate signal; providing an initialization voltage to an electrode of the driving transistor electrically connected to one end of a light-emitting unit via a sensing line; stopping the provision of the initialization voltage while applying the test voltage; and measuring the sense voltage based on the change in current flowing through the sensing line.

[0020] A display panel according to embodiments of the present disclosure may include: a substrate including a first region and a second region surrounding the first region; gate lines; data lines; pixels disposed in the first region and electrically connected to the gate lines and the data lines; a first pad and a second pad disposed in the second region; and a first demultiplexer disposed in the second region and electrically connected between the first pad and the data lines, wherein each of the pixels may include: a pixel circuit electrically connected to a corresponding one of the gate lines and a corresponding one of the data lines, and a light-emitting unit including one end electrically connected to the pixel circuit, and the light-emitting unit may include light-emitting elements connected in series.

[0021] In one implementation, the first demultiplexer can sequentially connect the first pads to at least a portion of the data line.

[0022] In one implementation, the first demultiplexer may include a sub-demultiplexer, and the first pad may be simultaneously connected to a portion of the data line via the sub-demultiplexer.

[0023] In an embodiment, the display panel may further include a second demultiplexer disposed in the second region and electrically connected between the second pad and the gate line.

[0024] In an embodiment, the gate line may include a scan line and a sensing scan line, the display panel may further include a sensing line, and the pixel circuit may include: a driving transistor electrically connected to one end of the light-emitting unit; a switching transistor electrically connected between the gate electrode of the driving transistor and a corresponding data line, and the switching transistor includes a gate electrode electrically connected to a corresponding scan line; and a sensing transistor electrically connected between one end of the light-emitting unit and a corresponding sensing line, the sensing transistor including a gate electrode electrically connected to a corresponding sensing scan line.

[0025] In this implementation, the scan lines can be connected to the sensing scan lines in the second region respectively.

[0026] In one embodiment, the display panel may further include a third pad disposed in the second region, and the first demultiplexer may sequentially connect at least a portion of the sensing lines to the third pad.

[0027] Beneficial effects

[0028] The method for testing a display panel according to embodiments of the present disclosure can determine whether the light-emitting elements in a pixel are effectively aligned (i.e., determine the alignment state of the light-emitting elements) based on the voltage level sensed at one end of the light-emitting unit (i.e., the node connected to the driving transistor) (or the threshold voltage sensed for the driving transistor).

[0029] The display panel according to embodiments of the present disclosure may further include a first demultiplexer that selectively connects data lines to test pads and can determine the alignment state of the light-emitting elements for each pixel.

[0030] Repair operations can be performed on misaligned light-emitting elements, thereby improving brightness deviations caused by misalignment of at least a portion of the light-emitting elements in a pixel, and improving display quality.

[0031] The effects of the embodiments disclosed herein are not limited to those described above, and various other effects are included in the specification. Attached Figure Description

[0032] Figure 1 This is a schematic block diagram illustrating a display panel according to an embodiment of the present disclosure.

[0033] Figure 2 and Figure 3 It is shown Figure 1 A schematic block diagram of an example display panel.

[0034] Figure 4 It is shown that it includes Figure 1 A schematic circuit diagram illustrating an example of pixels in a display panel.

[0035] Figure 5 It shows Figure 4 A schematic plan view of an example of pixels.

[0036] Figure 6 It is shown in Figure 4 A schematic waveform diagram of an example of a signal measured in a pixel.

[0037] Figure 7 It is shown that it includes Figure 1 A schematic circuit diagram of another example of pixels in a display panel.

[0038] Figure 8 It is shown in Figure 7 A schematic waveform diagram of an example of a signal measured in a pixel.

[0039] Figure 9 It is shown Figure 1 A schematic diagram of an example of a magnified portion of the display panel.

[0040] Figure 10 and Figure 11 It is shown Figure 1 A schematic diagram of another example of a magnified portion of the display panel.

[0041] Figure 12 It is shown in Figure 9A schematic waveform diagram of an example of a signal measured in the display panel.

[0042] Figure 13 This is a schematic flowchart illustrating a testing method for a display panel according to an embodiment of the present invention.

[0043] Figure 14 It shows through Figure 13 A schematic flowchart illustrating the detailed process steps for determining the alignment state of the light-emitting element.

[0044] Figure 15 It is shown schematically in Figure 1 A schematic perspective view of the light-emitting element used as a light source in the display panel.

[0045] Figure 16 yes Figure 15 A schematic cross-sectional view of the light-emitting element. Detailed Implementation

[0046] It will be apparent to those skilled in the art that various modifications and variations may be made to this disclosure without departing from the spirit or scope thereof, and that specific embodiments are illustrated in the accompanying drawings and described in the detailed description. Therefore, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of this disclosure and its equivalents.

[0047] Throughout this specification, the same reference numerals denote the same elements. In the drawings, the dimensions of the structures are exaggerated for clarity. The terms "first," "second," etc., may be used simply to describe various constituent elements, but their meanings may not be limited to the intended meaning. The above terms are used only to distinguish one element from others. For example, within the scope of the appended claims, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0048] In this specification, the terms "comprising," "including," or "having" are used to specify the presence of features, quantities, processes, operations, elements, portions, or combinations thereof, and it will be understood that the presence or addition of one or more other features, quantities, processes, operations, elements, portions, or combinations thereof is not excluded. Furthermore, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be intervening elements. In this specification, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being disposed "on" another element, the direction of disposal is not limited to the upward direction and includes the lateral or downward direction. Conversely, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being "below" another element, it may be directly below the other element, or there may be intervening elements.

[0049] In this application, when a component (e.g., "first component") is referred to as "(operably or communicatively) coupled / connected to another component (e.g., "second component")" or "connected to another component (e.g., "second component")", it should be understood that the component can be directly connected to the other component, or can be connected to the other component through other components (e.g., "third component"). On the other hand, when a component (e.g., "first component") is referred to as "directly coupled" or "directly connected" to another component (e.g., "second component"), it can be understood that there are no other components (e.g., "third component") between the component and the other component.

[0050] In the specification and claims, for the purposes of their meaning and interpretation, the phrase “at least one of…” is intended to include the meaning of “at least one selected from the group of…”. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”.

[0051] Unless otherwise specified or implied herein, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in commonly used dictionaries, shall be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and this disclosure, and shall not be interpreted in an ideal or overly formal sense unless expressly defined herein.

[0052] In the following description, embodiments of the present disclosure and other elements necessary for those skilled in the art to understand the contents of the disclosure will be described in more detail with reference to the accompanying drawings. Unless otherwise stated, singular terms may include plural forms.

[0053] Figure 1 This is a schematic block diagram illustrating a display panel according to an embodiment of the present disclosure. Figure 2 and Figure 3 It is shown Figure 1 A schematic block diagram of an example display panel.

[0054] First, refer to Figure 1 The display panel 10 may include a substrate SUB, scan lines (or gate lines) SL1 to SLn (where n is a positive integer), data lines DL1 to DLm (where m is a positive integer), and pixels PXL. Furthermore, the display panel 10 may include a pad group PDS, a first demultiplexer DEMUX1, and a second demultiplexer DEMUX2.

[0055] The substrate SUB can include a transparent insulating material and transmit light. The substrate SUB can be a rigid substrate or a flexible substrate.

[0056] The substrate SUB may include a first region A1 and a second region A2 surrounding the first region A1.

[0057] For example, the substrate SUB can be a mother substrate, which is the basis for manufacturing the panel, and the first region A1 of the substrate SUB cut along the cutting line L_CUT can be used as the panel (i.e., the display panel or unit disposed in the display device).

[0058] Scan lines SL1 to SLn, data lines DL1 to DLm and pixel PXL can be set in the first area A1, and pad group PDS, first demultiplexer DEMUX1 and second demultiplexer DEMUX2 can be set in the second area A2.

[0059] Scan lines SL1 to SLn can extend in the first direction DR1 and can be arranged in the second direction DR2. Data lines DL1 to DLm can extend in the second direction DR2 and can be arranged in the first direction DR1.

[0060] Pixel PXL can be set in an area (e.g., a pixel region) divided by scan lines SL1 to SLn and data lines DL1 to DLm.

[0061] Pixel PXL can be electrically connected to a corresponding scan line among scan lines SL1 to SLn and a corresponding data line among data lines DL1 to DLm. For example, if pixel PXL is set in the i-th row (where i is a positive integer less than or equal to n) and j-th column (where j is a positive integer less than or equal to m), pixel PXL can be electrically connected to the i-th scan line SL1 and the j-th data line DLj.

[0062] According to an embodiment, the display panel 10 may include sensing scan lines arranged parallel to scan lines SL1 to SLn and sensing lines (or readout lines) arranged parallel to data lines DL1 to DLm, and the pixel PXL may be further electrically connected to a corresponding sensing scan line and a corresponding sensing line among the sensing scan lines. Reference will be made below. Figure 4 and Figure 9 Describe the sensing scan line and sensing line.

[0063] The pixel PXL may include a light-emitting element and at least one transistor that provides drive current to the light-emitting element.

[0064] Pixel PXL can emit light with a brightness corresponding to the data signal (or data voltage) provided via data lines DL1 to DLm in response to a first gate signal (or first scan signal) provided via scan lines SL1 to SLn. Pixel PXL can also output information related to the characteristics of the light-emitting element via sensing lines (e.g., outputting a sensing voltage or sensing current as information related to the threshold voltage of the driving transistor) in response to a second gate signal (or second scan signal) provided via sensing scan lines.

[0065] Detailed specifications for the Pixel PXL can be found below. Figure 4 Describe it.

[0066] The pad group PDS includes multiple pads and can be located in a pad region A_PAD adjacent to at least one side of the first region A1. The pad region A_PAD can be included in a second region A2. For example, as... Figure 1 As shown, the pad group PDS can be set in the pad region A_PAD located in the second direction DR2 relative to the first region A1. For another example, as... Figure 2 As shown, the pad group PDS can be set in a first pad area A_PAD1 and a second pad area A_PAD2, wherein the first pad area A_PAD1 and the second pad area A_PAD2 are positioned in the second direction DR2 and the first area A1 is set between them. For another example, as... Figure 3 As shown, the pad group PDS can be set in the pad area A_PAD surrounding the first area A1. For example, the pad group PDS can be set to be adjacent to at least one side of the first area A1, depending on the number (or number of) pads included in the pad group PDS.

[0067] The pad group PDS may include a first pad group PDS1 and a second pad group PDS2. The first pad group PDS1 may be electrically connected to an external test device 20 and may receive a test voltage (or test signal S_TEST) and a first decompositing control signal (or first demultiplexer control signal) from the test device 20. The second pad group PDS2 may be electrically connected to the test device 20 and may receive a gate signal (or scan signal) and a second decompositing control signal from the test device 20. The test voltage, the first decompositing control signal, the gate signal, and the second decompositing control signal will be referenced below. Figure 6 and Figure 12 Describe it.

[0068] The first demultiplexer DEMUX1 can be electrically connected to data lines DL1 to DLm, and can also be electrically connected to the first pad group PDS1 via test lines TL1_1 to TL1_k (where k is a positive integer less than m). The first demultiplexer DEMUX1 can selectively connect some of the data lines DL1 to DLm to the first pad group PDS1 in response to a first demultiplexer control signal. For example, a test voltage applied to the first pad group PDS1 can be selectively applied to data lines DL1 to DLm. When the first demultiplexer DEMUX1 sequentially connects the data lines DL1 to DLm to the first pad group PDS1 in response to a first demultiplexer control signal, the test voltage applied to the first pad group PDS1 can be sequentially applied to the data lines DL1 to DLm.

[0069] For reference, to test the alignment (or emission state) of the internal light-emitting elements individually for each pixel PXL, it may be necessary to have test pads (i.e., pad groups PDS) individually connected to each of the pixels PXL (or pixel columns), and a pad area A_PAD with a large area may be required to arrange the test pads. Therefore, the area ratio of the second region A2 in the substrate SUB increases, while the area ratio of the first region A1 in the substrate SUB decreases, and the manufacturing cost of the panel (or cell) may increase. A test apparatus with a number of channels corresponding to the number of test pads may be required, and the testing cost (or manufacturing cost) may increase.

[0070] According to embodiments of the present disclosure, the display panel 10 can use a first demultiplexer DEMUX1 to selectively connect a first pad group PDS1 to at least some of the pixels PXL, thereby reducing the number of first pad groups PDS1 (or pad groups PDS).

[0071] The second demultiplexer DEMUX2 can be electrically connected to scan lines SL1 to SLn, and can also be electrically connected to the second pad group PDS2 via gate test line TLS2. The second demultiplexer DEMUX2 can selectively connect some of the scan lines SL1 to SLn to the second pad group PDS2 in response to a second demultiplexer control signal. For example, the gate signal applied to the second pad group PDS2 can be selectively applied to scan lines SL1 to SLn. When the second demultiplexer DEMUX2 sequentially connects scan lines SL1 to SLn to the second pad group PDS2 in response to a second demultiplexer control signal, the gate signal applied to the second pad group PDS2 can be sequentially applied to scan lines SL1 to SLn.

[0072] In another embodiment, the second demultiplexer DEMUX2 can be implemented as a shift register (or scan drive circuit) that sequentially generates and outputs pulse gate signals using the first demultiplexer control signal (or clock signal).

[0073] Since the second pad group PDS2 is selectively connected to at least some of the pixels PXL by using the second demultiplexer DEMUX2, the number of the second pad group PDS2 (or pad group PDS) can be reduced.

[0074] exist Figure 1 In this arrangement, the first demultiplexer DEMUX1 is positioned relative to the first region A1 in the second direction DR2, and the second demultiplexer DEMUX2 is positioned relative to the first region A1 in a direction opposite to the first direction DR1, but the arrangement is not limited to this. For example, as... Figure 2 and Figure 3 As shown, the display panel 10 may also include a third demultiplexer DEMUX3 and a fourth demultiplexer DEMUX4. For example... Figure 2 As shown, the third demultiplexer DEMUX3 can be positioned relative to the first region A1 in a direction opposite to the second direction DR2, and can selectively (e.g., sequentially) connect some of the data lines DL1 to DLm to pads located in the second pad region A_PAD2. Figure 2 As shown, the fourth demultiplexer DEMUX4 can be positioned relative to the first region A1 in the first direction DR1, and can also selectively (e.g., sequentially) connect at least some of the scan lines SL1 to SLn to the pads disposed in the second pad region A_PAD2.

[0075] The test apparatus 20 can detect or measure the sensing signal (e.g., sensing voltage) output from the pixel PXL through the sensing line according to the test voltage, and can determine the alignment state (or light emission state) of each internal light-emitting element in the pixel PXL based on the sensing signal.

[0076] In one embodiment, when the sensing signal is within the reference range (e.g., when it is greater than the reference voltage), the testing device 20 can determine that the alignment state of the light-emitting element in the corresponding pixel PXL is normal or valid. In another embodiment, when the sensing signal is outside the reference range (e.g., when it is less than or equal to the reference voltage), the testing device 20 can determine that the alignment state of the light-emitting element in the corresponding pixel PXL is abnormal or invalid. The configuration for determining the alignment state of the light-emitting element in pixel PXL will be referred to below along with the structure of pixel PXL. Figures 4 to 8 Describe it.

[0077] For reference Figures 1 to 3As described, the display panel 10 can selectively provide a test voltage applied to the first pad group PDS1 to the pixel PXL (or pixel column) by using a first demultiplexer DEMUX1, and can selectively provide a gate signal applied to the second pad group PDS2 to the pixel PXL (or pixel row) by using a second demultiplexer DEMUX2. Therefore, the total number of pad groups PDS can be relatively reduced, and the manufacturing cost of the panel can be lowered.

[0078] Figure 4 It is shown that it includes Figure 1 A schematic circuit diagram illustrating an example of pixels in a display panel.

[0079] refer to Figure 4 The pixel PXL may include a light-emitting unit (EMU) that generates light with a brightness corresponding to the data signal. The pixel PXL may optionally further include pixel circuitry (PXC) for driving the EMU.

[0080] The light-emitting unit (EMU) may include light-emitting elements (LDs) connected in parallel between a first power line PL1 and a second power line PL2, wherein a first power voltage VDD is applied to the first power line PL1 and a second power voltage VSS is applied to the second power line PL2. The first power line PL1 and the second power line PL2 may be electrically connected to a reference. Figure 1 Some of the pad groups PDS described (e.g., individual power pads).

[0081] For example, the light-emitting unit (EMU) may include a first electrode EL1 (or a first alignment electrode) electrically connected to a first power line PL1 via a pixel circuit PXC, a third electrode EL3 (or a second alignment electrode) electrically connected to a second power line PL2, and a light-emitting element LD electrically connected in parallel in the same direction between the first electrode EL1 and the third electrode EL3. In embodiments of this disclosure, the first electrode EL1 may be an anode electrode, and the third electrode EL3 may be a cathode electrode.

[0082] Each of the light-emitting elements (LDs) included in the light-emitting unit (EMU) may include one end electrically connected to the first power line PL1 via the first electrode EL1, and the other end electrically connected to the second power line PL2 via the third electrode EL3.

[0083] Each light-emitting element LD, electrically connected in parallel in the same direction between a first electrode EL1 and a third electrode EL3 that respectively receive voltages of different potentials (i.e., a first electrical voltage VDD and a second electrical voltage VSS), can form (or constitute) each effective light source. These effective light sources can be combined to form the light-emitting unit EMU of pixel PXL.

[0084] The light-emitting element (LD) of the light-emitting unit (EMU) can emit light with a brightness corresponding to the drive current ID provided by the corresponding pixel circuit (PXC). For example, the pixel circuit (PXC) can provide the light-emitting unit (EMU) with a drive current ID corresponding to the voltage level of the data signal Vdata applied through the j-th data line DLj. The drive current ID provided to the light-emitting unit (EMU) can be allocated and flows through the light-emitting element (LD). Therefore, when each light-emitting element (LD) emits light with a brightness corresponding to the current flowing therein, the light-emitting unit (EMU) can emit light with a brightness corresponding to the drive current ID.

[0085] In addition to the light-emitting elements (LDs) that form each effective light source, the light-emitting unit (EMU) may also include at least one inactive light source, such as a reverse light-emitting element (LDr). The reverse light-emitting element (LDr) may be electrically connected in parallel with the light-emitting elements (LDs) forming the effective light sources between the first electrode EL1 and the third electrode EL3, and may be electrically connected between the first electrode EL1 and the third electrode EL3 in the opposite direction (or with a different polarity) to the light-emitting elements (LDs). Even when a predetermined driving voltage (e.g., a forward driving voltage) is applied between the first electrode EL1 and the third electrode EL3, the reverse light-emitting element (LDr) may remain inactive, such that current substantially does not flow through it.

[0086] The pixel circuit PXC can be electrically connected to the i-th scan line SLi, the i-th sensing scan line SSLi, the j-th data line DLj, and the j-th sensing line RLj of the corresponding pixel PXL.

[0087] According to an implementation, the pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst. However, the structure of the pixel circuit PXC is not limited to this. Figure 4 The implementation shown is illustrated.

[0088] The first terminal (or first electrode) of the first transistor T1 (or driving transistor) can be electrically connected to the first power line PL1, and its second terminal (or second electrode) can be electrically connected to the second node N2 (or the first electrode EL1). Here, the first terminal and the second terminal of the first transistor T1 can be different terminals. For example, if the first terminal is the drain electrode, the second terminal can be the source electrode. The gate electrode of the first transistor T1 can be electrically connected to the first node N1. The first transistor T1 can control the amount of driving current ID supplied to the light-emitting element LD in response to the voltage of the first node N1.

[0089] The first terminal of the second transistor T2 (or switching transistor) can be electrically connected to the j-th data line DLj, and its second terminal can be electrically connected to the first node N1. The gate electrode of the second transistor T2 can be electrically connected to the i-th scan line SLi. When a scan signal SC (or a first gate signal) capable of turning on the gate of the second transistor T2 (e.g., a high voltage) is provided from the i-th scan line SLi, the second transistor T2 can be turned on to electrically connect the j-th data line DLj and the first node N1. In this case, the data signal Vdata can be provided to the j-th data line DLj, and therefore the data signal Vdata can be transmitted to the first node N1. The data signal Vdata transmitted to the first node N1 can be charged into the storage capacitor Cst.

[0090] One electrode of the storage capacitor Cst can be electrically connected to the first node N1, and its other electrode can be electrically connected to the second node N2. The storage capacitor Cst can be charged with a voltage corresponding to the data signal Vdata provided to the first node N1, and can maintain the charged voltage until the next data signal Vdata is provided.

[0091] The first terminal of the third transistor T3 (or sensing transistor) can be electrically connected to the second node N2, and its second terminal can be electrically connected to the j-th sensing line RLj. The gate electrode of the third transistor T3 can be electrically connected to the i-th sensing scan line SSLi. If the j-th sensing line RLj is omitted, the second terminal of the third transistor T3 can be electrically connected to the j-th data line DLj. If the i-th sensing scan line SSLi is omitted, the gate electrode of the third transistor T3 can be electrically connected to the i-th scan line SL1. The third transistor T3 can be turned on by a sensing scan signal SS (or a second gate signal) provided with a gate on-state voltage (e.g., a high level) to the i-th sensing scan line SSLi to electrically connect the j-th sensing line RLj and the second node N2.

[0092] According to the implementation, during the test cycle, the first transistor T1 can be turned on by applying a test voltage capable of turning on the first transistor T1 to the first node N1 via the j-th data line DLj and the second transistor T2. The first transistor T1 can be electrically connected to the j-th sensing line RLj by providing a sensing scan signal SS of the gate turn-on voltage to the third transistor T3 to turn on the third transistor T3. Therefore, the sensing voltage corresponding to the threshold voltage of the first transistor T1 can be extracted through the j-th sensing line RLj described above. The extracted sensing voltage can be used to determine the alignment state of the light-emitting element LD in the light-emitting unit (EMU).

[0093] Figure 4An embodiment in which the first transistor T1, the second transistor T2, and the third transistor T3 are all n-type transistors is shown, but this disclosure is not limited thereto. For example, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 described above can be changed to a p-type transistor. Figure 4 An embodiment is shown in which the light-emitting unit (EMU) is electrically connected between the pixel circuit PXC and the second power line PL2, but the light-emitting unit (EMU) can be electrically connected between the first power line PL1 and the pixel circuit PXC.

[0094] The light-emitting unit (EMU) may include a first-stage SET1 (or a first stack or a first sub-light-emitting unit) and a second-stage SET2 (or a second stack or a second sub-light-emitting unit) sequentially connected between a first electric line PL1 and a second electric line PL2. The EMU may include a first electrode EL1, a second electrode EL2, a third electrode EL3, and a fourth electrode EL4, and each of the first-stage SET1 and the second-stage SET2 may include a light-emitting element LD that is electrically connected in parallel in the same direction between two electrodes of electrodes EL1, EL2, EL3, and EL4.

[0095] The first stage SET1 may include a first electrode EL1 and a second electrode EL2 (or a first sub-intermediate electrode CTE-1), and may include at least one first light-emitting element LD1 electrically connected between the first electrode EL1 and the second electrode EL2 (or the first sub-intermediate electrode CTE-1). The first stage SET1 may include a reverse light-emitting element LDr electrically connected between the first electrode EL1 and the second electrode EL2 (or the first sub-intermediate electrode CTE-1) in the opposite direction to the first light-emitting element LD1.

[0096] The second-stage SET2 may include a third electrode EL3 and a fourth electrode EL4 (or a second sub-intermediate electrode CTE-2), and may include at least one second light-emitting element LD2 electrically connected between the fourth electrode EL4 (or the second sub-intermediate electrode CTE-2) and the third electrode EL3. The second-stage SET2 may include a reverse light-emitting element LDr electrically connected between the fourth electrode EL4 (or the second sub-intermediate electrode CTE-2) and the third electrode EL3 in the opposite direction to the second light-emitting element LD2.

[0097] The first sub-intermediate electrode CTE-1 of the first stage SET1 and the second sub-intermediate electrode CTE-2 of the second stage SET2 can be integral with each other or connected to each other. For example, the first sub-intermediate electrode CTE-1 and the second sub-intermediate electrode CTE-2 can form an electrically connected and continuous intermediate electrode CTE of the first stage SET1 and the second stage SET2. When the first sub-intermediate electrode CTE-1 and the second sub-intermediate electrode CTE-2 are integrally provided, the first sub-intermediate electrode CTE-1 and the second sub-intermediate electrode CTE-2 can be different parts of the intermediate electrode CTE.

[0098] In the embodiments described above, the first electrode EL1 can be the anode electrode of the light-emitting unit EMU of each pixel PXL, and the third electrode EL3 can be the cathode electrode of the light-emitting unit EMU.

[0099] As described above, the light-emitting unit (EMU) of the pixel PXL, which includes light-emitting elements (LDs) electrically connected in a series / parallel hybrid structure, can easily adjust the drive current (ID) / voltage conditions according to the product specifications of the application.

[0100] Specifically, compared to a light-emitting unit (EMU) with a structure where light-emitting elements (LDs) are only electrically connected in parallel, the light-emitting unit (EMU) of the pixel PXL, which includes light-emitting elements (LDs) electrically connected in a hybrid series / parallel structure, can reduce the drive current (ID).

[0101] For reference Figure 4 As described, the pixel PXL may include stages (e.g., a first stage SET1 and a second stage SET2) connected in series with the light-emitting unit EMU. Therefore, the drive current ID of the pixel PXL can be reduced.

[0102] exist Figure 4 In the diagram, a pixel PXL (or light-emitting unit EMU) is shown as comprising two levels (i.e., level 1 SET1 and level 2 SET2), but is not limited thereto. For example, a pixel PXL may comprise three or more levels.

[0103] Figure 5 It shows Figure 4 A schematic plan view of an example of pixels. Figure 5 For simplicity, the transistor connected to the light-emitting element (LD) and the signal lines connected to the transistor are omitted, and the focus is on the reference. Figure 4 The described light-emitting unit EMU schematically illustrates the pixel PXL.

[0104] refer to Figures 1 to 5Pixel PXL can be formed in pixel region PXA defining a substrate SUB. Pixel region PXA may include light-emitting region EMA. According to an embodiment, pixel PXL may include a dam BNK, and the light-emitting region EMA may be surrounded by and defined by the dam BNK. Figure 5 As shown, the embankment BNK may include a first opening OP1 and a second opening OP2 exposed below it, and the light-emitting region EMA may be defined by the first opening OP1 of the embankment BNK. The second opening OP2 may be spaced apart from the first opening OP1 within the pixel region PXA, and may be configured to be adjacent to one side (e.g., the lower or upper side) of the pixel region PXA.

[0105] Pixel PXL may include a first electrode EL1, a second electrode EL2, a third electrode EL3, and a fourth electrode EL4, which are physically separated or spaced apart from each other. The first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may each correspond to a reference electrode. Figure 4 The first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 are described.

[0106] The first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 can be arranged sequentially on the first direction DR1. Each of the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 can extend on the second direction DR2, which intersects the first direction DR1. The ends of the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 can be disposed in the second opening OP2 of the embankment BNK. For reference, the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 can extend to adjacent pixel areas in the manufacturing process of the display device before the light-emitting element LD is provided onto the substrate SUB, and can be separated from other electrodes (e.g., electrodes of adjacent pixels adjacent to each other on the second direction DR2) at the second opening OP2 after the light-emitting element LD is provided into the pixel area PXA and aligned in the pixel area PXA. For example, the second opening OP2 of the embankment BNK can be provided for a separation process of the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4.

[0107] The first electrode EL1 may include a protrusion in the light-emitting region EMA that protrudes toward the second electrode EL2 in a first direction DR1. The protrusion of the first electrode EL1 may be provided to maintain a predetermined gap between the first electrode EL1 and the second electrode EL2 in the light-emitting region EMA. Similarly, the fourth electrode EL4 may include a protrusion in the light-emitting region EMA that protrudes toward the third electrode EL3 in a direction opposite to the first direction DR1. The protrusion of the fourth electrode EL4 may be provided to maintain a predetermined gap between the third electrode EL3 and the fourth electrode EL4 in the light-emitting region EMA.

[0108] However, the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 are not limited thereto. For example, the shapes and / or arrangements of the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 can be varied. For example, each of the first electrode EL1 and the fourth electrode EL4 may not include a protrusion and may have a curved shape.

[0109] The first electrode EL1 can be electrically connected to the reference through the first contact hole CNT1. Figure 4 The first transistor T1 is described, and the third electrode EL3 can be electrically connected to the reference via the second contact hole CNT2. Figure 4 The second power line PL2 is described.

[0110] According to embodiments, each of the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may have a single-layer or multi-layer structure. For example, the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may have a multi-layer structure including a reflective electrode and a conductive capping layer. The reflective electrode may have a single-layer or multi-layer structure. For example, the reflective electrode may include at least one reflective conductive layer, and may further selectively include at least one transparent conductive layer disposed on and / or below the reflective conductive layer.

[0111] According to an embodiment, the pixel PXL may include a first dam pattern BNKP1 that overlaps with a portion of the first electrode EL1, a second dam pattern BNKP2 that overlaps with a portion of the second electrode EL2, a third dam pattern BNKP3 that overlaps with a portion of the third electrode EL3, and a fourth dam pattern BNKP4 that overlaps with a portion of the fourth electrode EL4.

[0112] The first embankment pattern BNKP1, the second embankment pattern BNKP2, the third embankment pattern BNKP3, and the fourth embankment pattern BNKP4 can be arranged to be spaced apart from each other in the light-emitting area EMA, and a portion of each of the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 can protrude upwards. For example, the first electrode EL1 (or the protrusion of the first electrode EL1) can be disposed on the first embankment pattern BNKP1 to protrude in the third direction DR3 (i.e., in the thickness direction of the substrate SUB) through the first embankment pattern BNKP1; the second electrode EL2 can be disposed on the second embankment pattern BNKP2 to protrude in the third direction DR3 through the second embankment pattern BNKP2; the third electrode EL3 can be disposed on the third embankment pattern BNKP3 to protrude in the third direction DR3 through the third embankment pattern BNKP3; and the fourth electrode EL4 (or the protrusion of the fourth electrode EL4) can be disposed on the fourth embankment pattern BNKP4 to protrude in the third direction DR3 through the fourth embankment pattern BNKP4.

[0113] Pixel PXL may include a first light-emitting element LD1 and a second light-emitting element LD2. Pixel PXL may also include a reference element. Figure 4 The described reverse-emitting element LDr.

[0114] A first light-emitting element LD1 can be disposed between a first electrode EL1 and a second electrode EL2. A first end (or one end) of the first light-emitting element LD1 can face the first electrode EL1, and a second end (or the other end) of the first light-emitting element LD1 can face the second electrode EL2. With the first light-emitting element LD1 disposed, it can be electrically connected in parallel between the first electrode EL1 and the second electrode EL2, and can form a reference. Figure 4 The first level described is SET1.

[0115] Similarly, a second light-emitting element LD2 can be disposed between the third electrode EL3 and the fourth electrode EL4. The first end of the second light-emitting element LD2 can face the fourth electrode EL4, and the second end of the second light-emitting element LD2 can face the third electrode EL3. The second end of the second light-emitting element LD2 and the second end of the first light-emitting element LD1 can include the same type of semiconductor layer (e.g., a p-type semiconductor layer) and can be disposed facing each other, with the second electrode EL2 and the third electrode EL3 interposed therebetween. When the second light-emitting element LD2 is disposed, it can be connected in parallel between the third electrode EL3 and the fourth electrode EL4, and can form a reference. Figure 4 The second level described is SET2.

[0116] exist Figure 5In the diagram, the light-emitting elements (LDs) are shown aligned in a first direction DR1 between the first electrode EL1 and the second electrode EL2, and between the third electrode EL3 and the fourth electrode EL4. However, the alignment direction of the light-emitting elements (LDs) is not limited to this. For example, at least one of the light-emitting elements (LDs) may be arranged in a diagonal direction.

[0117] In this embodiment, the first end of the first light-emitting element LD1 may not be directly disposed on the first electrode EL1, but may be electrically connected to the first electrode EL1 through at least one contact electrode (e.g., the first contact electrode CNE1). Similarly, the second end of the second light-emitting element LD2 may not be directly disposed on the third electrode EL3, but may be electrically connected to the third electrode EL3 through at least one contact electrode (e.g., the second contact electrode CNE2). However, this disclosure is not limited thereto. For example, the first end of the first light-emitting element LD1 may directly contact the first electrode EL1 and may be electrically connected to the first electrode EL1.

[0118] According to the embodiments, each of the first light-emitting element LD1 and the second light-emitting element LD2 may have a tiny size and comprise a material with an inorganic crystal structure, for example, having a size from the nanometer scale to the micrometer scale. A more specific configuration of the light-emitting elements LD will be referenced below. Figure 15 and Figure 16 Describe it.

[0119] According to an embodiment, the light-emitting element (LD) can be prepared in the form of a dispersion in a predetermined solution and can be provided to the light-emitting region EMA of the pixel region PXA by inkjet printing or slot coating. For example, the LD can be mixed with a volatile solvent and provided to the light-emitting region EMA. In this case, when a predetermined voltage is applied between the first electrode EL1 and the second electrode EL2 and between the third electrode EL3 and the fourth electrode EL4, an electric field is formed between the first electrode EL1 and the second electrode EL2 and between the third electrode EL3 and the fourth electrode EL4, and therefore the LD can self-align between the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4. By evaporating the solvent (or removing the solvent in any other way) after the LD is aligned, the LD can be stably arranged between the first electrode EL1 and the second electrode EL2, and between the third electrode EL3 and the fourth electrode EL4.

[0120] According to an implementation, the pixel PXL may include a first contact electrode CNE1, a second contact electrode CNE2, and an intermediate electrode CTE.

[0121] The first contact electrode CNE1 may be formed on at least a portion of the first end of the first light-emitting element LD1 and the corresponding first electrode EL1, and the first end of the first light-emitting element LD1 may be physically and / or electrically connected to the first electrode EL1.

[0122] The second contact electrode CNE2 can be formed on the second end of the second light-emitting element LD2 and at least a portion of the corresponding third electrode EL3, and the second end of the second light-emitting element LD2 can be physically and / or electrically connected to the third electrode EL3.

[0123] The intermediate electrode CTE may include a first sub-intermediate electrode CTE-1 (or a first intermediate electrode) and a second sub-intermediate electrode CTE-2 (or a second intermediate electrode) extending in the second direction DR2. The first sub-intermediate electrode CTE-1 may be formed on at least a portion of the second terminal of the first light-emitting element LD1 and the corresponding second electrode EL2. The first sub-intermediate electrode CTE-1 may extend to bypass the second contact electrode CNE2 or the second light-emitting element LD2, and the second sub-intermediate electrode CTE-2 may be formed on at least a portion of the first terminal of the second light-emitting element LD2 and the corresponding fourth electrode EL4. The intermediate electrode CTE may be electrically connected to the second terminal of the first light-emitting element LD1 and the first terminal of the second light-emitting element LD2.

[0124] like Figure 5 As shown, the intermediate electrode CTE can be spaced apart from the second contact electrode CNE2 and can have a closed-loop shape surrounding the second contact electrode CNE2. Therefore, the second light-emitting element LD2 can be electrically connected in series with the first light-emitting element LD1 through the intermediate electrode CTE.

[0125] For reference Figure 5 The first light-emitting element LD1 and the second light-emitting element LD2 can be disposed between the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4, and the first light-emitting element LD1 and the second light-emitting element LD2 can be connected in series via an intermediate electrode CTE. In this way, the light-emitting unit EMU of pixel PXL can be configured using the first light-emitting element LD1 and the second light-emitting element LD2, which are connected in series in the pixel region PXA of pixel PXL and aligned.

[0126] Figure 6 It is shown in Figure 4 A schematic waveform diagram of an example of a signal measured in a pixel. Figure 6 The diagram illustrates the signals used to explain the operation of pixel PXL during a test cycle. During the test cycle, a sensing voltage corresponding to the threshold voltage of the first transistor T1 of pixel PXL can be sensed.

[0127] refer to Figures 1 to 6 In the first cycle P1, the scan signal SC applied to the i-th scan line SLi can have a pulse with a gate turn-on voltage level.

[0128] In this case, during the first cycle P1, the second transistor T2 can be turned on in response to the scan signal SC of the gate turn-on voltage level, and the j-th data line DLj can be electrically connected to the first node N1.

[0129] When the data signal Vdata (or test voltage) is applied to the j-th data line DLj, the data signal Vdata can be applied to the first node N1. Here, the data signal Vdata can have a voltage level that is the threshold voltage Vth used to sense the first transistor T1.

[0130] In this implementation, the data signal Vdata can be set to be greater than a reference voltage, and the voltage level of the reference voltage can be equal to the voltage difference between the total operating voltage of the series-connected first stage SET1 (or first light-emitting element LD1) and second stage SET2 (or second light-emitting element LD2) and the operating voltage of one of the first stage SET1 and second stage SET2. Here, the operating voltage can be the voltage required for the light-emitting element LD to emit light, and for example, the operating voltage can be the threshold voltage of the light-emitting element LD. The voltage level of the data signal Vdata can be less than or equal to the total operating voltage of the first stage SET1 (or first light-emitting element LD1) and second stage SET2 (or second light-emitting element LD2).

[0131] For example, with the operating voltage of each of the first light-emitting element LD1 and the second light-emitting element LD2 being about 2.5V relative to the second power voltage VSS, the data signal Vdata can have a voltage level of about 4V, which is less than about 5V (i.e., 2.5V × 2) and greater than about 2.5V (i.e., 5V minus 2.5V).

[0132] Similar to the scan signal SC, in the first cycle P1, the sensing scan signal SS applied to the i-th sensing scan line SSLi can have a pulse with a gate turn-on voltage level. The waveform and phase of the sensing scan signal SS can be substantially the same as those of the scan signal SC.

[0133] In this case, during the first cycle P1, the third transistor T3 can be turned on in response to the sensing scan signal SS of the gate turn-on voltage level, and the j-th sensing line RLj and the second node N2 can be electrically connected.

[0134] When the initialization voltage Vinit is applied to the j-th sensing line RLj at the beginning of the first period P1, the initialization voltage Vinit can be applied to the second node N2. Therefore, at the beginning of the first period P1, the node voltage V_N2 (or V@N2) of the second node N2 can have the voltage level of the initialization voltage Vinit. For example, the initialization voltage Vinit can have a voltage level of approximately 2V.

[0135] After that, the supply of the initialization voltage Vinit can be cut off until the end of the first cycle P1.

[0136] In this configuration, the first transistor T1 can supply a current to the second node N2 corresponding to the gate-source voltage, and therefore, the node voltage V_N2 of the second node N2 can linearly increase to a specific voltage level (e.g., a first voltage level V1). For example, the node voltage V_N2 of the second node N2 can increase to a first voltage level V1 corresponding to the difference between the data signal Vdata and the threshold voltage Vth of the first transistor T1 (i.e., Vdata minus Vth).

[0137] Therefore, test device 20 (see Figure 1 The threshold voltage Vth (or node voltage V_N2) of the first transistor T1 can be sensed through the j-th sensing line RLj.

[0138] In this embodiment, if the first voltage level V1 (or sensed voltage) measured in the first cycle P1 is within the reference range, the test device 20 can determine that the light-emitting elements LD (i.e., the first light-emitting element LD1 and the second light-emitting element LD2, or the first stage SET1 and the second stage SET2) in the pixel PXL are properly (or effectively) aligned. For example, the reference range can be less than the total operating voltage of the first stage SET1 (or the first light-emitting element LD1) and the second stage SET2 (or the second light-emitting element LD2), and can be greater than the reference voltage (i.e., the voltage difference between the total operating voltage of the first stage SET1 and the second stage SET2 and the operating voltage of the light-emitting element LD). In other words, the reference range can be less than the product of the total number of stages (the first stage SET1 and the second stage SET2) and the operating voltage of the light-emitting element LD, and can be greater than the product of the number of stages excluding one stage (the first stage SET1 and the second stage SET2) (i.e., the total number minus 1) and the operating voltage of the light-emitting element LD.

[0139] For example, in the presence of two levels SET1 and SET2 and with the operating voltage of the light-emitting element LD being approximately 2.5V, the reference range can be less than approximately 5V and greater than approximately 2.5V. When the first voltage level V1 is approximately 3V, the first voltage level V1 is within the reference range, and therefore the test apparatus 20 can determine that the light-emitting element LD in pixel PXL is effectively aligned.

[0140] Figure 7 and Figure 8 This illustrates a case where the light-emitting element LD in pixel PXL is determined to be ineffectively aligned.

[0141] Figure 7 It is shown that it includes Figure 1 A schematic circuit diagram of another example of pixels in a display panel. Figure 7 It shows the relationship with Figure 4 The corresponding circuit diagram. Figure 8 It is shown in Figure 7 A schematic waveform diagram of an example of the signal measured in a pixel. Figure 8 In the middle, it is shown that... Figure 6 The corresponding waveform diagram.

[0142] First, refer to Figure 4 and Figure 7 Apart from the defect in the first light-emitting element LD1, Figure 7 The pixel PXL_1 can be with Figure 4 The pixels PXL are essentially the same or similar. Therefore, redundant descriptions will be omitted. The defect in the first light-emitting element LD1 is an example, and as another example, a defect may exist in the second light-emitting element LD2 rather than in the first light-emitting element LD1.

[0143] For example, the first electrode EL1 and the second electrode EL2 can be Figure 7 The first light-emitting element LD1 shown is short-circuited due to a defect. In this case, the drive current ID flowing between the first electrode EL1 and the second electrode EL2 can flow through the defective first light-emitting element LD1 (e.g., the short-circuited light-emitting element), and the drive current ID may not flow through other first light-emitting elements LD1 that require operating voltage.

[0144] For reference, when the first light-emitting element LD1 is electrically disconnected, the driving current ID can flow not only to the corresponding first light-emitting element LD1 but also through other first light-emitting elements LD1. Therefore, the display quality is hardly degraded. As the number of first light-emitting elements LD1 increases, the disconnection of a first light-emitting element LD1 may have almost no effect on the first stage SET1. Conversely, when the first light-emitting element LD1 is short-circuited, the first stage SET1 may not work (or not emit light), and the brightness of pixel PXL_1 may be greatly reduced (e.g., to about 1 / 2 level). When the same data signal Vdata is applied to Figure 4 PXL pixels and Figure 7 In the case of pixel PXL_1, Figure 7 The pixel PXL_1 may emit a signal with a higher resolution than... Figure 4 The PXL pixels emit light with low brightness. In the display panel 10 (see...) Figure 1 )include Figure 7 In the case of a defective pixel PXL_1 (i.e., a defective pixel PXL_1), brightness deviation may occur, which may degrade display quality.

[0145] Through the measurement display panel 10 (see Figure 1 Optical imaging methods that measure the brightness of a specific area of ​​the display panel 10, or methods that sense the current flowing through the display panel 10 (or pixel PXL_1), make it difficult to accurately determine whether a defect has occurred in each pixel PXL_1, or to detect defective pixels PXL_1. Specifically, conventional testing methods that determine the presence of defects in the light-emitting element LD based on whether simultaneously turned-on pixels PXL_1 emit light are insufficient to determine whether a defect has occurred in each pixel PXL_1.

[0146] Display panel 10 according to an embodiment of the present disclosure (see Figure 1 The test method can detect whether a defect (specifically, a short circuit that has a large impact on brightness changes) has occurred in pixel PXL_1 based on the threshold voltage Vth of the sensed first transistor T1 (or driving transistor).

[0147] refer to Figures 6 to 8 , Figure 8 The scan signal SC, sensing scan signal SS, and data signal Vdata shown can be respectively compared with the reference. Figure 6 The described scan signal SC, sensing scan signal SS, and data signal Vdata are essentially the same or similar. Therefore, repeated descriptions will be omitted.

[0148] The initialization voltage Vinit can be applied to the j-th sensing line RLj at the beginning of the first cycle P1, and thereafter the supply of the initialization voltage Vinit can be cut off until the end of the first cycle P1.

[0149] In this case, the first transistor T1 can supply a current to the second node N2 corresponding to the gate-source voltage, and therefore, the node voltage V_N2 of the second node N2 can increase linearly. However, if a defect has occurred in the first light-emitting element LD1, the node voltage V_N2 of the second node N2 may only increase to a second voltage level V2, which is lower than the first voltage level V1. This is because when Figure 7 When the first electrode EL1 and the second electrode EL2 are short-circuited, if the node voltage V_N2 of the second node N2 is greater than the operating voltage of the second light-emitting element LD2 (or the second stage SET2) relative to the second power voltage VSS, current flows through the second light-emitting element LD2 or leaks through the second light-emitting element LD2. Therefore, the second voltage level V2 relative to the second power voltage VSS can be equal to or similar to the operating voltage of the second light-emitting element LD2, and for example, the second voltage level V2 can be about 2.5V.

[0150] The second voltage level V2 measured in the first cycle P1 exceeds the reference range (i.e., the reference voltage level V2 is outside the reference range). Figure 6 In the case of the described reference range (or when the second voltage level V2 is less than or equal to the reference range), Figure 6 (In the case of the described reference voltage), test apparatus 20 (see Figure 1 It can be determined that the light-emitting elements LD (i.e., the first light-emitting element LD1 and the second light-emitting element LD2, or the first stage SET1 and the second stage SET2) in pixel PXL_1 are invalidally aligned. For example, when the second voltage level V2 is about 2.5V and the reference range is greater than 2.5V and less than 5V, the second voltage level V2 is outside the reference range, and therefore the test device 20 can determine that the light-emitting elements LD in pixel PXL_1 are invalidally aligned.

[0151] As another example, in the case where a defect (i.e., a short circuit) occurs in both the first light-emitting element LD1 and the second light-emitting element LD2, Figure 7 The first electrode EL1, second electrode EL2, third electrode EL3, and fourth electrode EL4 shown may be short-circuited, and the node voltage V_N2 of the second node N2 may be equal to the voltage level of the second electrical voltage VSS. Therefore, it is possible to detect inactive pixel PXL_1 that has an overall defect rather than a partial defect.

[0152] Repair operations can be performed on pixel PXL_1, including LDs with invalid alignment.

[0153] For example, cutting can be achieved using lasers or similar methods. Figure 7 The disconnected first light-emitting element LD1 or its connecting portion is used to perform a repair operation for the first light-emitting element LD1.

[0154] On the other hand, it can be described that the testing device 20 determines whether pixel PXL_1 (or pixel PXL) is defective based on whether the second voltage level V2 (or the first voltage level V1) is within a reference range, but this disclosure is not limited thereto. For example, the testing device 20 may determine whether pixel PXL_1 (or pixel PXL) is defective based on whether the sensed threshold voltage Vth_1 (or the sensed threshold voltage Vth) of the first transistor T1 of pixel PXL_1 is within a normal range.

[0155] For reference Figures 6 to 8 The test apparatus 20 (or the test method for the display device) described herein can determine whether pixel PXL or PXL_1 has a defect (specifically, a short circuit or an ineffectively aligned light-emitting element LD that has a large impact on brightness variation) based on the voltage level (first voltage level V1 or second voltage level V2) sensed at the second node N2 where the first transistor T1 and the light-emitting unit EMU are connected (or the threshold voltage Vth or Vth_1 sensed by the first transistor T1).

[0156] Figure 9 It is shown Figure 1 An example diagram of a magnified portion of the display panel. Figure 9 The image shows only the portion of display panel 10 corresponding to two rows and six columns as an example. Figure 10 and Figure 11 It is shown Figure 1 A schematic diagram of another example of a magnified portion of the display panel.

[0157] First, refer to Figure 9 The display panel 10 may include a substrate SUB, scan lines SL1 and SL2, sensing scan lines SSL1 and SSL2, data lines DL1, DL2, DL3, DL4, DL5 and DL6, sensing lines RL1, RL2, RL3, RL4, RL5 and RL6, pixels PXL11, PXL12, PXL13, PXL14, PXL15, PXL16, PXL21, PXL22, PXL23, PXL24, PXL25 and PXL26, a first pad group PDS1, a second pad group PDS2, a first demultiplexer DEMUX1 and a second demultiplexer DEMUX2.

[0158] Because each of pixels PXL11 to PXL16 and PXL21 to PXL26 is related to the reference Figures 1 to 4 The described pixel PXL (or reference) Figure 7 The described pixels (PXL_1) are essentially the same or similar, so repeated descriptions will be omitted.

[0159] For reference Figure 1 As described, the first pad group PDS1, the second pad group PDS2, the first demultiplexer DEMUX1, and the second demultiplexer DEMUX2 can be set or provided in the second region A2 of the substrate SUB, and the configuration of the substrate SUB in the second region A2 can be removed by a cutting process along the cutting line L_CUT.

[0160] The first pad group PDS1 may include a first pad PD1, a first control pad PD1_C, and sensing pads PD_S1, PD_S2, PD_S3, PD_S4, PD_S5, and PD_S6.

[0161] The first pad PD1 can be accessed from the outside (e.g., test setup 20 (see...)). Figure 1 )) Receive test voltage. The first pad PD1 can be electrically connected to the first demultiplexer DEMUX1 via the first test line TL_D1. The first test line TL_D1 can be included in the reference Figure 1 The test lines TL1_1 to TL1_k are described.

[0162] The first control pad PD1_C can receive a first demultiplexer control signal from an external source for controlling the first demultiplexer DEMUX1. The first control pad PD1_C can be electrically connected to the first demultiplexer DEMUX1 via a second test line TL_D2. The second test line TL_D2 can be included in the reference... Figure 1 The test lines TL1_1 to TL1_k are described. According to an implementation, the first control pad PD1_C may include multiple sub-control pads, depending on the number of first demultiplexer control signals required to control the operation of the first demultiplexer DEMUX1.

[0163] Sensing pads PD_S1 to PD_S6 can be electrically connected to sensing lines RL1 to RL6 respectively, and the sensing signals output from pixels PXL11 to PXL16 and PXL21 to PXL26 via sensing lines RL1 to RL6 can be transmitted to another component or external component (e.g., test device 20, see...). Figure 1 )).

[0164] The second pad group PDS2 may include the second pad PD2 and the second control pad PD2_C.

[0165] The second pad PD2 can be obtained from external components (e.g., test device 20, see...). Figure 1The second pad PD2 can be electrically connected to the second demultiplexer DEMUX2 via the first gate test line TL_G1. The first gate test line TL_G1 can be included in the reference... Figure 1 The gate test line TLS2 is described.

[0166] The second control pad PD2_C can receive a second demultiplexer control signal from an external component for controlling the second demultiplexer DEMUX2. The second control pad PD2_C can be electrically connected to the second demultiplexer DEMUX2 via the second gate test line TL_G2. The second gate test line TL_G2 can be included in the reference... Figure 1 The gate test line TLS2 is described.

[0167] According to the implementation, the second control pad PD2_C may include multiple sub-control pads depending on the number of second decompositing control signals required to control the operation of the second demultiplexer DEMUX2. For example, when the second demultiplexer DEMUX2 is implemented as a shift register that sequentially shifts and outputs gate signals, the second decompositing control signals may include a clock signal, a gate on-state voltage, and a gate off-state voltage, and the second control pad PD2_C may include sub-control pads that respectively receive the clock signal, the gate on-state voltage, and the gate off-state voltage.

[0168] The first demultiplexer DEMUX1 can be electrically connected to data lines DL1 to DL6. In response to a first demultiplexer control signal provided via a first control pad PD1_C (or a second test line TL_D2), the first demultiplexer DEMUX1 can selectively connect the first pad PD1 to one of the data lines DL1 to DL6, and can transmit a test voltage applied to the first pad PD1 to a selected one of the data lines DL1 to DL6. For example, the first demultiplexer DEMUX1 may include a switch electrically connected between the data lines DL1 to DL6 and the first pad PD1 (or the first test line TL_D1) and selectively turned on in response to the first demultiplexer control signal.

[0169] The second demultiplexer DEMUX2 can be electrically connected to scan lines SL1 and SL2 and sensing scan lines SSL1 and SSL2. In response to the second demultiplexer control signal provided via the second control pad PD2_C (or the second gate test line TL_G2), the second demultiplexer DEMUX2 can selectively connect the second pad PD2 to one of scan lines SL1 and SL2 and one of sensing scan lines SSL1 and SSL2, or select one of scan lines SL1 and SL2 and one of sensing scan lines SSL1 and SSL2 to provide a gate signal.

[0170] As described below, during the test cycle, the same gate signal can be applied to scan lines SL1 and SL2 and their corresponding sensing scan lines SSL1 and SSL2. Therefore, one of scan lines SL1 and SL2 (e.g., the first scan line SL1) and one of their corresponding sensing scan lines SSL1 and SSL2 (e.g., the first sensing scan line SSL1) can be electrically connected to each other via the second demultiplexer DEMUX2, or directly electrically connected in the second region A2.

[0171] exist Figure 9 In the diagram, display panel 10 is shown as including a first demultiplexer DEMUX1, but display panel 10 is not limited thereto.

[0172] like Figure 10 As shown, the display panel 10_1 (or the first demultiplexer DEMUX1) may include sub-demultiplexers DEMUX1_1 and DEMUX1_2. Each of the sub-demultiplexers DEMUX1_1 and DEMUX1_2 may be implemented as a 1:4 demultiplexer, but this is only an example, and each of the sub-demultiplexers DEMUX1_1 and DEMUX1_2 may have 3 or less outputs or 5 or more outputs (i.e., an input / output ratio of 1:5).

[0173] In response to the first demultiplexer control signal provided via the second test line TL_D2, the first sub-demultiplexer DEMUX1_1 can be electrically connected to the first data line DL1 to the fourth data line DL4, and one of the first data line DL1 to the fourth data line DL4 can be electrically connected to the first pad PD1.

[0174] Similarly, in response to the first demultiplexer control signal, the second sub-demultiplexer DEMUX1_2 can be electrically connected to other data lines (e.g., the fifth data line DL5 and the sixth data line DL6), and can electrically connect one of the other data lines to the first pad PD1. For example, the fifth data line DL5 can be electrically connected to the first pad PD1 through the second sub-demultiplexer DEMUX1_2, and simultaneously, the first data line DL1 can be electrically connected to the first pad PD1 through the first sub-demultiplexer DEMUX1_1. In this case, a test voltage can be applied to both the first data line DL1 and the fifth data line DL5 simultaneously, and the pixel electrically connected to the first data line DL1 (e.g., the eleventh pixel PXL11) and the pixel electrically connected to the fifth data line DL5 (e.g., the fifteenth pixel PXL15) can be tested simultaneously. Therefore, the total testing time of the display panel 10_1 can be relatively reduced.

[0175] exist Figure 9 and Figure 10In the diagram, sensing lines RL1 to RL6 are shown as being directly connected to sensing pads PD_S1 to PD_S6, respectively, but this disclosure is not limited thereto.

[0176] like Figure 11 As shown, in the display panel 10_2, the first demultiplexer DEMUX1 can be electrically connected to sensing lines RL1 to RL6, and can be electrically connected to the first sensing pad PD_S1 via the third test line TL_D3. The third test line TL_D3 can be included in the reference... Figure 1 The test lines TL1_1 to TL1_k are described. The first demultiplexer DEMUX1 can select one of the sensing lines RL1 to RL6 and electrically connect it to the first sensing pad PD_S1. It can selectively output the sensing signals from pixels PXL11 to PXL16 and PXL21 to PXL26 via sensing lines RL1 to RL6 to the first sensing pad PD_S1. For example, if the first demultiplexer DEMUX1 electrically connects the first data line DL1 to the first pad PD1, the pixel electrically connected to the first data line DL1 (e.g., the eleventh pixel PXL11 and the twenty-first pixel PXL21) can be tested. Therefore, the first demultiplexer DEMUX1 can select the first sensing line RL1 corresponding to the first data line DL1, electrically connect it to the first sensing pad PD_S1, and output the sensing signal from the pixel to the outside. Therefore, the number of sensing pads (or pads included in the first pad group PDS1) on the display panel 10_2 can be further reduced.

[0177] Reference Figure 12 describe Figure 9 Display panel 10 (or Figure 10 Display panel 10_1 Figure 11 The operation or testing method of the display panel 10_2).

[0178] Figure 12 It is shown in Figure 9 The waveform of an example signal measured in the display panel.

[0179] refer to Figure 1 , Figure 4 , Figures 6 to 8 as well as Figures 9 to 12In the first cycle P1, the first demultiplexer control signal C_DEMUX1 applied to the first control pad PD1_C may have a first switch control signal C_SW1 (or a first control value). In this case, the first demultiplexer DEMUX1 may electrically connect the first data line DL1 to the first pad PD1 in response to the first switch control signal C_SW1. The test voltage applied to the first pad PD1 may be provided to the first data line DL1, and the first data voltage VDATA1 transmitted through the first data line DL1 may have a voltage level (e.g., a logic high level) corresponding to the test voltage during the first cycle P1.

[0180] The second decompositing control signal C_DEMUX2 applied to the second control pad PD2_C during the first cycle P1 can be a logic high-level pulse. In this case, the second decompositing unit DEMUX2 can sequentially provide gate signals (or scan signals and sense scan signals) to scan lines SL1 and SL2 and sense scan lines SSL1 and SSL2 in response to the second decompositing control signal C_DEMUX2.

[0181] For example, such as Figure 12 As shown, each of the first scan signal SC1 applied to the first scan line SL1 and the first sensing scan signal SS1 applied to the first sensing scan line SSL1 can have a gate on-voltage level. In this case, the first data voltage VDATA1 can be applied to the eleventh pixel PXL11, and the eleventh sensing signal V_PXL11 (or eleventh sensing voltage) based on the first data voltage VDATA1 can be output as a sensing signal VSENSE from the eleventh pixel PXL11 to the test device 20 via the first sensing line RL1 (see [reference]). Figure 1 ).

[0182] The eleventh sensing signal V_PXL11 is at the reference Figure 6 and Figure 8 Within the described reference range (e.g., when it is greater than the reference voltage or the second voltage level V2, or less than the first voltage level V1), the light-emitting element LD in the eleventh pixel PXL11 can be determined (see...). Figure 4 It was effectively aligned.

[0183] After that, as Figure 12As shown, each of the second scan signal SC2 applied to the second scan line SL2 and the second sensing scan signal SS2 applied to the second sensing scan line SSL2 can have a gate on-voltage level. In this case, the first data voltage VDATA1 can be applied to the twenty-first pixel PXL21, and the twenty-first sensing signal V_PXL21 (or the twenty-first sensing voltage) based on the first data voltage VDATA1 can be output as a sensing signal VSENSE from the twenty-first pixel PXL21 to the test device 20 via the first sensing line RL1 (see [reference]). Figure 1 ).

[0184] If the 21st sensing signal V_PXL21 is within the reference range, it can be determined that the light-emitting element LD in the 21st pixel PXL21 is effectively aligned.

[0185] Similar to the first cycle P1, in the second cycle P2, the first demultiplexer control signal C_DEMUX1 applied to the first control pad PD1_C can have a second switch control signal C_SW2 (or a second control value). In this case, the first demultiplexer DEMUX1 can electrically connect the second data line DL2 to the first pad PD1 in response to the second switch control signal C_SW2. The test voltage applied to the first pad PD1 can be provided to the second data line DL2, and the second data voltage VDATA2 transmitted through the second data line DL2 can have a voltage level corresponding to the test voltage (e.g., a logic high level) during the second cycle P2.

[0186] The second decompositing control signal C_DEMUX2 applied to the second control pad PD2_C during the second cycle P2 can be a logic high-level pulse. In this case, the second decompositing unit DEMUX2 can sequentially provide gate signals (or scan signals and sense scan signals) to scan lines SL1 and SL2 and sense scan lines SSL1 and SSL2 in response to the second decompositing control signal C_DEMUX2.

[0187] For example, such as Figure 12 As shown, each of the first scan signal SC1 applied to the first scan line SL1 and the first sensing scan signal SS1 applied to the first sensing scan line SSL1 can have a gate on-voltage level. In this case, the second data voltage VDATA2 can be applied to the twelfth pixel PXL12, and the twelfth sensing signal V_PXL12 (or the twelfth sensing voltage) based on the second data voltage VDATA2 can be output as a sensing signal VSENSE from the twelfth pixel PXL12 to the test device 20 via the second sensing line RL2 (see [reference]). Figure 1 ).

[0188] The twelfth sensing signal V_PXL12 is at the reference Figure 6 and Figure 8 Within the described reference range, it can be determined that the light-emitting element LD in the twelfth pixel PXL12 is effectively aligned.

[0189] After that, as Figure 12 As shown, each of the second scan signal SC2 applied to the second scan line SL2 and the second sensing scan signal SS2 applied to the second sensing scan line SSL2 can have a gate on-voltage level. In this case, the second data voltage VDATA2 can be applied to the twentieth pixel PXL22, and the twentieth sensing signal V_PXL22 (or the twentieth sensing voltage) based on the second data voltage VDATA2 can be output as a sensing signal VSENSE from the twentieth pixel PXL22 to the test device 20 via the second sensing line RL2 (see [reference]). Figure 1 ).

[0190] If the 21st sensing signal V_PXL21 is outside the reference range (e.g., if it is less than or equal to the second voltage level V2), it can be determined that the light-emitting element LD in the 22nd pixel PXL22 is not properly aligned.

[0191] Similar to the first cycle P1, in the third cycle P3, the first demultiplexer control signal C_DEMUX1 applied to the first control pad PD1_C can have a third switch control signal C_SW3 (or a third control value). In this case, the first demultiplexer DEMUX1 can electrically connect the third data line DL3 to the first pad PD1 in response to the third switch control signal C_SW3. The test voltage applied to the first pad PD1 can be provided to the third data line DL3, and the third data voltage VDATA3 transmitted through the third data line DL3 can have a voltage level corresponding to the test voltage (e.g., a logic high level) during the third cycle P3.

[0192] The second decompositing control signal C_DEMUX2 applied to the second control pad PD2_C in the third cycle P3 can be a logic high-level pulse. In this case, the second decompositing unit DEMUX2 can sequentially provide gate signals (or scan signals and sense scan signals) to scan lines SL1 and SL2 and sense scan lines SSL1 and SSL2 in response to the second decompositing control signal C_DEMUX2.

[0193] In this case, similar to the first period P1, the thirteenth sensing signal V_PXL13 and the thirteenth sensing signal V_PXL23 can be output sequentially from the thirteenth pixel PXL13 and the thirteenth pixel PXL23, and it can be determined whether the light-emitting element LD in the thirteenth pixel PXL13 and the thirteenth sensing signal V_PXL23 are effectively aligned based on the thirteenth sensing signal V_PXL13 and the thirteenth sensing signal V_PXL23.

[0194] For reference Figure 12 The alignment state of each test light-emitting element (LD) in pixels PXL11 to PXL16 and PXL21 to PXL26 can be determined by the first demultiplexer DEMUX1 and the second demultiplexer DEMUX2.

[0195] Figure 13 This is a schematic flowchart illustrating a testing method for a display panel according to an embodiment of the present disclosure. Figure 14 It shows through Figure 13 A schematic flowchart illustrating the steps involved in determining the alignment state of a light-emitting element.

[0196] Figure 13 The method can be derived from Figure 1 The test device 20, which is connected to the display panel 10, performs the test. The following will refer to... Figures 1 to 14 Provide a detailed description.

[0197] Figure 13 The method allows a test voltage to be applied to each of the data lines DL1 to DLm (S100).

[0198] For reference Figure 6 As described, the test voltage can be set to be greater than the reference voltage, and the voltage level of the reference voltage can be equal to the voltage difference (e.g., 5V) between the total operating voltage of the series-connected light-emitting elements (LDs) and the operating voltage of one of the LDs (e.g., 2.5V). According to an embodiment, the test voltage can be less than or equal to the total operating voltage of the series-connected light-emitting elements (LDs).

[0199] For reference Figures 9 to 12 The description states that a test voltage is applied to the first pad PD1, and the test voltage can be sequentially applied to data lines DL1 through DL6 via the first demultiplexer DEMUX1. (As described) Figure 10 As shown, when the first demultiplexer DEMUX1 includes sub-demultiplexers DEMUX1_1 and DEMUX1_2, test voltages can be applied to some of the data lines DL1 to DL6 simultaneously.

[0200] In one implementation, the first demultiplexer DEMUX1 can sequentially connect the sensing lines to the third pad. (See reference...) Figure 11 As described, the first demultiplexer DEMUX1 can sequentially connect sensing lines RL1 to RL6 to the first sensing pad PD_S1.

[0201] Figure 13 The method can apply a gate signal to each of the gate lines (or scan lines SL1 to SLn and sensing scan lines) (S200).

[0202] For reference Figures 9 to 12 As described, a gate signal can be applied to the second pad PD2, and the gate signal (or scan signal) can be sequentially applied to scan lines SL1 and SL2 via the second demultiplexer DEMUX2. Furthermore, the gate signal (or sensing scan signal) can be sequentially applied to sensing scan lines SSL1 and SSL2 via the second demultiplexer DEMUX2.

[0203] In one implementation, a gate signal can be sequentially applied to the gate line while a test voltage is applied to one of the data lines.

[0204] For reference Figures 9 to 12 As described, when a test voltage is applied to the first data line DL1, scan signals SC1 and SC2 and sensing scan signals SS1 and SS2 can be sequentially applied to scan lines SL1 and SL2 and sensing scan lines SSL1 and SSL2, respectively. Furthermore, when a test voltage is applied to the second data line DL2, scan signals SC1 and SC2 and sensing scan signals SS1 and SS2 can be sequentially applied to scan lines SL1 and SL2 and sensing scan lines SSL1 and SSL2, respectively.

[0205] In this implementation, the gate signal can be simultaneously applied to one of the scan lines and one of the sensing scan lines using the second demultiplexer DEMUX2. (See reference...) Figures 9 to 12 As described, a first scan signal SC1 and a first sensing scan signal SS1 can be simultaneously applied to a first scan line SL1 and a first sensing scan line SSL1, respectively, and thereafter, a second scan signal SC2 and a second sensing scan signal SS2 can be simultaneously applied to a second scan line SL2 and a second sensing scan line SSL2, respectively.

[0206] After that, Figure 13 The method can respond to the gate signal and test voltage measurement by the pixel circuit PXC (see Figure 4 The light-emitting unit (EMU) applied to each of the pixels PXL (see) Figure 4 The sensing voltage at one end of the (S300).

[0207] refer to Figure 4 The test voltage can be applied to the gate electrode of the first transistor T1 (or the driving transistor) in response to the gate signal, and the initialization voltage can be provided to one electrode of the first transistor T1 (i.e., the electrode electrically connected to one end of the light-emitting unit EMU) through the j-th sensing line RLj. After that, the sensing voltage that changes based on the current flowing through the j-th sensing line RLj can be measured when the initialization voltage is stopped.

[0208] After that, Figure 13 The method can determine whether the light-emitting elements LD in each light-emitting unit EMU in pixel PXL are effectively or normally connected in series (i.e., determine the alignment state of the light-emitting elements LD) based on the sensing voltage (S400).

[0209] In the implementation method, such as Figure 14 As shown, Figure 13 The method can determine whether the sensed voltage is greater than the reference voltage (S410), and if the sensed voltage is greater than the reference voltage, it can be determined that the light-emitting element LD is effectively or normally connected in series (S420).

[0210] on the contrary, Figure 13 The method can determine that at least one of the light-emitting elements LD is short-circuited when the sensed voltage is less than or equal to the reference voltage (S430). A repair operation can be performed on at least one light-emitting element (or pixel PXL including it) in the light-emitting element LD that is determined to be short-circuited (S440).

[0211] Therefore, the brightness deviation caused by the ineffective alignment of at least some of the light-emitting elements (LDs) in the pixel PXL can be improved, and the display quality can be improved.

[0212] Figure 15 It is shown schematically in Figure 1 A three-dimensional view of a light-emitting element used as a light source in a display device. Figure 16 yes Figure 15 A schematic cross-sectional view of the light-emitting element.

[0213] In embodiments of this disclosure, the type and / or shape of the light-emitting element are not limited to... Figure 15 and Figure 16 The implementation shown is illustrated.

[0214] refer to Figure 15 and Figure 16The light-emitting element (LD) may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light-emitting element (LD) may be implemented as a light-emitting stacked structure, wherein the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are stacked sequentially.

[0215] The light-emitting element (LD) can be configured to extend in one direction. When the direction of extension of the LD is referred to as the longitudinal direction, the LD can include one end (or lower end) and the other end (or upper end) in the longitudinal direction. At one end (or lower end) of the LD, one of a first semiconductor layer 11 and a second semiconductor layer 13 can be disposed, and at the other end (or upper end) of the LD, the other of the first semiconductor layer 11 and the second semiconductor layer 13 can be disposed. For example, the first semiconductor layer 11 can be disposed at the said one end (or lower end) of the LD, and the second semiconductor layer 13 can be disposed at the other end (or upper end) of the LD.

[0216] The light-emitting element (LD) can be configured in various shapes. For example, the LD can have a rod-like or strip-like shape that is long in the longitudinal direction (i.e., with an aspect ratio greater than 1). In embodiments of this disclosure, the length L of the LD in the longitudinal direction can be greater than its diameter D (or the width of its cross-section). The LD can include a light-emitting diode (LED) manufactured in an ultra-small size, small enough to have a diameter D and / or length L on the micrometer or nanometer scale.

[0217] The diameter D of the light-emitting element (LD) can be from about 0.5 μm to about 500 μm, and its length L can be from about 1 μm to about 10 μm. However, the diameter D and length L of the light-emitting element (LD) are not limited to these, and the size of the light-emitting element (LD) can be changed to meet the requirements (or design conditions) of the lighting device or self-emissive display device to which the light-emitting element (LD) is applied.

[0218] The first semiconductor layer 11 may include at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include a semiconductor material such as InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as Si, Ge, Sn, etc. However, the materials constituting the first semiconductor layer 11 are not limited to these, and various other materials may constitute the first semiconductor layer 11. In embodiments of this disclosure, the first semiconductor layer 11 may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant). The first semiconductor layer 11 may include an upper surface in contact with the active layer 12 and a lower surface exposed to the outside in the direction of the length L of the light-emitting element LD. The lower surface of the first semiconductor layer 11 may be one end (or the lower end) of the light-emitting element LD.

[0219] The active layer 12 can be disposed on the first semiconductor layer 11 and can be formed as a single quantum well structure or a multi-quantum well structure. For example, in the case where the active layer 12 is formed in a multi-quantum well structure, the active layer 12 can have a structure in which a barrier layer (not shown), a strain enhancement layer, and a well layer are periodically stacked as a unit. Since the strain enhancement layer has a smaller lattice constant than the barrier layer, it can further enhance the strain applied to the well layer, such as compressive strain. However, the structure of the active layer 12 is not limited to the embodiments described above.

[0220] The active layer 12 can emit light with a wavelength of about 400 nm to about 900 nm and can use a dual heterostructure. In embodiments of this disclosure, a cladding layer (not shown) doped with a conductive dopant can be formed on and / or below the active layer 12 in the direction of the length L of the light-emitting element LD. For example, the cladding layer can be formed of an AlGaN layer or an InAlGaN layer. According to embodiments, materials such as AlGaN, AlInGaN, etc., can be used to form the active layer 12. However, the materials constituting the active layer 12 are not limited to these, and various other materials can be used to form the active layer 12. The active layer 12 may include a first surface contacting the first semiconductor layer 11 and a second surface contacting the second semiconductor layer 13.

[0221] When an electric field of a predetermined voltage or greater is applied to the end (or opposite end) of the light-emitting element LD, the light-emitting element LD emits light by forming electron-hole pairs in the active layer 12. By controlling the light emission of the light-emitting element LD using this principle, the light-emitting element LD can be used as a light source (or light source) for various light-emitting devices (including pixels of display devices).

[0222] The second semiconductor layer 13 may be disposed on the second surface of the active layer 12 and may include a semiconductor layer of a different type from the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as Mg. However, the materials constituting the second semiconductor layer 13 are not limited to these, and various other materials may be used to form the second semiconductor layer 13. In embodiments of this disclosure, the second semiconductor layer 13 may include gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or p-type dopant). The second semiconductor layer 13 may include a lower surface in contact with the second surface of the active layer 12 and an upper surface exposed to the outside in the direction of the length L of the light-emitting element LD. Here, the upper surface of the second semiconductor layer 13 may be the other end (or the upper end) of the light-emitting element LD.

[0223] In embodiments of this disclosure, the first semiconductor layer 11 and the second semiconductor layer 13 may have different thicknesses along the length L of the light-emitting element LD. For example, the first semiconductor layer 11 may have a relatively thicker thickness than the second semiconductor layer 13 along the length L of the light-emitting element LD. Therefore, the active layer 12 of the light-emitting element LD may be positioned closer to the upper surface of the second semiconductor layer 13 than to the lower surface of the first semiconductor layer 11.

[0224] Each of the first semiconductor layer 11 and the second semiconductor layer 13 is shown as a single layer, but this disclosure is not limited thereto. In embodiments of this disclosure, each of the first semiconductor layer 11 and the second semiconductor layer 13 may further include one or more layers, such as a cladding layer and / or a tensile strain barrier reduction (TSBR) layer, depending on the material of the active layer 12. The TSBR layer may be a strain mitigation layer disposed between semiconductor layers with different lattice structures and serves as a buffer for reducing differences in lattice constants. The TSBR layer may consist of a p-type semiconductor layer such as p-GaInP, p-AlInP, p-AlGaInP, etc., but this disclosure is not limited thereto.

[0225] According to an embodiment, in addition to the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 described above, the light-emitting element LD may further include an additional electrode (not shown, hereinafter referred to as the "first additional electrode") disposed on the second semiconductor layer 13. According to another embodiment, the light-emitting element LD may further include another additional electrode (not shown, hereinafter referred to as the "second additional electrode") disposed at one end of the first semiconductor layer 11.

[0226] Each of the first and second additional electrodes may be an ohmic contact electrode, but this disclosure is not limited thereto. According to embodiments, the first and second additional electrodes may be Schottky contact electrodes. The first and second additional electrodes may include conductive materials (or conductive substances). For example, the first and second additional electrodes may include opaque metals used alone or in combination with chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), and their oxides or alloys, but this disclosure is not limited thereto. According to embodiments, the first and second additional electrodes may include transparent conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), or indium tin zinc oxide (ITZO).

[0227] The materials included in the first and second additional electrodes can be the same or different from each other. The first and second additional electrodes can be substantially transparent or translucent. Therefore, light generated by the light-emitting element LD can be transmitted through each of the first and second additional electrodes to be emitted to the outside of the light-emitting element LD. According to an embodiment, in the case where light generated by the light-emitting element LD is emitted to the outside of the light-emitting element LD through a region other than the two ends of the light-emitting element LD without transmitting through the first and second additional electrodes, the first and second additional electrodes can comprise opaque metals.

[0228] In embodiments of this disclosure, the light-emitting element (LD) may further include an insulating film 14. However, according to embodiments, the insulating film 14 may be omitted, or may be configured to cover only a portion of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, or overlap only a portion of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0229] The insulating film 14 prevents electrical short circuits that may occur when the active layer 12 comes into contact with conductive materials other than the first semiconductor layer 11 and the second semiconductor layer 13. The insulating film 14 minimizes surface defects in the light-emitting element (LD), thereby improving the LD's lifetime and luminous efficiency. When the LDs are closely packed, the insulating film 14 prevents unwanted short circuits that may occur between the LDs. The insulating film 14 may or may not be provided, as long as it prevents short circuits between the active layer 12 and external conductive materials.

[0230] The insulating film 14 can completely surround the outer peripheral surface of the light-emitting stacked component including the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0231] In the embodiments described above, the insulating film 14 is described as completely surrounding the outer peripheral surface of each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13; however, this disclosure is not limited thereto. According to an embodiment, when the light-emitting element LD includes a first additional electrode, the insulating film 14 may completely surround the outer peripheral surface of each of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the first additional electrode. According to another embodiment, the insulating film 14 may not completely surround the outer peripheral surface of the first additional electrode, or it may only surround a portion of the outer peripheral surface of the first additional electrode, and may not surround the remaining portion of the outer peripheral surface of the first additional electrode. According to an embodiment, when the first additional electrode is disposed at the other end (or upper end) of the light-emitting element LD and the second additional electrode is disposed at said one end (or lower end) of the light-emitting element LD, the insulating film 14 may expose at least a portion of each of the first and second additional electrodes.

[0232] The insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include a material selected from silicon dioxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiON), aluminum oxide (AlO) x The insulating material is at least one of the group consisting of titanium dioxide (TiO2), but this disclosure is not limited thereto, and various materials with insulating properties can be used as the material of the insulating film 14.

[0233] The light-emitting elements (LDs) described above can be used as light sources for various display devices. The LDs can be manufactured using surface treatment processes. For example, when the LDs are mixed with a fluid solution (or solvent) and supplied to each light-emitting area (e.g., the light-emitting area of ​​each pixel or the light-emitting area of ​​each sub-pixel), each LD can be surface-treated, thereby allowing the LDs to be uniformly sprayed without uneven aggregation in the solution.

[0234] The light-emitting unit (or light-emitting device) including the light-emitting element LD described above can be used in various types of electronic devices (including display devices) that require a light source. For example, when the light-emitting element LD is disposed in the pixel area of ​​each pixel of a display panel, the light-emitting element LD can be used as a light source for each pixel. However, the application areas of the light-emitting element LD are not limited to the embodiments described above. For example, the light-emitting element LD can be used in other types of electronic devices that include a light source, such as lighting devices.

[0235] While this disclosure has been shown and described with reference to some embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure and its equivalents.

[0236] The technical scope of the invention to be protected shall be determined by the appended claims.

Claims

1. A method for testing a display panel, the display panel comprising pixels electrically connected to gate lines and data lines, each of the pixels comprising a pixel circuit and a light-emitting unit, the pixel circuit being electrically connected to a corresponding gate line and a corresponding data line, the light-emitting unit comprising one end electrically connected to the pixel circuit, the method comprising: Apply a test voltage to each of the data lines; Apply a gate signal to each of the gate lines; In response to the gate signal and the test voltage, the sense voltage applied by the pixel circuit to one end of the light-emitting unit in each of the pixels is measured; as well as Based on the sensed voltage, it is determined whether the light-emitting elements in each of the light-emitting units in the pixel are effectively connected in series.

2. The method according to claim 1, wherein, The test voltage is greater than the reference voltage, and The reference voltage is equal to the voltage difference between the total operating voltage of the series-connected light-emitting elements and the operating voltage of one of the light-emitting elements.

3. The method according to claim 2, wherein, The test voltage is less than or equal to the total operating voltage of the light-emitting element.

4. The method according to claim 2, wherein, Determining whether the light-emitting elements are effectively connected in series includes: determining that all the light-emitting elements are effectively aligned when the sensed voltage is greater than the reference voltage.

5. The method according to claim 2, wherein, Determining whether the light-emitting elements are effectively connected in series includes: determining that at least one of the light-emitting elements is ineffectively aligned when the sensed voltage is less than or equal to the reference voltage.

6. The method according to claim 5, further comprising: If the sensed voltage is less than or equal to the reference voltage, it is determined that at least one of the light-emitting elements is short-circuited; as well as At least one of the light-emitting elements is physically opened by a repair process.

7. The method according to claim 1, wherein, Applying the test voltage to each of the data lines includes: Apply the test voltage to the first pad; and The test voltage is sequentially applied to at least a portion of the data lines via a first demultiplexer electrically connected between the first pad and the data lines.

8. The method according to claim 7, wherein, The first demultiplexer includes a sub-demultiplexer, and Applying the test voltage sequentially to at least a portion of the data lines includes simultaneously applying the test voltage to a portion of the data lines via the sub-demultiplexer.

9. The method according to claim 7, wherein, Applying the gate signal to each of the gate lines includes: Apply the gate signal to the second pad; and The gate signal is sequentially applied to the gate line via a second demultiplexer electrically connected between the second pad and the gate line.

10. The method according to claim 9, wherein, Sequentially applying the gate signal to the gate line includes: sequentially applying the gate signal to the gate line while simultaneously applying the test voltage to one of the data lines.

11. The method according to claim 9, wherein, The gate lines include scan lines and sensing scan lines. The display panel also includes sensing lines. The pixel circuit includes a sensing transistor electrically connected between one end of the light-emitting unit and a corresponding one of the sensing lines, the sensing transistor including a gate electrode electrically connected to a corresponding one of the sensing scan lines, and The gate signal is simultaneously applied to one of the scan lines and one of the sensing scan lines by the second demultiplexer.

12. The method according to claim 11, wherein, The first demultiplexer sequentially connects at least a portion of the sensing lines to the third pad.

13. The method according to claim 1, wherein, Measuring the sensed voltage includes: In response to the gate signal, the test voltage is applied to the gate electrode of the drive transistor in the pixel circuit; An initialization voltage is provided to the electrode of the driving transistor that is electrically connected to one end of the light-emitting unit via a sensing line; Stop providing the initialization voltage while applying the test voltage; and The sensed voltage is measured based on the change in current flowing through the sensed line.

14. A display panel, including: The substrate includes a first region and a second region surrounding the first region; Gate line; Data cable; A pixel is disposed in the first region and electrically connected to the gate line and the data line; The first and second pads are disposed in the second region; as well as A first demultiplexer is disposed in the second region and electrically connected between the first pad and the data line, wherein... Each of the pixels includes: The pixel circuit is electrically connected to a corresponding gate line among the gate lines and a corresponding data line among the data lines, and The light-emitting unit includes one end electrically connected to the pixel circuit, and The light-emitting unit includes light-emitting elements connected in series. The first demultiplexer includes a sub-demultiplexer, and The first pad is directly connected to the sub-demultiplexer.

15. The display panel according to claim 14, wherein, The first demultiplexer sequentially connects the first pad to at least a portion of the data lines.

16. The display panel according to claim 15, wherein, The first pad is simultaneously connected to a portion of the data line via the sub-demultiplexer.

17. The display panel according to claim 14, further comprising: A second demultiplexer is disposed in the second region and electrically connected between the second pad and the gate line.

18. The display panel according to claim 14, wherein, The gate lines include scan lines and sensing scan lines. The display panel also includes sensing lines, and The pixel circuit includes: A driving transistor is electrically connected to one end of the light-emitting unit; A switching transistor, electrically connected between the gate electrode of the driving transistor and a corresponding data line in the data lines, and the switching transistor includes a gate electrode electrically connected to a corresponding scan line in the scan lines; and A sensing transistor is electrically connected between one end of the light-emitting unit and a corresponding one of the sensing lines, the sensing transistor including a gate electrode electrically connected to a corresponding one of the sensing scan lines.

19. The display panel according to claim 18, wherein, The scan lines are respectively connected to the sensing scan lines in the second region.

20. The display panel according to claim 18, further comprising: The third pad is located in the second area. The first demultiplexer sequentially connects at least a portion of the sensing lines to the third pad.

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