Display panel and display device

Abstract

A display panel (100) comprises a display area (AA), a fan-out area (FA) located on one side of the display area (AA), and a binding area (BA) located on the side of the fan-out area (FA) away from the display area (AA). The display panel (100) comprises a gate drive circuit (20) arranged in the display area (100), a plurality of data lines (DL) and a plurality of control signal lines (40) extending from the display area (AA) to the fan-out area (FA), and a plurality of data fan-out leads (30) and a plurality of first fan-out leads (50) arranged in the fan-out area (FA). Each data line (DL) is electrically connected to a data fan-out lead (30), and the plurality of data fan-out leads (30) converge into the binding area (BA). A plurality of control signal lines (40) are electrically connected to the gate drive circuit (20), and the plurality of control signal lines (40) are configured to transmit control signals to the gate drive circuit (20). Each control signal line (40) is electrically connected to a first fan-out lead (50), and a plurality of first fan-out leads (50) are gathered into a binding area (BA).

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, organic light-emitting diode (OLED) display devices have become increasingly popular among consumers due to their high screen-to-body ratio and narrow bezel, which have enhanced people's viewing experience.

[0003] By reducing the width of the OLED display's borders and increasing its screen-to-body ratio, a full-screen design can be achieved. Furthermore, by splicing full-screen displays together, the width of the splicing seams can be reduced, improving the integrity of the display's image.

[0004] Public content

[0005] In one aspect, a display panel is provided, comprising a display area, a fan-out area located on one side of the display area, and a binding area located on a side of the fan-out area away from the display area.

[0006] The display panel includes a gate drive circuit disposed in the display area, a plurality of data lines, a plurality of data fan-out leads, a plurality of control signal lines, and a plurality of first fan-out leads, wherein the plurality of data lines extend from the display area to the fan-out area. A plurality of data fan-out leads are disposed in the fan-out area, each data line being electrically connected to a data fan-out lead, and the plurality of data fan-out leads converge to the first sub-binding area. A plurality of control signal lines are electrically connected to the gate drive circuit, and a plurality of control signal lines are configured to transmit control signals to the gate drive circuit, and the plurality of control signal lines extend from the display area to the fan-out area. A plurality of first fan-out leads are disposed in the fan-out area, each control signal line being electrically connected to a first fan-out lead, and the plurality of first fan-out leads converge to the binding area.

[0007] In some embodiments, the first fan-out lead is electrically connected to an end of the control signal line extending to the fan-out region.

[0008] In some embodiments, the display panel further includes a power supply voltage bus disposed in the fan-out region and extending along the first direction. The first fan-out lead is made of the same material and layer as the power supply voltage bus, and the first fan-out lead detours from one of two opposite sides of the power supply voltage bus along the first direction and extends to a side of the power supply voltage bus away from the display region.

[0009] In some embodiments, the display panel further includes a plurality of first connection lines disposed between the power supply voltage bus and the display area and extending along the first direction, wherein the control signal lines are electrically connected to corresponding first fan-out leads via the first connection lines.

[0010] In some embodiments, the display panel includes a first gate conductive layer and a source-drain conductive layer, wherein the plurality of first fan-out leads, the plurality of first connection lines, and the power supply voltage bus are disposed in the first gate conductive layer. A source-drain conductive layer is disposed on a side of the first gate conductive layer away from the substrate of the display panel, and the plurality of control signal lines, the plurality of data lines, and the plurality of data fan-out leads are disposed in the source-drain conductive layer.

[0011] In some embodiments, the display panel further includes a first insulating layer disposed between the first gate conductive layer and the source / drain conductive layer, wherein the first insulating layer is provided with a first via hole, and the first connecting line is electrically connected to the corresponding control signal line through the first via hole.

[0012] In some embodiments, orthographic projections of the plurality of first fan-out leads on the substrate are staggered with orthographic projections of the plurality of data fan-out leads on the substrate.

[0013] In some embodiments, the display panel further includes a power voltage bus disposed in the fan-out region and extending along the first direction. At least a portion of the first fan-out lead is disposed on a different layer from the power voltage bus and the data fan-out lead. An orthographic projection of the first fan-out lead on the substrate of the display panel partially overlaps with an orthographic projection of the power voltage bus on the substrate, and also partially overlaps with an orthographic projection of at least one data fan-out lead on the substrate.

[0014] In some embodiments, the first fan-out lead includes a first lead segment and a second lead segment that are electrically connected, wherein one end of the first lead segment away from the second lead segment is electrically connected to the control signal line, and the second lead segment extends to the binding area away from one end of the first lead segment.

[0015] In some embodiments, at least one first lead segment includes a first sub-lead segment and a second sub-lead segment that are electrically connected, wherein the first sub-lead segment extends along the first direction and the second sub-lead segment extends along a second direction that is substantially perpendicular to the first direction.

[0016] In some embodiments, the display panel includes a first gate conductive layer, a source / drain conductive layer, and a first electrode layer. The power supply voltage bus is disposed in the first gate conductive layer. The source / drain conductive layer is disposed on a side of the first gate conductive layer away from the substrate. The multiple control signal lines, the multiple data lines, and the multiple data fan-out leads are disposed in the source / drain conductive layer. The first electrode layer is disposed on a side of the source / drain conductive layer away from the substrate. The first lead segment is disposed in the first electrode layer, and the second lead segment is disposed in the source / drain conductive layer or the first gate conductive layer.

[0017] The orthographic projection of the first lead segment on the substrate partially overlaps with the orthographic projection of the power voltage bus on the substrate and partially overlaps with the orthographic projection of at least one data fan-out lead on the substrate. The orthographic projection of the second lead segment on the substrate is staggered with the orthographic projections of the multiple data fan-out leads on the substrate.

[0018] In some embodiments, the display panel further comprises a second insulating layer disposed between the source / drain conductive layer and the first electrode layer, wherein the second insulating layer is provided with a second via and a third via. The first lead segment is electrically connected to the corresponding control signal line via the second via at one end thereof, the first lead segment being away from the second lead segment.

[0019] One end of the first lead segment is proximate to the second lead segment and is electrically connected to the second lead segment through the third via. Alternatively, the display panel further comprises a first insulating layer disposed between the first gate conductive layer and the source / drain conductive layer, wherein a first via is disposed in the first insulating layer, the first via being connected to the third via, and one end of the first lead segment is proximate to the second lead segment and is electrically connected to the second lead segment through the third via and the first via.

[0020] In some embodiments, the display panel further includes a peripheral area surrounding the display area, the peripheral area including a first sub-peripheral area, a second sub-peripheral area, a third sub-peripheral area, and a fourth sub-peripheral area. The first sub-peripheral area and the second sub-peripheral area are respectively located on opposite sides of the display area along a first direction, the third sub-peripheral area and the fourth sub-peripheral area are respectively located on opposite sides of the display area along a second direction, the first direction being substantially perpendicular to the second direction, and the fan-out area and the bonding area are located in the fourth sub-peripheral area.

[0021] The control signal line includes electrically connected first and second routing segments. A portion of the plurality of first routing segments extends from the third sub-peripheral area, along the first sub-peripheral area, to the fan-out area. Another portion of the first routing segments extends from the third sub-peripheral area, along the second sub-peripheral area, to the fan-out area. A plurality of second routing segments extend from the display area to the third sub-peripheral area.

[0022] One end of the first routing segment is electrically connected to one end of the second routing segment extending to the third sub-peripheral area, and the other end of the first routing segment is electrically connected to the corresponding first fan-out lead.

[0023] In some embodiments, the plurality of first fan-out leads, the plurality of control signal lines and the plurality of data fan-out leads are made of the same material and are arranged on the same layer. The plurality of first fan-out leads are arranged on opposite sides of the plurality of data fan-out leads along the first direction.

[0024] In some embodiments, the display panel further includes a power supply voltage bus disposed in the fan-out region and extending along the first direction. The first fan-out lead and the power supply voltage bus are disposed on different layers, and an orthographic projection of the first fan-out lead on the substrate of the display panel partially overlaps with an orthographic projection of the power supply voltage bus on the substrate.

[0025] In some embodiments, the display panel includes a first gate conductive layer and a source / drain conductive layer, the power supply voltage bus is provided in the first gate conductive layer, the source / drain conductive layer is provided on a side of the first gate conductive layer away from the substrate of the display panel, and the multiple control signal lines, the multiple data lines, the multiple data fan-out leads, and the multiple first fan-out leads are provided in the source / drain conductive layer.

[0026] In some embodiments, the display panel further includes a power supply voltage bus disposed in the fan-out region and extending along the first direction. The first routing segment of the control signal line and the plurality of first fan-out leads are made of the same material and disposed on the same layer as the power supply voltage bus. The first fan-out leads detour from one of two opposite sides of the power supply voltage bus along the first direction and extend to a side of the power supply voltage bus away from the display region.

[0027] In some embodiments, the display panel includes a first gate conductive layer and a source-drain conductive layer, wherein the first routing segment, the plurality of first fan-out leads, and the power supply voltage bus are disposed in the first gate conductive layer. The source-drain conductive layer is disposed on a side of the first gate conductive layer away from the substrate of the display panel, and the second routing segment of the control signal line, the plurality of data lines, and the plurality of data fan-out leads are disposed in the source-drain conductive layer.

[0028] In some embodiments, the binding area includes a first sub-binding area and two second sub-binding areas located on opposite sides of the first sub-binding area along a first direction. The multiple data fan-out leads are converged to the first sub-binding area. The multiple first fan-out leads are divided into two groups, and the two groups of first fan-out leads are respectively converged to the two second sub-binding areas.

[0029] In some embodiments, the display panel further comprises a plurality of pins configured to bind a flexible printed circuit board, wherein the plurality of pins comprises a plurality of first pins located in the first sub-binding area and a plurality of second pins located in the second sub-binding area.

[0030] The data fan-out lead is electrically connected to at least one first pin, and the first fan-out lead is electrically connected to at least one second pin.

[0031] In another aspect, a display device is provided, comprising: a display panel as described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0033] Figure 1 is a structural diagram of a display panel according to some embodiments of the present disclosure;

[0034] Figure 2 for Figure 1 A partial enlarged view of the display panel at position M;

[0035] Figure 3 for Figure 2 A cross-sectional view of the display panel along the section line AA';

[0036] Figure 4 is another structural diagram of a display panel according to some embodiments of the present disclosure;

[0037] Figure 5 for Figure 4 A partial enlarged view of position N of the display panel;

[0038] Figure 6 for Figure 5 A cross-sectional view of the display panel along section line BB';

[0039] Figure 7 for Figure 5 Another cross-sectional view of the display panel along the section line BB';

[0040] Figure 8 is another structural diagram of a display panel according to some embodiments of the present disclosure;

[0041] Figure 9 for Figure 8 A partial enlarged view of the display panel at position O;

[0042] Figure 10 for Figure 9 A cross-sectional view of the display panel along the section line CC';

[0043] Figure 11 is another structural diagram of a display panel according to some embodiments of the present disclosure;

[0044] Figure 12 for Figure 11 A cross-sectional view of the display panel along the section line DD';

[0045] Figure 13 is a structural diagram of a display device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0046] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0047] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0048] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0049] When describing some embodiments, the term "electrically connected" and its derivatives may be used. For example, when describing some embodiments, the term "electrically connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0050] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0051] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0052] As used herein, “approximately” includes the stated value and an average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0053] In this article, "same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask template through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses. In contrast, "different layers" refers to a layer structure formed by using corresponding film-forming processes to form film layers for forming specific patterns, and then using corresponding mask templates through a patterning process. For example, "two layer structures are arranged in different layers" means that the two layer structures are formed under corresponding process steps (film-forming process and patterning process).

[0054] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0055] In related art, a display panel adopts a GOA (Gate Driver on Array) driving method, that is, a gate driving circuit in the display panel is directly integrated in a peripheral area located on at least one side of the display area.

[0056] The display panel also includes multiple signal lines disposed in the peripheral region. These signal lines are electrically connected to the gate drive circuit and are used to transmit control signals to the gate drive circuit. However, the gate drive circuit and the multiple signal lines occupy a significant area of ​​the peripheral region, making the peripheral region relatively wide and hindering the narrow-framed display device employing the display panel.

[0057] To solve the above problems, some embodiments of the present disclosure provide a display panel, such as Figure 1 As shown, the display panel 100 includes an active area (AA area for short; also called an effective display area) AA, a fan-out area (FA) located on one side of the display area AA, and a binding area BA located on a side of the fan-out area FA away from the display area AA.

[0058] like Figure 1As shown, a plurality of sub-pixels P are provided in the display area AA of the display panel 100. For the convenience of explanation, the plurality of sub-pixels P disclosed in the present disclosure are described as being arranged in a matrix form. At this time, the sub-pixels P arranged in a row along the first direction X are called a row of sub-pixels, and the sub-pixels P arranged in a row along the second direction Y are called a column of sub-pixels. A row of sub-pixels can be connected to a gate line (GL) GL, and a column of sub-pixels can be connected to a data line (DL) DL. A pixel driving circuit T for controlling the sub-pixels P to display is provided in the sub-pixels P.

[0059] like Figure 1 As shown, the display panel 100 includes a gate driver circuit 20 disposed in the display area AA, that is, the gate driver circuit 20 is directly integrated in the display area AA of the display panel 100, and the gate driver circuit 20 is a GIA (Gatedriver Integrated in Active Array) circuit.

[0060] The gate line GL is electrically connected to the gate driving circuit 20 and is configured to receive a gate scanning signal from the gate driving circuit 20 and transmit the gate scanning signal to the pixel driving circuit 10 in the display area AA. That is, the gate driving circuit 20 is used to drive the gate line GL.

[0061] like Figure 1 As shown, multiple data lines DL extend from the display area AA to the fan-out area FA. The data lines DL are configured to transmit data signals to the pixel driving circuit T located in the display area AA. The display panel 100 also includes multiple data fan-out leads 30 disposed in the fan-out area FA. Each data line DL is electrically connected to a data fan-out lead 30. The multiple data fan-out leads 30 converge into the bonding area BA.

[0062] like Figure 1 As shown, the display panel 100 further includes a plurality of control signal lines 40 and a plurality of first fan-out leads 50, wherein the plurality of control signal lines 40 are electrically connected to the gate driving circuit 20 and are configured to transmit control signals to the gate driving circuit 20. The plurality of control signal lines 40 extend from the display area AA to the fan-out area FA.

[0063] A plurality of first fan-out leads 50 are provided in the fan-out area FA, and each control signal line 40 is electrically connected to a first fan-out lead. The plurality of first fan-out leads 50 are gathered in the bonding area BA.

[0064] It should be noted that Figure 1For illustrative purposes only, the following description uses as an example a case where the display panel 100 is provided with gate driving circuits 20 on both sides along the first direction X within the display area AA, and the gate lines GL are driven by the gate driving circuits 20 on both sides, i.e., double-sided driving. In other embodiments, the display panel 100 may be provided with gate driving circuits 20 on only one side along the first direction X within the display area AA, and the gate lines GL may be driven from only one side, i.e., single-sided driving.

[0065] The following embodiments of the present disclosure are described using bilateral drive as an example.

[0066] The display panel 100 in the above-mentioned embodiment of the present disclosure adopts the GIA driving method to directly integrate the gate driving circuit 20 in the display area AA, which can save the area of ​​the peripheral area of ​​the display panel 100 occupied by the gate driving circuit 20, thereby reducing the width of the peripheral area, which is conducive to the narrow frame of the display device using the display panel 100.

[0067] The specific wiring method of each signal line in the display panel 100 is described below with reference to the accompanying drawings.

[0068] In some embodiments, as Figure 1 and Figure 4 As shown, the first fan-out lead 50 is electrically connected to the end of the control signal line 40 that extends to the fan-out area FA. That is, the control signal line 40 extends from the display area AA to the fan-out area FA, and the end of the control signal line 40 near the fan-out area FA is electrically connected to the first fan-out lead 50. The first fan-out lead 50 and the control signal line 40 do not need to be arranged in other areas outside the display area AA and the fan-out area FA. This reduces the combined length of the control signal line 40 and the first fan-out lead 50 electrically connected thereto. This can alleviate the problem of signal line disconnection caused by excessive length of the signal lines (the first fan-out lead 50 and the control signal line 40), thereby improving the signal line yield.

[0069] In some embodiments, Figure 1 and Figure 2 A wiring method is shown. The display panel 100 includes a power voltage bus 60 disposed in the fan-out area FA. The power voltage bus 60 extends along a first direction X. The power voltage bus 60 is configured to transmit a first power voltage signal.

[0070] Among them, the first fan-out lead 50 is made of the same material and is arranged on the same layer as the power voltage bus 60. The first fan-out lead 50 detours from one of the two opposite sides of the power voltage bus 60 along the first direction X and extends to the side of the power voltage bus 60 away from the display area AA.

[0071] It should be noted that if Figure 1As shown, the entire power voltage bus 60 extends along the first direction X. The power voltage bus 60 includes a main line segment extending along the first direction X, and a branch line segment electrically connected to the main line and extending to the first bonding area BA1.

[0072] For example, Figure 2 As shown, the first fan-out lead 50 includes a first lead segment 51 extending along the second direction Y, and a second lead segment 52 extending along the first direction X. The first lead segment 51 of the first fan-out lead 50 is located on one of the two opposite sides of the power supply voltage bus 60 along the first direction X, and the second lead segment 52 of the first fan-out lead 50 extends to a side of the power supply voltage bus 60 away from the display area AA.

[0073] By adopting the above-mentioned wiring method of the first fan-out lead 50, the first fan-out lead 50 is insulated from the power supply voltage bus 60. In addition, the first fan-out lead 50 does not need to be arranged in other areas outside the fan-out area FA, so that the length of the first fan-out lead 50 is shortened. This can improve the problem of the first fan-out lead 50 being broken due to its excessive length and improve the yield of the first fan-out lead 50.

[0074] In some embodiments, as Figure 1 and Figure 2 As shown, the display panel 100 further includes a plurality of first connection lines 70, which are disposed between the power voltage bus 60 and the display area AA and extend along a first direction X. Figure 1 , the first connection line 70 is provided in the fan-out area FA. The control signal line 40 is electrically connected to the corresponding first fan-out lead 50 through the first connection line 70 to achieve transmission of control signals between the control signal line 40 and the corresponding first fan-out lead 50.

[0075] In some embodiments, Figure 3 Shown Figure 2 The display panel 100 is a cross-sectional view along the section line AA′ in FIG. 1 . The display panel 100 includes a first gate conductive layer 102 and a source-drain conductive layer 103 . The source-drain conductive layer 103 is disposed on a side of the first gate conductive layer 102 away from the substrate 101 of the display panel 100 .

[0076] The plurality of first fan-out leads 50, the plurality of first connection lines 70, and the power supply voltage bus 60 are provided in the first gate conductive layer 101. That is, the plurality of first fan-out leads 50, the plurality of first connection lines 70, and the power supply voltage bus 60 are provided in the same layer. The plurality of control signal lines 40, the plurality of data lines DL, and the plurality of data fan-out leads 30 are provided in the source-drain conductive layer 103. That is, the plurality of control signal lines 40, the plurality of data lines DL, and the plurality of data fan-out leads 30 are provided in the same layer.

[0077] It is understood that, since the plurality of first fan-out leads 50 and the plurality of first connection lines 70 are disposed on the same layer, the first connection lines 70 are directly electrically connected to the corresponding first fan-out leads 50. Similarly, the plurality of data lines DL and the plurality of data fan-out leads 30 are disposed on the same layer, and the data lines DL are directly electrically connected to the corresponding data fan-out leads 30.

[0078] In some embodiments, as Figure 3 As shown, the display panel 100 further includes a first insulating layer 104, which is disposed between the first gate conductive layer 101 and the source / drain conductive layer 103. A first via H1 is defined in the first insulating layer 104. The first connecting lines 70 are electrically connected to the corresponding control signal lines 40 through the first via H1, thereby enabling transmission of control signals between the control signal lines 40 and the corresponding first connecting lines 70.

[0079] It should be noted that the manufacturing process of the display panel 100 includes: sequentially forming a first gate conductive layer 101, a first insulating layer 104, and a source-drain conductive layer 103 on a substrate 101. As can be seen from the above, a plurality of first connecting lines 70 are provided in the first gate conductive layer 101, and a plurality of control signal lines 40 are provided in the source-drain conductive layer 103. That is, a plurality of first connecting lines 70 are first manufactured, and then a first insulating layer 104 covering the plurality of first connecting lines 70 is manufactured. The first insulating layer 104 is provided with a first via H1 exposing the first connecting lines 70. Finally, a plurality of control signal lines 40 are manufactured, so that at least a portion of each control signal line 40 is electrically connected to the first connecting line 70 within the first via H1, thereby achieving cross-layer electrical connection between the first connecting line 70 and the corresponding control signal line 40.

[0080] It can be understood that "cross-layer" refers to a cross-layer structure. For example, "cross-layer electrical connection between the first connecting line 70 and the corresponding control signal line 40" means that the first insulating layer 104 is arranged between the first gate conductive layer 101 and the source and drain conductive layer 103, and multiple first connecting lines 70 are arranged in the first gate conductive layer 101, and multiple control signal lines 40 are arranged in the source and drain conductive layer 103, and the first connecting line 70 and the corresponding control signal line 40 are electrically connected across the first insulating layer 104.

[0081] In some embodiments, as Figure 2 As shown, the orthographic projections of the plurality of first fan-out leads 50 on the substrate 101 are staggered with the orthographic projections of the plurality of data fan-out leads 30 on the substrate 101, thereby avoiding overlap between the first fan-out leads 50 and the data fan-out leads 30 along the thickness direction Z of the substrate 101, thereby avoiding the generation of parasitic capacitance between the first fan-out leads 50 and the data fan-out leads 30, which would cause interference between signals transmitted by different signal lines.

[0082] In some embodiments, Figure 4 and Figure 5 Another wiring method is shown. The display panel 100 includes a power supply voltage bus 60 disposed in the fan-out area FA, and the power supply voltage bus 6 extends along the first direction X.

[0083] At least a portion of the first fan-out lead 50 is disposed on a different layer from the power voltage bus 60 and the data fan-out lead 30. That is, at least a portion of the first fan-out lead 50 does not belong to the same structural layer as the power voltage bus 60 and the data fan-out lead 30. The orthographic projection of the first fan-out lead 50 on the substrate 101 of the display panel 100 partially overlaps with the orthographic projection of the power voltage bus 60 on the substrate 101, and also partially overlaps with the orthographic projection of at least one data fan-out lead 30 on the substrate 101.

[0084] In the above-described embodiment of the present disclosure, the orthographic projection of the first fan-out lead 50 on the substrate 101 of the display panel 100 partially overlaps with the orthographic projection of the power voltage bus 60 on the substrate 101, and also partially overlaps with the orthographic projection of at least one data fan-out lead 30 on the substrate 101. That is, along the thickness direction Z of the substrate 101, the first fan-out lead 50 partially overlaps with the power voltage bus 60, and the first fan-out lead 50 partially overlaps with at least one data fan-out lead 30. This allows the first fan-out lead 50 to converge to the bonding area BA without having to detour around the power voltage bus 60 and the data fan-out lead 30. This further reduces the length of the first fan-out lead 50, improves the problem of disconnection caused by the excessive length of the first fan-out lead 50, and thereby improves the yield of the first fan-out lead 50.

[0085] Furthermore, since the length of the first fan-out lead 50 is reduced, the area of ​​the fan-out area FA occupied by the first fan-out lead 50 does not increase, and therefore, the width of the frame of the display device corresponding to the fan-out area FA does not increase.

[0086] In some embodiments, as Figure 4 and Figure 5 As shown, the first fan-out lead 50 includes an electrically connected first lead segment 51 and a second lead segment 52, wherein one end of the first lead segment 51 away from the second lead segment 52 is electrically connected to the control signal line 40, and one end of the second lead segment 52 away from the first lead segment 51 extends to the binding area BA (second sub-binding area BA2).

[0087] It can be understood that, among the first lead segment 51 and the second lead segment 52 included in the first fan-out lead 50, the first lead segment 51 is used to electrically connect with the control signal line 40 to realize the electrical connection between the first fan-out lead 50 and the control signal line 40; the second lead segment 52 extends to the second sub-binding area BA2 to realize the convergence of multiple first fan-out leads 50 to the second sub-binding area BA2.

[0088] In some embodiments, as Figure 5 As shown, at least one first lead segment 51 includes a first sub-lead segment 511 and a second sub-lead segment 512 that are electrically connected. The first sub-lead segment 511 extends along a first direction X, and the second sub-lead segment 512 extends along a second direction Y. The second direction Y is substantially perpendicular to the first direction X.

[0089] It is understandable that, combined with Figure 5 Among the multiple control signal lines 40, some are close to the second sub-binding area BA2, while some are far from the second sub-binding area BA2. The first fan-out leads 50 electrically connected to the control signal lines 40 far from the second sub-binding area BA2 need to cross the data fan-out leads 30 and converge into the second sub-binding area BA2. Therefore, the first lead segment 51 of the first fan-out lead 50 electrically connected to the control signal lines 40 far from the second sub-binding area BA2 is configured to include a first sub-lead segment 511 and a second sub-lead segment 512. The first sub-lead segment 511 extends along the first direction X and crosses the data fan-out lead 30 to electrically connect to the second lead segment 52, thereby achieving electrical connection between the first lead segment 51 and the second lead segment 52.

[0090] In some embodiments, Figure 6 Shown Figure 5 The display panel 100 is a cross-sectional view along the section line BB', wherein the display panel 100 includes a first gate conductive layer 102, a source-drain conductive layer 103, and a first electrode layer 105 stacked in sequence, wherein the source-drain conductive layer 103 is arranged on a side of the first gate conductive layer 102 away from the substrate 101 of the display panel 100, and the first electrode layer 105 is arranged on a side of the source-drain conductive layer 103 away from the substrate 101 of the display panel 100.

[0091] The power supply voltage bus 60 is provided in the first gate conductive layer 101. A plurality of control signal lines 40, a plurality of data lines DL, and a plurality of data fan-out leads 30 are provided in the source-drain conductive layer 103. That is, the plurality of control signal lines 40, the plurality of data lines DL, and the plurality of data fan-out leads 30 are provided in the same layer. A first lead segment 51 is provided in the first electrode layer 105. A second lead segment 52 is provided in the source-drain conductive layer 103 or the first gate conductive layer 102.

[0092] It can be understood that, since the plurality of data lines DL and the plurality of data fan-out leads 30 are disposed in the same layer, the data lines DL are directly electrically connected to the corresponding data fan-out leads 30 .

[0093] like Figure 4 and Figure 5As shown, the orthographic projection of the first lead segment 51 on the substrate 101 partially overlaps with the orthographic projection of the power supply voltage bus 60 on the substrate 101, and also partially overlaps with the orthographic projection of at least one data fan-out lead 30 on the substrate 101. That is, along the thickness direction Z of the substrate 101, the first lead segment 51 partially overlaps with the power supply voltage bus 60, and the first lead segment 51 partially overlaps with the at least one data fan-out lead 30. This eliminates the need for the first lead segment 51 to bypass the power supply voltage bus 60 and the data fan-out lead 30, reducing the length of the first lead segment 51 and, consequently, the length of the first fan-out lead 50. This mitigates the problem of disconnection of the first fan-out lead 50 due to its excessive length, thereby improving the yield of the first fan-out lead 50.

[0094] Furthermore, since the length of the first lead segment 51 is reduced, the length of the first fan-out lead 50 is reduced, and the area occupied by the first fan-out lead 50 in the fan-out area FA does not increase. Therefore, the width of the frame of the display device corresponding to the fan-out area FA does not increase.

[0095] like Figure 4 and Figure 5 As shown, the orthographic projection of the second lead segment 52 on the substrate 101 is staggered with the orthographic projections of the multiple data fan-out leads 30 on the substrate 101, thereby avoiding overlap between the second lead segment 52 and the data fan-out leads 30 along the thickness direction Z of the substrate 101, thereby avoiding the generation of parasitic capacitance between the second lead segment 52 of the first fan-out lead 50 and the data fan-out lead 30, which would cause interference between signals transmitted by different signal lines.

[0096] In some embodiments, as Figure 6 As shown, the display panel 100 further includes a second insulating layer 106 . The second insulating layer 106 is disposed between the source-drain conductive layer 103 and the first electrode layer 105 . A second via hole H2 and a third via hole H3 are disposed in the second insulating layer 106 .

[0097] The end of the first lead segment 51 away from the second lead segment 52 is electrically connected to the corresponding control signal line 40 through the second via H2. It can be understood that the second insulating layer 106 is provided with a second via H2 that exposes the control signal line 40. At least a portion of each first lead segment 51 is electrically connected to the control signal line 40 within the second via H2, thereby achieving cross-layer electrical connection between the first lead segment 51 and the corresponding control signal line 40.

[0098] like Figure 6As shown, when the second lead segment 52 is disposed in the source-drain conductive layer 103, one end of the first lead segment 51, which is close to the second lead segment 52, is electrically connected to the second lead segment 52 through the third via H3. It can be understood that the second insulating layer 106 is provided with a third via H3 that exposes the second lead segment 52. At least a portion of each first lead segment 51 is electrically connected to the second lead segment 52 within the third via H3, thereby achieving cross-layer electrical connection between the first lead segment 51 and the corresponding second lead segment 52.

[0099] Or, as Figure 7 As shown, the display panel 100 further includes a first insulating layer 104 . The first insulating layer 104 is disposed between the first gate conductive layer 102 and the source / drain conductive layer 103 . A first via hole H1 is disposed in the first insulating layer 104 .

[0100] It should be noted that the via holes in the first insulating layer 104 are collectively referred to as first via holes H1. Figure 3 and Figure 7 It can be seen that Figure 3 The first via H1 in Figure 7 The first via H1 in is a different via, i.e. Figure 3 The position of the first via hole H1 in the first insulating layer 104 is Figure 7 The positions of the first via holes H1 in the first insulating layer 104 are different.

[0101] When the second lead segment 52 is disposed in the first gate conductive layer 102 and the first via H1 is connected to the third via H3, the first lead segment 51, located near one end of the second lead segment 52, is electrically connected to the second lead segment 52 through the third via H3 and the first via H1. It will be appreciated that the first via H1 and the third via H3 are connected and expose the second lead segment 52, and at least a portion of each first lead segment 51 is electrically connected to the second lead segment 52 within the via formed by the first via H1 and the third via H3, thereby achieving cross-layer electrical connection between the first lead segment 51 and the corresponding second lead segment 52.

[0102] In some embodiments, Figure 8 and Figure 9 Another wiring arrangement is shown. The display panel 100 further includes a peripheral area BB surrounding the display area AA. The peripheral area BB includes a first sub-peripheral area BB1, a second sub-peripheral area BB2, a third sub-peripheral area BB3, and a fourth sub-peripheral area BB4. The first sub-peripheral area BB1 and the second sub-peripheral area BB2 are located on opposite sides of the display area AA along a first direction X. The third sub-peripheral area BB3 and the fourth sub-peripheral area BB4 are located on opposite sides of the display area AA along a second direction Y. The first direction X is substantially perpendicular to the second direction Y.

[0103] The fan-out area FA and the bonding area BA mentioned above are located in the fourth sub-peripheral area BB4 , that is, the fan-out area FA and the bonding area BA also belong to the peripheral area BB of the display panel 100 , and belong to the fourth sub-peripheral area BB4 in the peripheral area BB.

[0104] like Figure 8 and Figure 9 As shown, the control signal line 40 includes electrically connected first routing segments 41 and second routing segments 42. A portion of the plurality of first routing segments 41 extends from the third peripheral sub-area BB3, along the first peripheral sub-area BB1, to the fan-out area FA. Another portion of the first routing segments 41 extends from the third peripheral sub-area BB3, along the second peripheral sub-area BB2, to the fan-out area FA. A plurality of second routing segments 42 extend from the display area AA to the third peripheral sub-area BB3.

[0105] One end of the first routing segment 41 is electrically connected to one end of the second routing segment 42 extending to the third sub-peripheral area BB3 , and the other end of the first routing segment 41 is electrically connected to the corresponding first fan-out lead 50 .

[0106] In the above-described embodiment of the present disclosure, the control signal lines 40 extend from the display area AA to the third sub-peripheral area BB3. A portion of the control signal lines 40 extends from the third sub-peripheral area BB3 along the first sub-peripheral area BB1 to the fan-out area FA, while another portion of the control signal lines 40 extends from the third sub-peripheral area BB3 along the second sub-peripheral area BB2 to the fan-out area FA. In other words, the control signal lines 40 extend from the side of the display area AA away from the fan-out area FA along the second direction Y to the third sub-peripheral area BB3, and then extend along the first sub-peripheral area BB1 or the second sub-peripheral area BB2 to the fan-out area FA.

[0107] By adopting the above-mentioned routing design, the length of the control signal line 40 can be made longer, and the resistance value of the control signal line 40 can be increased, which is conducive to reducing the difference in resistance values ​​between different control signal lines 40 and the ratio of the resistance value of each control signal line 40, thereby reducing the difference in IR-Drop (voltage drop) generated by the transmission of control signals by different control signal lines 40, thereby improving the phenomenon of horizontal stripes on the display screen of the display device.

[0108] Furthermore, with the above-mentioned routing design, the arrangement of the control signal line 40 does not increase the width of the peripheral area BB of the display panel 100. The arrangement area of ​​the control signal line 40 in the peripheral area BB corresponds to the package frame of the display device. Therefore, the arrangement of the control signal line 40 does not increase the width of the package frame of the display device.

[0109] In some embodiments, as Figure 8 and Figure 9As shown, the first fan-out leads 50 , the control signal lines 40 and the data fan-out leads 30 are made of the same material and are arranged on the same layer. The first fan-out leads 50 are arranged on opposite sides of the data fan-out leads 30 along the first direction X.

[0110] By adopting the above-mentioned wiring method of the first fan-out lead 50, the first fan-out lead 50 and the data fan-out lead 30 are insulated from each other, and the first fan-out lead 50 and the data fan-out lead 30 are arranged compactly along the first direction X, which can improve the utilization rate of the area of ​​the fan-out area FA, thereby reducing the width of the fan-out area FA, which is conducive to the narrow frame of the display device using the display panel 100.

[0111] In some embodiments, as Figure 8 and Figure 9 As shown, the display panel 100 further includes a power voltage bus 60 disposed in the fan-out area FA, and the power voltage bus 60 extends along the first direction X.

[0112] The first fan-out leads 50 and the power supply voltage bus 60 are arranged on different layers. The orthographic projection of the first fan-out leads 50 on the substrate 101 of the display panel 100 partially overlaps with the orthographic projection of the power supply voltage bus 60 on the substrate 101. This can reduce the area of ​​the fan-out area FA occupied by the first fan-out leads 50, thereby facilitating a reduction in the width of the fan-out area FA and facilitating a narrow frame of a display device using the display panel 100.

[0113] In some embodiments, Figure 10 Shown Figure 9 The display panel 100 is a cross-sectional view along the section line CC′ in FIG. 1 . The display panel 100 includes a first gate conductive layer 102 and a source-drain conductive layer 103 . The source-drain conductive layer 103 is disposed on a side of the first gate conductive layer 102 away from the substrate 101 of the display panel 100 .

[0114] The power supply voltage bus 60 is provided in the first gate conductive layer 102. The plurality of control signal lines 40, the plurality of data lines DL, the plurality of data fan-out leads 30, and the plurality of first fan-out leads 50 are provided in the source-drain conductive layer 103. That is, the plurality of control signal lines 40, the plurality of data lines DL, the plurality of data fan-out leads 30, and the plurality of first fan-out leads 50 are provided in the same layer.

[0115] It is understood that, since the multiple data lines DL and the multiple data fan-out leads 30 are arranged on the same layer, the data lines DL are directly electrically connected to the corresponding data fan-out leads 30. Similarly, the multiple control signal lines 40 and the multiple first fan-out leads 50 are arranged on the same layer, and the control signal lines 40 are directly electrically connected to the corresponding first fan-out leads 50.

[0116] like Figure 11As shown, in other embodiments, the first routing segment 41 of the control signal line 10 and the plurality of first fan-out leads 50 are made of the same material and arranged on the same layer as the power voltage bus 60, and the first fan-out leads 50 detour from one of the two opposite sides of the power voltage bus 60 along the first direction X and extend to the side of the power voltage bus 60 away from the display area AA.

[0117] By adopting the above-mentioned wiring method of the first fan-out lead 50, the first fan-out lead 50 is insulated from the power supply voltage bus 60, and the first fan-out lead 50 and the power supply voltage bus 60 are arranged compactly along the first direction X, which can improve the utilization rate of the area of ​​the fan-out area FA, thereby reducing the width of the fan-out area FA, which is conducive to the narrow frame of the display device using the display panel 100.

[0118] In some embodiments, as Figure 11 and Figure 12 As shown, the first routing segment 41 , multiple first fan-out leads 50 and the power voltage bus 60 are arranged in the first gate conductive layer 102 , and the second routing segment 42 of the control signal line 40 , multiple data lines DL and multiple data fan-out leads 30 are arranged in the source and drain conductive layer 103 .

[0119] Since the first routing segment 41 of the control signal line 40 is disposed in the first gate conductive layer 102 and the second routing segment 42 is disposed in the source-drain conductive layer 103, in order to achieve electrical connection between the first routing segment 41 and the second routing segment 42, in some embodiments, as shown in FIG. Figure 12 As shown, the display panel 100 includes a first insulating layer 104 disposed between the first gate conductive layer 102 and the source / drain conductive layer 103 . A first via hole H1 is provided in the first insulating layer 104 . The first wiring segment 41 is electrically connected to the corresponding second wiring segment 42 through the first via hole H1 .

[0120] It should be noted that the via holes in the first insulating layer 104 are collectively referred to as first via holes H1. Figure 8 It can be seen that the position where the first routing segment 41 is electrically connected to the corresponding second routing segment 42 is located in the third sub-peripheral area BB3 , that is, the first insulating layer 104 has a first via H1 formed at a corresponding position in the third sub-peripheral area BB3 .

[0121] In some embodiments, as Figure 1 、 Figure 4 and Figure 8 As shown, the binding area BA includes a first sub-binding area BA1 and at least one second sub-binding area BA2 arranged in parallel along the first direction X, multiple data fan-out leads 30 are gathered in the first sub-binding area BA1, and at least one of the multiple first fan-out leads 50 is gathered in the second sub-binding area BA2.

[0122] Exemplarily, the display panel 100 is provided with a gate drive circuit 20 on one side of the display area AA along the first direction X, driving each gate line GL from a single side, i.e., unilateral drive. In this case, the bonding area BA includes a first sub-bonding area BA1 and a second sub-bonding area BA2 arranged in parallel along the first direction X. Multiple data fan-out leads 30 converge into the first sub-bonding area BA1, and at least one of the multiple first fan-out leads 50 converges into the second sub-bonding area BA2.

[0123] In the above-mentioned embodiment of the present disclosure, the first sub-binding area BA1 and the second sub-binding area BA2 are arranged in parallel, and multiple data fan-out leads 30 are gathered to the first sub-binding area BA1, and at least one of the multiple first fan-out leads 50 is gathered to the second sub-binding area BA2. The area where the first fan-out leads 50 are gathered is located on one side of the area where the multiple data fan-out leads 30 are gathered along the first direction X, so that the first fan-out leads 50 and the data fan-out leads 30 are compactly arranged in the fan-out area FA, which can improve the utilization rate of the area of ​​the fan-out area FA, thereby reducing the width of the fan-out area FA, which is conducive to the narrow frame of the display device using the display panel 100.

[0124] In some embodiments, the display panel 100 is provided with gate driving circuits 20 on both sides of the display area AA along the first direction X, and each gate line GL is driven by the gate driving circuits 20 on both sides, i.e., double-sided driving. Figure 1 、 Figure 4 and Figure 8 As shown, the binding area BA includes a first sub-binding area BA1 and two second sub-binding areas BA2 located on opposite sides of the first sub-binding area BA1 along the first direction X. Multiple data fan-out leads 30 are gathered in the first sub-binding area BA1, and multiple first fan-out leads 50 are divided into two groups. The two groups of first fan-out leads 50 are respectively gathered in the two second sub-binding areas BA2.

[0125] In the above-mentioned embodiment of the present disclosure, the two second sub-binding areas BA2 are respectively located on the opposite sides of the first sub-binding area BA1 along the first direction X, and the plurality of data fan-out leads 30 are gathered to the first sub-binding area BA1, and the plurality of first fan-out leads 50 are divided into two groups, one group of first fan-out leads 50 is gathered to the second sub-binding area BA2 on one side, and the other group of first fan-out leads 50 is gathered to the second sub-binding area BA2 on the other side, that is, the areas where the two groups of first fan-out leads 50 are gathered are respectively located on the opposite sides of the area where the plurality of data fan-out leads 30 are gathered along the first direction X, so that the first fan-out leads 50 and the data fan-out leads 30 are compactly arranged in the fan-out area FA, which can improve the utilization rate of the area of ​​the fan-out area FA, thereby reducing the width of the fan-out area FA, which is conducive to the narrow frame of the display device using the display panel 100.

[0126] In some embodiments, as Figure 1 、 Figure 4 and Figure 8 As shown, the display panel 100 further includes a power supply voltage line 80 disposed in the fan-out area FA. The power supply voltage line 80 extends entirely along the first direction X. The power supply voltage line 80 includes a main line segment extending along the first direction X, and a branch line segment electrically connected to the main line segment and extending to the first bonding area BA1. The power supply voltage line 80 is configured to transmit a second power supply voltage signal.

[0127] In some embodiments, as Figure 2 、 Figure 5 and Figure 9 As shown, the display panel 100 further includes a plurality of pins 90 configured to bind the flexible printed circuit board, including a plurality of first pins 91 located in a first sub-binding area BA1 and a plurality of second pins 92 located in a second sub-binding area BA2.

[0128] Each data fan-out lead 30 is electrically connected to at least one first pin 91 , and each first fan-out lead 50 is electrically connected to at least one second pin 92 .

[0129] For example, Figure 2 、 Figure 5 and Figure 9 As shown, each data fan-out lead 30 is electrically connected to a first pin 91. Each first fan-out lead 50 is electrically connected to a second pin 92.

[0130] Exemplarily, each data fan-out lead 30 is electrically connected to two first pins 91 , and each first fan-out lead 50 is electrically connected to two second pins 92 .

[0131] Some embodiments of the present disclosure further provide a display device, such as Figure 11 As shown, the display device 200 includes the display panel 100 in any of the above embodiments.

[0132] In the above-mentioned embodiment of the present disclosure, the display panel 100 of the display device 200 adopts the GIA driving method, and the gate driving circuit 20 is directly integrated into the display area AA, which can save the area of ​​the peripheral area of ​​the display panel 100 occupied by the gate driving circuit 20, thereby reducing the width of the peripheral area, which is conducive to the narrow frame of the display device 200.

[0133] Furthermore, the first fan-out leads 50 and the data fan-out leads 30 in the display panel 100 are compactly arranged in the fan-out area FA, which can improve the utilization rate of the area of ​​the fan-out area FA, thereby reducing the width of the fan-out area FA, which is beneficial to the narrow frame of the display device using the display panel 100.

[0134] The display device 200 may be an electroluminescent display device, and the electroluminescent display device may be an OLED display device.

[0135] The display device 200 may be any device that displays an image, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual or graphic. More specifically, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), and the like.

[0136] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel comprising a display area, a fan-out area located on one side of the display area, and a binding area located on a side of the fan-out area away from the display area; The display panel includes: a plurality of data lines extending from the display area to the fan-out area; A plurality of data fan-out leads are arranged in the fan-out area; Each data line is electrically connected to a data fan-out lead; the plurality of data fan-out leads are gathered into the binding area; A gate driving circuit is provided in the display area; a plurality of control signal lines electrically connected to the gate drive circuit and configured to transmit control signals to the gate drive circuit; the plurality of control signal lines extending from the display area to the fan-out area along a second direction and in a direction close to the fan-out area, or extending to an edge of the display area along a direction away from the fan-out area and extending around the display area to the fan-out area; the second direction is parallel to an arrangement direction of the display area and the fan-out area; A plurality of first fan-out leads are provided in the fan-out area; each control signal line is electrically connected to a first fan-out lead; the plurality of first fan-out leads are gathered in the binding area; Wherein, the plurality of data lines and the plurality of control signal lines are arranged in the same layer.

2. The display panel according to claim 1, wherein The first fan-out lead is electrically connected to one end of the control signal line extending to the fan-out region.

3. The display panel according to claim 2, further comprising: a power voltage bus, disposed in the fan-out region and extending along a first direction; The first fan-out lead is made of the same material as the power voltage bus and is arranged on the same layer. The first fan-out lead detours from one of the two opposite sides of the power voltage bus along the first direction and extends to the side of the power voltage bus away from the display area.

4. The display panel according to claim 3, further comprising: a plurality of first connection lines, disposed between the power voltage bus and the display area and extending along the first direction; The control signal line is electrically connected to the corresponding first fan-out lead through a first connecting line.

5. The display panel according to claim 4, comprising: a first gate conductive layer, wherein the plurality of first fan-out leads, the plurality of first connection lines and the power supply voltage bus are arranged in the first gate conductive layer; The source-drain conductive layer is arranged on a side of the first gate conductive layer away from the substrate of the display panel, and the multiple control signal lines, the multiple data lines and the multiple data fan-out leads are arranged on the source-drain conductive layer.

6. The display panel according to claim 5, further comprising: a first insulating layer, disposed between the first gate conductive layer and the source / drain conductive layer; A first via hole is provided in the first insulating layer; The first connecting line is electrically connected to the corresponding control signal line through the first via hole.

7. The display panel according to claim 5 or 6, wherein: The orthographic projections of the plurality of first fan-out leads on the substrate are staggered with the orthographic projections of the plurality of data fan-out leads on the substrate.

8. The display panel according to claim 2, further comprising: a power voltage bus, disposed in the fan-out region and extending along a first direction; Wherein, at least part of the first fan-out lead is arranged in a different layer from the power supply voltage bus and the data fan-out lead; The orthographic projection of the first fan-out lead on the substrate of the display panel partially overlaps with the orthographic projection of the power voltage bus on the substrate, and partially overlaps with the orthographic projection of at least one data fan-out lead on the substrate.

9. The display panel according to claim 8, wherein: The first fan-out lead includes a first lead segment and a second lead segment that are electrically connected; One end of the first lead segment away from the second lead segment is electrically connected to the control signal line; The second lead segment extends to the binding area at one end away from the first lead segment.

10. The display panel according to claim 9, wherein: At least one first lead segment includes a first sub-lead segment and a second sub-lead segment that are electrically connected; The first sub-lead segment extends along the first direction; The second sub-lead segment extends along a second direction; the second direction is substantially perpendicular to the first direction.

11. The display panel according to claim 9 or 10, comprising: a first gate conductive layer, wherein the power supply voltage bus is provided on the first gate conductive layer; a source-drain conductive layer, arranged on a side of the first gate conductive layer away from the substrate, wherein the plurality of control signal lines, the plurality of data lines and the plurality of data fan-out leads are arranged on the source-drain conductive layer; A first electrode layer is provided on a side of the source / drain conductive layer away from the substrate; Wherein, the first lead segment is provided on the first electrode layer, and the second lead segment is provided on the source-drain conductive layer or the first gate conductive layer; The orthographic projection of the first lead segment on the substrate partially overlaps with the orthographic projection of the power voltage bus on the substrate, and partially overlaps with the orthographic projection of at least one data fan-out lead on the substrate; The orthographic projection of the second lead segment on the substrate is staggered with the orthographic projections of the plurality of data fan-out leads on the substrate.

12. The display panel according to claim 11, further comprising: a second insulating layer, disposed between the source-drain conductive layer and the first electrode layer; a second via hole and a third via hole being disposed in the second insulating layer; Wherein, one end of the first lead segment is away from the second lead segment and is electrically connected to the corresponding control signal line through the second via hole; The first lead segment is close to one end of the second lead segment and is electrically connected to the second lead segment through the third via; or, the display panel also includes a first insulating layer arranged between the first gate conductive layer and the source and drain conductive layer, and a first via is provided in the first insulating layer, and the first via is connected to the third via, and the first lead segment is close to one end of the second lead segment and is electrically connected to the second lead segment through the third via and the first via.

13. The display panel according to claim 1 , further comprising a peripheral area surrounding the display area, the peripheral area comprising a first sub-peripheral area, a second sub-peripheral area, a third sub-peripheral area, and a fourth sub-peripheral area; the first sub-peripheral area and the second sub-peripheral area are respectively located on opposite sides of the display area along a first direction, the third sub-peripheral area and the fourth sub-peripheral area are respectively located on opposite sides of the display area along a second direction, the first direction being substantially perpendicular to the second direction; the fan-out area and the bonding area are located in the fourth sub-peripheral area; The control signal line includes a first routing segment and a second routing segment that are electrically connected; A portion of the plurality of first routing segments extends from the third sub-peripheral region, along the first sub-peripheral region, to the fan-out region; another portion of the first routing segments extends from the third sub-peripheral region, along the second sub-peripheral region, to the fan-out region; A plurality of second wiring segments extend from the display area to the third sub-peripheral area; One end of the first routing segment is electrically connected to one end of the second routing segment extending to the third sub-peripheral area, and the other end of the first routing segment is electrically connected to the corresponding first fan-out lead.

14. The display panel according to claim 13, wherein: The plurality of first fan-out leads, the plurality of control signal lines and the plurality of data fan-out leads are made of the same material and are arranged on the same layer; The plurality of first fan-out leads are disposed on two opposite sides of the plurality of data fan-out leads along the first direction.

15. The display panel according to claim 14, further comprising: a power voltage bus, disposed in the fan-out region and extending along the first direction; Wherein, the first fan-out lead and the power supply voltage bus are arranged at different layers; An orthographic projection of the first fan-out lead on the substrate of the display panel partially overlaps with an orthographic projection of the power supply voltage bus on the substrate.

16. The display panel according to claim 15, comprising: a first gate conductive layer, wherein the power supply voltage bus is provided on the first gate conductive layer; The source-drain conductive layer is arranged on a side of the first gate conductive layer away from the substrate of the display panel, and the multiple control signal lines, the multiple data lines, the multiple data fan-out leads and the multiple first fan-out leads are arranged on the source-drain conductive layer.

17. The display panel according to claim 13, further comprising: a power voltage bus, disposed in the fan-out region and extending along the first direction; Among them, the first routing segment of the control signal line and the multiple first fan-out leads are made of the same material as the power voltage bus and are arranged on the same layer, and the first fan-out lead detours from one of the two opposite sides of the power voltage bus along the first direction and extends to the side of the power voltage bus away from the display area.

18. The display panel according to claim 17, comprising: a first gate conductive layer, wherein the first routing segment, the plurality of first fan-out leads and the power supply voltage bus are arranged in the first gate conductive layer; The source-drain conductive layer is arranged on a side of the first gate conductive layer away from the substrate of the display panel. The second routing segment of the control signal line, the multiple data lines and the multiple data fan-out leads are arranged on the source-drain conductive layer.

19. The display panel according to any one of claims 1 to 18, wherein: The binding area includes a first sub-binding area and two second sub-binding areas located on opposite sides of the first sub-binding area along a first direction; The plurality of data fan-out leads are gathered into the first sub-binding area; The plurality of first fan-out leads are divided into two groups, and the two groups of first fan-out leads are respectively gathered into two second sub-binding areas.

20. The display panel according to claim 19, further comprising: A plurality of pins are configured to bind a flexible printed circuit board; the plurality of pins include a plurality of first pins located in the first sub-binding area and a plurality of second pins located in the second sub-binding area; The data fan-out lead is electrically connected to at least one first pin; and the first fan-out lead is electrically connected to at least one second pin.

21. A display device comprising the display panel according to any one of claims 1 to 20.

Images