Memory device with multiple input / output interfaces

Abstract

This application relates to a memory device having multiple input / output interfaces. A memory device includes: a first plane group including a first plane; a second plane group including a second plane; a first input / output (I / O) interface configured to access the first plane group; and a second I / O interface configured to access the second plane group. The memory device further includes a controller operatively coupled to the first I / O interface via a first channel and operatively coupled to the second I / O interface via a second channel. The controller can transmit a first command via the first channel to the first I / O interface to perform a first memory access operation associated with the first plane. The controller can transmit a second command via the second channel to the second I / O interface to perform a second memory access operation associated with the second plane.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically to memory devices having multiple input / output interfaces. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, the host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] One embodiment of this disclosure provides a memory device comprising: a first plane group including a first plane; a second plane group including a second plane; a first input / output (I / O) interface configured to access the first plane group; a second I / O interface configured to access the second plane group; and a controller operably coupled to the first I / O interface via a first channel and operably coupled to the second I / O interface via a second channel, the controller performing operations including: transmitting a first command via the first channel to the first I / O interface to perform a first memory access operation associated with the first plane; and transmitting a second command via the second channel to the second I / O interface to perform a second memory access operation associated with the second plane.

[0004] Another embodiment of this disclosure provides a memory subsystem, the memory subsystem comprising: a first memory device including a first plane group, a second plane group, a first I / O interface, and a second I / O interface; and control logic operably coupled to the first I / O interface via a first channel and operably coupled to the second I / O interface via a second channel to perform operations including: transmitting a first command to the first I / O interface via the first channel to perform a first memory access operation associated with the first plane group; and transmitting a second command to the second I / O interface via the second channel to perform a second memory access operation associated with the second plane group.

[0005] Another embodiment of this disclosure provides a memory device comprising: a first plane group including a first set of planes; a second plane group including a second set of planes; a first I / O interface configured to access the first plane group; and a second I / O interface configured to access the second plane group. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 Examples of computing systems including a memory subsystem are shown according to some embodiments of the present disclosure.

[0008] Figure 2 This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to some embodiments of the present disclosure.

[0009] Figure 3 This is a schematic illustration of an example memory device according to embodiments of the present disclosure, comprising one or more memory dies having multiple input / output (I / O) interfaces configured to access multiple plane groups of the memory device.

[0010] Figure 4 This is a schematic illustration of an example memory device comprising multiple I / O interfaces operating in a multi-channel mode according to embodiments of the present disclosure.

[0011] Figure 5 This is a schematic illustration of an example memory device including multiplexer circuitry and multiple I / O interfaces operating in a multi-channel mode, according to embodiments of the present disclosure.

[0012] Figure 6 This is a schematic illustration of an example memory subsystem comprising multiple memory devices (e.g., multiple memory dies) and multiple I / O interfaces configurable to operate in a single-channel mode, according to embodiments of the present disclosure.

[0013] Figure 7 This is a flowchart of an example method for managing a memory device having multiple I / O interfaces according to one or more embodiments of the present disclosure, wherein the multiple I / O interfaces are configured to access multiple plane groups of the memory device to perform memory access operations.

[0014] Figure 8 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0015] This disclosure relates to a memory subsystem comprising a memory device having multiple input / output interfaces. The memory subsystem may be a memory device, a memory module, or a hybrid of a memory device and a memory module. The following is combined with… Figure 1Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0016] The memory subsystem may include high-density non-volatile memory devices, where data is expected to be retained when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described below. A non-volatile memory device is a package of one or more memory dies. Each memory die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states related to the number of bits being stored. Logic states may be represented by binary values ​​(e.g., “0” and “1”) or combinations of these values.

[0017] The host system can initiate memory access operations (e.g., programming, reading, erasing operations) associated with the memory array of one or more memory dies of the memory device. The memory device includes a serial input / output (I / O) interface comprising a series of I / O pads operatively coupled to a local media controller via one or more communication channels (e.g., one or more Open NAND Flash Interface Working Group (ONFI) channels). These pads are used to provide a serial high-frequency input data stream for transmitting data to the memory array via an input data bus.

[0018] Each channel (e.g., an 8-bit channel, a 16-bit channel) transmits commands and data associated with basic memory access operations (e.g., a target memory plane containing an address to identify the memory device) to the I / O interface associated with the target memory device. In some systems, each memory device communicates with the controller via a single I / O interface (i.e., each memory device has its own I / O interface for communicating with the controller) and a single channel (e.g., a single channel extending between the controller and the corresponding I / O interface of each memory device).

[0019] The I / O interface of a memory device comprises a set of I / O pins configured to handle communication between a local media controller and a group of memory planes of one or more memory dies in a memory subsystem. In some arrangements, each memory die communicates with the local media controller via I / O pins of a corresponding I / O interface (e.g., each memory die has its own I / O interface). For example, for a memory subsystem comprising a single memory device (e.g., a single memory die), all planes of the memory die (e.g., a group of eight planes) are accessed by a single I / O interface via a single communication channel. The individual pins of the I / O interface are wired to multiple planes of the memory die to enable the transmission of commands and data related to the execution of memory access operations (e.g., read operations, write operations, erase operations, etc.) between the respective plane of the memory die and the local media controller. Due to the physical arrangement of the single set of I / O pins, the wire connections between the pins and the stacked multiple planes of the memory die are staggered due to the limited availability of physical space.

[0020] The memory subsystem can be configured as a low-density system (e.g., with a single memory die) or a high-density system (e.g., with multiple memory dies), designed to handle a variety of different workloads with varying bandwidth requirements. For example, a typical low-density memory subsystem may comprise a single memory die communicatively coupled to a local media controller via a single channel and a single I / O interface (e.g., a single set of I / O pins). In this type of single I / O interface system, to increase bandwidth, the transmit rate is increased (e.g., using a 2× transmit rate). However, the use of higher transmit rates requires the use of high-speed I / O circuitry in the I / O interface, which can increase the cost of the memory device.

[0021] In other examples, wider channels are used to increase the bandwidth of communication between the local media controller and the memory die. For instance, a 16-bit channel or two 8-bit channels joined together can be used to increase bandwidth. However, this requires increasing the channel size or additionally joining multiple channels.

[0022] In addition, a typical memory subsystem includes other command pins configured at the memory die level (e.g., Chip Enable (CE) pin, Write Protect (WP) pin, Ready-Busy (RB) pin, etc.). Accordingly, these memory die-level command pins are provided along with each I / O interface to enable per-channel communication between the controller and each corresponding memory die. For some typical high-density systems, this can result in a large number of pins being placed, thus wasting physical space within the memory subsystem.

[0023] This disclosure addresses the above and other drawbacks by implementing a memory device that includes multiple I / O interfaces. In one embodiment, multiple I / O interfaces, including, for example, a first I / O interface and a second I / O interface, are provided to enable communication between a memory plane (e.g., memory plane 1 to memory plane N) and a local media controller. The memory subsystem includes corresponding channels associated with the multiple I / O interfaces, such as a first channel between the local media controller and the first I / O interface, and a second channel between the local media controller and the second I / O interface. In one embodiment, the memory device (e.g., a memory die) may include multiple plane groups, each comprising a group or set of planes that contain the memory device. For example, an 8-plane memory device may include a first plane group comprising planes 0, 1, 2, and 3, and a second plane group comprising planes 4, 5, 6, and 7.

[0024] In one embodiment, a memory device comprising multiple I / O interfaces (also referred to as a multi-interface memory device) can operate in a multi-channel mode (e.g., also referred to as a "dual-channel mode" or "first mode"), wherein each of the channels (e.g., the first channel and the second channel) is activated or enabled. In one embodiment, during operation in dual-channel mode, a first channel (channel 1) is configured to access a first plane group of the memory device (e.g., planes 0, 1, 2, and 3 of an 8-plane memory device with two plane groups), and a second channel (channel 2) is configured to access a second plane group of the memory device (e.g., planes 4, 5, 6, and 7 of an 8-plane memory device). Advantageously, multiple channels (e.g., channel 1 and channel 2) can extend to the same memory device because the memory device contains multiple I / O interfaces, thereby increasing bandwidth without necessarily increasing the transmit rate. In this respect, the two plane groups can operate independently of each other, such that memory access operations (e.g., read, program, erase operations) can be processed simultaneously relative to the planes of the independent plane groups. In one embodiment, the multi-channel mode can be used in low-density systems that benefit from a single memory device with multiple channels and multiple I / O interfaces.

[0025] In one embodiment, the memory device can operate in a single-channel mode (also referred to as "second mode"), wherein one channel is activated and the one or more other channels are deactivated or deactivated. In this embodiment, during operation in a single-channel mode, the activated channel is configured to handle communication between the controller and all plane groups of the memory device (e.g., a first plane group and a second plane group of a multi-plane memory device). In this embodiment, cross-plane group access is implemented, enabling the activated I / O interface to access multiple plane groups.

[0026] In one embodiment, multiple plane groups can be accessed via a single activated I / O interface while one or more I / O interfaces are disabled. For example, single-channel mode can be used in high-density systems containing memory subsystems with multiple memory devices (e.g., stacked arrangements of multiple memory dies (e.g., 8 memory dies per memory device, 16 memory dies per memory device)) to optimize system bandwidth without requiring I / O extenders or additional intermediate buffers.

[0027] Advantageously, compared to a typical single I / O interface configuration, the multiple I / O interfaces of the memory device according to this disclosure achieve increased bandwidth and configurable operation for both low-density and high-density memory devices. In this respect, the multi-interface memory device of this disclosure can be used to serve high-bandwidth systems (e.g., 256GB to 2TB) with a single memory die. Furthermore, the multi-interface memory device can be expanded to include any number of channels and I / O interfaces (e.g., memory devices with four channels, eight channels, etc.). Additional benefits are achieved by having a memory device with multiple I / O interfaces arranged in a side-by-side configuration so that a plane group can be wire-connected to a first I / O interface and a second plane group can be wire-connected to an adjacent second I / O interface, thereby avoiding the need for interleaved wire connections between a single interface and all plane groups. Furthermore, in one embodiment, a reduction in command pins can be achieved by establishing one or more common command pins (e.g., CE pin, WP pin, RB pin, etc.) shared by the multiple I / O interfaces and associated memory dies.

[0028] Figure 1 Example computing system 100 including memory subsystem 110 according to some embodiments of the present disclosure is illustrated. Memory subsystem 110 may include media, such as one or more non-volatile memory devices (e.g., memory device 140), one or more volatile memory devices (e.g., one or more memory devices 130), or a combination thereof. Memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules.

[0029] Memory device 130 may be a non-volatile memory device. An example of a non-volatile memory device is a NAND memory device. A non-volatile memory device is a package of one or more dies or logic units (LUNs). Therefore, each memory device 130 may be a die (or LUN) or may be a multi-die package containing multiple dies (or LUNs) on a chip, such as an integrated circuit package of dies. Each memory die may contain one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states related to the number of bits being stored. Logic states may be represented by binary values ​​(e.g., “0” and “1”) or combinations of these values.

[0030] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0031] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0032] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0033] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110 to, for example, write data to memory subsystem 110 and read data from memory subsystem 110.

[0034] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., the one or more memory devices 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0035] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0036] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. Crosspoint arrays of non-volatile memory can perform bit storage based on changes in volume resistance in conjunction with stackable cross-grid data access arrays. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0037] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0038] Although non-volatile memory components such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0039] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0040] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0041] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is shown to include a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0042] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to implement desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0043] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0044] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes a raw memory device having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0045] In one embodiment, memory subsystem 110 includes memory interface component 113. Memory interface component 113 is responsible for handling interactions between memory subsystem controller 115 and memory devices (e.g., memory device 130) of memory subsystem 110. For example, memory interface component 113 may send memory access commands corresponding to requests received from host system 120 to memory device 130, such as programming commands, read commands, or other commands. Furthermore, memory interface component 113 may receive data from memory device 130, such as data retrieved in response to confirmation of a read command or successful execution of a programming command. For example, memory subsystem controller 115 may include processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein.

[0046] In one embodiment, each memory device 130 (e.g., a memory die) includes a plurality of channels and I / O interfaces 137 configured to transmit communication between a local media controller 135 and a memory array. In one embodiment, the plurality of I / O interfaces 137 include a first I / O interface configured to access plane group 1 of the memory device 130 and a second I / O interface configured to access plane group 2 of the memory device 130. Figure 1 As shown, multiple channels provide communication paths extending between the memory device 130 and the controller.

[0047] In one embodiment, the local media controller 135 includes an I / O interface mode manager 136 configured to manage modes associated with multiple I / O interfaces 137. In one embodiment, the I / O interface mode manager 136 can configure the memory device 130 to operate in a multi-channel mode (i.e., a dual-channel mode or a first mode) or a single-channel mode (i.e., a second mode). In the multi-channel mode, multiple channels and corresponding I / O interfaces are activated. In an example containing two channels and two I / O interfaces, the first I / O interface is configured to access plane group 1 (e.g., planes 0, 1, 2, and 3 of an 8-plane memory die), and the second I / O interface is configured to access plane group 2 (e.g., planes 4, 5, 6, and 7 of an 8-plane memory die).

[0048] In one embodiment, the I / O interface mode manager 136 can configure the memory device 130 to operate in a single-channel (or second mode), wherein a first I / O interface of a plurality of I / O interfaces 137 is activated, and one or more other I / O interfaces of the plurality of I / O interfaces 137 are deactivated. In this embodiment, the activated I / O interfaces and associated channels are used to transmit communication to a plurality of plane groups of the memory device 130. For example, in this embodiment, the activated first I / O interfaces of the plurality of I / O interfaces 137 access plane groups 1 to plane groups N (e.g., where for an instance memory device with two plane groups, N=2, and each plane group contains four planes of an 8-plane memory die). The following is relative to Figure 3-7 A more detailed description is provided of aspects of the I / O interface mode manager 136, multiple I / O interfaces 137, multiple channels, and multiple configurable modes (e.g., dual-channel mode and single-channel mode).

[0049] Figure 2 It is a first device in the form of one or more memory devices 130 according to an embodiment and a memory subsystem (e.g., Figure 1 A simplified block diagram of a second device communicating with a memory subsystem controller 115 in the form of a memory subsystem 110. Examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The memory subsystem controller 115 (e.g., a controller external to memory device 130) can be a memory controller or other external host device. According to embodiments, the memory subsystem 110 may have multiple memory devices 130 (e.g., multiple memory dies), wherein each memory device 130 includes memory plane groups 1-N.

[0050] Each memory device 130 includes an array 204 of memory cells logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (e.g., a word line), while memory cells in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with memory cells in more than one logical row, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 204 ( Figure 2 (Not shown in the text) can be programmed as one of at least two target data states.

[0051] Row decoding circuitry 208 and column decoding circuitry 210 are provided to decode address signals. Address signals are received and decoded to access memory cell array 204. Each memory device 130 also includes input / output (I / O) control circuitry 212 to manage inputs of commands, addresses, and data to each memory device 130, as well as outputs of data and status information from each memory device 130. According to an embodiment, I / O control interface 212 includes multiple I / O interfaces to manage communication between local media controller 135 and the corresponding memory die containing memory cell array 204. Address register 214 communicates with I / O control circuitry 212, row decoding circuitry 208, and column decoding circuitry 210 to latch address signals before decoding. Command register 224 communicates with multiple I / O interfaces 212 and local media controller 135 to latch incoming commands.

[0052] A controller (e.g., a local media controller 135 within each memory device 130) responds to the command to control access to the memory cell array 204 and generates status information for the external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on the memory cell array 204. The local media controller 135 communicates with the row decoding circuitry 208 and column decoding circuitry 210 to control them in response to an address. In one embodiment, the local media controller 135 includes instructions that can be combined with the operation and function execution of the I / O interface mode manager 136 and I / O interface 212 of the memory device 130, as described herein.

[0053] According to embodiments of this disclosure, a local media controller 135 communicates with a plurality of I / O interfaces 212 via corresponding channels (e.g., each I / O interface is associated with a channel that provides a communication path to the local media controller 135). In one embodiment, the local media controller 135 includes an I / O interface mode manager 136 to manage the operating mode of each memory device 130. In one embodiment, the I / O interface mode manager 136 can configure (e.g., by using commands) the memory device 130 to operate in a multi-channel mode (e.g., a dual-channel mode of memory devices having two I / O interfaces each having a corresponding channel) or a single-channel mode. In one example, in dual-channel mode, a first I / O interface and a second I / O interface of the I / O interface 212 are activated. In one embodiment, the first I / O interface is activated to access a first plane group of memory dies, and the second I / O interface is activated to access a second plane group of memory dies.

[0054] In one embodiment, in single-channel mode, one of the I / O interfaces in I / O interface 212 (e.g., the first I / O interface) is activated, and the remaining one or more I / O interfaces (e.g., the second I / O interface in a dual-channel configuration) are deactivated. In one embodiment, in single-channel mode, each memory die of memory device 130 communicates with local media controller 135 via a single channel and a single activated I / O interface. For example, see the following description. Figure 6 In more detail, for a memory subsystem comprising two memory dies (e.g., a first memory die and a second memory die), in single-channel mode, all plane groups (e.g., plane group 1 and plane group 2) of the first memory die are accessed via I / O interface 1 (i.e., the activated or enabled I / O interface) and a first channel. In this example, all plane groups (e.g., plane group 1 and plane group 2) of the second memory die are accessed via I / O interface 1 (i.e., the activated or enabled I / O interface) and a second channel.

[0055] The local media controller 135 also communicates with cache register 218. Cache register 218 latches incoming or outgoing data, such as data guided by the local media controller 135, to temporarily store data while the memory cell array 204 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 218 to data register 220 for transfer to memory cell array 204; then, new data can be latched from I / O control circuitry 212 into cache register 218. During read operations, data can be transferred from cache register 218 to I / O control circuitry 212 for output to memory subsystem controller 115; then, new data can be transferred from data register 220 to cache register 218. Cache register 218 and / or data register 220 may form a page buffer of memory device 130 (e.g., may form a portion thereof). The page buffer may further include sensing devices ( Figure 2 (Not shown in the diagram) The status register 222 can sense the data status of the memory cells, for example, by sensing the status of the data lines connected to the memory cells of the memory cell array 204. The status register 222 can communicate with the I / O control circuitry system 212 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0056] Each memory device 130 receives control signals from the local media controller 135 at the memory subsystem controller 115 via control link 232. For example, the control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protection signal WP#. Depending on the nature of each memory device 130, additional or alternative control signals (not shown) may be received further via control link 232. In one embodiment, each memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the memory subsystem controller 115 via a multiplexed input / output (I / O) bus 234, and outputs data to the memory subsystem controller 115 via the I / O bus 234.

[0057] For example, commands can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] of I / O bus 234, and then written to command register 224. Addresses can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] of I / O bus 234, and then written to address register 214. Data can be received at one or more locations in I / O control interface 212 via 8-bit device input / output (I / O) pins [7:0] or 16-bit device input / output (I / O) pins [15:0], and then written to cache register 218. The data can then be written to data register 220 for programming memory cell array 204.

[0058] In this embodiment, the cache register 218 may be omitted, and data may be written directly to the data register 220. Data may also be output on the input / output (I / O) pins [7:0] for an 8-bit device or the input / output (I / O) pins [15:0] for a 16-bit device. Although references may be made to the I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to the memory device 130 via an external device (e.g., the memory subsystem controller 115).

[0059] Those skilled in the art should understand that additional circuitry and signals can be provided and have been simplified. Figure 2 Each memory device 130. It should be recognized that, reference... Figure 2 The functionality of the various block components described need not be divided into different components or component parts of the integrated circuit device. For example, a single component or component part of the integrated circuit device may be adapted to perform... Figure 2The functionality of one or more block components. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 2 The functionality of a single block component. Furthermore, although specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0060] Figure 3 This is a schematic illustration of an instance memory subsystem having a memory device 330 that is accessible via multiple plane groups (e.g., plane group 1 and plane group 2) through multiple I / O interfaces (e.g., I / O interface 1 and I / O interface 2). In one embodiment, the controller 335 may configure the memory device to operate in a first mode, wherein both I / O interface 1 and I / O interface 2 are activated or enabled. In this embodiment, commands and data are transmitted to I / O interface 1 via channel 1, and commands and data are transmitted to I / O interface 2 via channel 1.

[0061] In one embodiment, I / O interface 1, operating in a first mode (i.e., dual-channel mode), is configured to access plane group 1 (e.g., planes 0, 1, 2, and 3 of an 8-plane memory die), and I / O interface 2 is configured to access plane group 2 (e.g., planes 4, 5, 6, and 7 of an 8-plane memory die). In one embodiment, a default association for each I / O interface can be maintained (e.g., a default configuration can instruct I / O interface 1 to access plane group 1 and I / O interface 2 to access plane group 2), as described below. Figure 4 More detailed description. Advantageously, multiple I / O interfaces (e.g., I / O interface 1 and I / O interface 2) enable multiple channels (e.g., channel 1 and channel 2) to be extended to a single memory device 330 (e.g., a single memory die). This increases bandwidth without increasing the channel size (e.g., channel 1 and channel 2 could be 8-bit ONFI channels) and without increasing the transmission speed of communications transmitted via the channels.

[0062] In one embodiment, the corresponding I / O interfaces (e.g., I / O interface 1 and I / O interface 2) can access all plane groups. For example, both I / O interfaces 1 and 2 can be configured to access both plane group 1 and plane group 2. In this regard, in one embodiment, the two I / O interfaces can be configured to simultaneously access multiple planes in the same plane group (e.g., I / O interface 1 can access plane 0 of plane group 1, and I / O interface 2 can simultaneously access plane 3 of plane group 1). Advantageously, enabling two I / O interfaces to simultaneously access the same plane group improves the random access performance of the memory device.

[0063] In one embodiment, controller 335 may include logic for determining which channel or I / O interface to use when sending communication to a memory die. For example, controller 335 may have a first command to read plane 2 of plane group 1. In this example, controller 335 determines that I / O interface 1 is configured to access the default interface of plane group 1 when operating in dual-channel mode. In this example, controller 335 may determine that I / O interface 1 is busy (e.g., a write command is being executed on plane 0 of plane group 1 using I / O interface 1). In response to this determination, controller 335 may send a command via channel 2 to I / O interface 2 to execute a read command relative to plane 2.

[0064] In one embodiment, the memory device 330 may include multiplexer circuitry (i.e., MUX) configured to enable multiple I / O interfaces to selectively access planes in multiple plane groups, as described below. Figure 5 More detailed description. In this embodiment, the multiplexer can be used to enable access to a target plane in any plane group via any of the I / O interfaces and channels. In one embodiment, the multiplexer allows communication from each I / O interface to one or more plane groups.

[0065] In one embodiment, the memory device 330 may be configured in a first mode (e.g., a multi-channel mode) or a second mode (e.g., a single-channel mode). In one embodiment, the controller 335 may dynamically change from one mode to another in response to detecting a condition or factor. For example, in response to detecting that the memory device is operating in a low-power mode, the controller 335 may switch from a multi-channel mode to a single-channel mode.

[0066] In one embodiment, another advantage can be achieved by including common pins that can be shared by multiple I / O interfaces (e.g., die-level command pins, such as CE pin, WP pin, RB pin, etc.). In this embodiment, the total number of pins can be reduced by using common pins for multiple I / O interfaces, thereby saving space within the memory device.

[0067] In one embodiment, such as Figure 3 The diagram schematically illustrates that multiple I / O interfaces can be physically arranged side-by-side. In this side-by-side arrangement, each pin of the I / O group can be wire-contacted to a corresponding plane of the one or more memory dies without having the wire connections interleaved. Advantageously, avoiding wire connection interleaving reduces the complexity of manufacturing memory devices and further saves physical space.

[0068] Figure 4An embodiment is illustrated in which a low-density memory subsystem comprising a single memory device 430 (e.g., a single memory die) is configured to operate in a dual-channel mode. In this example, the single 8-plane memory device comprises two plane groups: plane group 1 comprising planes 0, 1, 2, and 3; and plane group 2 comprising planes 4, 5, 6, and 7. As shown, in this example, I / O interface 1 and I / O interface 2 are activated. In one embodiment, the I / O interfaces can be activated (or deactivated) by means of a command from controller 435. In one embodiment, the I / O interfaces can be activated or deactivated by fine-tuning commands or path engagement.

[0069] In the example shown, I / O interface 1 is configured to access plane group 1, and I / O interface 2 is configured to access plane group 2. As shown, a single memory device can be accessed using multiple I / O interfaces (e.g., I / O interface 1 and I / O interface 2) via multiple channels (e.g., channel 1 and channel 2).

[0070] Figure 5 A memory die 538 is shown, comprising multiplexer circuitry 540 to enable each of the I / O interfaces to access planes in multiple plane groups. As shown, the multiplexer 540 of the memory die 530 (e.g., the memory die itself) enables I / O interface 1 to access planes of plane group 1 and planes of plane group 2 when active. Similarly, a multiplexer can be used to enable I / O interface 2 to access planes of plane group 1 and planes of plane group 2 when active.

[0071] Figure 6 An embodiment of a memory subsystem (e.g., a high-density memory system comprising two memory dies) configured to operate in a single-channel mode (i.e., the second mode) is illustrated. In single-channel mode, each memory die (e.g., memory die 1 and memory die 2) is communicatively connected to the controller via a single channel and an activated I / O interface. In the illustrated example, I / O interface 1 is activated, and I / O interface 2 is deactivated (e.g., by means of a controller command, a fine-tuning command, or a path engagement). As shown, I / O interface 1 of memory die 1 and I / O interface 1 of memory die 2 are activated, while I / O interface 2 of each memory die is deactivated. In one embodiment, communication for memory die 1 is transmitted via channel 1, and communication for memory die 2 is transmitted via channel 2. In this embodiment, the activated I / O interface 1 accesses plane group 1 and plane group 2 of memory die 1. Similarly, in this embodiment, the activated I / O interface 1 of memory die 2 accesses plane group 1 and plane group 2. In one embodiment, controller 635 may be configured to deactivate or activate any of the I / O interfaces using commands (e.g., controller commands or tuning commands) or path engagement.

[0072] Figure 7 This is a flowchart illustrating an example method of performing memory access operations on a memory device according to one or more embodiments of the present disclosure, the memory device having multiple I / O interfaces associated with multiple plane groups for accessing the memory device. Method 700 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 700 is performed by… Figure 1 The local media controller 135 and multiple I / O interfaces 137 execute the process. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0073] At operation 710, a command is issued. For example, processing logic (e.g., local media controller 135) may issue a first command via a first channel to a first I / O interface of the memory device to perform a first memory access operation associated with a first plane in a first plane group of the memory device. In one embodiment, the memory device has a first plane group comprising a collection of memory planes containing the first plane. In one embodiment, the first I / O interface is activated and configured (e.g., in a default configuration) to access the first plane group in association with performing a memory access operation associated with a memory cell in the first plane group. In one embodiment, the first memory access operation may be a read operation, write operation, or erase operation associated with one or more memory cells in a memory plane (e.g., the first plane) of the first plane group.

[0074] At operation 720, a memory plane is accessed. For example, the processing logic may use a first I / O interface to access a first plane in a first plane group to perform a first memory access operation. In one embodiment, the first I / O interface is configured to access a plane within the first plane group. For example, such as... Figure 4 As shown, the first plane group may include plane group 1 accessed (as indicated by the double arrow lines) using the I / O interface 1 of memory device 430. In this example, the first plane may include plane 0, plane 1, plane 2, or plane 3 of plane group 1.

[0075] At operation 730, a command is issued. For example, the processing logic may issue a second command via a second channel to a second I / O interface of the memory die to perform a second memory access operation associated with a second plane in a first plane group of the memory die. In one embodiment, the memory device has a second plane group comprising a set of memory planes containing the second plane (e.g., Figure 4 (Plane group 2, planes 4, 5, 6, or 7). In one embodiment, the second I / O interface is activated and configured (e.g., in the default configuration) to access the second plane group in association with performing memory access operations associated with memory cells of the second plane group. In one embodiment, the second memory access operation may be a read operation, write operation, or erase operation associated with one or more memory cells of a memory plane (e.g., the second plane) of the second plane group.

[0076] At operation 740, a memory plane is accessed. For example, the processing logic may use a second I / O interface to access a second plane in a second plane group to perform a second memory access operation. In one embodiment, the second I / O interface is configured to access a plane within the second plane group. For example, such as... Figure 4 As shown, the second plane group may include plane group 2 accessed using I / O interface 2 of memory die 438 (as indicated by the double arrow lines). In this example, the second plane may include plane 4, plane 5, plane 6, or plane 7 of plane group 2. In one embodiment, the first memory access operation and the second memory access operation can be performed simultaneously due to multiple I / O interfaces and associated plane group accesses.

[0077] In one embodiment, the memory device may include multiplexer circuitry. In this embodiment, after the execution of a second memory access operation is completed, a third command to execute a third memory access operation associated with a third plane of the first plane group may be issued to the second I / O interface. In one embodiment, although the default configuration of the second I / O interface is to access the second plane group, the multiplexer circuitry allows access to the third plane, which is part of the first plane group, via the second I / O interface. In this example, as... Figure 5 As shown, because the first I / O interface is busy performing a first memory access operation, the third command can be issued by the processing logic to the second I / O interface, and the multiplexer circuitry can allow the second I / O interface to access the first plane group to perform a third memory access operation. In one embodiment, access to the first plane group via the first I / O interface and access to the second plane group via the second I / O interface can be performed simultaneously.

[0078] In one embodiment, in response to a certain condition being met, the processing logic can switch from the dual-channel mode described above to a single-channel mode. In this embodiment, the processing logic switches to single-channel mode by deactivating one of the first I / O interface or the second I / O interface. For example, the processing logic can deactivate the second I / O interface, causing commands to be transmitted to the first I / O interface via the first channel. In this embodiment, the first I / O interface can access a first plane group and a second plane group of the memory device. In one embodiment, the condition may include, for example, the memory device operating in a low-power mode.

[0079] Figure 8 An example machine of computer system 800 is shown, within which an instruction set executable for causing the machine to perform any one or more of the methods discussed herein is provided. In some embodiments, computer system 800 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform operations of the controller (e.g., execute the operating system to execute instructions 826 to perform operations corresponding to those of the controller). Figure 1 The I / O interface mode manager 136 manages multiple I / O interfaces 136 associated with dual-channel and single-channel modes of operation. In alternative embodiments, the machine may connect (e.g., network) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment within the capacity of a server or client machine in a client-server network environment.

[0080] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any set of machines that individually or jointly execute a set (or sets of sets) of instructions to perform any or more of the methods discussed herein.

[0081] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 806 (e.g., flash memory, static random access memory (SRAM)), and a data storage system 818, which communicate with each other via a bus 830.

[0082] Processing device 802 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 802 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 802 is configured to execute instructions 826 for performing the operations and steps discussed herein. Computer system 800 may further include a network interface device 808 for communication via network 820.

[0083] The data storage system 818 may include a machine-readable storage medium 824 (also referred to as a computer-readable medium, such as a non-transitory computer-readable medium) on which one or more instruction sets 826 or software embodying any one or more methods or functions described herein are stored. The instructions 826 may also reside wholly or at least partially within main memory 804 and / or processing device 802 during execution by computer system 800, which also constitute machine-readable storage media. The machine-readable storage medium 824, the data storage system 818, and / or main memory 804 may correspond to... Figure 1 The memory subsystem 110.

[0084] In one embodiment, instruction 826 includes implementations corresponding to Figure 1 (The machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, but the term "machine-readable storage medium" should be understood to include a single medium or multiple media storing the one or more instruction sets. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding instruction sets executable by a machine and causing the machine to perform any one or more methods of this disclosure. The term "machine-readable storage medium" should be accordingly understood to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0085] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. An algorithm here and generally is considered a self-consistent sequence of operations that produce the desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for reasons of common use, it has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0086] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0087] The present invention also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for a particular purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0088] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the teachings and procedures herein, or it may prove convenient to construct more specialized devices to implement the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure described herein can be implemented using a variety of programming languages.

[0089] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable for programming a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine-readable storage medium, such as a read-only memory (“ROM”), random access memory (“RAM”), disk storage medium, optical storage medium, flash memory components, etc.

[0090] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory device comprising: A first plane group, which includes a first plane; A second plane group, which includes a second plane; First input / output I / O interface; Second I / O interface; A multiplexer circuit is configured such that: The first I / O interface can access both the first plane group and the second plane group; and The second I / O interface can access both the first plane group and the second plane group; as well as A controller, operably coupled to the first I / O interface via a first channel and operably coupled to the second I / O interface via a second channel, the controller performing the following operations: A first command is transmitted to the first I / O interface via the first channel to execute a first memory access operation associated with the first plane. as well as A second command is transmitted via the second channel to the second I / O interface to execute a second memory access operation associated with the second plane.

2. The memory device of claim 1, wherein the first I / O interface performs a first access to the first plane of the first plane group to perform the first memory access operation, and wherein the second I / O interface performs a second access to the second plane of the second plane group to perform the second memory access operation.

3. The memory device of claim 2, wherein the first access to the first plane group via the first I / O interface and the second access to the second plane group via the second I / O interface are performed simultaneously.

4. The memory device of claim 1, wherein the second I / O interface is deactivated by at least one of a third command, a fine-tuning command, or a path engagement from the controller.

5. The memory device of claim 4, wherein the controller performs an operation further comprising: transmitting a fourth command via the first channel to the first I / O interface to perform a third memory access operation associated with a third plane of the second plane group.

6. The memory device of claim 5, wherein the first I / O interface performs a third access to the third plane of the second plane group.

7. The memory device of claim 1, further comprising at least a third plane group and a fourth plane group.

8. The memory device of claim 7, wherein the first I / O interface is activated and the second I / O interface is deactivated, and wherein the controller sends a command to the first I / O interface via the second channel to access the third plane group and the fourth plane group.

9. A memory subsystem comprising: A first memory device includes a first plane group, a second plane group, a multiplexer circuit, a first I / O interface, and a second I / O interface; as well as Control logic, which is operatively coupled to the first I / O interface via a first channel and to the second I / O interface via a second channel, performs operations including: A first command is transmitted to the first I / O interface via the first channel to execute a first memory access operation associated with the first plane group; as well as A second command is transmitted via the second channel to the second I / O interface to perform a second memory access operation associated with the second plane group. The multiplexer circuit is configured such that: The first I / O interface can access both the first plane group and the second plane group; and The second I / O interface can access both the first plane group and the second plane group.

10. The memory subsystem of claim 9, wherein the operation includes: Activate the first I / O interface; as well as Activate the second I / O interface.

11. The memory subsystem of claim 10, wherein the operation includes: The second I / O interface is deactivated, wherein the first I / O interface accesses the first plane group and the second plane group to perform one or more memory access operations.

12. The memory subsystem of claim 9, further comprising a second memory device including a third plane group and a fourth plane group.

13. The memory subsystem of claim 12, wherein the control logic transmits one or more first commands associated with the first plane group and the second plane group of the first memory device to the first I / O interface via the first channel.

14. The memory subsystem of claim 13, wherein the control logic transmits one or more second commands associated with the third plane group and the fourth plane group of the second memory device to the first I / O interface via the second channel.

15. A memory device comprising: A first group of planes, which includes a first group of planes; The second plane group includes a second set of planes; First I / O interface; Second I / O interface; as well as A multiplexer circuit is configured such that: The first I / O interface can access both the first plane group and the second plane group; and The second I / O interface can access both the first plane group and the second plane group. The first I / O interface receives a first command from the controller via a first channel, which is associated with a first memory access operation to be performed on a first plane of the first plane group, and the second I / O interface receives a second command from the controller via a second channel, which is associated with a second memory access operation to be performed on a second plane of the second plane group.

16. The memory device of claim 15, wherein the memory device is configured to operate in a first mode, wherein the first I / O interface and the second I / O interface are activated.

17. The memory device of claim 16, wherein the memory device is configured to operate in a second mode, wherein one of the first I / O interface or the second I / O interface is deactivated.

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