FPGA-Based Multi-Chip DAC Pulse Output Synchronization and Phase Adjustment Method and System

Abstract

The present invention discloses a method and system for multi-chip DAC pulse output synchronization and phase adjustment based on FPGA. The method configures an FPGA to construct a trigger signal processing module, a clock configuration module, a DAC synchronization configuration module, a phase adjustment module, and multiple waveform storage modules. Among them, the trigger signal processing module makes the path delays of the trigger signal reaching the clock configuration module and each waveform storage module consistent. The clock configuration module and the DAC configuration module keep the outputs of multiple DACs synchronized. The phase adjustment module delays the waveform data corresponding to each DAC according to the delay value corresponding to each DAC issued by the host computer, and outputs the delayed waveform data to each DAC respectively. Therefore, the present invention can not only realize phase adjustment based on the internal resources of the FPGA, but also does not need to check the initial phase after power-on, and can adjust the phase difference between the RF outputs of multiple DACs according to the usage scenario to maintain the synchronization of multiple RF pulse signals.

Description

Technical Field

[0001] The present invention relates to the technical field of quantum measurement and control, and particularly to a method and system for multi-chip DAC pulse output synchronization and phase adjustment based on FPGA. Background Art

[0002] The working principle of a quantum computer is as follows: through a quantum measurement and control system, the qubits prepared on a quantum chip are manipulated to implement a certain quantum algorithm, and the measurement output of the qubits is read through the quantum measurement and control system to obtain the calculation result. Among them, the quantum measurement and control system mainly consists of multiple functional units such as a low-noise precision voltage unit, a pulse generation unit, a radio frequency pulse unit, a reflection measurement unit, and a high-precision microwave source to form a measurement and control channel. Each measurement and control channel is used for the manipulation and measurement of a corresponding qubit. In order to implement quantum computing of more qubits, it is necessary for the quantum measurement and control system to have enough measurement and control channels to support the manipulation and measurement of more qubits.

[0003] Among them, the principle of generating a radio frequency pulse signal by the radio frequency pulse unit is as Figure 1 shown. The waveform data is cached in the RAM, and then according to the trigger signal, the waveform data cached in the RAM is output to the digital-to-analog converter (DAC). The DAC generates a waveform signal in real time according to the waveform data, and finally the radio frequency front-end unit (RF) generates a corresponding radio frequency pulse signal according to the waveform signal output by the DAC; since the radio frequency pulse signal generated by the radio frequency pulse unit is used to implement the manipulation of the qubit, it directly affects the manipulation fidelity, and for the manipulation of multiple qubits, the multiple radio frequency pulse signals output by the radio frequency pulse unit must be synchronized, that is, the arrival time at the device must be the same.

[0004] The currently adopted solution is as follows: after each device is powered on, first check the initial phase output by the DAC of each channel, and then determine the phase adjustment value according to the initial phase. Part of this phase adjustment value is adjusted through the function of the DAC itself, and the other part is adjusted through an additional delay chip. However, since it is necessary to check the initial phase output by the DAC of each channel every time the device is powered on, it will increase the device debugging time, and the phase adjustment range is limited by the DAC chip and the delay chip, greatly restricting the usage scenarios. Summary of the Invention

[0005] In view of the above-mentioned deficiencies of the prior art, the purpose of the present invention is to provide a method for multi-chip DAC pulse output synchronization and phase adjustment based on FPGA, which realizes phase adjustment through the internal resources of the FPGA, and can flexibly change the phase difference between the radio frequency outputs of multiple chips according to the changes and requirements of the usage scenario without checking the initial phase after power-on, so as to achieve the synchronization of multiple radio frequency pulse signals.

[0006] To achieve the above-mentioned invention object, the present invention provides the following technical solutions:

[0007] A method for multi-chip DAC pulse output synchronization and phase adjustment based on FPGA, which includes:

[0008] Configure the FPGA to build a trigger signal processing module, a clock configuration module, a DAC configuration module, a phase adjustment module, and multiple waveform storage modules; wherein,

[0009] The trigger signal processing module is configured to process the input trigger signal so that the path delays of the trigger signal reaching the clock configuration module and each of the waveform storage modules are the same;

[0010] The clock configuration module is configured to synchronize the externally input clock signal with the trigger signal, and after the synchronization is completed, feedback an enable signal to the DAC configuration module;

[0011] The DAC configuration module is configured to configure the outputs of multiple DACs to be synchronized after receiving the enable signal; moreover, the clock of each DAC is provided by the externally input clock signal;

[0012] Each of the waveform storage modules is configured to, after receiving the waveform playback command issued by the host computer, if the collected trigger signal is 1, output the waveform data to the phase adjustment module, and if the collected trigger signal is 0, stop the output;

[0013] The phase adjustment module is configured to perform delay processing on the waveform data output from each of the waveform storage modules to the corresponding DAC according to the delay value corresponding to each DAC issued by the host computer, and output the delay-processed waveform data to each DAC respectively.

[0014] According to a specific embodiment, in the method for multi-chip DAC pulse output synchronization and phase adjustment based on FPGA of the present invention, the calculation method of the delay value corresponding to each DAC is:

[0015] Determine the phases (M1, M2,..., Mn) required for the radio frequency pulse signals output by the radio frequency pulse unit to reach n devices respectively;

[0016] Determine the phase adjustment step K of the phase adjustment module, where K = 1 / DAC sampling rate;

[0017] Calculate the delay value (D1, D2,..., Dn) corresponding to each DAC; wherein, Dn = (Mn - N) / K, N = min(M1, M2,..., Mn).

[0018] Based on the same inventive concept, the present invention further provides a multi-chip DAC pulse output synchronization and phase adjustment system based on FPGA, which includes: a host computer, a clock source, a trigger source, and an FPGA; wherein,

[0019] The host computer is used to issue waveform data, waveform playback commands, and the delay value corresponding to each DAC;

[0020] The clock source is used to provide clock signals for the FPGA and multiple DACs;

[0021] The trigger source is used to provide a trigger signal for the FPGA;

[0022] The FPGA includes: a trigger signal processing module, a clock configuration module, a DAC configuration module, a phase adjustment module, and multiple waveform storage modules; wherein,

[0023] The trigger signal processing module is configured to process the trigger signal provided by the trigger source, so that the path delays of the trigger signal reaching the clock configuration module and each waveform storage module are the same;

[0024] The clock configuration module is configured to synchronize the clock signal provided by the clock source with the trigger signal, and after the synchronization is completed, feedback an enable signal to the DAC configuration module;

[0025] The DAC configuration module is configured to configure the outputs of multiple DACs to be synchronized after receiving the enable signal; moreover, the clock of each DAC is supplied by the clock source;

[0026] Each waveform storage module is configured to, after receiving the waveform playback command issued by the host computer, if the collected trigger signal is 1, output the waveform data to the phase adjustment module, and if the collected trigger signal is 0, stop outputting;

[0027] The phase adjustment module is configured to respectively perform delay processing on the waveform data output from each waveform storage module to the corresponding DAC according to the delay value corresponding to each DAC issued by the host computer, and output the delay-processed waveform data to each DAC respectively.

[0028] According to a specific embodiment, in the multi-chip DAC pulse output synchronization and phase adjustment system based on FPGA of the present invention, the way for the host computer to calculate the delay value corresponding to each DAC is: determine the phases (M1, M2,..., Mn) required for the radio frequency pulse signals output by the radio frequency pulse unit to reach n devices respectively;

[0029] Determine the phase adjustment step K of the phase adjustment module, where K = 1 / DAC sampling rate;

[0030] Calculate the delay values (D1, D2,..., Dn) corresponding to each DAC; where Dn = (Mn - N) / K, and N = min(M1, M2,..., Mn).

[0031] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0032] In the multi-chip DAC pulse output synchronization and phase adjustment based on FPGA of the present invention, a trigger signal processing module, a clock configuration module, a DAC synchronization configuration module, a phase adjustment module, and multiple waveform storage modules are constructed by configuring the FPGA; among them, the trigger signal processing module makes the path delays of the trigger signal reaching the clock configuration module and each waveform storage module the same; the clock configuration module and the DAC configuration module keep the outputs of multiple DACs synchronized; the phase adjustment module delays the waveform data output from each waveform storage module to the corresponding DAC according to the delay value corresponding to each DAC sent by the host computer, and outputs the delayed waveform data to each DAC respectively. Therefore, the present invention can realize phase adjustment based on the internal resources of the FPGA, and without checking the initial phase after power-on, the phase difference between the RF outputs of multiple DACs can be changed according to the usage scenario, and the synchronization of multiple RF pulse signals can be maintained. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic diagram of the principle of generating a single RF pulse signal for the RF pulse unit;

[0034] Figure 2 It is a schematic diagram of the structure of the system of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. However, this should not be construed as limiting the scope of the above-mentioned subject matter of the present invention to the following embodiments. All technologies implemented based on the content of the present invention belong to the scope of the present invention.

[0036] As Figure 2 shown, the multi-chip DAC pulse output synchronization and phase adjustment system based on FPGA of the present invention includes: a host computer 100, a clock source, a trigger source, and an FPGA; moreover, the clock source, the trigger source, the FPGA, and n RF pulse units (composed of DAC and RF) are all arranged on a circuit board 200.

[0037] The host computer 100 is used to send waveform data, waveform playback commands, and the delay value corresponding to each DAC;

[0038] The clock source is used to provide clock signals for the FPGA and multiple DACs;

[0039] The trigger source is used to provide a trigger signal for the FPGA;

[0040] The FPGA includes: a trigger signal processing module, a clock configuration module, a DAC synchronization configuration module, a phase adjustment module, and multiple waveform storage modules; among them,

[0041] The trigger signal processing module is configured to process the trigger signal provided by the trigger source, so that the path delays of the trigger signal reaching the clock configuration module and each of the waveform storage modules are the same;

[0042] The clock configuration module is configured to synchronize the clock signal provided by the clock source with the trigger signal, and after the synchronization is completed, feedback an enable signal to the DAC configuration module;

[0043] The DAC configuration module is configured to, after receiving the enable signal, configure the outputs of multiple DACs to be synchronized; moreover, the clock of each DAC is supplied by the clock source;

[0044] Each of the waveform storage modules is configured to, after receiving the waveform playback command sent by the host computer, if the collected trigger signal is 1, output waveform data to the phase adjustment module, and if the collected trigger signal is 0, stop outputting;

[0045] The phase adjustment module is configured to, according to the delay value corresponding to each DAC sent by the host computer, respectively perform delay processing on the waveform data output from each of the waveform storage modules to the corresponding DAC, and output the delay-processed waveform data to each DAC respectively.

[0046] In the present invention, by configuring the FPGA to call the internal hardware resources, the functions of the above-mentioned various modules are realized, thereby realizing the synchronous playback of waveform data and the synchronous output of DAC, and without having to check the initial phase after power-on, the phase difference between the RF outputs of multiple DACs can be changed according to the usage scenario, and the synchronism of multiple RF pulse signals can be maintained.

[0047] In the multi-chip DAC pulse output synchronization and phase adjustment system based on FPGA of the present invention, the way for the host computer to calculate the delay value corresponding to each DAC is: determining the phases (M1, M2,..., Mn) required for the RF pulse signals output by the RF pulse unit to reach n devices respectively. Preferably, the phases required for the RF pulse signals output by the RF pulse unit to reach n ports on the quantum chip 300 respectively.

[0048] Determining the phase adjustment step K of the phase adjustment module, where K = 1 / DAC sampling rate;

[0049] Calculate the delay values (D1, D2, …… Dn) corresponding to each DAC; where Dn = (Mn - N) / K, and N = min(M1, M2, …… Mn).

[0050] Based on the same inventive concept, the present invention also provides a method for multi-chip DAC pulse output synchronization and phase adjustment based on FPGA. This method configures the FPGA to construct a trigger signal processing module, a clock configuration module, a DAC synchronization configuration module, a phase adjustment module, and multiple waveform storage modules; among them, the trigger signal processing module makes the path delays of the trigger signal reaching the clock configuration module and each waveform storage module the same; the clock configuration module and the DAC configuration module make the outputs of multiple DACs synchronous; the phase adjustment module delays the waveform data output from each waveform storage module to the corresponding DAC respectively according to the delay value corresponding to each DAC sent by the host computer, and outputs the delayed waveform data to each DAC respectively. Therefore, the present invention can achieve phase adjustment based on the internal resources of the FPGA, and without checking the initial phase after power-on, it can change the phase difference between the radio frequency outputs of multiple DACs according to the usage scenario, and maintain the synchronization of multiple radio frequency pulse signals.

[0051] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for synchronizing multi-chip DAC pulse output and phase adjustment based on FPGA, characterized by comprising: Configuring the FPGA to construct a trigger signal processing module, a clock configuration module, a DAC configuration module, a phase adjustment module, and multiple waveform storage modules; wherein, The trigger signal processing module is configured to process the input trigger signal so that the path delays of the trigger signal reaching the clock configuration module and each of the waveform storage modules are the same; The clock configuration module is configured to synchronize the externally input clock signal with the trigger signal and feedback an enable signal to the DAC configuration module after the synchronization is completed; The DAC configuration module is configured to, after receiving the enable signal, configure the outputs of multiple DACs to be synchronized; moreover, the clock of each DAC is provided by the externally input clock signal; Each of the waveform storage modules is configured to, after receiving the waveform playback command issued by the host computer, output waveform data to the phase adjustment module when the collected trigger signal is 1, and stop output when the collected trigger signal is 0; The phase adjustment module is configured to delay the waveform data output from each of the waveform storage modules to the corresponding DAC respectively according to the delay value corresponding to each DAC issued by the host computer, and output the delayed waveform data to each DAC respectively.

2. The method for synchronizing multi-chip DAC pulse output and phase adjustment based on FPGA according to claim 1, characterized in that the calculation method of the delay value corresponding to each DAC is: Determine the phases (M1, M2,..., Mn) required for the radio frequency pulse signals output by the radio frequency pulse unit to reach n devices respectively; Determine the phase adjustment step K of the phase adjustment module, where K = 1 / DAC sampling rate; Calculate the delay value (D1, D2,..., Dn) corresponding to each DAC; wherein, Dn = (Mn - N) / K, N = min(M1, M2,..., Mn).

3. A multi-chip DAC pulse output synchronization and phase adjustment system based on FPGA, characterized in that, Including: A host computer, a clock source, a trigger source, and an FPGA; wherein, The host computer is used to issue waveform data, waveform playback commands, and the delay value corresponding to each DAC; The clock source is used to provide clock signals for the FPGA and multiple DACs; The trigger source is used to provide a trigger signal for the FPGA; The FPGA includes: a trigger signal processing module, a clock configuration module, a DAC configuration module, a phase adjustment module, and multiple waveform storage modules; wherein, The trigger signal processing module is configured to process the trigger signal provided by the trigger source so that the path delays of the trigger signal reaching the clock configuration module and each of the waveform storage modules are the same; The clock configuration module is configured to synchronize the clock signal provided by the clock source with the trigger signal and feedback an enable signal to the DAC configuration module after the synchronization is completed; The DAC configuration module is configured to, after receiving the enable signal, configure the outputs of multiple DACs to be synchronized; moreover, the clock of each DAC is provided by the clock source; Each of the waveform storage modules is configured to output waveform data to the phase adjustment module when the collected trigger signal is 1 after receiving the waveform playback command issued by the host computer, and stop output when the collected trigger signal is 0; The phase adjustment module is configured to perform delay processing on the waveform data output from each of the waveform storage modules to the corresponding DAC according to the delay value corresponding to each DAC issued by the host computer, and output the delay-processed waveform data to each DAC respectively.

4. A multi-chip DAC pulse output synchronization and phase adjustment system based on FPGA according to claim 3, characterized in that, The host computer calculates the delay value corresponding to each DAC in the following way: determine the phases (M1, M2,..., Mn) required for the radio frequency pulse signals output by the radio frequency pulse unit to reach n devices respectively; Determine the phase adjustment step K of the phase adjustment module, where K = 1 / DAC sampling rate; Calculate the delay value (D1, D2,..., Dn) corresponding to each DAC; where Dn = (Mn - N) / K, and N = min(M1, M2,..., Mn).

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