A polar code decoding method, system and device

Abstract

The application discloses a polar code decoding method, system and device, comprising: calculating a target log-likelihood ratio of current decoding bits in response to a decoding request, constructing two sub-paths of the current decoding bits, determining a metric value of the sub-paths based on a preset metric value model, judging whether the number of write-in paths with the same path length as the sub-paths is less than or equal to a preset search width, if yes, writing all the sub-paths, judging whether the number of updated write-in paths satisfies a preset storage depth condition, if yes, performing double sorting on the updated write-in paths according to write-in metric values, and outputting the updated write-in path with the minimum write-in metric value as an optimal path, and outputting the optimal path as a decoding result when the path length of the optimal path satisfies a decoding code length. In the whole polar code decoding process, the ascending sorting and parallel comparison are combined in the path competition process, the efficiency of searching the optimal path is improved, and the decoding delay is reduced.

Description

Technical Field

[0001] This invention relates to the field of channel coding technology, and in particular to a polar code decoding method, system, and device. Background Technology

[0002] With the widespread application of wireless communication in various scenarios, the requirements for communication transmission speed and accuracy are also increasing. To address the shortcomings of the continuous deletion decoding algorithm itself, a continuous deletion stack decoding algorithm has been proposed.

[0003] The sequential deletion stack decoding algorithm, based on sequential stack decoding, eliminates the error propagation defect of the sequential deletion decoding algorithm to some extent by measuring the posterior information of multiple paths, thus achieving an objective improvement in error correction performance. However, in the path competition process during polar code decoding, the redundant candidate path sorting method of the current sequential deletion stack decoding algorithm adds additional computational complexity to a certain extent, resulting in high decoding latency. Summary of the Invention

[0004] This invention provides a polar code decoding method, system, and device, which solves the technical problem of high decoding latency in existing continuous stack deletion decoding algorithms during polar code decoding.

[0005] The first aspect of this invention provides a polar code decoding method, comprising:

[0006] In response to the decoding request, obtain the initial log-likelihood ratio and partial sum value corresponding to the decoding path of the current decoded bit, perform recursive log-likelihood ratio calculation, and generate the corresponding target log-likelihood ratio;

[0007] Two sub-paths of the decoding path are constructed, and the target log-likelihood ratio, the estimated bit value of each sub-path, and a preset metric model are used to determine the metric value of all the sub-paths.

[0008] Obtain the path length of the write path in the preset memory group, and determine whether the number of write paths with the same path length as the sub-path is less than or equal to the preset search width.

[0009] If so, all the sub-paths are written to the memory group according to the write address of the current decoded bit, and it is determined whether the number of updated write paths meets the preset storage depth condition.

[0010] If satisfied, the updated write paths are then sorted bit-tone according to their write metric values, and the updated write path with the smallest write metric value is output as the optimal path.

[0011] When the path length of the optimal path meets the decoding code length corresponding to the decoding request, the optimal path is output as the decoding result.

[0012] Optionally, the step of constructing two sub-paths of the decoding path and determining the metric values ​​of all the sub-paths using the target log-likelihood ratio, the estimated bit values ​​of each sub-path, and a preset metric model includes:

[0013] The decoding path is expanded to construct two corresponding sub-paths;

[0014] Determine whether the currently decoded bit is an information bit;

[0015] If it is the information bit, then the estimated bit value of each sub-path is determined, and the comparison result between the target log-likelihood ratio and the preset likelihood ratio constant is determined;

[0016] The estimated bit values ​​and the comparison results are input into a preset metric model, and the metric value corresponding to each sub-path is output.

[0017] If it is not the information bit, then the metric value of all the sub-paths is determined to be positive infinity according to the preset metric value model;

[0018] The preset metric model is specifically as follows:

[0019]

[0020]

[0021] Where i represents the i-th decoded bit, PM i and PM i-1 Let A represent the metric values ​​of the i-th decoded bit and the (i-1)-th decoded bit, respectively; let B represent the information bit index set; and let B represent the decision condition. This represents the complement of the judgment conditions. LLR represents the estimated bit value of the i-th decoded bit. i Let represent the target log-likelihood ratio of the i-th decoded bit, with the likelihood ratio constant set to 0.

[0022] Optionally, if so, the step of writing all the sub-paths to the memory group according to the write address of the current decoded bit, and determining whether the number of updated write paths meets the preset storage depth condition, includes:

[0023] If so, obtain the write address corresponding to the current decoded bit;

[0024] Write all the sub-paths to the memory group according to the write address, and count the number of updated write paths in the memory group;

[0025] Determine whether the number is less than the difference between the storage depth of the memory group and a preset storage constant.

[0026] Optionally, it also includes:

[0027] If the number of write paths with the same path length as the sub-path is not less than or equal to the preset search width, then delete write paths whose path length is less than the path length of the sub-path.

[0028] If the jump proceeds to the step of writing all the sub-paths to the memory group according to the write address of the current decoded bit, and determining whether the number of updated write paths meets the preset storage depth condition.

[0029] Optionally, the step of performing a bitonic sort on the updated write paths based on their write metric values ​​and outputting the updated write path with the smallest write metric value as the optimal path if the condition is met includes:

[0030] If the number of updated write paths in the memory group meets the preset storage depth condition, then obtain the write metric value of all the updated write paths.

[0031] According to the address value corresponding to each write metric value in the memory group, write metric values ​​equal to the set number threshold are selected in sequence for comparison to determine the smaller write metric value.

[0032] Determine whether the smaller write metric value is unique;

[0033] If not unique, then according to the address values ​​corresponding to all the smaller write metric values, the smaller write metric values ​​of the number threshold are selected in sequence to determine the smaller write metric value, and then the step of determining whether the smaller write metric value is unique is executed.

[0034] If unique, the smaller write metric value is determined to be the smallest write metric value, and the updated write path to which the address value corresponding to the smallest write metric value belongs is taken as the optimal path.

[0035] Optionally, it also includes:

[0036] If the number of write paths with the same path length as the sub-path is not less than or equal to the preset search width, then delete write paths whose path length is less than the path length of the sub-path.

[0037] If the jump proceeds to the step of writing all the sub-paths to the memory group according to the write address of the current decoded bit, and determining whether the number of updated write paths meets the preset storage depth condition.

[0038] Optionally, it also includes:

[0039] If the number of updated write paths in the memory group does not meet the preset storage depth condition, then obtain the write metric value of all the updated write paths.

[0040] According to the address value corresponding to each write metric value in the memory group, write metric values ​​equal to the set number threshold are selected in sequence for comparison to determine the smallest and largest write metric values.

[0041] The updated write path corresponding to the address value of the minimum write metric value is taken as the optimal path, and the process jumps to execute the step of outputting the optimal path as the target decoding result when the path length of the optimal path meets the decoding code length corresponding to the decoding request.

[0042] Optionally, it also includes:

[0043] When the path length of the optimal path does not meet the decoding code length corresponding to the decoding request, the optimal path value of the previous decoded bit and the path value of the optimal path are obtained.

[0044] The optimal path value and the path value are XORed to determine the partial sum value of the next decoded bit.

[0045] The optimal path is used as the decoding path for the next decoded bit, and the write address for the next round of decoded bits is determined.

[0046] Jump to execute the step of obtaining the initial log-likelihood ratio and partial sum value corresponding to the decoding path of the current decoded bit, perform log-likelihood ratio recursive operation, and generate the corresponding target log-likelihood ratio.

[0047] Optionally, the step of determining the write address of the next round of decoded bits includes:

[0048] Determine whether the current bit outputs the worst path;

[0049] If the worst path is not output, the address value of the best path and the free address value in the memory group are used as the write address of the next round of decoded bits.

[0050] If the worst path is output, then the address value of the best path and the address value of the worst path are used as the write address of the next round of decoded bits.

[0051] A second aspect of the present invention provides a polar code decoding system, comprising:

[0052] The log-likelihood ratio calculation module is used to respond to decoding requests, obtain the initial log-likelihood ratio and partial sum value corresponding to the decoding path of the current decoding bit, perform log-likelihood ratio recursive calculation, and generate the corresponding target log-likelihood ratio.

[0053] The metric calculation module is used to construct two sub-paths of the decoding path, and to determine the metric values ​​of all the sub-paths using the target log-likelihood ratio, the estimated bit values ​​of each sub-path, and a preset metric model.

[0054] The search width determination module is used to obtain the path length of the write path in the preset memory group and determine whether the number of write paths with the same path length as the sub-path is less than or equal to the preset search width.

[0055] The storage depth determination module is used to write all the sub-paths to the memory group according to the write address of the current decoded bit if the storage depth determination module is true, and to determine whether the number of updated write paths meets the preset storage depth condition.

[0056] The path sorting module is used to perform a bitonic sort on the updated write path according to the write metric value of the updated write path if the condition is met, and output the updated write path with the smallest write metric value as the optimal path.

[0057] The decoding result output module is used to output the optimal path as the decoding result when the path length of the optimal path meets the decoding code length corresponding to the decoding request.

[0058] A third aspect of the present invention provides an electronic device in which a computer program is stored in a memory, and when the computer program is executed by the processor, the processor performs the steps of the polar code decoding method as described in any one of the first aspects of the present invention.

[0059] As can be seen from the above technical solutions, the present invention has the following advantages:

[0060] This invention, based on a decoding request sent by a demand-side platform, calculates the target log-likelihood ratio of the current decoded bit, constructs two sub-paths for the current decoded bit's decoding path, and determines the metric value of each sub-path using the target log-likelihood ratio and the estimated bit value of each sub-path based on a preset metric model. It then checks whether the number of write paths in the memory bank with the same path length as the sub-path is less than or equal to a preset search width. If so, all sub-paths are written according to the write address of the current decoded bit, and the updated number of write paths is checked to see if it meets a preset storage depth condition. If it does, the updated write paths are bitonically sorted according to the write metric values ​​in the memory bank, and the updated write path with the smallest write metric value is output as the optimal path. When the path length of the optimal path meets the decoding code length corresponding to the decoding request, the optimal path is output as the decoding result. Throughout the polar code decoding process, a combination of ascending tone sorting and parallel comparison is used during path contention, improving the efficiency of searching for the optimal path and reducing decoding latency. Attached Figure Description

[0061] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0062] Figure 1 This is a flowchart of the steps of a polar code decoding method provided in Embodiment 1 of the present invention;

[0063] Figure 2 This is a flowchart of the steps of a polar code decoding method provided in Embodiment 2 of the present invention;

[0064] Figure 3 A flowchart illustrating an application example of a polar code decoding method provided in Embodiment 2 of the present invention;

[0065] Figure 4 This is a structural block diagram of a polar code decoding system provided in Embodiment 3 of the present invention;

[0066] Figure 5 A top-level architecture diagram of a polar code decoding device provided in an embodiment of the present invention;

[0067] Figure 6 A schematic diagram of the recursive operation structure of the operation module provided in an embodiment of the present invention;

[0068] Figure 7 This is a schematic diagram illustrating the interaction between the path selection module and the control module provided in an embodiment of the present invention.

[0069] Figure 8 A schematic diagram of the update architecture of some parts and update modules provided in the embodiments of the present invention;

[0070] Figure 9 This is a schematic diagram of the storage strategy of the metric value memory provided in an embodiment of the present invention. Detailed Implementation

[0071] This invention provides a polar code decoding method, system, and device to solve the technical problem of high decoding latency in existing continuous deletion stack decoding algorithms during polar code decoding.

[0072] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0073] Please see Figure 1 , Figure 1 This is a flowchart illustrating the steps of a polar code decoding method provided in Embodiment 1 of the present invention.

[0074] This invention provides a polar code decoding method, comprising:

[0075] Step 101: Respond to the decoding request, obtain the initial log-likelihood ratio and partial sum value corresponding to the decoding path of the current decoded bit, perform log-likelihood ratio recursive operation, and generate the corresponding target log-likelihood ratio.

[0076] See Figure 5 The polar code decoding device includes a control module, an LLR memory, and an SC decoder. The SC decoder includes a partial sum update module and an arithmetic module. The control module controls the entire polar code decoding process, including reading and writing addresses for LLR values, writing addresses for new paths, and reading and writing addresses for optimal paths, as well as determining when the decoding process terminates. The LLR memory stores channel layer LLR values ​​and intermediate layer LLR values. The partial sum update module retrieves the latest partial sum values. (See also...) Figure 6 The arithmetic module consists of arithmetic units that form a recursive arithmetic structure. It is used to calculate the target log-likelihood ratio through the f-operation function and g-operation function contained in each arithmetic unit. Here, fg_sel represents the selection signal for the f-operation function or g-operation function of the arithmetic unit to execute the f-operation function or the g-operation function. LLR0~LLR7 are LLR values ​​read from the LLR memory.

[0077] The f operation function is as follows:

[0078] f(L a ,L b ) = sign(L a ,L b )min{|L a |,|L b |};

[0079] The g operation function is as follows:

[0080]

[0081] Among them, L a and L b This represents the LLR value input to each arithmetic unit, u s This represents the partial sum of values.

[0082] A decoding request refers to a request message sent by a demand-side platform that can support applications of polar code decoding devices.

[0083] The initial log-likelihood ratio refers to the channel layer LLR index and intermediate layer LLR value associated with the decoding path in the LLR memory.

[0084] The target log-likelihood ratio refers to the decision level LLR value of the decoding path.

[0085] In this embodiment of the invention, in response to a decoding request sent by the demand-side platform, the control module reads and writes the initial log-likelihood ratio corresponding to the decoding path of the current decoded bit from the LLR memory, obtains the corresponding partial sum value from the partial sum update module, and inputs the initial log-likelihood ratio and the partial sum value into the operation module. Based on the path length of the decoding path of the current decoded bit, the operation unit is controlled to execute the corresponding operation function according to the recursive operation structure to calculate and output the target log-likelihood ratio, and sends the target log-likelihood ratio to the LLR memory for storage.

[0086] Step 102: Construct two sub-paths of the decoding path, and use the target log-likelihood ratio, the estimated bit value of each sub-path, and the preset metric model to determine the metric value of all sub-paths.

[0087] See Figure 5The polar code decoding device also includes a path expansion module, a path contention module, a metric memory, a path value memory, and a path length memory. The path expansion module is used for path expansion. The path contention module controls the metric memory, path value memory, and path length value memory to store the path information of the written path. The metric memory, path value memory, and path length value memory are three memories of the same storage depth forming a memory group, used to store the three types of path information—metric value, path value, and path length value—in blocks. Through unified control of the three memories, information corresponding to the same decoding path is associated through the same read / write address. During the decoding process, only data needs to be read and written from the corresponding memory; for example, during path contention, only data read / write operations need to be performed on the metric memory storing the metric value.

[0088] A sub-path refers to a path generated by extending the decoding path to bits "0" and "1".

[0089] Estimated bit value refers to the decoding result of a sub-path.

[0090] A metric model refers to a model used to calculate a metric, which is based on the maximum likelihood decoding criterion and applies cumulative penalties to different paths to determine their reliability. The metric is used to judge the reliability of a path; the smaller the metric, the higher the reliability.

[0091] In this embodiment of the invention, the decoding path of the current decoded bit is extended by the path extension module to generate two sub-paths. The estimated bit value of each sub-path is obtained by the path competition module. The target log-likelihood ratio and the estimated bit value are input into the metric model. The metric value of all sub-paths is output based on the metric model. The metric value memory is controlled to write and store the metric value.

[0092] Step 103: Obtain the path length of the write path in the preset memory group, and determine whether the number of write paths with the same path length as the sub-path is less than or equal to the preset search width.

[0093] The write path refers to the path where relevant information has already been stored in the memory group.

[0094] Search width is the maximum number of write paths of the same path length in the memory.

[0095] In this embodiment of the invention, the path length of the write path stored in the path length value memory is read and written to determine the path length of the extended sub-path, the number of write paths with the same path length as the sub-path is counted, and it is determined whether the number is less than or equal to the preset search width.

[0096] Step 104: If yes, write all sub-paths to the memory group according to the write address of the current decoded bit, and determine whether the number of updated write paths meets the preset storage depth condition.

[0097] The write address refers to the address value in the metric value memory, path value memory, and path length value memory that stores path information.

[0098] The storage depth condition refers to whether the number of path information in the write path of the memory group is less than the difference between the storage depth of the memory group and a preset storage constant, where the storage constant is set to 1. It can be understood that the storage depth of the memory group refers to the storage depth of any one of the metric value memory, path value memory, and path length value memory.

[0099] In this embodiment of the invention, if it is determined that the number is less than or equal to the preset search width, then the path information of all sub-paths is written into the memory group according to the write address of the current decoded bit, and the number of path information of the latest updated write path stored in the memory group is determined to be less than the difference between the memory depth and the preset storage constant.

[0100] Step 105: If satisfied, sort the updated write paths by their write metric values ​​and output the updated write path with the smallest write metric value as the optimal path.

[0101] See Figure 5 and Figure 7 The polar code decoding device also includes a path selection module, which includes a multi-stage comparator for bitone sorting of the write paths. The path contention module also controls the path selection module to sort and select the address value of the current optimal path, outputting the optimal path to continue decoding bit extension.

[0102] Writing a metric value refers to storing a metric value in the metric value memory.

[0103] Bitone sort is a sorting method that combines ascending sorting with parallel comparison.

[0104] The optimal path refers to the decoding path with the highest reliability.

[0105] In this embodiment of the invention, if the storage depth condition is met, the path selection module is controlled by the path contention module to read and write all the write metric values ​​and corresponding address values ​​of the updated write path from the metric value memory, perform bitone sorting, determine the address value of the updated write path with the smallest write metric value, and output it to the control module for address reading and writing. The current optimal path is determined by the address reading and writing of the optimal path address by the control module.

[0106] Step 106: When the path length of the optimal path meets the decoding code length corresponding to the decoding request, output the optimal path as the decoding result.

[0107] In this embodiment of the invention, after determining the optimal path, the control module extracts the path length of the optimal path from the path length memory and compares it with the decoding code length corresponding to the decoding request. If the decoding code length is satisfied, the optimal path is output as the final decoding result.

[0108] In this embodiment of the invention, in response to a decoding request sent by the demand-side platform, the target log-likelihood ratio of the current decoded bit is calculated, two sub-paths of the decoding path for the current decoded bit are constructed, and the metric value of the sub-path is determined based on a preset metric model using the target log-likelihood ratio and the estimated bit value of each sub-path. It is then determined whether the number of write paths in a preset memory group with the same path length as the sub-path is less than or equal to a preset search width. If so, all sub-paths are written according to the write address of the current decoded bit, and it is determined whether the number of updated write paths meets a preset storage depth condition. If so, the updated write paths are bitonically sorted according to the write metric values ​​in the memory group, and the updated write path with the smallest write metric value is output as the optimal path. When the path length of the optimal path meets the decoding code length corresponding to the decoding request, the optimal path is output as the decoding result. Throughout the polar code decoding process, a combination of ascending tone sorting and parallel comparison is used during path contention, improving the efficiency of searching for the optimal path and reducing decoding latency.

[0109] Please see Figure 2 , Figure 2 This is a flowchart illustrating the steps of a polar code decoding method provided in Embodiment 2 of the present invention.

[0110] This invention provides a polar code decoding method, comprising:

[0111] Step 201: Respond to the decoding request, obtain the initial log-likelihood ratio and partial sum value corresponding to the decoding path of the current decoded bit, perform log-likelihood ratio recursive operation, and generate the corresponding target log-likelihood ratio.

[0112] In this embodiment of the invention, the specific implementation process of step 201 is similar to that of step 101, and will not be repeated here.

[0113] Step 202: Construct two sub-paths of the decoding path, and use the target log-likelihood ratio, the estimated bit value of each sub-path, and the preset metric model to determine the metric value of all sub-paths.

[0114] Optionally, step 202 includes the following sub-steps:

[0115] The decoding path is expanded to construct two corresponding sub-paths;

[0116] Determine whether the currently decoded bit is an information bit;

[0117] If it is an information bit, then determine the estimated bit value of each sub-path, and determine the comparison result between the target log-likelihood ratio and the preset likelihood ratio constant;

[0118] Input the estimated bit values ​​and comparison results into the preset metric model, and output the metric value corresponding to each sub-path;

[0119] If it is not an information bit, then the metric value of all sub-paths is determined to be positive infinity according to the preset metric value model;

[0120] The preset metric model is as follows:

[0121]

[0122]

[0123] Where i represents the i-th decoded bit, PM i and PM i-1 Let A represent the metric values ​​of the i-th decoded bit and the (i-1)-th decoded bit, respectively; let B represent the information bit index set; and let B represent the decision condition. This represents the complement of the judgment conditions. LLR represents the estimated bit value of the i-th decoded bit. i Let represent the target log-likelihood ratio of the i-th decoded bit, with the likelihood ratio constant set to 0.

[0124] In this embodiment of the invention, after constructing two corresponding sub-paths by extending the decoding path, the current decoded bit is first determined to be an information bit according to the metric model. If it is an information bit, the estimated bit value of each sub-path is determined, and the calculated target log-likelihood ratio is compared with a preset likelihood ratio constant, where the likelihood ratio constant is set to 0. The estimated bit value and the comparison result are input into the metric model, and the metric value corresponding to each sub-path is calculated according to the decision condition. If the current decoded bit is not an information bit, according to the metric model, it belongs to the "otherwise" case, and the metric value of the sub-path is determined to be positive infinity.

[0125] Step 203: Obtain the path length of the write path in the preset memory group, and determine whether the number of write paths with the same path length as the sub-path is less than or equal to the preset search width.

[0126] In this embodiment of the invention, the specific implementation process of step 203 is similar to that of step 103, and will not be repeated here.

[0127] Step 204: If yes, then obtain the write address corresponding to the current decoded bit.

[0128] In this embodiment of the invention, if the number of write paths in the memory group with the same path length as the sub-path is less than or equal to the preset search width, it means that the sub-path can be written into the memory group, and then the write address corresponding to the current decoded bit is obtained.

[0129] Optionally, the method further includes:

[0130] If the number of write paths with the same path length as the subpath is not less than or equal to the preset search width, then delete write paths whose path length is less than the path length of the subpath.

[0131] If the jump is executed, then all sub-paths are written to the memory group according to the write address of the current decoded bit, and the steps of determining whether the number of updated write paths meets the preset storage depth condition are followed.

[0132] In this embodiment of the invention, if it is determined that the number of write paths in the memory group with the same path length as the sub-path does not meet the requirement of being less than or equal to the preset search width, then the search width of the memory group that has been reached before decoding is completed needs to first delete the write paths in the memory group whose path length is less than the sub-path length, and then jump to step 204.

[0133] Step 205: Write all sub-paths to the memory group according to the write address, and count the number of updated write paths in the memory group.

[0134] In this embodiment of the invention, all sub-paths are written into the memory group according to the address value corresponding to the write address, and the updated write path in the memory group is obtained. The number of updated write paths is then counted.

[0135] Step 206: Determine whether the number is less than the difference between the storage depth of the memory group and the preset storage constant.

[0136] In this embodiment of the invention, after counting the number of updated write paths, the number is compared with the difference between the storage depth of the memory group and a preset storage constant to determine whether the number is less than the difference.

[0137] Step 207: If satisfied, sort the updated write paths by their write metric values ​​and output the updated write path with the smallest write metric value as the optimal path.

[0138] Optionally, step 207 includes:

[0139] If the number of updated write paths in the memory group meets the preset storage depth condition, then obtain the write metric value of all updated write paths.

[0140] Based on the address value corresponding to each write metric in the memory group, write metric values ​​equal to the set number threshold are selected sequentially for comparison to determine the smaller write metric value.

[0141] Determine if the smaller write metric value is unique;

[0142] If not unique, then according to the address values ​​corresponding to all smaller write metrics, select the smaller write metrics that are within the number threshold to determine the smaller write metric, and jump to the step of determining whether the smaller write metric is unique.

[0143] If there is only one, then the smaller write metric value is determined as the minimum write metric value, and the updated write path corresponding to the address value of the minimum write metric value is taken as the optimal path.

[0144] Optionally, the number threshold is set to 2.

[0145] In this embodiment of the invention, reference is made to Figure 7 If the number of updated write paths in the memory bank meets the preset storage depth condition, all write metrics and their corresponding address values ​​are extracted from the current metric memory. According to the order of the address values ​​corresponding to each write metric in the metric memory, the first-level comparator sequentially selects write metrics in pairs to form comparison groups, performs parallel size comparisons and ascending sorting to determine the smaller write metric. It then checks if the smaller write metric is unique. If not unique, it means the smallest write metric has not yet been selected, and the next-level comparator sorts the data. The smaller values ​​in each comparison group determined by the first-level comparator are grouped into a new sequence and input into the next-level comparator. Based on the address values ​​corresponding to all smaller write metrics, the next-level comparator sequentially selects smaller write metrics in pairs, using a parallel comparison structure to determine the smallest write metric. It then jumps to the step of checking if the smaller write metric is unique. If unique, the smaller write metric is determined to be the smallest write metric, and the updated write path corresponding to the address value of this smallest write metric is taken as the optimal path.

[0146] Optionally, the method further includes:

[0147] If the number of updated write paths in the memory group does not meet the preset storage depth condition, then obtain the write metric value of all updated write paths.

[0148] Based on the address value corresponding to each write metric in the memory group, write metric values ​​equal to the set number threshold are selected sequentially for comparison to determine the smallest and largest write metric values.

[0149] The updated write path corresponding to the address value with the smallest write metric value is taken as the optimal path, and the process jumps to execute the step of outputting the optimal path as the target decoding result when the path length of the optimal path meets the decoding code length corresponding to the decoding request.

[0150] The updated write path corresponding to the address value with the largest write metric is taken as the worst path.

[0151] In this embodiment of the invention, if the number of updated write paths in the memory group does not meet the preset storage depth condition, it indicates that there are no free write addresses in the memory group. Therefore, the write metric values ​​of all updated write paths in the memory group are obtained. In the first-level comparator, comparison groups are formed in pairs according to the corresponding address values, and the values ​​are sorted by ascending tone to determine the smaller and larger write metric values. If neither is unique, the smaller and larger values ​​in each comparison group determined by the first-level comparator are combined into a new sequence and input into the next-level comparator. Through multi-level comparators comparing each other one by one, the updated write path corresponding to the address value with the smallest write metric value is output as the optimal path, and step 208 is executed; the updated write path corresponding to the address value with the largest write metric value is output as the worst path.

[0152] Step 208: When the path length of the optimal path meets the decoding code length corresponding to the decoding request, output the optimal path as the decoding result.

[0153] In this embodiment of the invention, the specific implementation process of step 208 is similar to that of step 106, and will not be repeated here.

[0154] Optionally, the method further includes:

[0155] When the path length of the optimal path does not meet the decoding code length corresponding to the decoding request, obtain the optimal path value and the path value of the previous decoding bit.

[0156] The optimal path value and the path value are XORed to determine the partial sum value of the next decoded bit.

[0157] The optimal path is used as the decoding path for the next bit, and the write address for the next round of decoding bits is determined.

[0158] Jump to execute the step of obtaining the initial log-likelihood ratio and partial sum value corresponding to the decoding path of the current decoded bit, performing log-likelihood ratio recursive operation, and generating the corresponding target log-likelihood ratio.

[0159] The optimal path value refers to the path value formed by the estimated bit values ​​of the optimal path.

[0160] In this embodiment of the invention, when the path length of the optimal path does not meet the decoding code length corresponding to the decoding request, it indicates that decoding has not yet been completed, and the decoding of the next bit needs to continue. See also... Figure 5 and Figure 8 After each optimal path selection, the address value of the optimal path is fed back to the partial sum update module. The partial sum output selector in the partial sum update module, based on the path length corresponding to the optimal path of the current decoded bit, performs an XOR operation with the optimal path value of the previous decoded bit and the path value of the optimal path, outputting the partial sum value of the next decoded bit. The optimal path is then used as the decoding path for path expansion of the next decoded bit, and the write address for the next round of decoded bits is determined. The process then jumps to the step of recursively calculating the log-likelihood ratio (LRPR) and partial sum value corresponding to the decoding path of the current decoded bit to generate the corresponding target LRPR.

[0161] Optionally, the step of determining the write address of the next round of decoded bits includes:

[0162] Determine whether the current bit should output the worst path;

[0163] If the worst path is not output, the address value of the best path and the free address value in the memory bank are used as the write address of the next round of decoded bits.

[0164] If the worst path is output, then the address values ​​of the best path and the worst path are used as the write addresses for the next round of decoding bits.

[0165] The free address value refers to the free write address in the memory bank.

[0166] In this embodiment of the invention, determining whether the worst path is output for the current bit, i.e., after the sub-path of the current bit is written to the memory group, checks whether there are still free write addresses. (See also...) Figure 9 Taking the metric memory as an example, if the worst path is not output, it means that there are still free write addresses in the memory group. In this case, the write path pointer of the write address of the next decoded bit points to the write address POP_ADDR where the address value of the optimal path is located and the write address CNT_ADDR where the free address value is located. If the worst path is output, the write path pointer of the write address of the next decoded bit points to the write address POP_ADDR where the address value of the optimal path is located and the address DEL_ADDR where the worst path is located.

[0167] Optionally, in the two sub-paths of the next decoded bit, sub-path "0" is written to address POP_ADDR, and sub-path "1" is written to address CNT_ADDR or address DEL_ADDR.

[0168] Please see Figure 3 , Figure 3 This is a flowchart illustrating an application example of a polar code decoding method provided in Embodiment 2 of the present invention.

[0169] The received channel layer log-likelihood ratios are sequentially written into the LLR memory. The corresponding initial log-likelihood ratios are read from and written from the LLR memory and input into the SC decoder. The control module, based on the current decoding path length, controls the operation function executed by the current operation unit to perform recursive calculations to obtain the target log-likelihood ratio. The decoding path of the current decoded bit is extended to bits "0" and "1", and the corresponding metric values ​​of the two newly extended sub-paths are calculated according to a preset metric model.

[0170] Determine the number of write paths c in the memory bank that have the same path length i as the subpath of the currently decoded bit. i Is c less than or equal to the search width L? i If the length is not less than L, then first delete the write paths in the memory group whose path length is less than i, or if c i If the number of write paths s in the current memory group is less than L, then check if the memory depth D-1 is less than the memory group depth. If s is less than D-1, sort the paths to find the optimal path; if s is not less than D-1, sort the paths to find the optimal and worst paths. Output the optimal path and check if its path length i is equal to the decoding code length N. If it is equal, the decoding is considered complete; if it is not equal, update the partial sum value and jump to the step of recursively calculating the target log-likelihood ratio, and execute the decoding of the next bit.

[0171] In this embodiment of the invention, in response to a decoding request sent by the demand-side platform, the target log-likelihood ratio of the current decoded bit is calculated, two sub-paths of the decoding path of the current decoded bit are constructed, and the metric value of the sub-path is determined based on a preset metric model using the target log-likelihood ratio and the estimated bit value of each sub-path. It is then determined whether the number of write paths in the preset memory group with the same path length as the sub-path is less than or equal to the preset search width. If so, the write address corresponding to the current decoded bit is obtained, and all sub-paths are written to the memory group according to the write address. The number of updated write paths is counted, and it is determined whether this number is less than the storage capacity of the memory group. If the difference between the depth and the preset storage constant is less than a certain value, the updated write paths are bitonically sorted according to the write metric values ​​in the memory bank. The updated write path with the smallest write metric value is output as the optimal path. When the path length of the optimal path meets the decoding code length corresponding to the decoding request, the optimal path is output as the decoding result. When the path length of the optimal path does not meet the decoding code length corresponding to the decoding request, partial sum feedback updates are performed using the optimal path value of the previous decoded bit and the path value of the optimal path. The optimal path is then used as the decoding path for the next decoded bit, and the write address for the next round of decoded bits is determined before the decoding of the next decoded bit is executed. Throughout the polar code decoding process, a combination of ascending tone sorting and parallel comparison is used during path contention. Combinational logic is applied to implement cross-layer registering and updating of partial sum values, improving the efficiency of searching for the optimal path and reducing decoding latency.

[0172] Please see Figure 4 , Figure 4 This is a structural block diagram of a polar code decoding system provided in Embodiment 3 of the present invention.

[0173] A polar code decoding system, comprising:

[0174] The log-likelihood ratio calculation module 401 is used to respond to the decoding request, obtain the initial log-likelihood ratio and partial sum value corresponding to the decoding path of the current decoding bit, perform log-likelihood ratio recursive calculation, and generate the corresponding target log-likelihood ratio.

[0175] The metric calculation module 402 is used to construct two sub-paths of the decoding path and determine the metric values ​​of all sub-paths by using the target log-likelihood ratio, the estimated bit values ​​of each sub-path, and a preset metric model.

[0176] The search width determination module 403 is used to obtain the path length of the write path in the preset memory group and determine whether the number of write paths with the same path length as the sub-path is less than or equal to the preset search width.

[0177] The storage depth determination module 404 is used to write all sub-paths to the memory group according to the write address of the current decoded bit if the storage depth is true, and to determine whether the number of updated write paths meets the preset storage depth condition.

[0178] The path sorting module 405 is used to perform a bitonic sort on the updated write path according to the write metric value of the updated write path if the condition is met, and output the updated write path with the smallest write metric value as the optimal path.

[0179] The decoding result output module 406 is used to output the optimal path as the decoding result when the path length of the optimal path meets the decoding code length corresponding to the decoding request.

[0180] Optionally, the measurement calculation module 402 is specifically used for:

[0181] The decoding path is expanded to construct two corresponding sub-paths;

[0182] Determine whether the currently decoded bit is an information bit;

[0183] If it is an information bit, then determine the estimated bit value of each sub-path, and determine the comparison result between the target log-likelihood ratio and the preset likelihood ratio constant;

[0184] Input the estimated bit values ​​and comparison results into the preset metric model, and output the metric value corresponding to each sub-path;

[0185] If it is not an information bit, then the metric value of all sub-paths is determined to be positive infinity according to the preset metric value model;

[0186] The preset metric model is as follows:

[0187]

[0188]

[0189] Where i represents the i-th decoded bit, PM i and PM i-1 Let A represent the metric values ​​of the i-th decoded bit and the (i-1)-th decoded bit, respectively; let B represent the information bit index set; and let B represent the decision condition. This represents the complement of the judgment conditions. LLR represents the estimated bit value of the i-th decoded bit. i Let represent the target log-likelihood ratio of the i-th decoded bit, with the likelihood ratio constant set to 0.

[0190] Optionally, the storage depth determination module 404 is specifically used for:

[0191] If so, obtain the write address corresponding to the current decoded bit;

[0192] Write all subpaths to the memory group according to the write address, and count the number of updated write paths in the memory group.

[0193] Determine if the number is less than the difference between the storage depth of the memory bank and the preset storage constant.

[0194] Optionally, the storage depth determination module 404 is also used for:

[0195] If the number of write paths with the same path length as the subpath is not less than or equal to the preset search width, then delete write paths whose path length is less than the path length of the subpath.

[0196] If the jump is executed, then all sub-paths are written to the memory group according to the write address of the current decoded bit, and the steps of determining whether the number of updated write paths meets the preset storage depth condition are followed.

[0197] Optionally, the optimal path determination module 405 is specifically used for:

[0198] If the number of updated write paths in the memory group meets the preset storage depth condition, then obtain the write metric value of all updated write paths.

[0199] Based on the address value corresponding to each write metric in the memory group, write metric values ​​equal to the set number threshold are selected sequentially for comparison to determine the smaller write metric value.

[0200] Determine if the smaller write metric value is unique;

[0201] If not unique, then according to the address values ​​corresponding to all smaller write metrics, select the smaller write metrics that are within the number threshold to determine the smaller write metric, and jump to the step of determining whether the smaller write metric is unique.

[0202] If there is only one, then the smaller write metric value is determined as the minimum write metric value, and the updated write path corresponding to the address value of the minimum write metric value is taken as the optimal path.

[0203] Optionally, the path sorting module 405 is also used for:

[0204] If the number of updated write paths in the memory group does not meet the preset storage depth condition, then obtain the write metric value of all updated write paths.

[0205] Based on the address value corresponding to each write metric in the memory group, write metric values ​​equal to the set number threshold are selected sequentially for comparison to determine the smallest and largest write metric values.

[0206] The updated write path corresponding to the address value with the smallest write metric value is taken as the optimal path, and the process jumps to execute the step of outputting the optimal path as the target decoding result when the path length of the optimal path meets the decoding code length corresponding to the decoding request.

[0207] The updated write path corresponding to the address value with the largest write metric is taken as the worst path.

[0208] Optionally, a decoding update module is also included for:

[0209] When the path length of the optimal path does not meet the decoding code length corresponding to the decoding request, obtain the optimal path value and the path value of the previous decoding bit.

[0210] The optimal path value and the path value are XORed to determine the partial sum value of the next decoded bit.

[0211] The optimal path is used as the decoding path for the next bit, and the write address for the next round of decoding bits is determined.

[0212] Jump to execute the step of obtaining the initial log-likelihood ratio and partial sum value corresponding to the decoding path of the current decoded bit, performing log-likelihood ratio recursive operation, and generating the corresponding target log-likelihood ratio.

[0213] Optionally, it also includes a write address determination module, used for:

[0214] Determine whether the current bit should output the worst path;

[0215] If the worst path is not output, the address value of the best path and the free address value in the memory bank are used as the write address of the next round of decoded bits.

[0216] If the worst path is output, then the address values ​​of the best path and the worst path are used as the write addresses for the next round of decoding bits.

[0217] The present invention provides an electronic device, including a memory and a processor. The memory stores a computer program, and when the computer program is executed by the processor, the processor performs the steps of the polar code decoding method as described in any embodiment of the present invention.

[0218] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the system and modules described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0219] In the several embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0220] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0221] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0222] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A polar code decoding method, characterized in that, include: In response to the decoding request, obtain the initial log-likelihood ratio and partial sum value corresponding to the decoding path of the current decoded bit, perform recursive log-likelihood ratio calculation, and generate the corresponding target log-likelihood ratio; Two sub-paths of the decoding path are constructed, and the target log-likelihood ratio, the estimated bit value of each sub-path, and a preset metric model are used to determine the metric value of all the sub-paths. Obtain the path length of the write path in the preset memory group, and determine whether the number of write paths with the same path length as the sub-path is less than or equal to the preset search width. If so, all the sub-paths are written to the memory group according to the write address of the current decoded bit, and it is determined whether the number of updated write paths meets the preset storage depth condition. If satisfied, the updated write paths are then sorted bit-tone according to their write metric values, and the updated write path with the smallest write metric value is output as the optimal path. When the path length of the optimal path meets the decoding code length corresponding to the decoding request, the optimal path is output as the decoding result. Also includes: If the number of updated write paths in the memory group does not meet the preset storage depth condition, then obtain the write metric value of all the updated write paths. According to the address value corresponding to each write metric value in the memory group, write metric values ​​equal to the set number threshold are selected in sequence for comparison to determine the smallest and largest write metric values. The updated write path corresponding to the address value of the minimum write metric value is taken as the optimal path, and the process jumps to execute the step of outputting the optimal path as the target decoding result when the path length of the optimal path meets the decoding code length corresponding to the decoding request. The updated write path corresponding to the address value of the largest write metric is taken as the worst path.

2. The polar code decoding method according to claim 1, characterized in that, The step of constructing two sub-paths of the decoding path and determining the metric values ​​of all the sub-paths using the target log-likelihood ratio, the estimated bit values ​​of each sub-path, and a preset metric model includes: The decoding path is expanded to construct two corresponding sub-paths; Determine whether the currently decoded bit is an information bit; If it is the information bit, then the estimated bit value of each sub-path is determined, and the comparison result between the target log-likelihood ratio and the preset likelihood ratio constant is determined; The estimated bit values ​​and the comparison results are input into a preset metric model, and the metric value corresponding to each sub-path is output. If it is not the information bit, then the metric value of all the sub-paths is determined to be positive infinity according to the preset metric value model; The preset metric model is specifically as follows: ; ; Where i represents the i-th decoded bit. and Let A represent the metric values ​​of the i-th decoded bit and the (i-1)-th decoded bit, respectively; let B represent the information bit index set; and let B represent the decision condition. This represents the complement of the judgment conditions. This represents the estimated bit value of the i-th decoded bit. Let represent the target log-likelihood ratio of the i-th decoded bit, with the likelihood ratio constant set to 0.

3. The polar code decoding method according to claim 1, characterized in that, If so, the step of writing all the sub-paths to the memory group according to the write address of the current decoded bit, and determining whether the number of updated write paths meets the preset storage depth condition, includes: If so, obtain the write address corresponding to the current decoded bit; Write all the sub-paths to the memory group according to the write address, and count the number of updated write paths in the memory group; Determine whether the number is less than the difference between the storage depth of the memory group and a preset storage constant.

4. The polar code decoding method according to claim 1, characterized in that, If the condition is met, the step of performing a bitonic sort on the updated write paths based on their write metric values ​​and outputting the updated write path with the smallest write metric value as the optimal path includes: If the number of updated write paths in the memory group meets the preset storage depth condition, then obtain the write metric value of all the updated write paths. According to the address value corresponding to each write metric value in the memory group, write metric values ​​equal to the set number threshold are selected in sequence for comparison to determine the smaller write metric value. Determine whether the smaller write metric value is unique; If not unique, then according to the address values ​​corresponding to all the smaller write metric values, the smaller write metric values ​​of the number threshold are selected in sequence to determine the smaller write metric value, and then the step of determining whether the smaller write metric value is unique is executed. If unique, the smaller write metric value is determined to be the smallest write metric value, and the updated write path to which the address value corresponding to the smallest write metric value belongs is taken as the optimal path.

5. The polar code decoding method according to claim 1, characterized in that, Also includes: If the number of write paths with the same path length as the sub-path is not less than or equal to the preset search width, then delete write paths whose path length is less than the path length of the sub-path. If the jump proceeds to the step of writing all the sub-paths to the memory group according to the write address of the current decoded bit, and determining whether the number of updated write paths meets the preset storage depth condition.

6. The polar code decoding method according to claim 1, characterized in that, Also includes: When the path length of the optimal path does not meet the decoding code length corresponding to the decoding request, the optimal path value of the previous decoded bit and the path value of the optimal path are obtained. The optimal path value and the path value are XORed to determine the partial sum value of the next decoded bit. The optimal path is used as the decoding path for the next decoded bit, and the write address for the next round of decoded bits is determined. Jump to execute the step of obtaining the initial log-likelihood ratio and partial sum value corresponding to the decoding path of the current decoded bit, perform log-likelihood ratio recursive operation, and generate the corresponding target log-likelihood ratio.

7. The polar code decoding method according to claim 6, characterized in that, The step of determining the write address of the next round of decoded bits includes: Determine whether the current bit should output the worst path; If the worst path is not output, the address value of the best path and the free address value in the memory group are used as the write address of the next round of decoded bits. If the worst path is output, then the address values ​​of the best path and the worst path are used as the write addresses for the next round of decoded bits.

8. A polar code decoding system, characterized in that, include: The log-likelihood ratio calculation module is used to respond to decoding requests, obtain the initial log-likelihood ratio and partial sum value corresponding to the decoding path of the current decoding bit, perform log-likelihood ratio recursive calculation, and generate the corresponding target log-likelihood ratio. The metric calculation module is used to construct two sub-paths of the decoding path, and to determine the metric values ​​of all the sub-paths using the target log-likelihood ratio, the estimated bit values ​​of each sub-path, and a preset metric model. The search width determination module is used to obtain the path length of the write path in the preset memory group and determine whether the number of write paths with the same path length as the sub-path is less than or equal to the preset search width. The storage depth determination module is used to write all the sub-paths to the memory group according to the write address of the current decoded bit if the storage depth determination module is true, and to determine whether the number of updated write paths meets the preset storage depth condition. The path sorting module is used to perform a bitonic sort on the updated write path according to the write metric value of the updated write path if the condition is met, and output the updated write path with the smallest write metric value as the optimal path. The decoding result output module is used to output the optimal path as the decoding result when the path length of the optimal path meets the decoding code length corresponding to the decoding request. The path sorting module is also used for: If the number of updated write paths in the memory group does not meet the preset storage depth condition, then obtain the write metric value of all the updated write paths. According to the address value corresponding to each write metric value in the memory group, write metric values ​​equal to the set number threshold are selected in sequence for comparison to determine the smallest and largest write metric values. The updated write path corresponding to the address value of the minimum write metric value is taken as the optimal path, and the process jumps to execute the step of outputting the optimal path as the target decoding result when the path length of the optimal path meets the decoding code length corresponding to the decoding request. The updated write path corresponding to the address value of the largest write metric is taken as the worst path.

9. An electronic device, characterized in that, The device includes a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor causes the processor to perform the steps of the polar code decoding method as described in any one of claims 1-7.

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