Array substrate, light-emitting substrate and display device

Abstract

The application discloses an array substrate, a light-emitting substrate and a display device, and relates to the technical field of display. The array substrate comprises a connecting lead (200), a signal channel area (500) extending along a first direction, a first power voltage lead (310) and a second power voltage lead (320); any signal channel area (500) comprises at least two control area columns (510) extending along the first direction, and any control area column (510) comprises a plurality of control areas arranged along the first direction; any control area comprises a pad connecting circuit (511) and a first pad group (410) for binding a microchip (600), the first pad group (410) is electrically connected with the first power voltage lead (310); the pad connecting circuit (511) comprises a plurality of second pad groups (420), a first end of which is electrically connected with the first pad group (410), and a second end of which is electrically connected with the second power voltage lead (320); wherein in at least one signal channel area (500), each first pad group (410) in the at least two control area columns (510) is electrically connected with the same first power voltage lead (310). The array substrate can improve the signal disturbance resistance.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a light-emitting substrate, and a display device. Background Art

[0002] In actively driven Mini-LED (mini light-emitting diode) display devices, Mini-LED uses addressing control, which can accurately control the brightness and darkness of each partition lamp, effectively achieving precise Local Diming (local dimming) effects, and its display contrast can reach the million level. Summary of the Invention

[0003] The present disclosure aims to provide an array substrate, a light-emitting substrate and a display device, so as to improve the signal disturbance resistance capability of the array substrate.

[0004] To achieve the above-mentioned purpose, the present invention adopts the following technical solutions:

[0005] According to a first aspect of the present disclosure, an array substrate is provided, comprising at least one signal channel region extending along a first direction and a plurality of driving leads extending along the first direction; the driving leads comprising a first power supply voltage lead and a second power supply voltage lead;

[0006] Any one of the signal channel regions includes at least two control region columns extending along the first direction, and any one of the control region columns includes a plurality of control regions arranged along the first direction;

[0007] Any one of the control areas includes at least one pad connection circuit and a first pad group for binding a microchip, the first pad group being electrically connected to the first power supply voltage lead; any one of the pad connection circuits includes a plurality of second pad groups connected by connection leads, a first end of the pad connection circuit being electrically connected to the first pad group, and a second end of the pad connection circuit being electrically connected to the second power supply voltage lead;

[0008] In the at least one signal channel region, each of the first pad groups in at least two control region columns is electrically connected to the same first power supply voltage lead.

[0009] In an exemplary embodiment of the present disclosure, any one of the signal channel regions includes two control region columns; within any one of the signal channel regions, the number of the first power supply voltage lead is one, and the number of the second power supply voltage lead is two, one located on either side of the first power supply voltage lead;

[0010] In any one of the signal channel regions, each of the first pad groups is electrically connected to the first power supply voltage lead, and the second end of each of the pad connection circuits is electrically connected to the second power supply voltage lead.

[0011] In an exemplary embodiment of the present disclosure, in two adjacent signal channel regions, two adjacent second power supply voltage leads are electrically connected to each other.

[0012] In an exemplary embodiment of the present disclosure, the array substrate further includes a plurality of conductive connection portions, and two adjacent second power supply voltage leads are connected via the plurality of conductive connection portions.

[0013] In an exemplary embodiment of the present disclosure, the drive lead also includes at least one microchip drive lead connected to the first pad group and used to drive the microchip, and in any one of the signal channel areas, the microchip drive lead is located between the first power supply voltage lead and the second power supply voltage lead.

[0014] In an exemplary embodiment of the present disclosure, any one of the first pad groups includes a first input signal sub-pad for loading a first input signal, a first power supply voltage sub-pad for loading a first power supply voltage, and at least one output sub-pad for loading an output signal;

[0015] In any one of the signal channel regions, the microchip drive leads include at least one first input signal lead located between the first power supply voltage lead and the second power supply voltage lead;

[0016] The first input signal sub-pad is directly connected to the first input signal lead or is connected via the connecting lead;

[0017] The first power supply voltage sub-pad is directly connected to the first power supply voltage lead or is connected via the connecting lead;

[0018] In any one of the control areas, the at least one pad connection circuit and the at least one output sub-pad are arranged in a one-to-one correspondence, and a first end of any one of the pad connection circuits is connected to the corresponding output sub-pad through the connecting lead.

[0019] In an exemplary embodiment of the present disclosure, in any one of the signal channel areas, the number of the first input signal leads is two, and they are respectively located on both sides of the first power supply voltage lead.

[0020] In an exemplary embodiment of the present disclosure, the second direction is parallel to the plane where the array substrate is located and perpendicular to the first direction;

[0021] In any one of the signal channel regions, along the second direction, the first control region column corresponds to the first second power supply voltage lead and the first first input signal lead, and the second control region column corresponds to the second second power supply voltage lead and the second first input signal lead;

[0022] The second end of each of the pad connection circuits in the control area column is electrically connected to the corresponding second power supply voltage lead through the connecting lead, and each of the first input signal sub-pads in the control area column is connected to the corresponding first input signal lead through the connecting lead.

[0023] In an exemplary embodiment of the present disclosure, in any one of the signal channel areas, the microchip drive lead further includes a second input signal lead, and the first pad group further includes a second input signal sub-pad; the second input signal lead is used to load a second input signal to at least one of the second input signal sub-pads.

[0024] In an exemplary embodiment of the present disclosure, in any one of the signal channel areas, P first pad groups are numbered in sequence according to a preset order; wherein, the second input signal sub-pad of the first pad group numbered 1 is connected to the second input signal lead through the connecting lead, and the output sub-pad of the first pad group numbered p is electrically connected to the second input signal sub-pad of the first pad group numbered p+1 through the connecting lead, wherein p and P are both integers, and p takes a value within the range of greater than 1 and less than P.

[0025] In an exemplary embodiment of the present disclosure, in any one of the signal channel regions, the second input signal lead is located between the first input signal lead and the second power supply voltage lead.

[0026] In an exemplary embodiment of the present disclosure, the array substrate further includes a binding area, in which are provided various binding pads connected to the various driving leads; the control area farthest from the binding area in any one of the control area columns is the first control area in the control area column.

[0027] In an exemplary embodiment of the present disclosure, the bonding area is provided with a floating bonding pad, and the floating bonding pad is connected to the output sub-pad of the first pad group numbered P in the signal channel region.

[0028] In an exemplary embodiment of the present disclosure, the second direction is parallel to the plane where the array substrate is located and perpendicular to the first direction;

[0029] In any one of the signal channel regions, along the second direction, the second input signal lead is located between a first second power supply voltage lead and a second first input signal lead;

[0030] The distance between a first one of the second power supply voltage leads and a second one of the first input signal leads is equal to the distance between a second one of the second power supply voltage leads and a second one of the first input signal leads.

[0031] In an exemplary embodiment of the present disclosure, the array substrate also includes a binding area, in which at least one binding pad group corresponding one-to-one to the at least one signal channel area is provided; wherein any one of the binding pad groups includes a plurality of binding pads connected one-to-one to the plurality of driving leads in the corresponding signal channel area.

[0032] In an exemplary embodiment of the present disclosure, the arrangement order of the multiple driving leads in any one of the signal channel areas along the first direction is the same as the arrangement order of the multiple binding pads correspondingly connected to the multiple driving leads in the same direction.

[0033] In an exemplary embodiment of the present disclosure, any one of the bonding pad groups includes a second power supply voltage bonding pad for connecting to the second power supply voltage lead;

[0034] Wherein, the two second power supply voltage binding pads corresponding to the two adjacent second power supply voltage leads in the two adjacent signal channel areas are connected to each other as a whole.

[0035] In an exemplary embodiment of the present disclosure, the second pad group consists of a first sub-pad and a second sub-pad arranged in pairs.

[0036] In an exemplary embodiment of the present disclosure, any one of the pad connection circuits includes a plurality of second pad groups connected in sequence, wherein the first sub-pad of the first second pad group is electrically connected to the second power supply voltage lead through the connecting lead, the second sub-pad of the last second pad group is electrically connected to the first pad group through the connecting lead, and the second sub-pad of the previous second pad group is electrically connected to the first sub-pad of the next second pad group through the connecting lead.

[0037] In an exemplary embodiment of the present disclosure, the array substrate includes a base substrate, a first metal wiring layer, an insulating material layer and a second metal wiring layer stacked in sequence, wherein the driving lead and the binding pad group are located in the first metal wiring layer, and the connecting lead, the first pad group and the second pad group are located in the second metal wiring layer; the second metal wiring is electrically connected to the first metal wiring layer through a via located in the insulating material layer.

[0038] According to a second aspect of the present disclosure, a light-emitting substrate is provided, comprising the above-mentioned array substrate, and microchips bound and connected to each of the first pad groups in a one-to-one correspondence, and light-emitting elements bound and connected to each of the first pad groups in a one-to-one correspondence.

[0039] According to a third aspect of the present disclosure, a display device is provided, comprising the above-mentioned light-emitting substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the accompanying drawings.

[0041] Figure 1 Schematic diagram of the structural principle of an array substrate in one embodiment of the present disclosure.

[0042] Figure 2 Schematic diagram of the partial structure of the first metal wiring layer and the second metal wiring layer of the array substrate in one embodiment of the present disclosure.

[0043] Figure 3 for Figure 2 Schematic diagram of the structure of the first metal wiring layer in.

[0044] Figure 4 for Figure 2 Schematic diagram of the structure of the second metal wiring layer in.

[0045] Figure 5 Schematic diagram of the structure of the pins of a microchip in one embodiment of the present disclosure.

[0046] Figure 6 Schematic diagram of the structure of the first pad group in one embodiment of the present disclosure.

[0047] Figure 7 This is a structural diagram of an embodiment of the present disclosure, in which the first pad group and the driving leads are both located in the first metal wiring layer.

[0048] Figure 8 This is a schematic structural diagram of an embodiment of the present disclosure, in which the driving lead and the first pad group are respectively located in the first metal wiring layer and the second metal wiring layer.

[0049] Figure 9 This is a schematic diagram of the partial structure of the microchip, light-emitting element, first metal wiring layer and second metal wiring layer of the light-emitting substrate at one end near the binding area in one embodiment of the present disclosure.

[0050] Figure 10 for Figure 9 Schematic diagram of the structure of the first metal wiring layer in.

[0051] Figure 11 for Figure 9 Schematic diagram of the structure of the microchip, light-emitting element and second metal wiring layer.

[0052] Figure 12 For the array substrate Figure 2 Schematic diagram of the cross-sectional structure at the MN position in .

[0053] Figure 13 for Figure 9 Schematic diagram of the enlarged area C in FIG.

[0054] Figure 14 for Figure 2 Schematic diagram of the structure of the first metal wiring layer in.

[0055] The main components in the figure are described as follows:

[0056] 110, substrate; 120, buffer layer; 130, first metal wiring layer; 131, copper seed layer; 132, copper growth layer; 140, insulating material layer; 141, first passivation layer; 142, planarization organic material layer; 150, second metal wiring layer; 160, second passivation layer; 170, insulating protection layer; 200, connecting lead; 300, driving lead; 310, first power supply voltage lead; 320, second power supply voltage lead. Pressed lead; 330, microchip drive lead; 331, first input signal lead; 332, second input signal lead; 340, conductive connection portion; 410, first pad group; 411, first input signal sub-pad; 412, second input signal sub-pad; 413, first power supply voltage sub-pad; 414, output sub-pad; 420, second pad group; 421, first sub-pad; 422, second sub-pad; 430, binding pad ;4301, binding electrode;431, first power supply voltage binding pad;432, second power supply voltage binding pad;433, first input signal binding pad;434, second input signal binding pad;435, floating binding pad;436, dummy electrode;440, fan-out lead;441, first power supply voltage fan-out lead;442, second power supply voltage fan-out lead;443, first input signal fan-out lead;444, second input signal fan-out lead;445, floating fan-out lead;500, signal channel area;510, control area column;511, pad connection circuit;600, microchip;610, first input signal pin;620, second input signal pin;630, first power supply voltage pin;640, output pin;700, light-emitting element;801, light-emitting circuit;A, control area;B, binding area;D, first direction;E, second direction DETAILED DESCRIPTION

[0057] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of the embodiments of the present disclosure.

[0058] In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

[0059] The described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or other methods, components, materials, etc. can be adopted. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid obscuring the main technical ideas of the present disclosure.

[0060] When a structure is “on” another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is “directly” disposed on the other structure, or that the structure is “indirectly” disposed on the other structure via another structure.

[0061] The terms "a," "an," and "the" are used to indicate the presence of one or more elements / components; the terms "including" and "having" are used to indicate an open-ended inclusiveness and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc. The terms "first," "second," etc. are used merely as labels and do not limit the quantity of the items to which they refer.

[0062] In this disclosure, when two structures "overlap," it means that the orthographic projection of one structure on the substrate at least partially overlaps the orthographic projection of the other structure on the substrate. In this disclosure, when two structures "completely overlap," it means that the orthographic projection of one structure on the substrate is completely within the orthographic projection of the other structure on the substrate.

[0063] The present disclosure provides an array substrate, see Figure 1 The array substrate includes a plurality of connection leads 200 , at least one signal channel region 500 extending along a first direction D, and a plurality of driving leads 300 extending along the first direction D. The driving leads 300 include at least a first power supply voltage lead 310 and a second power supply voltage lead 320 .

[0064] Any signal channel region 500 includes at least two control region columns 510 extending along the first direction D, and any control region column 510 includes a plurality of control regions A arranged along the first direction D.

[0065] Any control area A includes at least one pad connection circuit 511 and a first pad group 410 for bonding the microchip 600. The first pad group 410 is electrically connected to the first power supply voltage lead 310. Figure 2 and Figure 4Any one of the pad connection circuits 511 includes a plurality of second pad groups 420 connected by the connecting lead 200 , and a first end of the pad connection circuit 511 is electrically connected to the first pad group 410 , and a second end of the pad connection circuit 511 is electrically connected to the second power supply voltage lead 320 .

[0066] In at least one signal channel region 500 , each first pad group 410 in at least two control region columns 510 is electrically connected to the same first power supply voltage lead 310 .

[0067] In the array substrate provided by the present disclosure, at least two control region columns 510 share the same first power voltage lead 310. Compared with the design method of setting a first power voltage lead 310 for each control region column 510, the arrangement method of the first power voltage lead 310 disclosed in the present disclosure can have a larger width to reduce impedance and reduce the first power voltage V G The fluctuation of the first power supply voltage V G The stability of the array substrate is improved, thereby improving the array substrate's ability to resist signal disturbances and facilitating debugging of the array substrate. In some embodiments, any signal channel region 500 includes 2M control region columns 510 extending along the first direction D, and any control region column 510 includes multiple control regions A arranged along the first direction D, where M is a positive integer greater than or equal to 1. Within a signal channel region 500, at least two adjacent control region columns 510 can share the same first power supply voltage lead 310, so that the number of first power supply voltage leads 310 in the signal channel region is less than 2M, thereby increasing the width of the first power supply voltage lead 310 and improving the array substrate's ability to resist signal disturbances.

[0068] In some embodiments, any one signal channel region 500 includes 2M control region columns 510 extending along a first direction D, and any one control region column 510 includes a plurality of control regions A arranged along the first direction D, where M is a positive integer greater than or equal to 1. Within a signal channel region 500, 2m adjacent control region columns 510 can share the same first power supply voltage lead 310, where m is a positive integer greater than 1. The first power supply voltage lead 310 can be located in an area between two middle control region columns 510 of the 2m control region columns 510. In this way, the number of first power supply voltage leads 310 in the signal channel region is reduced to less than 2M, thereby increasing the width of the first power supply voltage lead 310 and improving the array substrate's ability to resist signal disturbances.

[0069] In some embodiments, any signal channel region 500 includes 2M control region columns 510 extending along a first direction D, and any control region column 510 includes multiple control regions A arranged along the first direction D, where M is a positive integer greater than or equal to 1. The 2M control region columns 510 within the signal channel region can be divided into M groups, each group including two adjacent control region columns 510, and different groups do not share the same control region column 510. In other words, the 2M control region columns 510 can be sequentially divided into M groups along a second direction E, with each group including two control region columns 510. The second direction E is within the plane of the array substrate and perpendicular to the first direction D. Each group can share the same first power supply voltage lead 310, so that only M first power supply voltage leads 310 need be provided within a signal channel region 500, further increasing the width of the first power supply voltage lead 310 and improving the array substrate's ability to resist signal disturbances.

[0070] In some other embodiments, any one signal channel region 500 includes 2M+1 control region columns 510 extending along the first direction D, and any one control region column 510 includes multiple control regions A arranged along the first direction D, where M is a positive integer greater than 1. Within a signal channel region 500, at least two adjacent control region columns 510 can share the same first power supply voltage lead 310, so that the number of first power supply voltage leads 310 within the signal channel region is less than 2M, thereby increasing the width of the first power supply voltage lead 310 and improving the array substrate's ability to resist signal disturbances.

[0071] Furthermore, the 2M+1 control area columns 510 in the signal channel area can be divided into M+1 groups, one of which includes one control area column 510, and each of the remaining M groups includes two adjacent control area columns 510, and different groups do not share the same control area column 510; each group can share the same first power supply voltage lead 310, so that only M+1 first power supply voltage leads 310 need to be set in a signal channel area 500, further increasing the width of the first power supply voltage lead 310 and improving the array substrate's ability to resist signal disturbances.

[0072] In some embodiments of the present disclosure, see Figure 1 Any signal channel region 500 includes two control region columns 510 extending along the first direction D. Within any signal channel region 500 , there is one first power supply voltage lead 310 and two second power supply voltage leads 320 , one located on either side of the first power supply voltage lead 310 .

[0073] In this way, compared with the design method of setting a separate first power supply voltage lead 310 for a control area column 510, the array substrate disclosed in the present invention can reduce the number of first power supply voltage leads 310 by half, thereby more effectively increasing the width of the first power supply voltage lead 310 and improving the array substrate's ability to resist signal disturbances.

[0074] The structure, principle and effect of the array substrate disclosed herein will be further explained and illustrated below with reference to the accompanying drawings.

[0075] Alternatively, see Figure 12 The array substrate of the present disclosure may include a base substrate 110 and one or more metal wiring layers disposed on the base substrate 110; see Figure 1 The metal wiring layer can form the conductive structures required by the array substrate, such as the driving leads 300, the connecting leads 200, the first pad group 410 and the second pad group 420. When the array substrate has multiple metal wiring layers, an insulating layer can be provided between two adjacent metal wiring layers. The insulating layer can include an organic insulating layer, an inorganic insulating layer, or a mixture of the two. Vias can be provided on the insulating layer to electrically connect the upper and lower metal wiring layers. For further information, see Figure 12 , the array substrate may also be provided with an insulating protective layer 170. The material of the insulating protective layer 170 may include an organic insulating material. The opening portion of the insulating protective layer 170 may expose the first pad group and the second pad group on the array substrate, while the other portions of the insulating protective layer may protect the driving leads and the connecting leads. When a light-emitting substrate is formed by arranging light-emitting elements and microchips on the array substrate, the light-emitting elements may be electrically connected to the second pad 420 through a connecting structure, and the microchip may be electrically connected to the first pad group through a connecting structure. The connecting structure may be composed of materials such as solder paste or conductive glue, or the connecting structure may be a concave-convex structure with a spike shape composed of a hard metal material. For example, the functional device may be connected to the device pad through a connecting structure composed of solder paste through processes such as printed soldering, die bonding, and reflow soldering.

[0076] In one embodiment of the present disclosure, see Figure 2 、 Figure 4 and Figure 8 , the connection lead 200, the first pad group 410 and the second pad group 420 may be located in the same metal wiring layer, while the driving lead 300 is located in another metal wiring layer. Figure 12The array substrate includes a base substrate 110, a first metal wiring layer 130, an insulating material layer 140, and a second metal wiring layer 150, which are stacked in sequence. The driving leads 300 are located in the first metal wiring layer 130, and the connecting leads 200, the first pad group 410, and the second pad group 420 are located in the second metal wiring layer 150. The second metal wiring is electrically connected to the first metal wiring layer 130 through vias located in the insulating material layer 140.

[0077] Alternatively, in another embodiment of the present disclosure, see Figure 7 The first pad group 410 and the driving lead 300 may also be located in the same metal layer, for example, both are located in the first metal wiring layer.

[0078] Optionally, the thickness of the first metal wiring layer 130 is greater than the thickness of the second metal wiring layer 150. By increasing the thickness of the driving lead 300, the signal fluctuation on the driving lead 300 can be reduced. Accordingly, the impedance of the first power supply voltage lead 310 and the second power supply voltage lead 320 is reduced, which is beneficial to the debugging of the array substrate.

[0079] Furthermore, the thickness of the first metal wiring layer 130 can be between 1.5 and 20 microns. In some embodiments, the thickness of the first metal wiring layer 130 can be between 1.5 and 7 microns. The first metal wiring layer 130 can be formed using electroplating copper or chemical copper plating.

[0080] The array substrate provided by the present disclosure is Figure 4 and Figure 9 , which has a first pad group 410 for bonding the microchip 600 and a pad connection circuit 511 electrically connected to the first pad group 410. The pad connection circuit 511 has a second pad group 420 for bonding functional devices. In this way, the microchip 600 and the functional devices can be bonded to the array substrate, thereby forming a functional substrate that actively drives the functional devices through the microchip 600. The functional devices can be current-driven components, such as heating components, light-emitting components 700, sound-generating components, etc., or they can be electronic components that implement sensing functions, such as photosensors, thermosensitive components, etc.

[0081] Exemplarily, the second pad group 420 of the array substrate provided by the present disclosure can be used to bind the light-emitting element 700, for example, it can be used to bind micro light-emitting diodes (including Micro LED, Mini LED), etc., so that a light-emitting substrate can be formed. It is understandable that the second pad group 420 can also be used to bind other sensors, such as temperature sensors, pressure sensors, infrared sensors and other electronic components. In this case, the second pad group 420 may include multiple sub-pads. In some embodiments, the second pad group 420 can be used to bind micro light-emitting diodes, or all used to bind components such as sensors, or a part of the second pad group 420 can be used to bind micro light-emitting diodes, and a part can be used to bind sensors. Even, some of the second pad groups 420 may not be bound to any electronic components.

[0082] In some embodiments, the array substrate provided by the present disclosure may further include a third pad group for binding other electronic components. The present disclosure does not limit the position, function and connection relationship of the third pad group, which can be set according to actual needs.

[0083] In some embodiments, see Figure 4 The second pad group 420 consists of a first sub-pad 421 and a second sub-pad 422; in the pad connection circuit 511, when the second pad group 420 is bound and connected to the light-emitting element 700, the first sub-pad 421 and the second sub-pad 422 can be respectively bound and connected to the two electrodes of the light-emitting element 700.

[0084] See also Figure 4 In a pad connection circuit 511, each second pad group 420 can be connected by a connecting wire 200; see Figure 11 When each second pad group 420 is bound to a light-emitting element 700, the pad connection circuit 511 and the light-emitting element 700 can form a light-emitting circuit 801. The connection method of each second bonding pad group 430 can be determined according to the needs of the light-emitting circuit 801, so that the light-emitting circuit 801 can drive each light-emitting element 700. The pad connection circuit 511 can be configured to enable the light-emitting elements 700 in the light-emitting circuit 801 to be connected in series, in parallel, or in a combination of series and parallel.

[0085] For example, see Figure 4, any one pad connection circuit 511 includes Q second pad groups 420 connected in series in sequence. Among them, the first sub-pad 421 of the first second pad group 420 serves as the second end of the pad connection circuit 511 and is electrically connected to the second power supply voltage lead 320 through the connecting lead 200; the second sub-pad 422 of the Q-th second pad group 420 serves as the first end of the pad connection circuit 511 and is electrically connected to the first pad group 410 through the connecting lead 200. The second sub-pad 422 of the q-th second pad group 420 is electrically connected to the first sub-pad 421 of the (q+1)-th second pad group 420 through the connecting lead 200, wherein q is a positive integer and 1≤q≤Q-1. In this way, see Figure 11 When the light-emitting elements 700 are bonded to the pad connection circuit 511 to form a light-emitting circuit 801 , the light-emitting elements 700 in the light-emitting circuit 801 are sequentially connected in series.

[0086] In a pad connection circuit 511, the number of the second pad groups 420 included can be determined according to the needs of the array substrate, for example, 2 to 8 second pad groups 420 can be included. Figure 2 , a pad connection circuit 511 includes four second pad groups 420 .

[0087] In one embodiment of the present disclosure, the second pad groups 420 on the array substrate may be distributed in an array as a whole, so that the light-emitting elements 700 on the light-emitting substrate may be distributed in an array.

[0088] In some embodiments, see Figure 2 , the orthographic projection of part of the second pad group 420 on the base substrate 110 may be located in the orthographic projection of the first power supply voltage lead 310 on the base substrate 110; and the orthographic projection of part of the second pad group 420 on the base substrate 110 may be located in the orthographic projection of the second power supply voltage lead 320 on the base substrate 110. For example, see Figure 2 A pad connection circuit may include four second pad groups. In some control areas, particularly in control area A that is not close to the bonding area of ​​the array substrate, two second pad groups completely overlap with the first power supply voltage lead 310, and another two second pad groups completely overlap with the second power supply voltage lead 310.

[0089] In other embodiments, part of the second pad group 420 may not overlap with the first power supply voltage lead 310 and the second power supply voltage lead 320. For example, see Figure 9 In a row of control areas closest to the binding area, part of the second binding pads 420 may overlap with the fan-out leads, and part of the second binding pads 420 may not overlap with the first power supply voltage lead 310, the second power supply voltage lead 320 and the fan-out leads.

[0090] See also Figures 1-3 , a plurality of driving leads 300 can be provided in a signal channel area 500, and gaps need to be provided between each driving lead 300 to avoid signal interference between each other. Compared with the design scheme in which a first power supply voltage lead 310 is provided for each control area column in a signal channel area, the array substrate provided by the embodiment of the present disclosure combines at least two first power supply voltage leads 310 in a signal channel area into one, thereby reducing the number of driving leads 300 located in the same signal channel area, thereby saving the area occupied by the gaps that need to be left between adjacent driving leads 300, and increasing the area of ​​at least one first power supply voltage lead 310 in a signal channel area, further reducing the impedance of the first power supply voltage lead 310. In this way, the first power supply voltage V loaded on the first power supply voltage lead 310 can be increased without increasing the thickness of the driving lead 320. G Furthermore, in the array substrate provided by the present disclosure, since the area of ​​at least one first power supply voltage lead 310 within a signal channel region can be increased, the thickness of the driving lead 300 can be reduced in some embodiments, thereby reducing the cost of the array substrate and further achieving a thinner and lighter array substrate.

[0091] For example, in a design scheme of the related art, a signal channel region includes two control region columns, each of which is provided with a first power supply voltage lead 310 having a thickness of, for example, 1.8 microns. To minimize IR voltage drop and electrical interference between signal lines, the minimum width of each first power supply voltage lead 310 is, for example, 8 mm, and the impedance of a first power supply voltage lead 310 is 1.58 Ω. In contrast, in the array substrate provided in the embodiment of the present disclosure, a signal channel region includes two control region columns, each of which is provided with only one first power supply voltage lead 310 having a thickness of 1.8 microns. The minimum width of the first power supply voltage lead 310 can be multiplied, for example, to 18 mm, and the impedance can be reduced to 0.65 Ω. Therefore, it can be seen that the first power supply voltage lead 310 in the array substrate using the embodiment of the present disclosure has a lower impedance.

[0092] It should be understood that the above-described examples of the width, thickness, and resistance of the first power supply voltage lead 310 are merely examples of one embodiment. In other embodiments of the present disclosure, the thickness and width of the first power supply voltage lead 310 can be adjusted and determined based on the electrical requirements of the first power supply voltage lead 310, so as to meet the electrical requirements of the array substrate, particularly the array substrate's requirement for low signal perturbation of the first power supply voltage lead 310. Generally speaking, the shorter the length, the wider the width, and the thicker the first power supply voltage lead 310, the lower the resistance of the first power supply voltage lead 310, the lower the voltage signal perturbation caused by current fluctuations on the first power supply voltage lead 310, and the stronger the first power supply voltage lead 310's ability to resist signal perturbations, thereby improving the stability of the microchip. When the size of the array substrate increases, the length of the first power supply voltage lead 310 can be longer, and the thickness or width of the first power supply voltage lead 310 can be increased to improve the array substrate's ability to resist signal perturbations. In some embodiments, when the size of the array substrate increases, the length of the first power supply voltage lead 310 increases substantially proportionally, causing its resistance to increase substantially proportionally. In other embodiments, when the thickness of the first power supply voltage lead 310 increases, the resistance of the first power supply voltage lead 310 increases substantially proportionally.

[0093] In some embodiments, the first power supply voltage V G The first power supply voltage V loaded on the first power supply voltage lead 310 is a DC constant voltage. G The more stable and the smaller the fluctuation, the more stable the signal transmission of the array substrate, the better the array substrate's anti-signal disturbance performance, and the easier it is to debug.

[0094] See also Figure 1 The second direction E is parallel to the plane where the array substrate is located and perpendicular to the first direction D. In a signal channel area 500, along the second direction E or the opposite direction thereof, two channels for loading the second power supply voltage V LED The second power supply voltage leads 320 are located on both sides of the first power supply voltage lead 310. In some embodiments, the second power supply voltage V LED It can be a driving voltage V for driving each functional device bound to the second pad group 420. LED .

[0095] In some embodiments, the second power supply voltage is a DC constant voltage. The more stable and less volatile the second power supply voltage applied to the second power supply voltage lead 320 is, the more stable the signal transmission of the array substrate is, the better the anti-signal disturbance performance of the array substrate is, and the easier it is to debug. Figure 2Two adjacent second power supply voltage leads 320 located in two different signal channel regions 500 are electrically connected to each other. Thus, when the signals on two adjacent second power supply voltage leads 320 are inconsistent, the two connected second power supply voltage leads 320 can achieve signal shunting, preventing signal overload on one of the second power supply voltage leads 320. This provides the array substrate with improved overload resistance.

[0096] Alternatively, see Figure 2 and Figure 3 The array substrate further includes a plurality of conductive connecting portions 340, and two adjacent second power supply voltage leads 320 are connected via the plurality of conductive connecting portions 340. Thus, the two adjacent second power supply voltage leads 320 are connected via the plurality of conductive connecting portions 340 to form a grid pattern. This not only allows for fully and effectively signal splitting between the two second power supply voltage leads 320, but also prevents two adjacent second power supply voltage leads 320 from being completely merged into one second power supply voltage lead 320, which would result in an excessively large metal area of ​​the metal wiring layer.

[0097] It is understood that in some other embodiments, two adjacent second power supply voltage leads 320 may be completely merged into a single second power supply voltage lead 320 to reduce the impedance of the second power supply voltage lead 320 and improve its overload resistance. Furthermore, the metal area ratio of the metal wiring layer can be adjusted to meet the manufacturing process requirements of the array substrate by adjusting the spacing between different driving leads, hollowing out portions of the first power supply voltage lead 310 and / or the second power supply voltage lead 320, and other methods.

[0098] In one embodiment of the present disclosure, see Figure 2 The conductive connection portion 340 and the second power supply voltage lead 320 can be located in the same metal wiring layer. For example, the conductive connection portion 340 and the second power supply voltage lead 320 can both be located in the first metal wiring layer 130, with the conductive connection portion 340 located between and connected to two adjacent second power supply voltage leads 320, so that the two adjacent second power supply voltage leads 320 and the conductive connection portion 340 therebetween form a grid.

[0099] Of course, part or all of the conductive connection portion 340 may also be located in a different metal wiring layer from the second power supply voltage lead 320. For example, in another embodiment of the present disclosure, the second power supply voltage lead 320 is located in the first metal wiring layer 130, and the conductive connection portion 340 is located in the second metal wiring layer 150, and the conductive connection portion 340 is connected to two adjacent second power supply voltage leads 320 through a via. For another example, in another embodiment of the present disclosure, the second power supply voltage lead 320 is located in the first metal wiring layer 130, and the conductive connection portion 340 includes a first portion and a second portion, wherein the first portion is located in the first metal wiring layer 130 and is connected to one of the second power supply voltage leads 320, and the second portion is located in the second metal wiring layer 150 and is connected to the first portion and the other second power supply voltage lead 320 through a via.

[0100] See also Figure 2 The drive leads 300 further include at least one microchip drive lead 330 connected to the first pad group 410 and used to drive the microchip 600. Within any signal channel region 500, the microchip drive lead 330 is located between the first power supply voltage lead 310 and the second power supply voltage lead 320. Thus, in the second direction E or the opposite direction thereof, the two second power supply voltage leads 320 are located on opposite sides of the signal channel region 500, and the other drive leads 320 within the signal channel region 500 are located between the two second power supply voltage leads 320. This facilitates electrical connection between two adjacent second power supply voltage leads 320 in two adjacent signal channel regions 500, and allows the first power supply voltage lead 310 and the second power supply voltage lead 320 to be spaced apart from each other, thereby reducing the possibility of signal crosstalk between different drive leads 300.

[0101] See also Figure 6 Any first pad group 410 includes at least a first input signal sub-pad 411 for loading a first input signal Pwr, a first power supply voltage V G The first power supply voltage sub-pad 413 and at least one output sub-pad 414 for loading an output signal. Figure 5 The microchip 600 on the light-emitting substrate includes at least a first input signal pin 610 for correspondingly binding and connecting to the first input signal sub-pad 411, a first power supply voltage pin 630 for correspondingly binding and connecting to the first power supply voltage sub-pad 413, and at least one output pin 640 for correspondingly binding and connecting to each output sub-pad 414. In the light-emitting substrate, the array substrate can provide the first input signal Pwr to the microchip 600 through the first input signal sub-pad 411, and provide the first power supply voltage V to the microchip 600 through the first power supply voltage sub-pad 413. G, and receives the signal output by the microchip 600 through the output sub-pad 414. Optionally, the first input signal Pwr can be a chip power supply voltage or a power line carrier communication signal, which includes a communication signal for controlling the light emitting element 700 to emit light.

[0102] Optionally, the first power supply voltage sub-pad 413 is directly connected to the first power supply voltage lead 310 or connected via a connecting lead 200. For example, in one embodiment of the present disclosure, see Figure 8 and Figure 12 , the first power supply voltage sub-pad 413 is located on the second metal wiring layer 150, and the first power supply voltage lead 310 is located on the first metal wiring layer 130, the first power supply voltage sub-pad 413 is connected to the connection lead 200 located on the second metal wiring layer 150, and the connection lead 200 is connected to the first power supply voltage lead 310 through a via. For example, in another embodiment, see Figure 7 and Figure 12 , the first power supply voltage sub-pad 413 and the first power supply voltage lead 310 are both located on the first metal wiring layer 130, and the two are directly connected. The insulating material layer of the array substrate is provided with a via that exposes at least a portion of the first power supply voltage sub-pad 413, so that the first power supply voltage pin 630 of the microchip 600 is bound and connected to the first power supply voltage sub-pad 413 through the via. As another example, in another embodiment of the present disclosure, the first power supply voltage sub-pad 413 is located on the second metal wiring layer 150, and the first power supply voltage lead 310 is located on the first metal wiring layer 130; the orthographic projection of the first power supply voltage sub-pad 413 on the base substrate 110 overlaps with the orthographic projection of the first power supply voltage lead 310 on the base substrate 110, and the first power supply voltage sub-pad 413 is connected to the first power supply voltage lead 310 through the via.

[0103] Alternatively, see Figure 4 and Figure 6 In any control area A, at least one pad connection circuit 511 is provided in a one-to-one correspondence with at least one output sub-pad 414 in the first pad group 410, and the first end of any pad connection circuit 511 is connected to the corresponding output sub-pad 414 via a connecting lead 200. In this way, in the light-emitting substrate, the signal output by the microchip 600 can be loaded into the pad connection circuit 511 to drive the light-emitting state of each light-emitting element 700 connected to the pad connection circuit 511.

[0104] In one embodiment of the present disclosure, the output sub-pad 414 and the second pad group 420 are located in the same metal wiring layer, for example, both are located in the second metal wiring layer 150 .

[0105] Alternatively, seeFigures 1-3 In any signal channel region 500, the microchip drive lead 330 includes at least one first input signal lead 331 located between the first power supply voltage lead 310 and the second power supply voltage lead 320. The first input signal sub-pad 411 is directly connected to the first input signal lead 331 or connected via a connecting lead 200. For example, in one embodiment of the present disclosure, see Figure 8 and Figure 12 , the first input signal sub-pad 411 is located on the second metal wiring layer 150, and the first input signal lead 331 is located on the first metal wiring layer 130, the first input signal sub-pad 411 is connected to the connection lead 200 located on the second metal wiring layer 150, and the connection lead 200 is connected to the first input signal lead 331 through a via. For example, in another embodiment, see Figure 7 and Figure 12 , the first input signal sub-pad 411 and the first input signal lead 331 are both located on the first metal wiring layer 130, and the two are directly connected. The insulating material layer 140 of the array substrate is provided with a via that exposes at least a portion of the first input signal sub-pad 411, so that the first input signal pin 610 of the microchip 600 is bound and connected to the first input signal sub-pad 411 through the via. As another example, in another embodiment of the present disclosure, the first input signal sub-pad 411 is located on the second metal wiring layer 150, and the first input signal lead 331 is located on the first metal wiring layer 130; the orthographic projection of the first input signal sub-pad 411 on the base substrate 110 overlaps with the orthographic projection of the first input signal lead 331 on the base substrate 110, and the first input signal sub-pad 411 is connected to the first input signal lead 331 through the via.

[0106] In one embodiment of the present disclosure, within any signal channel area 500 , the number of first input signal leads 331 is consistent with the number of control area columns 511 , for example, two, so that the first input signal leads 331 can be located on both sides of the first power supply voltage lead 310 respectively.

[0107] Alternatively, see Figure 1 、 Figure 2 and Figure 6Within any signal channel region 500, along the second direction E, the first control region column 510 corresponds to the first second power supply voltage lead 320 and the first first input signal lead 331, and the second control region column 510 corresponds to the second second power supply voltage lead 320 and the second first input signal lead 331. The second end of each pad connection circuit 511 in the control region column 510 is electrically connected to the corresponding second power supply voltage lead 320 via a connection lead 200, and each first input signal sub-pad 411 in the control region column 510 is connected to the corresponding first input signal lead 331 via a connection lead 200.

[0108] Thus, in the light-emitting substrate, two control area columns 510 are respectively provided with corresponding second power supply voltage leads 320 and first input signal leads 331 ; at the same time, the two control area columns 510 in the same signal channel area 500 share the same first power supply voltage lead 310 .

[0109] Alternatively, see Figure 1 and Figure 2 In any signal channel region 500, the microchip drive lead 330 further includes a second input signal lead 332; see Figure 6 , the first pad group 410 further includes a second input signal sub-pad 412; the second input signal lead 332 is used to load the second input signal Di to at least one second input signal sub-pad 412. Figure 5 The microchip 600, which is used to be bonded to the first pad group 410, may further include a second input signal pin 620 for bonding to the second input signal sub-pad 412. In this way, the microchip 600 can receive the second input signal Di through the second input signal pin 620. Alternatively, the second input signal Di can be an address signal, or a selection signal that turns on the first input signal pin 610 to receive the first input signal Pwr.

[0110] In the present disclosure, each first pad group 410 within a signal channel region 500 is connected to the same second input signal lead 332. In other words, a signal channel region 500 is composed of each control region A corresponding to each first pad group 410 that is directly or indirectly connected to the same second input signal lead 332. When a second input signal lead 332 is used to directly or indirectly drive multiple control region columns, these multiple control region columns constitute a signal channel region 500. Exemplarily, when a signal channel region 500 includes two control region columns 510, these two control region columns 510 share the same second input signal lead 332. Furthermore, exemplarily, when a signal channel region 500 includes three or more control region columns 510, these three or more control region columns 510 share the same second input signal lead 332.

[0111] Referring to Figure 5 , the microchip 600 has a first input signal pin 610, a first power voltage pin 630, an output pin 640 and a second input signal pin 620. The first power voltage pin 630 is used to provide the first power voltage V G , the first input signal pin 610 is used to provide the first input signal Pwr to the microchip 600, and the second input signal pin 620 is used to provide the second input signal Di to the microchip 600. The microchip 600 can be configured to output a relay signal through the output pin 640 in a first time period and output a driving signal for driving the light emitting element 700 to emit light through the output pin 640 in a second time period according to the first input signal Pwr loaded on the first input signal pin 610 and the second input signal Di loaded on the second input signal pin 620. The relay signal is an address signal or a strobe signal. When the second input pin of a microchip 600 is loaded with the relay signal, the microchip 600 can receive the first input signal Pwr through the first input pin. The first input signal Pwr is a power line carrier communication signal, which can provide a driving voltage and a communication signal to the microchip at the same time.

[0112] Optionally, in any one signal channel region 500, the second input signal lead 332 is located between the first input signal lead 331 and the second power voltage lead 320.

[0113] Optionally, each second input signal sub-pad 412 and each output sub-pad 414 are located in the same metal wiring layer. In an embodiment of the present disclosure, each second input signal sub-pad 412 and each output sub-pad 414 are located in the second metal wiring layer 150.

[0114] In an embodiment of the present disclosure, referring to Figure 1 and Figure 6 , in any one signal channel region 500, P first pad groups 410 numbered in a preset order are included; the second input signal sub-pad 412 of the first pad group 410 numbered 1 is connected with the second input signal lead 332 through the connection lead 200, and the output sub-pad 414 of the first pad group 410 numbered p is electrically connected with the second input signal sub-pad 412 of the first pad group 410 numbered (p+1) through the connection lead 200, where 0

[0115] When the second input signal pin of the first microchip 600 is loaded with the second input signal Di, the first input signal pin of the first microchip 600 can receive the first input signal Pwr loaded thereon; then, according to the first input signal Pwr and the second input signal Di, the first microchip 600 outputs a relay signal in the subsequent first time period and outputs a driving light signal for driving the light emitting element 700 to emit light in the second time period. The microchip 600 numbered (p+1) can receive the first input signal Pwr loaded on the first input signal pin after receiving the relay signal output by the microchip 600 numbered p through the second input signal pin; then, the microchip 600 numbered (p+1) outputs a relay signal in the subsequent first time period and outputs a driving light signal for driving the light emitting element 700 to emit light in the second time period. In this way, each microchip 600 in a signal channel area 500 is cascaded in turn, and each light emitting element 700 in the corresponding control area A is driven to emit light.

[0116] Optionally, the array substrate is provided with a binding area B. In any one signal channel area 500, 2M control area columns are included, and each control area column 510 includes N control areas A, M and N are positive integers, and P=2M*N. The first pad group 410 numbered 1 is the one closest to or farthest from the binding area B in the signal channel area 500; and the P first pad groups 410 can be numbered in turn in a Z-shaped manner row by row and column by column, or in an S-shaped manner row by row and column by column, or in an N-shaped manner column by row, or in a U-shaped or inverted U-shaped manner column by row. In the present disclosure, the row direction is the direction along the second direction or the opposite direction thereof, and the column direction is the direction along the first direction or the opposite direction thereof.

[0117] For example, within any signal channel region 500, there are 2M control region columns, and each control region column 510 includes N control regions A, where M and N are both positive integers, and P = 2M*N. Taking M = 1 as an example, within a signal channel region 500, the first pad group 410B(1, i) is the first pad group 410 in the control region A of the i-th row in the first control region column 510, that is, the first pad group 410 numbered 2i-1. The first pad group 410B(2, i) is the first pad group 410 in the i-th row of the control region A in the second control region column 510, that is, the first pad group 410 numbered 2i; the first pad group 410B(1, i+1) is the first pad group 410 in the i+1-th row of the control region A in the first control region column 510, that is, the first pad group 410 numbered 2i+1; i is a positive integer and less than N; the first pad group 410B(1, 1) is the first pad group 410 in the i+1-th row of the control region A in the first control region column 510, that is, the first pad group 410 numbered 2i+1; 510, that is, the first pad group 410 numbered 1; the first pad group 410B(1, N) is the first pad group 410 of the control area A in the Nth row in the first control area column 510, that is, the first pad group 410 numbered P-1; the first pad group 410B(2, N) is the first pad group 410 of the control area A in the Nth row in the second control area column 510, that is, the first pad group 410 numbered P.

[0118] In any signal channel area 500, the second input signal sub-pad 412 of the first pad group 410B(1, 1) is connected to the second input signal lead 332 through the connecting lead 200; the output sub-pad 414 of the first pad group 410B(1, i) is connected to the second input signal sub-pad 412 of the first pad group 410B(2, i) through the connecting lead 200; the output sub-pad 414 of the first pad group 410B(2, i) is connected to the second input signal sub-pad 412 of the first pad group 410B(1, i+1) through the connecting lead 200; the output sub-pad 414 of the first pad group 410B(1, N) is connected to the second input signal sub-pad 412 of the first pad group 410B(2, N) through the connecting lead 200.

[0119] Thus, within a signal channel region 500, the array substrate includes 2N first pad groups 410 connected in series. Correspondingly, within a signal channel region 500, the light-emitting substrate includes 2N microchips 600 connected in series, with the output pin 640 of the previous microchip 600 electrically connected to the second input pin of the next microchip 600 via the connecting wire 200.

[0120] Alternatively, see Figures 9-11 and Figure 13The array substrate further includes a bonding area B, and each bonding pad 430 connected with each driving lead 300 is arranged in the bonding area B. The control area A farthest from the bonding area B in any one control area column 510 is the first control area A in the control area column 510. In other words, in the light-emitting substrate, among the plurality of microchips 600 cascaded in one signal channel area 500, the first-level microchip 600 is located at one end of the signal channel area 500 far from the bonding pad 430, and the last-level microchip 600 is located at one end of the signal channel area 500 close to the bonding pad 430.

[0121] In some embodiments, the first pad group 410 can include a plurality of sub-pads. Each first pad group 410 can be arranged close to the first power voltage lead 310, such that the orthographic projection of each sub-pad of the first pad group 410 on the substrate substrate 110 does not overlap with the orthographic projection of the second power voltage lead 320 on the substrate substrate 110. In an embodiment of the present disclosure, part of the first pad group 410 can partially overlap with the first power voltage lead 310. That is, referring to FIG. 4, in the first row of the first pad group 410 (blocked by the microchip 600), the orthographic projection of each first pad group 410 on the substrate substrate 110 is partially located in the orthographic projection of the first power voltage lead 310 on the substrate substrate 110. Figure 8 In another embodiment of the present disclosure, part of the first pad group 410 can not overlap with the first power voltage lead 310. That is, referring to FIG. 4, in the second row of the first pad group 410 (blocked by the microchip 600), the orthographic projection of each first pad group 410 on the substrate substrate 110 is completely located out of the orthographic projection of the first power voltage lead 310 on the substrate substrate 110. Figure 8 In another embodiment of the present disclosure, part of the first pad group 410 can not overlap with the first power voltage lead 310. That is, referring to FIG. 4, in the second row of the first pad group 410 (blocked by the microchip 600), the orthographic projection of each first pad group 410 on the substrate substrate 110 is completely located out of the orthographic projection of the first power voltage lead 310 on the substrate substrate 110. Figure 9 , Figure 9 Three rows of microchips 600 are shown in FIG. 4, and one first pad group 410 is arranged below each microchip 600. In the second row of the first pad group 410 (blocked by the microchip 600), the orthographic projection of each first pad group 410 on the substrate substrate 110 is completely located in the orthographic projection of the first power voltage lead 310 on the substrate substrate 110.

[0122] In the embodiments of the present disclosure, each first pad group 410 can be positioned away from the second power supply voltage lead 320, thereby preventing voltage fluctuations caused by current fluctuations in the second power supply voltage lead 320 from interfering with the microchip and improving the stability of the electromagnetic environment in which the microchip operates. Accordingly, the first pad group 410 is positioned as close as possible to the first power supply voltage lead 310 or completely within the first power supply voltage lead 310. Due to the low resistance of the first power supply voltage lead 310 of the present disclosure, voltage disturbances caused by current fluctuations thereon are very small. This allows the first power supply voltage lead 310 to not only provide a stable first power supply voltage to the microchip, but also stabilize the electromagnetic environment surrounding the first power supply voltage lead 310, thereby reducing electromagnetic interference to the microchip.

[0123] Optionally, in a light-emitting substrate based on the array substrate, in the same control area column 510, each microchip 600 can be arranged along the first direction D, or partially arranged along the first direction D and the rest arranged in a dispersed manner, whichever is more suitable for achieving the required electrical connection. Figure 11 In a control area column 510 , except for the microchip 600 that is second closest to the binding area B, the other microchips 600 are arranged in a straight line along the first direction D; the microchip 600 that is second closest to the binding area B can deviate from the straight line where the other microchips 600 are located to avoid the connecting lead 200.

[0124] See also Figure 9 and Figure 13 The binding region B may be disposed near an edge of the array substrate and may be provided with at least one row of binding pads 430. Furthermore, within the same row of binding pads 430, the binding pads 430 may be arranged along the second direction E. In one embodiment of the present disclosure, the binding pads 430 are arranged in a row along the second direction E and are provided in a one-to-one correspondence with the driving leads 300.

[0125] For example, see Figure 9 and Figure 13 A row of binding pads 430 may be provided in the binding area B, and the row of binding pads 430 includes a first power supply voltage binding pad 431 for connecting to the first power supply voltage lead 310, a second power supply voltage binding pad 432 for connecting to the second power supply voltage lead 320, a first input signal binding pad 433 for connecting to the first input signal lead 331, and a second input signal binding pad 434 for connecting to the second input signal lead 332.

[0126] Alternatively, see Figure 9 and Figure 13The array substrate further includes a plurality of fan-out leads 440 , each fan-out lead 440 is arranged in one-to-one correspondence with each binding pad 430 , and the binding pad 430 is connected to the corresponding driving lead 300 through the corresponding fan-out lead 440 .

[0127] For example, see Figure 9 and Figure 13 The fan-out lead 440 includes a first power supply voltage fan-out lead 441 connecting the first power supply voltage lead 310 and the first power supply voltage binding pad 431, a second power supply voltage fan-out lead 442 connecting the second power supply voltage lead 320 and the second power supply voltage binding pad 432, a first input signal fan-out lead 443 connecting the first input signal lead 331 and the first input signal binding pad 433, and a second input signal fan-out lead 444 connecting the second input signal lead 332 and the second input signal binding pad 434.

[0128] Alternatively, see Figure 9 and Figure 13 The bonding area B is further provided with a floating bonding pad 435, and the floating bonding pad 435 is connected to the last level first bonding pad group 410 ( Figure 9 The fan-out leads 440 are connected to the output sub-pads 414 of the first pad group 410 (obscured by the microchip 600). Furthermore, the fan-out leads 440 include floating fan-out leads 445 for connecting the output sub-pads 414 of the last-stage first pad group 410 and the floating bonding pads 435. For example, the floating bonding pads 435 are connected to the output sub-pads 414 of the first pad group 410B(2,N). This enables loop feedback of the signal on the second input signal lead, facilitating testing and debugging of the array substrate.

[0129] Alternatively, see Figure 9 and Figure 10 In any signal channel region 500, along the second direction E, the second input signal lead 332 is located between the first second power supply voltage lead 320 and the first first input signal lead 331; the distance d1 between the first second power supply voltage lead 320 and the first first input signal lead 331 is equal to the distance d2 between the second second power supply voltage lead 320 and the second first input signal lead 331. Thus, see Figure 14 A blank area F is reserved between the second second power supply voltage lead 320 and the second first input signal lead 331, which can reduce the metal area ratio of the first metal wiring layer 130 on the array substrate and avoid the metal area ratio of the first metal wiring layer 130 being too large to affect the subsequent process of the array substrate.

[0130] Optionally, each bonding pad 430 can be divided into at least one bonding pad group corresponding to at least one signal channel region 500. Any bonding pad group includes multiple bonding pads 430 connected to multiple driving leads 300 in a signal channel in a one-to-one correspondence. In other words, at least one bonding pad group corresponding to at least one signal channel region 500 is provided in the bonding area B; each bonding pad 430 in a bonding pad group corresponds to each driving lead 300 in the corresponding signal channel region 500.

[0131] Further, optionally, the arrangement order of the plurality of driving leads 300 in any signal channel region 500 along the direction perpendicular to the first direction D is the same as the arrangement order of the plurality of bonding pads 430 corresponding to the plurality of driving leads 300 in the same direction. In this way, the fan-out leads 440 corresponding to the bonding pads 430 can also be arranged in the same order, and the connection can be completed without crossover wires.

[0132] Optionally, each bonding pad 430 , each fan-out lead 440 and each driving lead 300 are located in the same metal wiring layer, for example, all are located in the first metal wiring layer 130 .

[0133] Alternatively, see Figure 10 and Figure 13 , the two second power supply voltage binding pads 432 corresponding to the two adjacent second power supply voltage leads 320 in the two adjacent signal channel areas 500 are connected to each other as a whole. Furthermore, the two fan-out leads 440 connected to the two adjacent second power supply voltage binding pads 432 can also be connected to each other as a whole. In this way, it is equivalent to that the two adjacent second power supply voltage leads 320 are connected to the same second power supply voltage binding pad 432 through the same fan-out lead 440. Furthermore, the width of the second power supply voltage binding pad 432 connected to two second power supply voltage leads 320 can be twice the width of the second power supply voltage binding pad 432 connected to one second power supply voltage lead 320. Among them, the width of the binding pad 430 refers to its size in the second direction E.

[0134] Optionally, the width of each bonding pad 430 may be different depending on the connected driving lead 300. Figure 13 , the first power supply voltage bonding pad 431 has a large width to ensure that the loaded first power supply voltage V G The second power supply voltage bonding pad 432 may also have a large width to ensure that the loaded second power supply voltage V LEDWith small disturbance. The first input signal binding pad 433 and the second input signal binding pad 434 may have a smaller width so as to reduce the overall width of the binding area B and facilitate the connection between the array substrate and the circuit board. The circuit board may be a flexible circuit board or a chip on film (COF). Furthermore, the width of the first input signal binding pad 433 may not be less than that of the second input signal binding pad 434 to ensure that the first input signal binding pad 433 can more effectively load the power line carrier communication signal, so that the first input signal Pwr can provide the chip power supply voltage for driving the microchip 600, and can provide a communication signal for controlling the light-emitting element 700 to emit light.

[0135] In one embodiment of the present disclosure, the width of the second power supply voltage bonding pad 432 connected to the second power supply voltage lead 320 for driving a control region column 510 may be approximately half the width of the first power supply voltage bonding pad 431 connected to the first power supply voltage lead 310 for driving a signal channel region 500. In the present disclosure, "approximately" refers to an acceptable fluctuation or adjustment within a range of 10% for variables such as size, number, and thickness.

[0136] In another embodiment of the present disclosure, the width of the second power supply voltage binding pad 432 commonly connected to two adjacent second power supply voltage leads 320 can be approximately the width of the first power supply voltage binding pad 431 connected to the first power supply voltage lead 310 used to drive a signal channel area 500.

[0137] In one embodiment of the present disclosure, the width of the first input signal bonding pad 433 is the same as that of the second input signal bonding pad 434 .

[0138] Optionally, the bonding pad 430 may be one or more bonding electrodes 4301 connected to the same fan-out lead 440. The width of the bonding pad 430 is the total size occupied by the individual bonding electrodes 4301 in the second direction E. The greater the number of bonding electrodes 4301 in the bonding pad 430, the greater the width of the bonding pad 430. Of course, in other embodiments, the multiple bonding electrodes 4301 in the bonding pad 430 connected to the same fan-out lead 440 can be formed into an integrated structure in subsequent processes.

[0139] In one embodiment of the present disclosure, see Figure 13 Each bonding pad 430 may be composed of one or more bonding electrodes 4301, and there may be gaps between the bonding electrodes 4301. The number of bonding electrodes 4301 included in each bonding pad 430 may be adjusted to determine the width of each bonding pad 430.

[0140] For example, seeFigure 13 In the binding area B, a plurality of binding electrodes 4301 can be arranged at equal intervals along the second direction E; one binding electrode 4301 or a plurality of adjacent binding electrodes 4301 can form one binding pad 430, and there is no multiplexing binding electrode 4301 between each binding pad 430.

[0141] The first power voltage binding pad 431 can include a plurality of sequentially adjacent binding electrodes 4301, for example, can include 20-30 sequentially adjacent binding electrodes 4301. Exemplarily, the first power voltage binding pad 431 can include 26 sequentially adjacent binding electrodes 4301.

[0142] The second power voltage binding pad 432 can include a plurality of sequentially adjacent binding electrodes 4301, for example, can include 10-15 sequentially adjacent binding electrodes 4301. Exemplarily, the second power voltage binding pad 432 can include 13 sequentially adjacent binding electrodes 4301. Further, two second power voltage binding pads 432 connected with two adjacent second power voltage leads 320 can be connected as one second power voltage binding pad 432, and the binding pad 430 for driving two second power voltage leads 320 can have 20-30 sequentially adjacent binding electrodes 4301, for example, include 26 sequentially adjacent binding electrodes 4301.

[0143] The first input binding pad 430, the second input binding pad 430 and the floating binding pad 435 can each include 1-3 binding electrodes 4301, for example, can each include 1 binding electrode 4301.

[0144] Further, referring to Figure 13 , there is no other binding electrode 4301 between the two adjacent second input binding pads 430. The dummy electrode 436 not coupled with any structure on the array substrate can be arranged between the adjacent second power voltage binding pad 432 and the first input binding pad 430, between the adjacent first power voltage binding pad 431 and the second input binding pad 430, and between the adjacent first power voltage binding pad 431 and the floating binding pad 435, so as to facilitate the connection of the array substrate and the circuit board.

[0145] Optionally, referring to Figure 10 and Figure 13The fan-out lead 440 includes a first straight segment connected to the drive lead 300, a second straight segment connected to the first bonding pad 430, and an oblique segment connecting the first and second straight segments. The width of the first straight segment can be the same as the width of the drive lead 300 to which it is connected; the width of the second straight segment can be no less than the width of the bonding pad 430 to which it is connected. As it extends from the end connected to the first straight segment to the end connected to the second straight segment, the width of the oblique segment uniformly transitions from the width of the first straight segment to the width of the second straight segment to which it is connected. The first and second straight segments both extend in a first direction D, and the oblique segment extends in an acute angle with the direction of extension of the drive lead 300. The widths of the first, second, and oblique segments are their respective dimensions in a second direction E. Furthermore, the width of the drive lead 300 is greater than the width of the bonding pad 430 to which it is connected, such that the width of the oblique segment gradually decreases toward the bonding area B.

[0146] For example, see Figure 13 The width of the second straight segment of the first power supply voltage fan-out lead 441 is equal to the width of the first power supply voltage bonding pad 431; the width of the second straight segment of the second power supply voltage fan-out lead 442 is equal to the width of the second power supply voltage bonding pad 432; the width of the second straight segment of the second input signal fan-out lead 444 is equal to the width of the second input signal bonding pad 434; and the width of the second straight segment of the floating fan-out lead 445 is equal to the width of the floating bonding pad 435. The width of the second straight segment of the first input signal fan-out lead 443 at the end away from the first input signal bonding pad 433 is greater than the width at the end closer to the first input signal bonding pad 433.

[0147] As an example, see Figure 12 The array substrate includes a base substrate 110, a buffer layer 120, a first metal wiring layer 130, a first passivation layer 141, a planarization organic material layer 142, a second metal wiring layer 150, a second passivation layer 160, and an insulating protection layer 170, which are stacked in sequence. The first passivation layer 141 and the planarization organic material layer 142 form the insulating material layer 140 of the array substrate of the present disclosure.

[0148] The base substrate 110 may be a glass substrate. The buffer layer 120 may be made of an inorganic dielectric material, such as silicon nitride, silicon oxide, or silicon oxynitride, to eliminate stress from subsequent film layers on the glass substrate. In one embodiment of the present disclosure, the buffer layer 120 may be made of silicon nitride.

[0149] From a hierarchical structure perspective, the first metal wiring layer 130 may include a copper seed layer 131 and a copper growth layer 132 sequentially stacked on one side of the base substrate 110. In some embodiments, the copper growth layer 132 may be disposed on a surface of the copper seed layer 131 away from the base substrate, and at least a portion of the side surface of the copper seed layer 131 may be exposed. For example, the orthographic projections of the copper seed layer 131 and the copper growth layer 132 on the base substrate 110 may substantially overlap. In other embodiments, such as Figure 12 As shown, the copper growth layer 132 may completely cover the side surfaces of the copper seed layer 131 and the surface thereof away from the substrate.

[0150] The copper seed layer 131 may be formed by magnetron sputtering, and the copper growth layer 132 may be formed by electroplating or chemical plating. Optionally, the copper seed layer 131 may include a first metal adhesion layer and a first copper metal layer stacked sequentially on one side of the base substrate 110. The first metal adhesion layer may enhance the bonding between the first copper metal layer and the buffer layer 120. The material of the first metal adhesion layer may be an alloy containing molybdenum, such as a molybdenum-niobium alloy or a molybdenum-niobium-copper alloy. Optionally, the first metal wiring layer 130 may further include a first metal protective layer located on the side of the copper growth layer 132 away from the base substrate 110. The first metal protective layer may be an alloy containing nickel, such as a copper-nickel alloy. In terms of pattern and function, the first metal wiring layer 130 may include the array substrate's drive leads 300 and fan-out leads 440. In one embodiment of the present disclosure, the first metal wiring layer 130 may also include bonding pads 430.

[0151] The first passivation layer 141 and the second passivation layer 160 may be made of an inorganic dielectric material, such as silicon nitride, silicon oxide, or silicon oxynitride. In one embodiment of the present disclosure, the first passivation layer 141 and the second passivation layer 160 may be made of silicon nitride.

[0152] The material of the planarization organic material layer 142 may be an organic material, such as polyimide, epoxy resin, phenolic resin or other organic materials. In one embodiment of the present disclosure, the planarization organic material layer 142 may be an organic material containing a photosensitizer.

[0153] Vias may be provided on the first passivation layer 141 and the planarized organic material layer 142 to expose at least a portion of the first metal wiring layer 130, so that the second metal wiring layer 150 can be connected to the first metal wiring layer 130 through the vias. For example, a portion of the connection lead 200 can be connected to the driving lead 300 through the vias.

[0154] In one embodiment of the present disclosure, the bonding pad 430 is located on the first metal wiring layer 130, and the first passivation layer 141 and the planarized organic material layer 142 may also expose at least a portion of the bonding pad 430 to facilitate connection of the bonding pad 430 to the circuit board. In another embodiment of the present disclosure, the bonding pad 430 is located on the second metal wiring layer 150, and the first passivation layer 141 and the planarized organic material layer 142 may expose at least a portion of the fan-out lead 440 to ensure that the bonding pad 430 can be connected to the fan-out lead 440 through a via.

[0155] The second metal wiring layer 150 may include a second metal adhesion layer and a second copper metal layer stacked in sequence. The second metal adhesion layer is used to enhance the bonding between the second copper metal layer and the planarized organic material layer 142. The second metal adhesion layer may be made of an alloy containing molybdenum, such as a molybdenum-niobium alloy or a molybdenum-niobium-copper alloy. Furthermore, the second metal wiring layer 150 may also include a second metal protective layer located on the side of the second copper metal layer away from the base substrate 110 to prevent surface oxidation of the second copper metal layer and to enhance the bonding between the light-emitting element 700 and the microchip 600 and the second metal wiring layer 150. The second metal protective layer may be made of an alloy containing nickel, such as a copper-nickel alloy or a copper-titanium alloy. In terms of pattern and function, the second metal wiring layer 150 may include the first pad group 410 and the second pad group 420 of the array substrate, as well as the connecting leads 200. In one embodiment of the present disclosure, the second metal wiring layer 150 may further include a bonding pad 430; further, the surface of the bonding pad 430 may further be provided with a conductive metal oxide, such as indium tin oxide (ITO), to prevent the surface of the bonding pad 430 from being oxidized.

[0156] The material of the insulating protective layer 170 may include an organic insulating material, for example, a resin material. Optionally, the insulating protective layer 170 may also contain an inorganic material, for example, inorganic particles dispersed in a resin. Exemplarily, the insulating protective layer 170 may be an organic-inorganic composite layer formed by cross-linking and curing an acrylic monomer in which nano-titanium oxide particles are dispersed. The insulating protective layer 170 and the second passivation layer 160 may have vias that expose the various sub-pads of the first pad group 410 and the various sub-pads of the second pad group 420, so as to bind and connect the light-emitting element 700 and the microchip 600 on the array substrate.

[0157] Exemplarily, the array substrate may be prepared using the following method shown in steps S110 to S160:

[0158] In step S110, a base substrate 110 is provided. The base substrate 110 may be a glass substrate.

[0159] Step S120: forming a buffer layer 120 on one side of the base substrate 110. Optionally, the buffer layer 120 may be formed by a deposition method.

[0160] In step S130, a first metal wiring layer 130 is formed on a side of the buffer layer 120 away from the base substrate 110. The first metal wiring layer 130 can be prepared by various methods.

[0161] By way of example, in one embodiment of the present disclosure, an unpatterned copper seed layer 131 covering the base substrate 110 may be formed first, copper may then be deposited using copper electroplating to form an unpatterned copper growth layer 132, and finally the patterned copper seed layer 131 and the unpatterned copper growth layer 132 may be patterned to obtain the first metal wiring layer 130. By way of example, in another embodiment of the present disclosure, a patterned copper seed layer 131 may be formed first, a pattern defining layer covering the base substrate 110 and exposing the copper seed layer 131 may be formed, and a patterned copper growth layer 132 may then be formed on the patterned copper seed layer 131 using copper electroplating to obtain the first metal wiring layer 130, and the pattern defining layer may then be removed. As another example, in another embodiment of the present disclosure, an unpatterned copper seed layer 131 covering the base substrate 110 can be first formed, and then a pattern defining layer can be formed on the side of the copper seed layer 131 away from the base substrate 110, and the pattern defining layer only exposes the position where the copper growth layer 132 needs to be formed; then, a patterned copper growth layer 132 is formed on the unpatterned copper seed layer 131 by copper electroplating, and after removing the pattern defining layer, the unpatterned copper seed layer 131 is patterned to obtain the first metal wiring layer 130.

[0162] In step S140, a first passivation material layer and a planarization organic material layer 142 are sequentially formed on a side of the first metal wiring layer 130 away from the base substrate 110. The planarization organic material layer 142 has a via hole. The first passivation material layer is etched using the planarization organic material layer 142 as a mask, so that the via hole penetrates the first passivation material layer and exposes a portion of the first metal wiring layer 130. The first passivation material layer is patterned into a first passivation layer 141.

[0163] In step S150 , a second metal wiring layer 150 is formed on a side of the planarized organic material layer 142 away from the base substrate 110 .

[0164] In step S160, a second passivation material layer and an insulating protective layer 170 are sequentially formed on a side of the second metal wiring layer 150 away from the base substrate 110. The insulating protective layer 170 has a via hole. The second passivation material layer is etched using the insulating protective layer 170 as a mask, so that the via hole penetrates the second passivation material layer and exposes a portion of the second metal wiring layer 150. The second passivation material layer is patterned to form the second passivation layer 160.

[0165] It should be noted that although the steps of the method of the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additional or alternative steps, such as omitting certain steps, combining multiple steps into one step, and / or decomposing a step into multiple steps, should all be considered part of this disclosure.

[0166] Optionally, multiple different array substrates can be spliced ​​together to form a larger spliced ​​array substrate. In particular, after the array substrate is bound with the microchip 600 and the light-emitting element 700 to form a light-emitting substrate, multiple light-emitting substrates can be spliced ​​together to form a larger light-emitting substrate.

[0167] For example, in one embodiment of the present disclosure, the array substrate may be a 50-100 inch array substrate, for example, a 65-inch or 75-inch array substrate. Furthermore, for example, in another embodiment of the present disclosure, the array substrate may be a 10-50 inch array substrate, and multiple array substrates may be spliced ​​together to form a large-sized spliced ​​array substrate, for example, a 65-inch array substrate or a 75-inch array substrate.

[0168] The present disclosure also provides a light-emitting substrate, comprising any of the array substrates described in the above array substrate embodiments, and including microchips bound and connected to each of the first pad groups 410 in a one-to-one correspondence, and light-emitting elements bound and connected to each of the first pad groups 410 in a one-to-one correspondence. The light-emitting substrate can be a MicroLED light-emitting substrate, a MiniLED light-emitting substrate, or other types of light-emitting substrates. Since the light-emitting substrate comprises any of the array substrates described in the above array substrate embodiments, it has the same beneficial effects, and the present disclosure will not elaborate on them here.

[0169] The present disclosure also provides a display device comprising any of the light-emitting substrates described in the aforementioned light-emitting substrate embodiments. The display device can be a television, a computer screen, a mobile phone screen, or another type of display device. Because the display device comprises any of the light-emitting substrates described in the aforementioned light-emitting substrate embodiments, it exhibits the same beneficial effects, and the present disclosure will not elaborate further here.

[0170] In one embodiment of the present disclosure, a display device includes a direct backlight source and a liquid crystal display panel, wherein the direct backlight source includes the light-emitting substrate provided by the present disclosure.

[0171] It should be understood that the present disclosure is not limited in its application to the detailed structure and arrangement of the components set forth in this specification. The present disclosure is capable of other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or evident in the text and / or the drawings. All of these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments of this specification illustrate the best mode known for implementing the present disclosure and will enable those skilled in the art to utilize the present disclosure.

Claims

1. An array substrate comprising at least one signal channel region extending along a first direction and a plurality of driving leads extending along the first direction; the driving leads comprising a first power supply voltage lead and a second power supply voltage lead; Any one of the signal channel regions includes at least two control region columns extending along the first direction, and any one of the control region columns includes a plurality of control regions arranged along the first direction; Any one of the control areas includes at least one pad connection circuit and a first pad group for binding a microchip, the first pad group being electrically connected to the first power supply voltage lead; any one of the pad connection circuits includes a plurality of second pad groups connected in sequence, the second pad group consisting of a first sub-pad and a second sub-pad; wherein, The first sub-pad of the first second pad group is electrically connected to the second power supply voltage lead through a connecting lead, the second sub-pad of the last second pad group is electrically connected to the first pad group through a connecting lead, and the second sub-pad of the previous second pad group is electrically connected to the first sub-pad of the next second pad group through a connecting lead; Wherein, in the at least one signal channel region, each of the first pad groups in at least two control region columns is electrically connected to the same first power supply voltage lead; The array substrate comprises a base substrate, a first metal wiring layer, an insulating material layer, and a second metal wiring layer stacked in sequence, wherein the driving lead is located in the first metal wiring layer, and the connecting lead, the first pad group, and the second pad group are located in the second metal wiring layer; the second metal wiring is electrically connected to the first metal wiring layer through a via located in the insulating material layer; In a control area that is not close to the binding area of ​​the array substrate, the orthographic projections of part of the second pad group on the base substrate are located in the orthographic projections of the first power supply voltage lead on the base substrate, and the orthographic projections of the remaining second pad group on the base substrate are located in the orthographic projections of the second power supply voltage lead on the base substrate.

2. The array substrate according to claim 1, wherein: Any one of the signal channel areas includes two control area columns; in any one of the signal channel areas, the number of the first power supply voltage lead is one, the number of the second power supply voltage lead is two and they are respectively located on both sides of the first power supply voltage lead; In any one of the signal channel regions, each of the first pad groups is electrically connected to the first power supply voltage lead, and the second end of each of the pad connection circuits is electrically connected to the second power supply voltage lead.

3. The array substrate according to claim 2, wherein: In two adjacent signal channel regions, two adjacent second power supply voltage leads are electrically connected to each other.

4. The array substrate according to claim 3, wherein: The array substrate further includes a plurality of conductive connection portions, and two adjacent second power supply voltage leads are connected via the plurality of conductive connection portions.

5. The array substrate according to claim 2, wherein: The driving leads also include at least one microchip driving lead connected to the first pad group and used to drive the microchip. In any one of the signal channel areas, the microchip driving lead is located between the first power supply voltage lead and the second power supply voltage lead.

6. The array substrate according to claim 5, wherein: Any one of the first pad groups includes a first input signal sub-pad for loading a first input signal, a first power supply voltage sub-pad for loading a first power supply voltage, and at least one output sub-pad for loading an output signal; In any one of the signal channel regions, the microchip drive leads include at least one first input signal lead located between the first power supply voltage lead and the second power supply voltage lead; The first input signal sub-pad is directly connected to the first input signal lead or is connected via the connecting lead; The first power supply voltage sub-pad is directly connected to the first power supply voltage lead or is connected via the connecting lead; In any one of the control areas, the at least one pad connection circuit and the at least one output sub-pad are arranged in a one-to-one correspondence, and a first end of any one of the pad connection circuits is connected to the corresponding output sub-pad through the connecting lead.

7. The array substrate according to claim 6, wherein: In any one of the signal channel areas, the number of the first input signal leads is two, and the leads are located on both sides of the first power supply voltage lead respectively.

8. The array substrate according to claim 7, wherein: The second direction is parallel to the plane where the array substrate is located and perpendicular to the first direction; In any one of the signal channel regions, along the second direction, the first control region column corresponds to the first second power supply voltage lead and the first first input signal lead, and the second control region column corresponds to the second second power supply voltage lead and the second first input signal lead; The second end of each of the pad connection circuits in the control area column is electrically connected to the corresponding second power supply voltage lead through the connecting lead, and each of the first input signal sub-pads in the control area column is connected to the corresponding first input signal lead through the connecting lead.

9. The array substrate according to claim 7, wherein: In any of the signal channel areas, the microchip drive lead further includes a second input signal lead, and the first pad group further includes a second input signal sub-pad; the second input signal lead is used to load a second input signal to at least one of the second input signal sub-pads.

10. The array substrate according to claim 9, wherein: In any one of the signal channel areas, the P first pad groups are numbered in sequence according to a preset order; wherein, the second input signal sub-pad of the first pad group numbered 1 is connected to the second input signal lead through the connecting lead, and the output sub-pad of the first pad group numbered p is electrically connected to the second input signal sub-pad of the first pad group numbered p+1 through the connecting lead, wherein p and P are both integers, and p takes a value within the range of greater than 1 and less than P.

11. The array substrate according to claim 9, wherein: In any one of the signal channel regions, the second input signal lead is located between the first input signal lead and the second power supply voltage lead.

12. The array substrate according to claim 11, wherein: The array substrate also includes a binding area, in which are provided various binding pads connected to the various driving leads; the first pad group farthest from the binding area or closest to the binding area in any one of the signal channel areas is the first pad group numbered 1 in the signal channel area.

13. The array substrate according to claim 12, wherein: The bonding area is provided with a floating bonding pad, and the floating bonding pad is connected to the output sub-pad of the first pad group numbered P in the signal channel area.

14. The array substrate according to claim 12, wherein: The second direction is parallel to the plane where the array substrate is located and perpendicular to the first direction; In any one of the signal channel regions, along the second direction, the second input signal lead is located between a first second power supply voltage lead and a second first input signal lead; The distance between a first one of the second power supply voltage leads and a second one of the first input signal leads is equal to the distance between a second one of the second power supply voltage leads and a second one of the first input signal leads.

15. The array substrate according to any one of claims 1 to 14, wherein: The array substrate also includes a binding area, in which at least one binding pad group corresponding one-to-one to the at least one signal channel area is provided; wherein any one of the binding pad groups includes a plurality of binding pads connected one-to-one to the plurality of driving leads in the corresponding signal channel area.

16. The array substrate according to claim 15, wherein: The arrangement order of the plurality of driving leads in any one of the signal channel regions along the first direction is the same as the arrangement order of the plurality of binding pads correspondingly connected to the plurality of driving leads in the same direction.

17. The array substrate according to claim 15, wherein: Any one of the bonding pad groups includes a second power supply voltage bonding pad for connecting to the second power supply voltage lead; Wherein, the two second power supply voltage binding pads corresponding to the two adjacent second power supply voltage leads in the two adjacent signal channel areas are connected to each other as a whole.

18. The array substrate according to claim 15, wherein: The bonding pad group is located in the first metal wiring layer.

19. A light-emitting substrate, comprising the array substrate according to any one of claims 1 to 18, and comprising a microchip bound and connected to each of the first pad groups in a one-to-one correspondence, and a light-emitting element bound and connected to each of the first pad groups in a one-to-one correspondence.

20. A display device comprising the light-emitting substrate according to claim 19.

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