floating point operation unit

Abstract

The present application provides a floating point operation unit, comprising: in-memory computing circuitry configured to perform a logical operation on input data and / or stored data to form a first computation result, wherein the input data and the stored data represent floating point numbers; and floating point computing circuitry configured to perform a floating point operation on the input data and / or the first computation result to form a second computation result.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a floating-point arithmetic unit. Background Technology

[0002] Existing CMOS circuits have the following drawbacks: For a long time in the past, due to low computing power requirements, the traditional von Neumann architecture, which separates the storage and computing parts, has been the mainstream design. The development of artificial intelligence has made the communication cost between different modules significant. If the traditional von Neumann architecture is used, it will lead to the "memory wall", that is, the problem of high power consumption. In other words, the traditional architecture cannot limit the significant increase in power consumption.

[0003] In-memory computing (IMC) chips are chips that perform operations within or near memory. Due to their advantages such as lower power consumption and smaller chip area, IMC chips are attracting increasing attention from the industry. However, current in-memory computing circuits are complex to implement and have low precision. Summary of the Invention

[0004] The purpose of this invention is to provide a floating-point arithmetic unit to solve the problem of complex implementation of existing in-memory computing circuits.

[0005] The present invention also aims to provide a floating-point arithmetic unit to solve the problem of low precision in existing in-memory computing circuits.

[0006] To solve the above-mentioned technical problems, the present invention provides a floating-point arithmetic unit, comprising:

[0007] An in-memory computing circuit is configured to perform logical operations on input data and / or stored data to form a first calculation result, wherein the input data and stored data represent floating-point numbers; and

[0008] A floating-point calculation circuit is configured to perform floating-point operations on input data and / or a first calculation result to form a second calculation result.

[0009] Optionally, the floating-point arithmetic unit further includes:

[0010] The input module is configured to provide input data to in-memory computing circuitry and / or floating-point computing circuitry;

[0011] The output module is configured to output the first calculation result of the in-memory calculation circuit and / or the second calculation result of the floating-point calculation circuit.

[0012] Optionally, in the floating-point arithmetic unit, the input data and the stored data are processed by the calculation unit of the in-memory calculation circuit and then calculated by the subsequent floating-point calculation circuit.

[0013] The floating-point calculation circuit includes parallel floating-point multiplication operations; and

[0014] The logical operations include one or more of AND, OR, NOT, NAND, NOR, AND-OR-NOT, XOR, and XNOR.

[0015] Optionally, in the floating-point arithmetic unit, the floating-point number includes: a 1-bit sign bit, n bits of exponent bits, and m bits of mantissa bits to store a number in the format ±1.xx*2^x; and

[0016] Parallel floating-point multiplication operations include XORing the sign bit, adding the exponent bits, multiplying the mantissa bits, and normalizing the result based on the XORing of the sign bit, the addition of the exponent bits, and the multiplication of the mantissa bits.

[0017] Optionally, in the floating-point arithmetic unit, the in-memory computing circuit performs a one-to-one logical operation on each bit of the input data and each bit of the stored data, and performs an XOR operation on the sign bit of the two in each cycle, and an AND operation on the other bits.

[0018] The floating-point arithmetic circuit processes the input data and / or the calculation results of the in-memory arithmetic circuit in each cycle. It shifts and registers the exponent bits of the input data and / or the calculation results, shifts and adds the mantissa bits of the input data and / or the calculation results, normalizes them after a complete calculation cycle, and outputs the result of the floating-point multiplication.

[0019] Optionally, in the floating-point arithmetic unit, the calculation unit of the in-memory calculation circuit is configured to perform a sign bit XOR operation to replace the sign bit XOR operation in the floating-point multiplication operation of the floating-point calculation circuit.

[0020] Optionally, in the floating-point arithmetic unit,

[0021] The first floating-point number is stored in the in-memory calculation circuit, and the first part of the second floating-point number is input to the in-memory calculation circuit by the input module, and the second and third parts of the second floating-point number are input to the floating-point calculation circuit by the input module.

[0022] In each cycle, n bits of the second floating-point number are input. The first part of the second floating-point number undergoes logical operations with the first floating-point number within the computation unit of the in-memory computing circuit to obtain the first calculation result; the second and third parts of the second floating-point number are synchronously delayed; and

[0023] The first calculation result of the in-memory calculation circuit is stored in the floating-point arithmetic circuit, and normalized after each bit of the second floating-point number is processed to obtain the second calculation result.

[0024] Optionally, in the floating-point arithmetic unit, bf16 is divided into two 8-bit data, which facilitates storage and operation in the memory computing circuit.

[0025] The floating-point number fp16 is stored and operated on in 2x8 format;

[0026] Storing and performing operations on floating-point numbers (fp32) in 4x8 format; and

[0027] The first part of the second floating-point number is the sign bit, the second part is the exponent bit, and the third part is the mantissa bit.

[0028] Optionally, in the floating-point arithmetic unit, the floating-point calculation circuit includes:

[0029] The shift register is configured to shift and register the second part of the second floating-point number to obtain the first result;

[0030] A shift adder is configured to shift and add the third part of the second floating-point number to the calculation result to obtain a second result; and

[0031] The adder is configured to perform an AND operation on the first result, the second result, and the first calculation result to obtain the second calculation result, and the carry signal determines the corresponding normalization operation.

[0032] Optionally, in the floating-point arithmetic unit,

[0033] The lower bits of the second calculation result consist of the sign bit and the mantissa bit, while the higher bits of the second calculation result consist of the exponent bit.

[0034] In the 8 cycles, because the bf16 storage format in the in-memory calculation circuit is 2x8, 2 bits of input data are input per cycle for calculation, and after an interval of three calculation cycles, the data is output to the floating-point arithmetic circuit for processing; and

[0035] Due to the special nature of the mantissa, the least significant bit of the input data is set to a high level one cycle in advance as the 1 before the floating point;

[0036] For details on the special characteristics of the mantissa, please refer to the definition in the IEEE 754 standard. It refers to the number that it represents, which is a number formed by adding 1 before the mantissa. For example, if the mantissa is 01001, the corresponding number is 1.01001.

[0037] Optionally, in the floating-point arithmetic unit, the calculation unit of the in-memory arithmetic circuit includes:

[0038] The first MOSFET has its gate connected to the output signal of the memory cell allocated to the in-memory operation circuit, the first of its drain and source connected to a fixed level, and the second of its drain and source connected to the first of the drain and source of the second MOSFET.

[0039] The second MOSFET has its gate connected to the first input signal allocated to the in-memory operation circuit, and its drain and source, the second of the two, are connected to the output terminal.

[0040] The third MOSFET has its gate connected inverted to the output signal of the memory cell allocated to the in-memory arithmetic circuit; the first of its drain and source is connected to a fixed level; and the second of its drain and source is connected to the first of the drain and source of the fourth MOSFET.

[0041] The fourth MOSFET has its gate connected to the second input signal allocated to the in-memory operation circuit, and its drain and source, the second of which, are connected to the output.

[0042] The present invention also provides an in-memory computing circuit, including a floating-point arithmetic unit as described in any of the preceding claims.

[0043] The inventors of this invention discovered through research that the current mainstream in-memory computing circuits use circuits such as ADCs and DACs (analog-to-digital / digital-to-analog converters) to perform multiplication and addition operations on the data stored in RAM and the input data, which is essentially an accumulation algorithm. However, the disadvantage of this circuit structure is that the precision is too low; n RAMs can only achieve the precision of log2(n) bits of binary numbers.

[0044] In the floating-point arithmetic unit provided by this invention, the in-memory computing circuit performs logical operations on the input data and / or stored data to form a calculation result. The floating-point computing circuit performs floating-point operations on the input data and / or calculation result, using a floating-point format for calculation. While retaining the low-power advantage of in-memory computing circuits, the calculation accuracy is also increased. For example, using mainstream floating-point formats such as fp16 / bf16 / fp32 / fp64 for in-memory calculation can theoretically better meet the accuracy and computing power requirements of current AI chips.

[0045] This invention improves upon the use of in-memory computing circuits by reducing the dependence of most circuits on ADC / DAC and decreasing the required power consumption. In addition, as an alternative in-memory computing processor, it simultaneously performs floating-point number storage and high-parallel floating-point number multiplication operations within the circuit. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the overall floating-point arithmetic unit according to an embodiment of the present invention;

[0047] Figure 2 This is a schematic diagram of the specific structure of the in-memory calculation circuit and the floating-point calculation circuit of an embodiment of the present invention;

[0048] Figure 3 This is a schematic diagram of the format of the floating-point arithmetic unit BF16 according to an embodiment of the present invention;

[0049] Figure 4 This is a schematic diagram illustrating an example of multiplying two bf16 units in a floating-point arithmetic unit according to an embodiment of the present invention;

[0050] Figure 5 This is a schematic diagram of the overall timing of a floating-point arithmetic unit circuit according to an embodiment of the present invention. Detailed Implementation

[0051] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0052] It should be noted that the components in the various figures may be shown exaggeratedly for illustrative purposes and are not necessarily to scale. In each figure, the same reference numerals are used for components that are identical or have the same function.

[0053] In this invention, unless otherwise specified, "arranged on," "arranged above," and "arranged on" do not exclude the possibility of an intermediate element between them. Furthermore, "arranged on or above" merely indicates the relative positional relationship between two components, and in certain cases, such as when the product orientation is reversed, it can also be converted to "arranged below or under," and vice versa.

[0054] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0055] In this invention, unless otherwise specified, the quantifiers “a” and “one” do not exclude scenarios involving multiple elements.

[0056] It should also be noted that, in the embodiments of the present invention, only a portion of the components or parts may be shown for clarity and simplicity. However, those skilled in the art will understand that, under the teachings of the present invention, necessary components or parts can be added as needed for specific scenarios. Furthermore, unless otherwise stated, features in different embodiments of the present invention can be combined with each other. For example, a feature in the second embodiment can replace a corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment will also fall within the scope of disclosure or description of this application.

[0057] It should also be noted that, within the scope of this invention, the terms "same," "equal," and "equal to" do not imply that the two values ​​are absolutely equal, but rather allow for a certain reasonable margin of error. In other words, the terms also encompass "substantially the same," "substantially equal," and "substantially equal to." Similarly, in this invention, the directional terms "perpendicular to," "parallel to," etc., also encompass the meanings of "substantially perpendicular to" and "substantially parallel to."

[0058] Furthermore, the numbering of the steps in the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps may be executed in different orders.

[0059] The floating-point arithmetic unit proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0060] The purpose of this invention is to provide a floating-point arithmetic unit to solve the problem of complex implementation of existing in-memory computing circuits.

[0061] The present invention also aims to provide a floating-point arithmetic unit to solve the problem of low precision in existing in-memory computing circuits.

[0062] To achieve the above objectives, the present invention provides a floating-point arithmetic unit, comprising: an in-memory computing circuit configured to perform logical operations on input data and / or stored data to form a first calculation result, wherein the input data and stored data represent floating-point numbers; and a floating-point computing circuit configured to perform floating-point operations on the input data and / or the first calculation result to form a second calculation result.

[0063] In one embodiment of the present invention, the present invention improves the dependence of most circuits on ADC / DAC and reduces the required power consumption by using in-memory computing circuits; at the same time, it uses floating-point format for calculation, which increases the calculation accuracy while retaining the low power consumption advantage of in-memory computing circuits.

[0064] In one embodiment of the present invention, the present invention can use mainstream floating-point formats such as fp16 / bf16 / fp32 / fp64 for in-memory calculations, which theoretically can better meet the accuracy and computing power requirements of current AI chips. The overall circuit structure consists of an in-memory calculation circuit 20 and a floating-point calculation circuit 30, as follows: Figure 1 As shown. Furthermore, it also includes an input module 10 and an output module 40.

[0065] In one embodiment of the present invention, Figure 2The specific structure of the in-memory calculation circuit and the floating-point calculation circuit can be basically divided into two parts: input data is input from the left terminal IN, and the second calculation result is output from the right terminal. The specific circuit is roughly as follows: Figure 2 As shown, the input data and stored data are processed by the computation unit (LPU) of the in-memory computing circuit through NAND or XOR logic operations, and then processed by the subsequent floating-point computing unit to achieve high-parallel floating-point multiplication operations.

[0066] In one embodiment of the present invention, the implementation of floating-point arithmetic includes: floating-point numbers of various formats are mainly composed of three parts: 1 bit sign bit, n bits exponent bits, and m bits mantissa bits, to store numbers in the format ±1.xx*2^x. In the specific multiplication operation, the main operations are: XORing the sign bit, adding the exponent bits, multiplying the mantissa bits, and normalizing the result. Figure 3 It is a floating-point number in BF16 format, which has 8 bits for the exponent and 7 bits for the sign bit.

[0067] In one embodiment of the present invention, the in-memory arithmetic circuit mainly performs logical operations on each bit of data. Specifically, in each cycle, the sign bit is XORed, and the other bits are ANDed. The floating-point arithmetic circuit mainly processes the first calculation result of each cycle of the in-memory arithmetic circuit, including storing the exponent bit by bit, adding the mantissa bit by bit, normalizing after a certain number of cycles of operation, and then outputting the result of the floating-point multiplication. Taking bf16 as an example, a single multiplication calculation is as follows: Figure 4 As shown.

[0068] In one embodiment of the present invention, the specific implementation of the calculation by this circuit is as follows: a floating-point number (first floating-point number) is stored in the in-memory calculation circuit, and different parts of another floating-point number (second floating-point number) are input from the outside, n bits are fed in each cycle and logical operations are performed at the LPU to obtain the result of the in-memory calculation circuit; the result of the in-memory calculation circuit is stored in the floating-point operation circuit, and after each bit of the external floating-point number is operated, a final normalization is performed to obtain the second calculation result.

[0069] In one embodiment of the present invention, bf16 is divided into two 8-bit data, which facilitates storage and operation in the memory computing circuit; and for floating-point numbers such as fp16 and fp32, the same method can be used to store and operate in 2x8 / 4x8 format. Figure 2 In the floating-point arithmetic circuit, the sign bit XOR is directly implemented by the LPU in the in-memory computing circuit; the exponent bit addition is implemented by the shift register ShiftReg and the subsequent adder Add; and the mantissa bit multiplication is implemented by the shift adder Shift&Add, with the carry signal determining the corresponding normalization operation. The specific timing diagram of the BF16 computing circuit is as follows: Figure 5 As shown.

[0070] In one embodiment of the present invention, such as Figure 5 As shown in the overall timing diagram of the circuit, Out_L consists of the sign bit and mantissa bit of the second calculation result, and Out_R consists of the exponent bit of the second calculation result. In the 8 cycles, since the bf16 storage format in the in-memory calculation circuit is 2x8, 2 bits of data are input and calculated in each cycle. At the same time, the data is output to the floating-point operation circuit for processing after an interval of three calculation cycles. Due to the special nature of the mantissa, In_L needs to be set to high level one cycle in advance as the 1 before the floating point.

[0071] Current in-memory computing chips generally only perform a fixed type of operation. Specifically, during computation, only one of the most common operations can be performed within the memory, while all other calculations still require additional processing circuitry. This reduces the utilization rate of in-memory computing, making the chip too expensive in terms of design area, power consumption, and efficiency. Furthermore, changing the type of operation requires significant modifications to the circuit structure. These modifications are costly, thus limiting the application scenarios of in-memory computing.

[0072] In one embodiment of the present invention, the computing unit of the in-memory computing circuit includes: a first MOSFET, the gate of which is connected to the output signal of the memory cell allocated to the in-memory computing circuit, the first of its drain and source being connected to a fixed level, and the second of its drain and source being connected to the first of the drain and source of a second MOSFET; a second MOSFET, the gate of which is connected to the first input signal allocated to the in-memory computing circuit, and the second of its drain and source being connected to an output terminal; a third MOSFET, the gate of which is connected to the inverted output signal of the memory cell allocated to the in-memory computing circuit, the first of its drain and source being connected to a fixed level, and the second of its drain and source being connected to the first of the drain and source of a fourth MOSFET; and a fourth MOSFET, the gate of which is connected to the second input signal allocated to the in-memory computing circuit, and the second of its drain and source being connected to an output terminal.

[0073] In this invention, the term "MOSFET" refers to a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). The term "inverting" refers to the digital signal obtained after inverting a digital signal (such as by passing it through an inverter), for example, the inverted form of signal "1" is "0", and the inverted form of signal "0" is "1".

[0074] In an extended embodiment of the present invention, the first to fourth MOSFETs are specified to be n-type MOSFETs; or the first to fourth MOSFETs are p-type MOSFETs.

[0075] In another extension of the invention, the fixed level is specified as ground (GND) or the supply voltage (Vdd). It should be noted that in other scenarios, the fixed level may also be other levels, for example, in the case of a voltage divider resistor in series, the fixed level may be a fraction of the supply voltage.

[0076] In a preferred embodiment of the present invention, when the fixed level is ground (GND), the levels of the first input signal (INL1) and / or the second input signal (INR1) are set as follows:

[0077] The second input signal (INR1) is low, and the in-memory arithmetic unit is configured to perform a NAND operation between the output signal (W1) and the first input signal (INL1);

[0078] The first input signal (INL1) is low, wherein the in-memory arithmetic unit is configured to perform an OR operation between the output signal (W1) and the second input signal (INR1); and the first input signal (INL1) is the inverse of the second input signal (INR1), wherein the in-memory arithmetic unit is configured to perform an XNOR operation between the output signal (W1) and the second input signal (INR1).

[0079] In another preferred embodiment of the invention, when the fixed level is the supply voltage (Vdd), the levels of the first input signal (INL1) and / or the second input signal (INR1) are set as follows:

[0080] The second input signal (INR1) is low, and the in-memory arithmetic unit is configured to perform an AND operation between the output signal (W1) and the first input signal (INL1);

[0081] The first input signal (INL1) is low, wherein the in-memory arithmetic unit is configured to perform a NOR operation between the output signal (W1) and the second input signal (INR1); and the first input signal (INL1) is the inverse of the second input signal (INR1), wherein the in-memory arithmetic unit is configured to perform an XOR operation between the output signal (W1) and the second input signal (INR1).

[0082] It should be noted that the above list of combinations of the level of the first and second input signals is not exhaustive; other logical operations can be implemented with other level combinations. These logical operations also fall within the scope of this invention.

[0083] Through the above embodiments, the signal output by the memory can directly participate in the operations of the in-memory arithmetic circuit and the floating-point arithmetic circuit without the need for digital-to-analog conversion, and the second calculation result does not require analog-to-digital conversion, thereby avoiding the quantization error caused by two analog-to-digital and digital-to-analog conversions, thus greatly improving the calculation accuracy. The operation type of the in-memory arithmetic circuit of the present invention can be easily changed by controlling the levels of the first and second input signals. Thus, the operation type can be changed according to the needs of the scenario without changing the hardware, or all the required operation types can be executed in the same in-memory computing circuit. This greatly expands the application scenarios and flexibility of the in-memory computing circuit and enables all operations to be performed in the same in-memory computing circuit.

[0084] The present invention also provides an in-memory computing circuit, including a floating-point arithmetic unit as described in any of the preceding claims.

[0085] This invention has the following advantages, firstly in terms of structure:

[0086] Significant circuit optimizations have been implemented, avoiding the separation of storage and computing units in traditional architectures and reducing communication costs.

[0087] Compared to conventional in-memory computing architectures, it avoids dependence on ADC / DAC structures, facilitating circuit layout design while reducing area requirements.

[0088] Secondly, in terms of functionality:

[0089] • It can perform both storage and computing functions simultaneously.

[0090] • Using floating-point numbers such as BF16 or FP16 for corresponding digital operations enables high-precision vector operations with relatively low power consumption.

[0091] Unlike ordinary integer data, BF16 format can support up to 2^.

[0092] In summary, the above embodiments have provided detailed descriptions of different configurations of the floating-point arithmetic unit. Of course, this invention includes, but is not limited to, the configurations listed in the above embodiments. Any modifications made based on the configurations provided in the above embodiments are within the scope of protection of this invention. Those skilled in the art can apply the knowledge gained from the above embodiments to other similar applications.

[0093] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the method section.

[0094] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A floating-point arithmetic unit, characterized in that, include: An in-memory computing circuit is configured to perform logical operations on input data and stored data to form a first calculation result, wherein the input data and stored data represent floating-point numbers; as well as A floating-point calculation circuit is configured to perform floating-point operations on the input data and the first calculation result to form a second calculation result. The first floating-point number is stored in the in-memory calculation circuit, and the first part of the second floating-point number is input to the in-memory calculation circuit by the input module, and the second and third parts of the second floating-point number are input to the floating-point calculation circuit by the input module. In each cycle, n bits of the second floating-point number are input. The first part of the second floating-point number undergoes logical operations with the first floating-point number within the computation unit of the in-memory computing circuit to obtain the first calculation result. The second and third parts of the second floating-point number are synchronously delayed. The first calculation result of the in-memory calculation circuit is stored in the floating-point arithmetic circuit, and normalized after each bit of the second floating-point number is processed to obtain the second calculation result.

2. The floating-point arithmetic unit as described in claim 1, characterized in that, Also includes: The input module is configured to provide input data to the in-memory computing circuit and the floating-point computing circuit; The output module is configured to output the first calculation result of the in-memory calculation circuit and the second calculation result of the floating-point calculation circuit.

3. The floating-point arithmetic unit as described in claim 2, characterized in that, The input data and the stored data are processed by the calculation unit of the in-memory calculation circuit through logical operations, and then processed by the subsequent floating-point calculation circuit. The floating-point calculation circuit includes parallel floating-point multiplication operations; and The logical operations include AND and XOR.

4. The floating-point arithmetic unit as described in claim 3, characterized in that, Floating-point numbers consist of: a 1-bit sign bit, n bits of exponent bits, and m bits of mantissa bits, to store ±1.xx. Numbers in the format 2^x; and Parallel floating-point multiplication operations include XORing the sign bit, adding the exponent bits, multiplying the mantissa bits, and normalizing the result based on the XORing of the sign bit, the addition of the exponent bits, and the multiplication of the mantissa bits.

5. The floating-point arithmetic unit as described in claim 4, characterized in that, The in-memory computing circuit performs a one-to-one logical operation on each bit of the input data and each bit of the stored data. In each cycle, it performs an XOR operation on the sign bit of the two data and an AND operation on the other bits. The floating-point arithmetic circuit processes the input data and the calculation results of the in-memory arithmetic circuit in each cycle. It shifts and stores the exponent of the input data, shifts and adds the mantissa of the input data and the calculation result, normalizes the result after a complete calculation cycle, and outputs the result of the floating-point multiplication.

6. The floating-point arithmetic unit as described in claim 4, characterized in that, The computation unit of the in-memory computing circuit is configured to perform a sign bit XOR operation, replacing the sign bit XOR operation in the floating-point multiplication operation of the floating-point computing circuit.

7. The floating-point arithmetic unit as described in claim 1, characterized in that, Divide the bf16 into two 8-bit data segments to facilitate storage and computation within the memory computing circuit. The floating-point number fp16 is stored and operated on in 2x8 format; Floating-point numbers fp32 are stored and operated on in 4x8 format; as well as The first part of the second floating-point number is the sign bit, the second part is the exponent bit, and the third part is the mantissa bit.

8. The floating-point arithmetic unit as described in claim 7, characterized in that, Floating-point calculation circuits include: The shift register is configured to shift and register the second part of the second floating-point number to obtain the first result; A shift adder is configured to shift and add the third part of the second floating-point number to the calculation result to obtain a second result; and The adder is configured to perform an AND operation on the first result, the second result, and the first calculation result to obtain the second calculation result, and the carry signal determines the corresponding normalization operation.

9. The floating-point arithmetic unit as described in claim 8, characterized in that, The lower bits of the second calculation result consist of the sign bit and the mantissa bit, while the higher bits of the second calculation result consist of the exponent bit. In the 8 cycles, since the bf16 storage format in the in-memory calculation circuit is 2x8, 2 bits of input data are input for calculation in each cycle, and after an interval of three calculation cycles, the data is output to the floating-point operation circuit for processing. as well as Due to the special nature of the mantissa bits, the least significant bit of the input data is set to a high level one cycle in advance as the 1 before the floating point.

10. The floating-point arithmetic unit as described in claim 1, characterized in that, The computing unit of the in-memory arithmetic circuit includes: The first MOSFET has its gate connected to the output signal of the memory cell allocated to the in-memory operation circuit, the first of its drain and source connected to a fixed level, and the second of its drain and source connected to the first of the drain and source of the second MOSFET. The second MOSFET has its gate connected to the first input signal allocated to the in-memory operation circuit, and its drain and source, the second of the two, are connected to the output terminal. The third MOSFET has its gate connected inverted to the output signal of the memory cell allocated to the in-memory arithmetic circuit; the first of its drain and source is connected to a fixed level; and the second of its drain and source is connected to the first of the drain and source of the fourth MOSFET. The fourth MOSFET has its gate connected to the second input signal allocated to the in-memory operation circuit, and its drain and source, the second of which, are connected to the output.

11. A memory computing integrated circuit, characterized in that, Includes the floating-point arithmetic unit as described in any one of claims 1 to 10.

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