Dma control method, dma controller, and electronic device
By generating target stitching data internally through the DMA controller, the problems of image size reduction and information loss in convolution operations are solved, thereby improving system performance and storage efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANDONG IND RES KUNYUN ARTIFICIAL INTELLIGENCE RES INST CO LTD
- Filing Date
- 2022-11-29
- Publication Date
- 2026-06-05
AI Technical Summary
Image convolution operations in existing convolutional neural networks lead to image size reduction and information loss, and padding operations increase storage and transmission burdens, thus reducing system performance.
The target splicing data is generated internally through the register configuration module, cache module, selector module, fill position recognition module and splicing data generation module in the DMA controller, avoiding the storage of fill data in external memory, and only transmitting the original data and configuration information.
This reduces the external memory's storage space utilization and data transfer time, while improving the utilization of the on-chip bus and overall system performance.
Smart Images
Figure CN115964317B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data processing technology, and in particular to a DMA control method, a DMA controller, and an electronic device. Background Technology
[0002] Currently, Convolutional Neural Networks (CNNs) are an important branch of artificial intelligence research. Convolution involves performing a convolution operation between the original image and a specific filter to obtain the desired feature map. However, directly performing convolution operations on an image has two drawbacks. First, convolution operations result in feature map sizes smaller than the original image. For example, a 6×6 image convolved with a 3×3 filter yields a 4×4 convolution result, and the more convolutions are performed, the smaller the image becomes. Second, information is lost. As the filter moves across the original image, pixels in the center of the original image are convolved multiple times, while pixels at the edges are convolved less frequently, leading to the loss of information from some edge positions. Therefore, when performing convolution operations, it is usually necessary to pad the original image for convolution. For example, padding another layer of pixels along the edge of the original image, filling and stitching the 6×6 original image into an 8×8 image, storing it in external memory, and then transferring it from external memory to the convolution module. The convolution module uses a 3×3 filter to convolve the 8×8 image, outputting a 6×6 image, thus obtaining a feature map with the same size as the original image. Since the edge pixels of the original 6×6 image are closer to the center, they can participate in more convolution calculations.
[0003] When a 6×6 image is filled and stitched into an 8×8 image, the image area increases by 1.78 times, which is equivalent to a 43.75% reduction in both image storage efficiency and transmission efficiency. In other words, the image filling operation increases the storage space occupancy of external memory and increases the data transmission time, resulting in a decrease in the utilization rate of the on-chip bus and the overall system performance. Summary of the Invention
[0004] In view of the above, this application provides a DMA control method, a DMA controller, and an electronic device, the purpose of which is to solve the above-mentioned technical problems.
[0005] In a first aspect, this application provides a DMA control method, which is applied to a DMA controller. The DMA controller includes a register configuration module, a cache module, a selector module, a fill position identification module, and a splicing data generation module. The method includes:
[0006] The register configuration module receives configuration information from each module sent by the processor, and distributes the configuration information accordingly to the selector module and the fill position recognition module;
[0007] The selector module receives the raw data sent by the cache module, and the padding data carried by the configuration information sent by the register configuration module;
[0008] The filling position identification module receives the configuration information sent by the register configuration module and outputs splicing instruction information to the splicing data generation module according to the configuration information. It also generates a selection signal according to the configuration information so that the selector module outputs the data to be spliced to the splicing data module according to the selection signal. The data to be spliced includes the original data or the filling data.
[0009] The splicing data generation module generates target splicing data based on the data to be spliced and the splicing instruction information.
[0010] Secondly, this application provides a DMA controller, which includes a register configuration module, a cache module, a selector module, a fill position identification module, and a splicing data generation module. The register configuration module is communicatively connected to the cache module, the selector module, the fill position identification module, and the splicing data generation module, respectively.
[0011] The register configuration module is used to receive configuration information of each module sent by the processor, and distribute the configuration information to the selector module and the fill position recognition module accordingly.
[0012] The selector module is used to receive the raw data sent by the cache module, and to receive the padding data carried by the configuration information sent by the register configuration module;
[0013] The filling position identification module is used to receive the configuration information sent by the register configuration module and output splicing instruction information to the splicing data generation module according to the configuration information, and generate a selection signal according to the configuration information so that the selector module outputs the corresponding data to be spliced to the splicing data module according to the selection signal, wherein the data to be spliced includes the original data or the filling data;
[0014] The splicing data generation module is used to generate target splicing data based on the data to be spliced and the splicing instruction information.
[0015] Thirdly, this application provides an electronic device, which includes a processor, a communication interface, a memory, a communication bus, and a DMA controller. The DMA controller includes a register configuration module, a cache module, a selector module, a fill position identification module, and a splicing data generation module. The processor, the communication interface, and the memory communicate with each other through the communication bus.
[0016] Memory, used to store computer programs;
[0017] When a processor executes a program stored in memory, it performs the following steps:
[0018] The register configuration module receives configuration information from each module sent by the processor, and distributes the configuration information accordingly to the selector module and the fill position recognition module;
[0019] The selector module receives the raw data sent by the cache module, and the padding data carried by the configuration information sent by the register configuration module;
[0020] The fill position identification module receives the configuration information sent by the register configuration module and outputs splicing instruction information to the splicing data generation module according to the configuration information. It also generates a selection signal according to the configuration information so that the selector module outputs the corresponding data to be spliced to the splicing data module according to the selection signal. The data to be spliced includes the original data or the fill data.
[0021] The splicing data generation module generates target splicing data based on the data to be spliced and the splicing instruction information.
[0022] The technical solutions provided in this application have the following advantages compared with the prior art:
[0023] This application uses the configuration information distributed by the register configuration module through the DMA controller to concatenate the original data and the padding data to obtain the target concatenated data. Since the target concatenated data is generated inside the DMA controller, the external memory does not need to pre-store the concatenated data. Furthermore, the DMA controller and the on-chip bus only need to transmit the original data and configuration information, which greatly reduces the storage space occupancy of the external memory and the data transmission time, thereby improving the utilization rate of the on-chip bus and the overall system performance. Attached Figure Description
[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1This is a flowchart illustrating a preferred embodiment of the DMA control method of this application;
[0027] Figure 2 This is a schematic diagram of the DMA controller of this application;
[0028] Figure 3 This is a schematic diagram of a preferred embodiment of the electronic device of this application;
[0029] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0030] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.
[0031] This application provides a DMA control method. (Refer to...) Figure 1 The diagram shown is a flowchart illustrating an embodiment of the DMA control method of this application. This method is applied to a DMA controller, which includes a register configuration module, a cache module, a selector module, a fill position identification module, and a data splicing generation module. The method includes:
[0032] Step S10: The register configuration module receives the configuration information of each module sent by the processor, and distributes the configuration information to the selector module and the fill position identification module accordingly;
[0033] Step S20: The selector module receives the raw data sent by the cache module, and receives the padding data carried by the configuration information sent by the register configuration module;
[0034] Step S30: The filling position identification module receives the configuration information sent by the register configuration module and outputs splicing instruction information to the splicing data generation module according to the configuration information, and generates a selection signal according to the configuration information so that the selector module outputs the corresponding data to be spliced to the splicing data module according to the selection signal, wherein the data to be spliced includes the original data or the filling data;
[0035] Step S40: The splicing data generation module generates target splicing data based on the data to be spliced and the splicing instruction information.
[0036] A Direct Memory Access (DMA) controller is a device used within a computer system for data transfer between the CPU and external devices. DMA controllers enable high-speed data transfer between internal and external memory within the computer system. (See reference...) Figure 2 The diagram shown is a schematic of the DMA controller of this application. Figure 2 right Figure 1 The DMA control method will be further explained.
[0037] The register configuration module includes a transmission interface conforming to the on-chip bus format and several register signals. The CPU or other controllers access the transmission interface through the on-chip bus and configure these registers. In turn, the register configuration module can control the operation of other modules.
[0038] The register configuration module receives configuration information for each module sent by the processor (e.g., CPU) and distributes the configuration information to the corresponding modules accordingly. Specifically, it distributes the configuration information of the cache module to the cache module, the configuration information of the selector module to the selector module, the configuration information of the fill position recognition module to the fill position recognition module, and the configuration information of the splicing data generation module to the splicing data generation module. Furthermore, the DMA controller also includes a DMA read module and a DMA write module. The configuration information of the DMA read module is distributed to the DMA read module, and the configuration information of the DMA write module is distributed to the DMA write module. The DMA read module and the DMA write module are responsible for generating interface signals that conform to the on-chip bus format (e.g., AXI, AHB, etc.).
[0039] The caching module can receive the following configuration information: the bit width of the original data, the bit width of the output original data, etc. Taking a 6×6 image data that needs to be padded to an 8×8 image data as an example, the 6×6 image data refers to the original data, the 8×8 image data refers to the target stitching data, and the data used to padded the 6×6 image data is called the padding data.
[0040] The selector module can receive the following configuration information: padding data (padding data is invalid data transferred by the DMA controller, which can be configured in the register and sent to the selector module; in contrast, the original data is valid data transferred by the DMA controller).
[0041] The fill location recognition module can receive the following configuration information: the size of the target stitched data (e.g., the length, width, and shape of the target stitched data), which directions of the original data need to be filled (e.g., top, bottom, left, right, or inserting fill inside the image), and the size of the fill in each direction (e.g., the length, width, and shape of the fill data).
[0042] The data splicing generation module can receive the following configuration information: the output rules of the target spliced data (e.g., whether it is output in a loop, the number of loops, whether the data is output by skipping, the skipping interval, etc.).
[0043] The DMA read module can receive the following configuration information: the address of the raw data in external memory (e.g., the starting address of the external memory), the length of the raw data (data volume), the destination address of the raw data (which module the raw data is transferred to), the number of read operation cycles, DMA startup, etc.
[0044] The DMA write module can receive the following configuration information: the address of the raw data in the DMA controller, the length (data volume) of the raw data, the destination address of the raw data (where to write the data to external memory), the number of write operation cycles, DMA startup, etc.
[0045] After the register configuration module distributes the configuration information to the corresponding modules, the on-chip bus starts DMA, the DMA controller starts transmitting data, the cache module sends the received raw data to the selector module, and the selector module can receive the raw data sent by the cache module, as well as the padding data carried by the configuration information sent by the register configuration module.
[0046] The fill position identification module receives the configuration information sent by the register configuration module and outputs splicing instruction information to the splicing data generation module according to the configuration information. The splicing instruction information is used to indicate what kind of data the splicing data generation module has received (which of the received data is original data and which is fill data), what kind of target splicing data needs to be generated, which parts of each target splicing data are fill data and which parts are original data, and how to splice the original data and fill data (in which direction to splice the fill data in the original data), etc. The fill position identification module generates a selection signal according to the configuration information. The selector module outputs the corresponding data to be spliced to the splicing data module according to the selection signal. The data to be spliced includes original data or fill data. The selection signal is used to select one from multiple data sent to the selector module and output it. For example, if the data sent to the selector module includes fill data M and original data N, the selection signal can make the selector module output M or N, that is, select one of fill data M and original data N for output.
[0047] After receiving the data to be stitched and the stitching instruction information, the stitching data generation module stitches the data according to the instructions to generate the target stitched data. For example, if the stitching instruction information indicates that the original data (a 3×3 image containing 9 points, where the 9 points are 123456789) needs to be filled into the target stitched data (5×3 image data), with one padding data in each direction, using 0 to represent the padding position and 1 to represent the original data position, then the first row of the target stitched data obtained by stitching the data to be stitched will be 01110. The position indicated by 0 will be the padding data 0, and the positions indicated by 1 will be the original data 123. That is, the first row of the target stitched data is 01230, and so on. The second row is 04560, and the third row is 07890. Thus, the 3×3 image data becomes 5×3 image data. It should be noted that at any given moment, the selector module can only output one type of data to the splicing data generation module (either the original data or the filler data). If at a certain moment the selector module outputs the original data based on the selection signal, the splicing data generation module will only have the original data at this time. However, splicing requires filler data. At the next moment, the filler position recognition module controls the selector module to output the corresponding filler data to the splicing data generation module through the selection signal. At this time, the splicing data generation module has both the original data and the filler data and can perform data splicing.
[0048] This application utilizes a DMA controller to concatenate the original data and padding data to obtain the target concatenated data. The padding data is only transmitted within the DMA controller and does not need to be transmitted from external memory to the DMA controller. This eliminates the need for external memory to store padding data. The DMA controller and the on-chip bus only need to transmit the original data and configuration information, which greatly reduces the occupancy rate of external memory and the data transmission time, thereby improving the utilization rate of the on-chip bus and the overall system performance.
[0049] Furthermore, the method also includes:
[0050] The splicing data generation module sends the target splicing data to the computing module that is communicatively connected to the DMA controller.
[0051] The computation module can be a module that performs convolution operations. The computation module communicates with the DMA controller. After obtaining the target stitching data, the stitching data generation module sends the target stitching data to the computation module. Since the feature map size obtained after convolution is smaller than the original image, and some original information will be lost, the original image usually needs to be padded before the convolution operation to ensure that the size obtained by convolution is consistent with the size of the original image and to prevent information loss. However, after the original image is padded, the image area will increase, which will reduce the image storage efficiency and transmission efficiency. By padding the original data in the DMA controller to obtain the target stitching data, and then sending the target stitching data to the convolution operation module, the size obtained by convolution can be consistent with the size of the original image, and the information after convolution will not be lost, while ensuring the image storage efficiency and transmission efficiency.
[0052] Furthermore, before the selector module receives the raw data sent by the cache module, the method further includes:
[0053] The cache module receives the raw data sent by the DMA read module and outputs the raw data to the selector module according to the bit width information of the configuration information.
[0054] The cache module receives raw data from the DMA read module and outputs raw data to the selector module based on the bit width information in the configuration information distributed by the register configuration module. It's important to note that the cache module can be Random Access Memory (RAM) or a FIFO (First-In, First-Out) buffer; the first data to enter the FIFO is the first to be removed. The raw data stored in the cache module is called cached data. The bit widths of the raw data and the cached data may differ. For example, if the raw data has a bit width of 30 bits and the cached data has a bit width of 60 bits, then one cached data is a concatenation of two raw data sets. Another example: the raw data is a 3×3 image with 9 pixels, where the pixels are 123456789. The first row of the image contains 123, the second row contains 456, and the third row contains 789. If the raw data has a bit width of 3 pixels, and the cached data has a bit width of 6 pixels, then the first memory address of the cache module stores 123456, and the second memory address stores 789xxx.
[0055] The step of outputting the original data to the selector module according to the bit width information of the configuration information includes:
[0056] Obtain the first width of the target splicing data from the configuration information;
[0057] Obtain the second bit width of the padding data;
[0058] Calculate the bit width difference between the first bit width and the second bit width, and output the original data corresponding to the bit width difference to the selector module.
[0059] For example, if the original data and cached data are both 30 bits wide, and the target concatenated data is 40 bits wide, with 10 bits padded to the left and right of the original data (i.e., the padded data is 10 bits wide), then when the cache module outputs data to the selector module, it only needs to output the 30 bits of the original data sequentially. As another example, if the original data and cached data are both 30 bits wide, and the target concatenated data is 20 bits wide, with 5 bits padded to the left and right (i.e., the padded data is 5 bits wide), then when the cache module outputs data to the selector module, it only outputs 15 bits of the 30 bits at a time.
[0060] Furthermore, before the cache module receives the raw data sent by the DMA read module and outputs the raw data to the selector module according to the bit width information of the configuration information, the method further includes:
[0061] The DMA read module reads the raw data from the external memory according to the configuration information and sends the raw data to the cache module.
[0062] Since the configuration information distributed by the register configuration module to the DMA read module contains the address of the original data, the DMA read module can read the original data from the external memory according to the address information in the configuration information, and then send the original data to the cache module.
[0063] Reference Figure 2 The diagram shown is a schematic of the DMA controller of this application.
[0064] The DMA controller includes a register configuration module, a cache module, a selector module, a fill position identification module, and a splicing data generation module. The register configuration module is communicatively connected to the cache module, the selector module, the fill position identification module, and the splicing data generation module, respectively.
[0065] The register configuration module is used to receive configuration information of each module sent by the processor, and distribute the configuration information to the selector module and the fill position recognition module accordingly.
[0066] The selector module is used to receive the raw data sent by the cache module, and to receive the padding data carried by the configuration information sent by the register configuration module;
[0067] The filling position identification module is used to receive the configuration information sent by the register configuration module and output splicing instruction information to the splicing data generation module according to the configuration information, and generate a selection signal according to the configuration information so that the selector module outputs the corresponding data to be spliced to the splicing data module according to the selection signal, wherein the data to be spliced includes the original data or the filling data;
[0068] The splicing data generation module is used to generate target splicing data based on the data to be spliced and the splicing instruction information.
[0069] In one embodiment, the DMA controller further includes a DMA read module, and the cache module is further configured to receive raw data sent by the DMA read module and output the raw data to the selector module according to the bit width information of the configuration information.
[0070] In one embodiment, the DMA read module is used to read raw data from the external memory according to the configuration information and send the raw data to the cache module.
[0071] In one embodiment, the splicing data generation module is further configured to send the target splicing data to a computing module that is communicatively connected to the DMA controller.
[0072] In one embodiment, outputting the raw data to the selector module according to the bit width information of the configuration information includes:
[0073] Obtain the first width of the target splicing data from the configuration information;
[0074] Obtain the second bit width of the padding data;
[0075] Calculate the bit width difference between the first bit width and the second bit width, and output the original data corresponding to the bit width difference to the selector module.
[0076] like Figure 3 As shown, this application embodiment provides an electronic device, including a processor 111, a communication interface 112, a memory 113, a communication bus 114, and a DMA controller 115. The processor 111, the communication interface 112, and the memory 113 communicate with each other through the communication bus 114. The memory 113 is used to store computer programs. The DMA controller 115 includes a register configuration module, a cache module, a selector module, a fill position identification module, and a splicing data generation module.
[0077] In one embodiment of this application, when the processor 111 executes a program stored in the memory 113, it performs the following steps:
[0078] The register configuration module receives configuration information from each module sent by the processor, and distributes the configuration information accordingly to the selector module and the fill position recognition module;
[0079] The selector module receives the raw data sent by the cache module, and the padding data carried by the configuration information sent by the register configuration module;
[0080] The fill position identification module receives the configuration information sent by the register configuration module and outputs splicing instruction information to the splicing data generation module according to the configuration information. It also generates a selection signal according to the configuration information so that the selector module outputs the corresponding data to be spliced to the splicing data module according to the selection signal. The data to be spliced includes the original data or the fill data.
[0081] The splicing data generation module generates target splicing data based on the data to be spliced and the splicing instruction information.
[0082] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, performs the following steps:
[0083] The register configuration module receives configuration information from each module sent by the processor, and distributes the configuration information accordingly to the selector module and the fill position recognition module;
[0084] The selector module receives the raw data sent by the cache module, and the padding data carried by the configuration information sent by the register configuration module;
[0085] The fill position identification module receives the configuration information sent by the register configuration module and outputs splicing instruction information to the splicing data generation module according to the configuration information. It also generates a selection signal according to the configuration information so that the selector module outputs the corresponding data to be spliced to the splicing data module according to the selection signal. The data to be spliced includes the original data or the fill data.
[0086] The splicing data generation module generates target splicing data based on the data to be spliced and the splicing instruction information.
[0087] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0088] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.
Claims
1. A DMA control method, applied to a DMA controller, characterized in that, The DMA controller includes a register configuration module, a cache module, a selector module, a padding position recognition module, and a data splicing generation module. The method includes: The register configuration module receives configuration information from each module sent by the processor, and distributes the configuration information accordingly to the selector module and the fill position recognition module; The selector module receives the raw data sent by the cache module, and the padding data carried by the configuration information sent by the register configuration module; The fill position identification module receives the configuration information sent by the register configuration module and outputs splicing instruction information to the splicing data generation module according to the configuration information. It also generates a selection signal according to the configuration information so that the selector module outputs the corresponding data to be spliced to the splicing data module according to the selection signal. The data to be spliced includes the original data or the fill data. The splicing data generation module generates target splicing data based on the data to be spliced and the splicing instruction information.
2. The DMA control method as described in claim 1, characterized in that, The DMA controller further includes a DMA read module, and the method further includes the following steps before the selector module receives the raw data sent by the cache module: The cache module receives the raw data sent by the DMA read module and outputs the raw data to the selector module according to the bit width information of the configuration information.
3. The DMA control method as described in claim 2, characterized in that, Before the cache module receives the raw data sent by the DMA read module and outputs the raw data to the selector module according to the bit width information of the configuration information, the method further includes: The DMA read module reads the raw data from the external memory according to the configuration information and sends the raw data to the cache module.
4. The DMA control method as described in claim 2, characterized in that, The step of outputting the raw data to the selector module according to the bit width information of the configuration information includes: Obtain the first width of the target splicing data from the configuration information; Obtain the second bit width of the padding data; Calculate the bit width difference between the first bit width and the second bit width, and output the original data corresponding to the bit width difference to the selector module.
5. The DMA control method as described in claim 1, characterized in that, The method further includes: The splicing data generation module sends the target splicing data to the computing module that is communicatively connected to the DMA controller.
6. A DMA controller, characterized in that, The DMA controller includes a register configuration module, a cache module, a selector module, a fill position identification module, and a splicing data generation module. The register configuration module is communicatively connected to the cache module, the selector module, the fill position identification module, and the splicing data generation module, respectively. The register configuration module is used to receive configuration information of each module sent by the processor, and distribute the configuration information to the selector module and the fill position recognition module accordingly. The selector module is used to receive the raw data sent by the cache module, and to receive the padding data carried by the configuration information sent by the register configuration module; The filling position identification module is used to receive the configuration information sent by the register configuration module and output splicing instruction information to the splicing data generation module according to the configuration information, and generate a selection signal according to the configuration information so that the selector module outputs the corresponding data to be spliced to the splicing data module according to the selection signal, wherein the data to be spliced includes the original data or the filling data; The splicing data generation module is used to generate target splicing data based on the data to be spliced and the splicing instruction information.
7. The DMA controller as described in claim 6, characterized in that, The DMA controller further includes a DMA read module, and the cache module is also used to receive the raw data sent by the DMA read module and output the raw data to the selector module according to the bit width information of the configuration information.
8. The DMA controller as described in claim 7, characterized in that, The DMA read module is used to read the raw data from the external memory according to the configuration information and send the raw data to the cache module.
9. The DMA controller as claimed in claim 6, characterized in that, The splicing data generation module is also used to send the target splicing data to the computing module that is communicatively connected to the DMA controller.
10. An electronic device, characterized in that, The electronic device includes a processor, a communication interface, a memory, a communication bus, and a DMA controller. The DMA controller includes a register configuration module, a cache module, a selector module, a fill position recognition module, and a splicing data generation module. The processor, communication interface, and memory communicate with each other through the communication bus. Memory, used to store computer programs; When a processor executes a program stored in memory, it performs the following steps: The register configuration module receives configuration information from each module sent by the processor, and distributes the configuration information accordingly to the selector module and the fill position recognition module; The selector module receives the raw data sent by the cache module, and the padding data carried by the configuration information sent by the register configuration module; The fill position identification module receives the configuration information sent by the register configuration module and outputs splicing instruction information to the splicing data generation module according to the configuration information. It also generates a selection signal according to the configuration information so that the selector module outputs the corresponding data to be spliced to the splicing data module according to the selection signal. The data to be spliced includes the original data or the fill data. The splicing data generation module generates target splicing data based on the data to be spliced and the splicing instruction information.