Selection drive circuit and display device including the thereof

Abstract

A gate drive circuit and a display device including the same are disclosed. A signal transmitter includes: a first charge controller configured to charge a first control node in response to a voltage of a VST node; a second charge controller configured to charge a second control node using a first transistor turned on in response to an (N+1)th clock generated following an Nth clock; a first discharge controller configured to discharge the first control node during a charging period of the second control node; and a second discharge controller configured to discharge the second control node when the voltage of the VST node is a high voltage or during a charging period of the first control node.

Description

Technical Field

[0001] The present disclosure relates to a gate driving circuit and a display device including the same. Background Art

[0002] Electroluminescent display devices can be divided into inorganic light-emitting display devices and organic light-emitting display devices according to the material of the light-emitting layer. Active matrix organic light-emitting display devices include organic light-emitting diodes (OLEDs) that generate light by themselves, and have advantages in terms of high response rate, high luminous efficiency, high brightness, and wide viewing angle. In an organic light-emitting display device, an OLED is formed at each pixel. The organic light-emitting display device has a high response rate, high luminous efficiency, high brightness, and a wide viewing angle, and can express black gradation in full black, thereby achieving high contrast and high color reproduction rate.

[0003] The pixel circuit of the organic light-emitting display device includes a light-emitting element, a driving element for driving the light-emitting element, and one or more switching elements. The switching element is turned on or off according to a gate voltage to connect or disconnect the main node of the pixel circuit. The driving element and the switching element can be implemented as a transistor together.

[0004] The gate drive circuit generates a gate pulse to be applied to the gate electrode of the switching element constituting the pixel circuit to control the switching element. Since such a gate drive circuit is composed of many transistors, when it is disposed on the substrate of the display panel, the frame area of ​​the display panel may increase. Summary of the invention

[0005] The present disclosure has been made in an effort to address the above-mentioned needs and / or disadvantages.

[0006] The present disclosure provides a gate driving circuit capable of reducing a border area of ​​a display panel, and a display device including the same.

[0007] In addition, when the number of transistors in the gate drive circuit is reduced to reduce the border area of ​​the display panel, undesirable output or leakage current may occur, thereby increasing power consumption. Therefore, the present disclosure also provides a gate drive circuit capable of reducing the border area of ​​the display panel while preventing leakage current and a display device including the same.

[0008] Problems to be solved by the present disclosure are not limited to those described above, and other unmentioned problems will be clearly understood by those skilled in the art through the following description.

[0009] A gate driving circuit according to an embodiment of the present disclosure includes a shift register including a signal transmitter configured to receive a start pulse and a shift clock and connected in a cascade structure to sequentially generate gate pulses.

[0010] The Nth (N is a positive integer) signal transmitter includes: a VST node, to which a start pulse or a carry signal from a previous signal transmitter is applied; one or more CLK nodes, to which a shift clock is input; a VDD node, to which a high potential drive voltage is applied; a VSS node, to which a low potential reference voltage is applied; a first control node, which is configured to control a first pull-up transistor; a second control node, which is configured to control a first pull-down transistor; a first charge controller, configured to charge a first control node in response to a voltage at a VST node; a second charging controller configured to charge a second control node using a first transistor that is turned on in response to an (N+1)th clock generated following an Nth clock; a first discharging controller configured to discharge the first control node during a charging period of the second control node; and a second discharging controller configured to discharge the second control node when the voltage at the VST node is a high voltage or during a charging period of the first control node.

[0011] The display device disclosed in the present invention includes the gate driving circuit.

[0012] According to the present disclosure, by integrating transistors for causing charging of the second control node controlling the pull-down transistor and discharging of the first control node controlling the pull-up transistor into one transistor in the gate driver, the configuration of the charging controller is simplified or minimized, thereby reducing the frame area.

[0013] According to the present disclosure, by applying a negative reverse bias to the transistor of the discharge controller for discharging the second control node, or by controlling the threshold voltage of the transistor to a negative voltage with a sufficient voltage margin, the threshold voltage of the transistor constituting the discharge controller is adjusted and leakage current of the transistor can be prevented.

[0014] According to the present disclosure, the charging controller allows the second control node to be charged in response to multiple clocks generated after the clock for precharging the first control node and the clock for boosting the first control node, thereby reducing the floating period and stabilizing the voltage of the low level period of the selection pulse.

[0015] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0017] Figure 1 is a schematic diagram of a shift register of a gate drive circuit according to an embodiment of the present disclosure;

[0018] Figure 2 is a circuit diagram illustrating in detail an N-th signal transmitter according to the first embodiment of the present disclosure;

[0019] Figure 3 is a waveform diagram illustrating a start pulse, a shift clock, and a constant voltage to be input to a signal transmitter;

[0020] Figure 4 is an example Figure 2 The waveform diagram of the voltages of the control node and the output node of the Nth signal transmitter shown;

[0021] Figure 5 is a waveform diagram illustrating a ripple of a VGL holding period of a gate pulse generated due to an undesired discharge in a second control node in a case where a transistor constituting a second discharge controller is implemented as a transistor having a single gate;

[0022] Figure 6 is an example of Figure 2 The simulation result of the discharge suppression effect on the voltage of the second control node when the fifth transistor and the sixth transistor are negatively reverse biased is shown;

[0023] Figure 7 is a circuit diagram illustrating in detail an N-th signal transmitter according to a second embodiment of the present disclosure;

[0024] Figure 8 is an example Figure 7 The waveform diagram of the voltages of the control node and the output node of the Nth signal transmitter shown;

[0025] Fig. 9 It is a comparison Figure 2 The floating period of the second control node in the gate drive circuit shown in FIG. Figure 7 FIG. 1 is a diagram showing a floating period of a second control node in a gate driving circuit shown in FIG.

[0026] Fig.10 is a circuit diagram illustrating in detail an Nth signal transmitter according to a third embodiment of the present disclosure;

[0027] Fig.11 This is an example configuration Fig.10 A circuit diagram of a gate-source voltage of a transistor of a second discharge controller shown;

[0028] Fig.12 is an example Fig.10 The waveform diagram of the voltages of the control node and the output node of the Nth signal transmitter shown;

[0029] Fig.13 is a block diagram illustrating a display device according to an embodiment of the present disclosure; and

[0030] Fig.14 is an example Fig.13 A cross-sectional view of the cross-sectional structure of the display panel shown. DETAILED DESCRIPTION

[0031] The advantages and features of the present disclosure and the methods for realizing the same will be more clearly understood from the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments, but can be implemented in various different forms. On the contrary, the embodiments of the present disclosure will make the disclosure of the present disclosure complete and enable those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is limited only within the scope of the appended claims.

[0032] The shapes, sizes, proportions, angles, quantities, etc. shown in the drawings for describing the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout this specification, similar reference numerals generally represent similar elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0033] Terms such as “including,” “comprising,” “having,” and “consisting of” used herein are generally intended to allow the addition of other components unless these terms are used with the term “only.” Any reference to the singular may include the plural unless explicitly stated otherwise.

[0034] Even if not explicitly stated, components are interpreted as including ordinary margins of error.

[0035] When terms such as “on,” “over,” “below,” and “next to” are used to describe the positional relationship between two components, one or more components may be located between the two components unless these terms are used with the term “immediately” or “directly.”

[0036] The terms “first”, “second”, etc. may be used to distinguish components from each other, but the function or structure of the components is not limited by the preceding sequence numbers or component names.

[0037] The following embodiments may be partially or completely combined or combined with each other, and may be technically linked and operated in various ways. These embodiments may be performed independently of each other or in association with each other.

[0038] Each pixel may include a plurality of sub-pixels with different colors in order to reproduce the color of an image on the screen of the display panel. Each sub-pixel includes a transistor used as a switching element or a driving element. Such a transistor may be implemented as a TFT (thin film transistor).

[0039] The driving circuit of the display device writes the pixel data of the input image to the pixels on the display panel. To this end, the driving circuit of the display device may include a data driving circuit configured to provide a data signal to the data line, a gate driving circuit configured to provide a gate signal to the gate line, and the like.

[0040] In the display device of the present disclosure, the pixel circuit and the gate drive circuit may include a plurality of transistors. The transistor may be implemented as an oxide thin film transistor (oxide TFT) including an oxide semiconductor, a low temperature polycrystalline silicon (LTPS) TFT including low temperature polycrystalline silicon, etc. In the embodiment, a description will be given based on an example in which the transistor of the gate drive circuit is implemented as an n-channel oxide TFT, but the present disclosure is not limited thereto.

[0041] A transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that provides carriers to the transistor. In a transistor, carriers flow from the source. The drain is an electrode through which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, so that electrons can flow from the source to the drain. An n-channel transistor has a current direction flowing from the drain to the source. In the case of a p-channel transistor (p-channel metal oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed according to the applied voltage. Therefore, the present disclosure is not limited to the source and drain of a transistor. In the following description, a source and a drain of a transistor will be referred to as a first electrode and a second electrode.

[0042] The gate signal swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than a threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0043] The transistor is turned on in response to a gate-on voltage and turned off in response to a gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage, and the gate-off voltage may be a gate low voltage.

[0044] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, the display device will be described focusing on an organic light emitting display device, but the present disclosure is not limited thereto.

[0045] Reference Figure 1 The gate drive circuit of the present disclosure includes a shift register, which sequentially outputs pulses [Gout(N-1) to Gout(N+2)] (hereinafter referred to as "gate pulses") of a gate signal in synchronization with a shift clock [CLK(N-1) to CLK(N+2)]. Here, "N" is a positive integer.

[0046] The shift register includes signal transmitters [ST(N-1) to ST(N+2)] connected in a cascade structure, and sequentially generates output signals, i.e., strobe pulses [Gout(N-1) to Gout(N+2)]. Each of the signal transmitters [ST(N-1) to ST(N+2)] includes: a VST node to which a start signal VST or a carry signal CAR from a previous signal transmitter is input; a CLK node to which a shift clock [CLK(N-1) to CLK(N+2)] is input; a VDD node to which a high potential driving voltage VGH is applied; a VSS node to which low potential reference voltages VGL and VGL2 are applied; and a first node and a second node for driving a buffer transistor.

[0047] The start signal VST is input to the first signal transmitter. The shift clock [CLK(N-1) to CLK(N+2)] may be a 4-phase clock, but is not limited thereto.

[0048] The signal transmitters [ST(N) to ST(N+2)] which are dependently connected to the (N-1)th signal transmitter [ST(N-1)] start to be driven by receiving the carry signal CAR as a start signal from their corresponding previous signal transmitters. Each of the signal transmitters [ST(N-1) to ST(N+2)] can output a strobe pulse [Gout(N-1) to Gout(N+2)] through a first output node and can simultaneously output a carry signal CAR through a second output node.

[0049] Figure 2 1 is a circuit diagram illustrating in detail the Nth signal transmitter [ST(N)] according to the first embodiment of the present disclosure. Signal transmitters other than the Nth signal transmitter [ST(N)] may be implemented as circuits substantially the same as the Nth signal transmitter [ST(N)]. Figure 3is a waveform diagram illustrating the start pulse VST, the shift clock [CLK(N-1) to CLK(N+2)] and the DC power supply (or constant voltage) VGH, VGL and VGL2 input to the signal transmitter [ST(N-1) to ST(N+2)]. Figure 4 is an example Figure 2 2 is a waveform diagram of the voltages at the control node and the output node of the Nth signal transmitter ST(N).

[0050] Reference Figures 2 to 4 , the Nth signal transmitter [ST(N)] includes a first control node [Q(N)], a second control node [QB(N)], a first charge controller 22 for charging the first control node [Q(N)], a second charge controller 24 for charging the second control node [QB(N)], a first discharge controller 26 for discharging the first control node [Q(N)], a second discharge controller 28 for discharging the second control node [QB(N)], and buffer transistors T7, T8, T9, and T10. All transistors T1 to T10 constituting the Nth signal transmitter [ST(N)] may be implemented as n-channel oxide TFTs having a coplanar structure.

[0051] The Nth signal transmitter [ST(N)] includes: a VST node, to which a start signal VST or a carry signal CAR from a previous signal transmitter is input; a VDD node, to which a high potential driving voltage VGH is applied; a first VSS node, to which a first low potential reference voltage VGL is applied; a second VSS node, to which a second low potential reference voltage VGL2 is applied; a first CLK node, to which the Nth [CLK(N)] is input; and a second CLK node, to which the (N+1)th clock [CLK(N+1)] is input. In another embodiment, the Nth signal transmitter [ST(N)] also includes a third CLK node, to which the (N+2)th clock [CLK(N+2)] is applied.

[0052] The start pulse VST applied to the VST node or the carry signal CAR from the previous signal transmitter is at an AC voltage swinging between the gate drive voltage VGH and the low potential reference voltage VGL. Similarly, the Nth clock and the (N+1)th clock [CLK(N) and CLK(N+1)] are at an AC voltage swinging between the gate drive voltage VGH and the low potential reference voltage VGL. Figure 3 As shown, the gate driving voltage VGH applied to the VST node and the CLK node may be 16V, and the low potential reference voltage VGL applied to the VST node and the CLK node may be -12V, but is not limited thereto.

[0053] The high potential driving voltage VGH may be a DC voltage higher than the low potential reference voltages VGL and VGL2, for example, 16 V, but not limited thereto. The first low potential reference voltage VGL may be a DC voltage of -12 V. In this case, the second low potential reference voltage VGL2 may be a DC voltage lower than the first low potential reference voltage VGL, for example, -16 V, but not limited thereto.

[0054] The Nth signal transmitter [ST(N)] generates a gate pulse [Vgout(N)] through the first output node 31 and generates a pulse of a carry signal [Cout(N)] through the second output node 32 .

[0055] The buffer transistors T7 , T8 , T9 , and T10 include one or more pull-up transistors T7 and T9 driven according to the voltage of the first control node [Q(N)], and one or more pull-down transistors T8 and T10 driven according to the voltage of the second control node [QB(N)].

[0056] The first pull-up transistor T7 is driven according to the voltage of the first control node [Q(N)] to charge the first output node 31. The first pull-down transistor T8 is driven according to the voltage of the second control node [QB(N)] to discharge the first output node 31. The first pull-up transistor T7 and the first pull-down transistor T8 generate a gate pulse [Vgout(N)] swinging between a high potential driving voltage VGH and a low potential reference voltage VGL through the first output node 31.

[0057] The second pull-up transistor T9 is driven according to the voltage of the first control node [Q(N)] to charge the second output node 32. The second pull-down transistor T10 is driven according to the voltage of the second control node [QB(N)] to discharge the second output node 32. The second pull-up transistor T9 and the second pull-down transistor T10 generate a pulse [Cout(N)] of a carry signal that swings between the high potential driving voltage VGH and the low potential reference voltage VGL through the second output node 32.

[0058] The first pull-up transistor T7 includes a gate electrode connected to the first control node [Q(N)], a first electrode connected to the first CLK node (the N-th clock [CLK(N)] is input to the first CLK node), and a second electrode connected to the first output node 31. The second pull-up transistor T9 includes a gate electrode connected to the first control node [Q(N)], a first electrode connected to the first CLK node, and a second electrode connected to the second output node 32.

[0059] The first pull-down transistor T8 includes a gate electrode connected to the second control node [QB(N)], a first electrode connected to the first output node 31, and a second electrode connected to the first VSS node (the low potential reference voltage VGL is applied to the first VSS node). The second pull-down transistor T10 includes a gate electrode connected to the second control node [QB(N)], a first electrode connected to the second output node 32, and a second electrode connected to the first VSS node (the low potential reference voltage VGL is applied to the first VSS node).

[0060] The first charge controller 22 precharges the first control node to the voltage of the VST node in response to the gate drive voltage VGH of the VST node (see Figure 4 ① in the figure). In the state where the first control node [Q(N)] has been precharged to the gate drive voltage VGH, when the gate drive voltage VGH of the Nth clock [CLK(N)] is applied to the pull-up transistors T7 and T9, a bootstrap occurs through the capacitor C (see Figure 4 ②), resulting in the voltage of the first control node Q(N) being boosted and further increased (VGH+α). When the voltage of the first control node [Q(N)] is boosted to VGH+α, the pull-up transistors T7 and T9 are turned on and a gate pulse [Gout(N)] is output from the first output node 31, and a pulse of a carry signal [Cout(N)] is output from the second output node 32 at the same time.

[0061] The second charge controller 24 charges the second control node [QB(N)] to the high potential drive voltage VGH (see FIG. 1 ) in response to the gate drive voltage VGH of the second CLK node (following the (N+1)th clock [CLK(N+1)] generated after the Nth clock [CLK(N)] is applied to the second CLK node). Figure 4 In this case, the pull-down transistors T8 and T10 are turned on according to the gate drive voltage VGH of the second control node [QB(N)]. Figure 4 As shown in ③ in FIG. 3 , the voltages of the output nodes 31 and 32 are discharged to the first low potential reference voltage VGL.

[0062] When the voltage of the second CLK node is reversed to the first low potential reference voltage VGL, the second charge controller 24 is turned off. In this case, since the charging / discharging paths from the controllers 22, 24, 26 and 28 are blocked, the second control node [QB(N)] is floated (see Figure 4 ④) in the above.

[0063] In the charging period in which the second control node [QB(N)] is charged to the gate drive voltage VGH, the first discharge controller 26 discharges the first control node [Q(N)] to the first low potential reference voltage VGL. In this case, the voltage of the first control node [Q(N)] decreases to the first low potential reference voltage VGL, so that the pull-up transistors T7 and T9 are turned off.

[0064] When the voltage of the VST node is the gate drive voltage VGH or the voltage of the first control node [Q(N)] is the gate drive voltage VGH, the second discharge controller 28 discharges the second control node [QB(N)] until the first low potential reference voltage VGL. In this case, the voltage of the second control node [QB(N)] decreases to the first low potential reference voltage VGL, so that the pull-down transistors T8 and T10 are turned off.

[0065] The first charge controller 22 includes at least a 2-1 transistor T2a, a 2-2 transistor T2b, and a third transistor T3. The 2-1 transistor T2a is turned on in response to a gate drive voltage VGH of a VST node (a start pulse VST or a carry signal from a previous signal transmitter is applied to the VST node), and connects the VST node to a buffer node Qh. The 2-2 transistor T2b is turned on in response to a gate drive voltage VGH of the VST node, and connects the first control node Q(N) to the buffer node Qh. When the voltage of the VST node is a first low potential reference voltage VGL, the 2-1 transistor T2a and the 2-2 transistor T2b are turned off.

[0066] The 2-1 transistor T2a includes a gate electrode and a first electrode commonly connected to the VST node, and a second electrode connected to the buffer node Qh. The 2-2 transistor T2b includes a gate electrode connected to the VST node, a first electrode connected to the buffer node Qh, and a second electrode connected to the first control node Q(N). The 2-1 transistor T2a and the 2-2 transistor T2b are connected in series, and the buffer node Qh to be charged to the high potential driving voltage VGH is connected to the node between the 2-1 transistor T2a and the 2-2 transistor T2b. Therefore, the leakage current in the 2-1 transistor T2a and the 2-2 transistor T2b can be reduced or minimized.

[0067] The third transistor T3 is turned on in response to the gate drive voltage VGH of the first control node [Q(N)], and connects the VDD node (the high potential drive voltage VGH is applied to the VDD node) to the buffer node Qh to charge the buffer node Qh. When the voltage of the first control node [Q(N)] is the first low potential reference voltage VGL, the third transistor T3 is turned off. The third transistor T3 includes a gate electrode connected to the first control node [Q(N)], a first electrode connected to the VDD node, and a second electrode connected to the buffer node Qh.

[0068] The second charge controller 24 includes a first transistor T1. The first transistor T1 is turned on in response to the gate drive voltage VGH of the (N+1)th clock [CLK(N+1)], and provides the high potential drive voltage VGH to the second control node [QB(N)], thereby charging the second control node [QB(N)] and driving the first discharge controller 26 to discharge the first control node [Q(N)] (see Figure 4 ③ in ). When the voltage of the (N+1)th clock [CLK(N+1)] is at the first low potential reference voltage VGL, the first transistor T1 is turned off. In this case, the second control node [QB(N)] can be floated (see Figure 4 ④) in the above.

[0069] The first transistor T1 includes a gate electrode connected to a second CLK node (the (N+1)th clock [CLK(N+1)] is applied to the second CLK node), a first electrode connected to a VDD node (a high potential driving voltage VGH is applied to the VDD node), and a second electrode connected to a second control node [QB(N)].

[0070] The first discharge controller 26 includes at least a 4-1 transistor T4a and a 4-2 transistor T4b. The 4-1 transistor T4a is turned on in response to the gate drive voltage VGH of the second control node [QB(N)], and connects the first control node [Q(N)] to the buffer node Qh. The 4-2 transistor T4b is turned on in response to the gate drive voltage VGH of the second control node [QB(N)], and connects the buffer node Qh to the first VSS node (the first low potential reference voltage VGL is applied to the first VSS node). Therefore, when the voltage of the second control node [QB(N)] is the gate drive voltage VGH by means of the second charge controller 24 (see Figure 4③), the 4-1st transistor T4a and the 4-2nd transistor T4b connect the first control node [Q(N)] to the first VSS node, so that the first control node [Q(N)] is discharged until the first low potential reference voltage VGL. When the voltage of the second control node [QB(N)] is the first low potential reference voltage VGL, the 4-1st transistor T4a and the 4-2nd transistor T4b are turned off (see Figure 4 ① and ② in it).

[0071] The 4-1 transistor T4a includes a gate electrode connected to the second control node [QB(N)], a first electrode connected to the first control node [Q(N)], and a second electrode connected to the buffer node Qh. The 4-2 transistor T4b includes a gate electrode connected to the second control node [QB(N)], a first electrode connected to the buffer node Qh, and a second electrode connected to the first VSS node (the low potential reference voltage VGL is applied to the first VSS node). The 4-1 transistor T4a and the 4-2 transistor T4b are connected in series, and the buffer node Qh to be charged to the high potential driving voltage VGH is connected to the node between the 4-1 transistor T4a and the 4-2 transistor T4b. Therefore, the leakage current in the 4-1 transistor T4a and the 4-2 transistor T4b can be reduced or minimized.

[0072] The second discharge controller 28 includes at least a fifth transistor T5 and a sixth transistor T6. When the voltage of the VST node (the start pulse VST or the carry signal from the previous signal transmitter is applied to the VST node) is the gate drive voltage VGH, the fifth transistor T5 is turned on and the second control node [QB (N)] is discharged until the first low potential reference voltage VGL. When the voltage of the first control node [Q (N)] is the gate drive voltage VGH, the sixth transistor T6 is turned on and the second control node [QB (N)] is discharged until the first low potential reference voltage VGL. The fifth transistor T5 is turned off when the voltage of the VST node is the first low potential reference voltage VGL, and the sixth transistor T6 is turned off when the voltage of the first control node [Q (N)] is the low potential reference voltage VGL.

[0073] The transistors constituting the gate drive circuit may be implemented as n-channel oxide TFTs having a coplanar structure. The on-current (Ion) of the n-channel oxide TFT having a coplanar structure is large and the slope of the S factor is high because the thickness of the gate insulating film is thinner than the thickness of the back channel etching (BCE) structure. As a result, when the fifth transistor T5 and the sixth transistor T6 are implemented as n-channel oxide TFTs having a coplanar structure, when the initial threshold voltage Vth is "Vth<0", leakage current may occur when the gate-source voltage Vgs is "Vgs=0".

[0074] In the case where the second charge controller 24 is implemented as one transistor T1 and the transistors T1 to T10 are implemented as n-channel oxide TFTs having a coplanar structure, the second control node [QB(N)] is discharged due to leakage current that may occur when the threshold voltage Vth of the fifth transistor T5 and the sixth transistor T6 is negatively shifted. As a result, Figure 5 As shown, clock ripples may be generated in the VGL holding period of the strobe pulse [Gout(N)].

[0075] like Figure 2 As shown, the present disclosure can form the fifth transistor T5 and the sixth transistor T6 as TFTs with a coplanar structure having a double gate, thereby shifting the threshold voltage Vth of the fifth transistor T5 and the sixth transistor T6 to a voltage higher than 0. Therefore, by preventing the threshold voltage Vth of the fifth transistor T5 and the sixth transistor T6 from being negatively shifted, the discharge of the second control node [QB(N)] can be suppressed during the VGH holding period of the second control node [QB(N)]. The VGH holding period of the second control node [QB(N)] is the same as the VGL holding period of the gate pulse [Gout(N)].

[0076] The fifth transistor T5 includes a first gate electrode connected to a VST node (a start pulse VST or a carry signal from a previous signal transmitter is applied to the VST node), a second gate electrode connected to a second VSS node (a second low potential reference voltage VGL2 is applied to the second VSS node), a first electrode connected to a second control node [QB(N)], and a second electrode connected to a first VSS node (a first low potential reference voltage is applied to the first VSS node). Since the second low potential reference voltage VGL2 is a voltage lower than the first low potential reference voltage VGL, a negative reverse bias is applied between the second gate electrode and the second electrode of the fifth transistor T5, and the threshold voltage Vth of the fifth transistor T5 is positively shifted to a voltage higher than 0V, thereby reducing or minimizing the leakage current of the fifth transistor T5.

[0077] The sixth transistor T6 includes a first gate electrode connected to the first control node [Q(N)], a second gate electrode connected to the second VSS node (the second low potential reference voltage VGL2 is applied to the second VSS node), a first electrode connected to the second control node [QB(N)], and a second electrode connected to the first VSS node (the first low potential reference voltage is applied to the first VSS node). Since the second low potential reference voltage VGL2 is a voltage lower than the first low potential reference voltage VGL, a negative reverse bias is applied between the second gate electrode and the second electrode of the sixth transistor T6, and the threshold voltage Vth of the sixth transistor T6 is positively shifted to a voltage higher than 0V, thereby reducing or minimizing the leakage current of the sixth transistor T6.

[0078] Figure 6 The simulation results comparing the case where the negative reverse bias is applied to the fifth transistor T5 and the sixth transistor T6 and the case where the negative reverse bias is not applied to the fifth transistor T5 and the sixth transistor T6 are illustrated. Figure 6 In , "QB_BB" represents the voltage of the second control node [QB(N)] when the fifth transistor T5 and the sixth transistor T6 are implemented by a dual-gate structure and a negative reverse bias is applied thereto. "QB_NS" represents the voltage of the second control node [QB(N)] when the fifth transistor T5 and the sixth transistor T6 are implemented by a single-gate structure and no negative reverse bias is applied thereto. Figure 6 In FIG. 1 , “Q” represents the voltage of the first control node [Q(N)], and “Gout” represents the voltage of the gate pulse. Figure 6 It can be seen that when a negative reverse bias is applied to the fifth transistor T5 and the sixth transistor T6 , the threshold voltage is positively shifted, which causes the second control node [QB(N)] not to be discharged within the VGH holding period of the second control node [QB(N)].

[0079] Figure 7 is a circuit diagram illustrating in detail the Nth signal transmitter [ST(N)] according to the second embodiment of the present disclosure. Signal transmitters other than the Nth signal transmitter [ST(N)] may be implemented as circuits substantially the same as the Nth signal transmitter [ST(N)]. Figure 7 Components that are substantially the same as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. Figure 8 is an example Figure 7 2 is a waveform diagram of the voltages at the control node and the output node of the Nth signal transmitter ST(N).

[0080] Reference Figures 7 and 8, the Nth signal transmitter [ST(N)] includes a first control node [Q(N)], a second control node [QB(N)], a first charge controller 22 for charging the first control node [Q(N)], a second charge controller 74 for charging the second control node [QB(N)], a first discharge controller 26 for discharging the first control node [Q(N)], a second discharge controller 28 for discharging the second control node [QB(N)], and buffer transistors T7, T8, T9, and T10. All transistors T1 to T11 constituting the Nth signal transmitter [ST(N)] may be implemented as n-channel oxide TFTs.

[0081] The second charge controller 74 charges the second control node [QB(N)] to the high potential drive voltage VGH (see FIG. 1 ) in response to the gate drive voltage VGH of the second CLK node (the (N+1)th clock [CLK(N+1)] generated following the Nth clock [CLK(N)] is applied to the second CLK node) and the gate drive voltage VGH of the third CLK node (the (N+2)th clock [CLK(N+2)] generated following the (N+1)th clock [CLK(N+1)] is applied to the third CLK node). Figure 8 In this case, the pull-down transistors T8 and T10 are turned on according to the gate drive voltage VGH of the second control node [QB(N)]. Figure 8 As shown in ③ and ④ in FIG. 8 , the voltages of the output nodes 31 and 32 are discharged to the first low potential reference voltage VGL.

[0082] When the voltages of the second CLK node and the third CLK node are inverted to the first low potential reference voltage VGL, the second charge controller 74 is turned off. In this case, since the charge / discharge paths from the controllers 22, 74, 26, and 28 are blocked, the second control node [QB(N)] is floated (see Figure 8 ⑤).

[0083] The second charge controller 74 includes a first transistor T1 and an eleventh transistor T11. The first transistor T1 is turned on in response to the gate drive voltage VGH of the (N+1)th clock [CLK(N+1)], and provides the high potential drive voltage VGH to the second control node [QB(N)], thereby charging the second control node [QB(N)] and driving the first discharge controller 26 to discharge the first control node [Q(N)] (see Figure 8③ in the figure). The eleventh transistor T11 is turned on in response to the gate drive voltage VGH of the (N+2)th clock [CLK(N+2)], and provides the high potential drive voltage VGH to the second control node [QB(N)], thereby charging the second control node [QB(N)] and driving the first discharge controller 26 to discharge the first control node [Q(N)] (see Figure 8 ④ in). According to this embodiment, the floating period is reduced in the VGH holding period of the second control node [QB(N)], so the voltage of the gate line (the gate pulse [Gout(N)] is applied to the gate line) can be more stably maintained in the VGL holding period of the gate pulse [Gout(N)]. In this embodiment, the floating period of the second control node [QB(N)] includes Figure 8 The period between ③ and ④ in Figure 8 The period after ④ in , for example, Figure 8 ⑤ in the.

[0084] The clock for controlling the eleventh transistor T11 is not limited to the (N+2)th clock [CLK(N+2)]. For example, the (N+2)th clock [CLK(N+2)] may be any clock following the (N+1)th clock [CLK(N+1)] except for the clock for causing precharge and boost of the first control node [Q(N)]. Figure 2 In the example of , since four-phase clocks are applied from four clock lines in a cyclic manner, the (N+2)th clock [CLK(N+2)] can be replaced by the (N-1)th clock [CLK(N-1)] to be generated after the (N+2)th clock [CLK(N+2)].

[0085] When the (N+1)th clock [CLK(N+1)] is at the first low potential reference voltage VGL, the first transistor T1 is turned off, and the second control node QB(N) is floated (see Figure 8 When the (N+2)th clock [CLK(N+2)] is at the first low potential reference voltage VGL, the eleventh transistor T11 is turned off, and the second control node [QB(N)] is floated (see Figure 8 The eleventh transistor T11 includes a gate electrode connected to the third CLK node (the (N+2)th clock [CLK(N+2)] is applied to the third CLK node), a first electrode connected to the VDD node (the high potential driving voltage VGH is applied to the VDD node), and a second electrode connected to the second control node [QB(N)].

[0086] In the VGH holding period of the second control node [QB(N)], the first transistor T1 and the eleventh transistor T11 supply the high potential driving voltage VGH to the second control node [QB(N)] in response to the (N+1)th clock [CLK(N+1)] and the (N+2)th clock [CLK(N+2)]. As a result, Figure 8 and Fig. 9 As shown, compared with the above-described first embodiment, the floating period in the VGH holding period of the second control node [QB(N)] is reduced, whereby the pull-down transistors T8 and T10 can be driven more stably. Figure 8 The period ⑤ in is the floating period. Fig. 9 In the Figure 2 The floating period of the second control node [QB(N)] in the gate drive circuit shown in FIG. 1 is “TF2”. Figure 7 The floating period of the second control node [QB(N)] in the gate driving circuit is shown.

[0087] Fig.10 is a circuit diagram illustrating in detail an Nth signal transmitter according to a third embodiment of the present disclosure. Signal transmitters other than the Nth signal transmitter [ST(N)] may be implemented as circuits substantially the same as the Nth signal transmitter [ST(N)]. Fig.10 Components that are substantially the same as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. Fig.11 This is an example configuration Fig.10 Circuit diagram of the gate-source voltage of the transistor of the second discharge controller shown. Fig.12 is an example Fig.10 FIG. 4 is a waveform diagram of the voltages at the control node and the output node of the Nth signal transmitter.

[0088] Reference Figures 10 to 12 , the Nth signal transmitter [ST(N)] includes a first control node [Q(N)], a second control node [QB(N)], a first charge controller 22 for charging the first control node [Q(N)], a second charge controller 24 for charging the second control node [QB(N)], a first discharge controller 26 for discharging the first control node [Q(N)], a second discharge controller 108 for discharging the second control node [QB(N)], and buffer transistors T7, T8, T9, and T10. All transistors T1 to T10 and T12 constituting the Nth signal transmitter [ST(N)] may be implemented as n-channel oxide TFTs.

[0089] exist Fig.10In the embodiment, the second charging controller 24 may charge the second control node [QB(N)] by means of the first transistor T1 in response to the (N+1)th clock [CLK(N+1)] generated following the Nth clock [CLK(N)]. The second charging controller 24 may also include Figure 7 The eleventh transistor T11 shown in FIG. 1 charges the second control node [QB(N)] in response to the (N+2)th clock [CLK(N+2)]. For example, Fig.10 The second charge controller 24 may also be implemented as Figure 7 The second charging controller 74 is provided, but the present disclosure is not limited thereto.

[0090] When the voltage of the VST node is the gate drive voltage VGH or the voltage of the first control node [Q(N)] is the gate drive voltage VGH, the second discharge controller 108 discharges the second control node [QB(N)] to the first low potential reference voltage VGL. When it is difficult to apply a transistor to which a reverse bias voltage is applied, the second discharge controller 108 of this embodiment can prevent leakage current by expanding the gate-source voltage margin.

[0091] The second discharge controller 108 includes at least a 5-1st transistor T5a, a 5-2nd transistor T5b, a 6-1st transistor T6a, a 6-2nd transistor T6b, and a twelfth transistor T12.

[0092] When the voltage of the VST node (the start pulse VST or the carry signal from the previous signal transmitter is applied to the VST node) is the gate drive voltage VGH, the 5-1st transistor T5a and the 5-2nd transistor T5b are turned on and discharge the second control node [QB(N)] to the first low potential reference voltage VGL. When the voltage of the first control node [Q(N)] is the gate drive voltage VGH, the 6-1st transistor T6a and the 6-2nd transistor T6b are turned on and discharge the second control node [QB(N)] to the first low potential reference voltage VGL. When the voltage of the VST node is the low potential reference voltage VGL, the 5-1st transistor T5a and the 5-2nd transistor T5b are turned off, and when the voltage of the first control node [Q(N)] is the low potential reference voltage VGL, the 6-1st transistor T6a and the 6-2nd transistor T6b are turned off.

[0093] When the second control node [QB(N)] is charged to the gate drive voltage VGH, the twelfth transistor T12 is turned on and the high potential drive voltage VGH is provided to the second buffer node QBh between the transistors T5a, T5b, T6a and T6b connected in series between the second control node [QB(N)] and the VSS node. When the voltage of the second buffer node QBh increases to the voltage level of the second control node [QB(N)] charged to the gate drive voltage VGH, the gate-source voltage Vgs of the 5-1 transistor T5a and the 6-1 transistor T6a can ensure that the voltage margin is far below 0V. Therefore, even if the threshold voltages of the 5-1 transistor T5a and the 6-1 transistor T6a are negatively shifted to a voltage below 0V, the transistors T5a and T6a can be turned off without leakage current.

[0094] like Fig.11 As shown, when the voltages of the second control node [QB(N)] and the second buffer node QBh are the high potential driving voltage VGH (=16V) and the first control node [Q(N)] is discharged to the low potential reference voltage VGL (=-12V), the gate-source voltage Vgs of the 5-1st transistor T5a and the 6-1st transistor T6a is -28V which is much lower than 0V. In this case, the gate-source voltage Vgs of the 5-2nd transistor T5b and the 6-2nd transistor T6b is 0V.

[0095] The 5-1st transistor T5a includes a gate electrode connected to the VST node, a first electrode connected to the second control node [QB(N)], and a second electrode connected to the second buffer node QBh. The 5-2nd transistor T5b includes a gate electrode connected to the VST node, a first electrode connected to the second buffer node QBh, and a second electrode connected to the VSS node (the low potential reference voltage VGL is applied to the VSS node).

[0096] The 6-1 transistor T6a includes a gate electrode connected to the first control node [Q(N)], a first electrode connected to the second control node [QB(N)], and a second electrode connected to the second buffer node QBh. The 6-2 transistor T6b includes a gate electrode connected to the first control node [Q(N)], a first electrode connected to the second buffer node QBh, and a second electrode connected to a VSS node to which a low potential reference voltage VGL is applied.

[0097] The twelfth transistor T12 includes a gate electrode connected to the second control node [QB(N)], a first electrode connected to the second buffer node QBh, and a second electrode to which a high potential driving voltage is applied.

[0098] Fig.13is a block diagram illustrating a display device according to an embodiment of the present disclosure. Fig.14 is an example Fig.13 A cross-sectional view of the cross-sectional structure of the display panel shown.

[0099] Reference Fig.13 and Fig.14 , a display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driver for writing pixel data to pixels of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driver.

[0100] The display panel 100 may be a panel having a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 includes a pixel array that displays an input image on a screen. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 that intersect the data lines 102, and pixels arranged in a matrix form. The display panel 100 may also include a power line that is commonly connected to the pixel. The power line provides the constant voltage required to drive the pixel 101 to the pixel 101. For example, the display panel 100 may include a VDD line through which a pixel drive voltage EVDD is applied and a VSS line through which a low potential pixel reference voltage EVSS is applied. In addition, the power line may also include a REF line through which a reference voltage Vref is applied and an INIT line through which an initialization voltage Vinit is applied.

[0101] like Fig.14 As shown, the cross-sectional structure of the display panel 100 may include a circuit layer 12 , a light emitting element layer 14 , and an encapsulation layer 16 stacked on a substrate 10 .

[0102] The circuit layer 12 may include a thin film transistor (TFT) array including pixel circuits connected to wirings such as data lines, gate lines, power lines, etc., a demultiplexer array 112, and a gate driver 120. The wirings and circuit elements in the circuit layer 12 may include a plurality of insulating layers, two or more metal layers separated by insulating layers therebetween, and an active layer including a semiconductor material. All transistors formed in the circuit layer 12 may be implemented as n-channel oxide TFTs having a coplanar structure.

[0103] The light emitting element layer 14 may include a light emitting element EL driven by a pixel circuit. The light emitting element EL may include a red (R) light emitting element, a green (G) light emitting element, and a blue (B) light emitting element. In another embodiment, the light emitting element layer 14 may include a white light emitting element and a color filter. The light emitting element EL in the light emitting element layer 14 may be covered by a protective layer including an organic film and a passivation film.

[0104] The light emitting element EL can be implemented as an OLED. The OLED includes an organic compound layer formed between an anode electrode and a cathode electrode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a voltage is applied to the anode electrode and the cathode electrode of the OLED, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the light emitting layer EML and form excitons. In this case, visible light is emitted from the light emitting layer (EML). The OLED used as the light emitting element EL may have a series structure in which a plurality of light emitting layers are stacked. An OLED having a series structure can improve the brightness and life of a pixel.

[0105] The encapsulation layer 16 covers the light emitting element layer 14 to seal the circuit layer 12 and the light emitting element layer 14. The encapsulation layer 16 may be a multi-insulating film structure in which organic films and inorganic films are alternately stacked. The inorganic film blocks the penetration of moisture or oxygen. The organic film flattens the surface of the inorganic film. When the organic film and the inorganic film are stacked into multiple layers, the movement path of moisture or oxygen is longer than that of a single layer, so the penetration of moisture and oxygen that may affect the light emitting element layer 14 can be effectively blocked.

[0106] Although not shown, a touch sensor layer may be formed on the encapsulation layer 16 and a polarizing plate or a color filter layer may be provided on the touch sensor layer. The touch sensor layer may include a capacitive touch sensor that senses a touch input based on a change in capacitance before and after a touch input is input. The touch sensor layer may include an insulating film and a metal interconnect pattern that form a capacitance of the touch sensor. The insulating film may insulate the crossover of the metal interconnect pattern and flatten the surface of the touch sensor layer. The polarizing plate may convert the polarization of external light reflected from the metal of the touch sensor layer and the circuit layer to improve visibility and contrast. The polarizing plate may be implemented as a linear polarizing plate or a circular polarizing plate in which a linear polarizing plate and a phase delay film are combined with each other. The cover glass may be adhered to the polarizing plate. The color filter layer may include a red filter, a green filter, and a blue filter. The color filter layer may also include a black matrix pattern. The color filter layer may absorb some of the light reflected from the circuit layer and the touch sensor layer instead of the polarizing plate, and improve the color purity of the image reproduced on the pixel array.

[0107] The pixel array includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes pixels in a pixel row arranged along a row direction (X-axis direction) on the pixel array of the display panel 100. The pixels arranged in the first pixel row share a gate line 103. Sub-pixels arranged in a column direction Y along a data line direction share the same data line 102. 1 horizontal period is a time obtained by dividing the first frame period by the total number of pixel rows L1 to Ln.

[0108] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel is suitable for a transparent display device that displays an image on a screen and through which a real background is visible. The display panel 100 may be manufactured as a flexible display panel.

[0109] Each pixel 101 can be divided into a red sub-pixel, a green sub-pixel and a blue sub-pixel to realize color. Each pixel 101 can also include a white sub-pixel. Each sub-pixel includes a pixel circuit. Hereinafter, "pixel" can be understood to have the same meaning as "sub-pixel". Each pixel circuit is connected to a data line, a gate line and a power line.

[0110] The pixel circuit includes a light emitting element EL, a driving element for driving the light emitting element, and one or more switching elements. The switching element is turned on or off according to the gate voltage of the gate pulse to connect or disconnect the main node of the pixel circuit. The switching element is turned on in response to the gate on voltage, and it is turned off in response to the gate off voltage. In the case of an n-channel oxide TFT, the gate on voltage is a high potential driving voltage VGH of the gate pulse [Gout(N)] output from the gate driver 120, and the gate off voltage is a low potential reference voltage VGL of the gate pulse [Gout(N)]. The driving element and the switching element of the pixel circuit can be implemented as an n-channel oxide TFT having a coplanar structure.

[0111] Due to process deviations and changes in component characteristics caused during the manufacturing process of the display panel, there may be differences in the electrical characteristics of the driving elements between pixels, and this difference may increase as the driving time of the pixels passes. In order to compensate for the changes in the electrical characteristics of the driving elements between pixels, an internal compensation circuit can be embedded in the pixel circuit, or an external compensation circuit can be connected to the pixel circuit. The internal compensation circuit can be embedded in the pixel circuit and sense the threshold voltage change of the driving element, thereby compensating the gate-source voltage of the driving element for the threshold voltage change. By generating a compensation value based on the result of sensing the electrical characteristics of the driving element using an external compensation circuit connected to the pixel circuit, the external compensation circuit can compensate for the changes in the electrical characteristics of the driving element. The pixel circuit of each sub-pixel may include an internal compensation circuit or may be connected to an external compensation circuit.

[0112] The pixels may be arranged as true color pixels and pentile pixels. Pentile pixels may achieve higher resolution than true color pixels by driving two sub-pixels with different colors as one pixel 101 using a preset pixel rendering algorithm. The pixel rendering algorithm may utilize the color of light emitted from adjacent pixels to compensate for insufficient color reproduction in each pixel.

[0113] The power supply 140 generates a DC voltage (or constant voltage) required to drive the pixel array and the display panel driver of the display panel 100 by using a DC-DC converter. The DC-DC converter may include a charge pump, a rectifier, a buck converter, a boost converter, etc. The power supply 140 may adjust the level of the DC input voltage applied from the host system (not shown) to generate a constant voltage, such as a gamma reference voltage VGMA, a gate voltage VGH, VEH, VGL and VEL, a pixel driving voltage EVDD, a pixel driving voltage ELVDD and a low potential pixel reference voltage ELVSS. The gamma reference voltage VGMA is provided to the data driver 110. The gate voltage VGH and VGL are provided to the gate driver 120. The pixel driving voltage ELVDD and the low potential pixel reference voltage ELVSS are provided to the pixel 101 through a power line commonly connected to the pixel 101.

[0114] The display panel driver writes pixel data of an input image to pixels of the display panel 100 under the control of the timing controller 130 .

[0115] The display panel driver includes a data driver 110 and a gate driver 120. The display panel driver may further include a demultiplexer array 112 located between the data driver 110 and the data lines 102.

[0116] The demultiplexer array 112 sequentially applies data voltages output from channels of the data driver 110 to the data lines 102 using a plurality of demultiplexers (DEMUX). The DEMUX may include a plurality of switching elements on the display panel 100. When the DEMUX is provided between the output terminal of the data driver 110 and the data lines 102, the number of channels of the data driver 110 may be reduced. The demultiplexer array 112 may be omitted.

[0117] The display panel driver may further include a touch sensor driver for driving the touch sensor. Fig.13 The touch sensor driver is omitted. The data driver 110 and the touch sensor driver may be integrated into one driver integrated circuit (IC). In a mobile device or a wearable device, the timing controller 130, the power supply 140, the data driver 110, etc. may be integrated into one driver IC.

[0118] The display panel driver can operate in a low-speed drive mode under the control of the timing controller 130. The low-speed drive mode can be set to analyze the input image and reduce the power consumption of the display device when the degree of change of the input image is less than a predetermined number of frames. In the low-speed drive mode, when a still image is input for a certain period of time or longer, the refresh rate of the pixel can be reduced to reduce the power consumption of the display panel driver and the display panel 100. The low-speed drive mode is not limited to the case of inputting a still image. For example, when the display device is operating in a standby mode or when a user command or an input image is not input to the display panel driver within a certain period of time, the display panel driver can operate in a low-speed drive mode.

[0119] The data driver 110 receives pixel data of an input image in the form of a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 generates a data voltage by converting the pixel data of the input image into a gamma compensation voltage in each frame period using a digital-to-analog converter (DAC). The gamma reference voltage VGMA is divided into a gamma compensation voltage for each grayscale by a voltage divider circuit. The gamma compensation voltage for each grayscale is provided to the DAC of the data driver 110. The data voltage is output through an output buffer in each channel of the data driver 110.

[0120] The gate driver 120 may be implemented as a gate in panel (GIP) circuit formed on a circuit layer 12 on the display panel 100 together with the TFT array and interconnections with the pixel array. The gate driver 120 may be disposed on a bezel region BZ that is a non-display region of the display panel 100, or dispersed in a pixel array that reproduces an input image.

[0121] like Fig.13 As shown, the gate driver 120 may be disposed in the bezel region BZ on one side of the display panel 100, and may provide the gate pulse [Gout(N)] to the gate line 103 in a single-feed manner. In addition, the gate driver 120 may be disposed in the bezel region BZ on opposite sides of the display panel 100 (with the pixel array interposed therebetween), and may provide the gate pulse [Gout(N)] to the gate line 103 in a dual-feed manner.

[0122] Under the control of the timing controller 130, the gate driver 120 sequentially outputs the gate pulse [Gout(N)] to the gate line 103. The gate driver 120 can shift the gate pulse [Gout(N)] by using a shift register to sequentially provide the gate pulse [Gout(N)] to the gate line 103. The signal transmitter in the shift register can be implemented as the above-mentioned circuit. The gate driver 120 may include two or more shift registers, such as a shift register for generating a scan pulse, a shift register for generating a sensing pulse, a shift register for generating an initialization pulse, and a shift register for generating a light emitting control pulse (or EM pulse), and each shift register may be implemented as the circuit adopted in the above-mentioned embodiment.

[0123] The timing controller 130 receives the digital video data DATA of the input image and the timing signal synchronized with the digital video data from the host system. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock CLK, and a data enable signal DE. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a cycle of one horizontal period (1H).

[0124] The host system may be one of a television (TV) system, a tablet computer, a notebook computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system. The host system may scale the image signal from the video source to fit the resolution of the display panel 100, and may send it to the timing controller 130 together with the timing signal.

[0125] The timing controller 130 can multiply the input frame frequency by i (i is a natural number) in the normal driving mode so that it can control the operation timing of the display panel driver at a frame frequency of input frame frequency×i Hz. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) system and 50 Hz in the PAL (Phase Alternating Line) system.

[0126] In the low-speed drive mode, the timing controller 130 reduces the frequency of the frame rate at which pixel data is written to the pixel compared to the normal drive mode. For example, the data refresh frame frequency at which pixel data is written to the pixel in the normal drive mode may occur at a refresh rate of 60 Hz or higher (e.g., any one of 60 Hz, 120 Hz, or 144 Hz), while the data refresh frame DRF in the low-speed drive mode may occur at a refresh rate lower than the frequency in the normal drive mode. In order to reduce the refresh rate of the pixel in the low-speed drive mode, the timing controller 130 may reduce the drive frequency of the display panel driver by reducing the frame frequency to a frequency between 1 Hz and 30 Hz.

[0127] The timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110 based on the timing signals Vsync, Hsync, and DE received from the host system, and generates a control signal for controlling the operation timing of the demultiplexer array 112, and a gate timing control signal for controlling the operation timing of the gate driver 120. The timing controller 130 synchronizes the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120 by controlling the operation timing of the display panel driver.

[0128] The gate timing control signal generated from the timing controller 130 may be input to the shift register of the gate driver 120 through a level shifter (not shown). The level shifter may receive the gate timing control signal and generate a start pulse and a shift clock to provide them to the shift register of the gate driver 120.

[0129] The above-described objects to be achieved by the present disclosure, means for achieving the objects, and effects of the present disclosure do not specify essential features of the claims, and therefore, the scope of the claims is not limited to the disclosed contents of the present disclosure.

[0130] Although the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-mentioned embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the attached claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

[0131] CROSS-REFERENCE TO RELATED APPLICATIONS

[0132] This application claims priority to and the benefit of Korean Patent Application No. 10-2021-0133835, filed on October 8, 2021, and Korean Patent Application No. 10-2021-0176375, filed on December 10, 2021, the disclosures of which are incorporated herein by reference in their entirety.

Claims

1. A gate drive circuit, the gate drive circuit comprising: a shift register, the shift register comprising a signal transmitter configured to receive a start pulse and a shift clock and connected in a cascade structure to sequentially generate a strobe pulse; Wherein, the Nth signal transmitter includes: A VST node to which the start pulse or the carry signal from the previous signal transmitter is applied; one or more CLK nodes, the shift clock is input to the one or more CLK nodes; a VDD node to which a high potential driving voltage is applied; a VSS node to which a low potential reference voltage is applied; a first control node configured to control a first pull-up transistor; a second control node configured to control the first pull-down transistor; a first charging controller configured to charge the first control node in response to a voltage of the VST node; a second charging controller configured to charge the second control node using a first transistor turned on in response to an (N+1)th clock generated following the Nth clock; a first discharge controller configured to discharge the first control node during a charging period of the second control node; and a second discharge controller configured to discharge the second control node when the voltage of the VST node is a high voltage or during a charging period of the first control node, wherein N is a positive integer, Wherein, the shift clock comprises: the Nth clock input to the first CLK node, the (N+1)th clock input to the second CLK node following the Nth clock, and another clock input to the third CLK node following the (N+1)th clock, Wherein, the low potential reference voltage includes: a first low potential reference voltage applied to a first VSS node; and a second low potential reference voltage, which is set lower than the first low potential reference voltage and is applied to a second VSS node, Wherein, the first transistor comprises: a gate electrode connected to the second CLK node, a first electrode connected to the VDD node, and a second electrode connected to the second control node, and Wherein, the second discharge controller comprises: a fifth transistor including a first gate electrode connected to the VST node, a second gate electrode connected to the second VSS node, a first electrode connected to the second control node, and a second electrode connected to the first VSS node; and A sixth transistor includes a first gate electrode connected to the first control node, a second gate electrode connected to the second VSS node, a first electrode connected to the second control node, and a second electrode connected to the first VSS node.

2. The gate drive circuit according to claim 1, wherein: The one or more CLK nodes include the first CLK node, the second CLK node, and the third CLK node, and The VSS nodes include the first VSS node and the second VSS node.

3. The gate drive circuit according to claim 1, wherein: The other clock input to the third CLK node following the (N+1)th clock is the (N+2)th clock generated after the (N+1)th clock or the (N-1)th clock generated after the (N+2)th clock.

4. The gate drive circuit according to claim 1, further comprising: a second pull-up transistor configured to be controlled by the first control node; as well as a second pull-down transistor, the second pull-down transistor being configured to be controlled by the second control node, wherein the first pull-up transistor includes a gate electrode connected to the first control node, a first electrode connected to the first CLK node, and a second electrode connected to the first output node, The second pull-up transistor includes a gate electrode connected to the first control node, a first electrode connected to the first CLK node, and a second electrode connected to a second output node, The first pull-down transistor includes a gate electrode connected to the second control node, a first electrode connected to the first output node, and a second electrode connected to the first VSS node, and The second pull-down transistor includes a gate electrode connected to the second control node, a first electrode connected to the second output node, and a second electrode connected to the first VSS node.

5. The gate drive circuit according to claim 4, wherein: The first output node is configured to output the strobe pulse, and the second output node is configured to output the carry signal.

6. The gate drive circuit according to claim 1, wherein: The first charging controller comprises: a 2-1st transistor, the 2-1st transistor including a gate electrode and a first electrode commonly connected to the VST node, and a second electrode connected to a buffer node; a 2-2 transistor including a gate electrode connected to the VST node, a first electrode connected to the buffer node, and a second electrode connected to the first control node; and A third transistor includes a gate electrode connected to the first control node, a first electrode connected to the VDD node, and a second electrode connected to the buffer node.

7. The gate drive circuit according to claim 6, wherein: The first discharge controller comprises: a 4-1th transistor, the 4-1th transistor including a gate electrode connected to the second control node, a first electrode connected to the first control node, and a second electrode connected to the buffer node; and A 4-2 th transistor, the 4-2 th transistor including a gate electrode connected to the second control node, a first electrode connected to the buffer node, and a second electrode connected to the first VSS node.

8. The gate drive circuit according to claim 1, wherein: The second charging controller further includes: An eleventh transistor includes a gate electrode connected to the third CLK node, a first electrode connected to the VDD node, and a second electrode connected to the second control node.

9. A display device, comprising: A display panel is provided with a plurality of data lines to which data voltages are applied, a plurality of gate lines crossing the plurality of data lines and to which gate signals are applied, and pixels connected to a plurality of power lines, the display panel comprising a gate driving circuit configured to provide gate pulses to the gate lines, The shift register of the gate drive circuit includes a signal transmitter, which is configured to receive a start pulse and a shift clock and is connected in a cascade structure. Wherein, the Nth signal transmitter includes: A VST node to which the start pulse or the carry signal from the previous signal transmitter is applied; one or more CLK nodes, the shift clock is input to the one or more CLK nodes; a VDD node to which a high potential driving voltage is applied; a VSS node to which a low potential reference voltage is applied; a first control node configured to control a first pull-up transistor; a second control node configured to control the first pull-down transistor; a first charging controller configured to charge the first control node in response to a voltage of the VST node; a second charging controller configured to charge the second control node using a first transistor turned on in response to an (N+1)th clock generated following the Nth clock; a first discharge controller configured to discharge the first control node during a charging period of the second control node; and a second discharge controller configured to discharge the second control node when the voltage of the VST node is a high voltage or in a charging period of the first control node, wherein N is a positive integer, Wherein, the shift clock comprises: the Nth clock input to the first CLK node, the (N+1)th clock input to the second CLK node following the Nth clock; and Following another clock input to the third CLK node after the (N+1)th clock, Wherein, the low potential reference voltage includes: a first low potential reference voltage applied to a first VSS node; and a second low potential reference voltage, which is set lower than the first low potential reference voltage and is applied to a second VSS node, wherein the first transistor includes a gate electrode connected to the second CLK node, a first electrode connected to the VDD node, and a second electrode connected to the second control node, and Wherein, the second discharge controller comprises: a fifth transistor including a first gate electrode connected to the VST node, a second gate electrode connected to the second VSS node, a first electrode connected to the second control node, and a second electrode connected to the first VSS node; and A sixth transistor includes a first gate electrode connected to the first control node, a second gate electrode connected to the second VSS node, a first electrode connected to the second control node, and a second electrode connected to the first VSS node.

10. The display device according to claim 9, wherein: The one or more CLK nodes include the first CLK node, the second CLK node, and the third CLK node, and The VSS nodes include the first VSS node and the second VSS node.

11. The display device according to claim 9, wherein: The other clock input to the third CLK node following the (N+1)th clock is the (N+2)th clock generated after the (N+1)th clock or the (N-1)th clock generated after the (N+2)th clock.

12. The display device according to claim 9, wherein: The first charging controller comprises: a 2-1st transistor, the 2-1st transistor including a gate electrode and a first electrode commonly connected to the VST node, and a second electrode connected to a buffer node; a 2-2 transistor including a gate electrode connected to the VST node, a first electrode connected to the buffer node, and a second electrode connected to the first control node; and a third transistor including a gate electrode connected to the first control node, a first electrode connected to the VDD node, and a second electrode connected to the buffer node, and Wherein, the first discharge controller comprises: a 4-1th transistor, the 4-1th transistor including a gate electrode connected to the second control node, a first electrode connected to the first control node, and a second electrode connected to the buffer node; and A 4-2 th transistor, the 4-2 th transistor including a gate electrode connected to the second control node, a first electrode connected to the buffer node, and a second electrode connected to the first VSS node.

13. The display device according to claim 9, wherein: The second charging controller further includes: An eleventh transistor includes a gate electrode connected to the third CLK node, a first electrode connected to the VDD node, and a second electrode connected to the second control node.

14. The display device according to claim 9, wherein: The circuit layer of the display panel includes a pixel circuit of each of the pixels and the gate drive circuit, and Wherein, all transistors arranged in the circuit layer of the display panel are n-channel oxide thin film transistors TFT with a coplanar structure.

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