Electronic device

Abstract

An electronic device includes a light emitting unit, a current source, a voltage comparator, and an emission control unit. The voltage comparator is configured to receive voltage data and a ramp signal and output a comparison signal based on the voltage data and the ramp signal. The emission control unit is configured to output a drive current to the light emitting unit based on the supply current, an emission enable signal, and the comparison signal. The ramp signal is a first ramp signal during a first frame, and the ramp signal is a second ramp signal during a second frame after the first frame. The emission control unit is configured to operate in a first mode based on the first ramp signal, and the emission control unit is configured to operate in a second mode based on the second ramp signal.

Description

[0001] Cross-citation of related applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 255,961, filed October 15, 2021. The entire contents of the aforementioned patent application are hereby incorporated herein by reference and form part of this specification. Technical Field

[0003] This disclosure relates to an apparatus, and more particularly to an electronic apparatus. Background Technology

[0004] Electronic devices can use control signals and programmed voltage data circuitry to implement pulse-width modulation (PWM) to define the pulse width. However, propagation delays and distortions in the control signals of the electronic devices can cause timing errors in the PWM (offset from the target), which can be viewed as a murmur in the displayed image. Summary of the Invention

[0005] The electronic device disclosed herein includes a light-emitting unit, a current source, a voltage comparator, and a transmission control unit. The current source is configured to output a supply current. The voltage comparator is configured to receive voltage data and a ramp signal, and output a comparison signal based on the voltage data and the ramp signal. The transmission control unit is coupled to the light-emitting unit, the current source, and the voltage comparator. The transmission control unit is configured to receive a transmission enable signal and a comparison signal, and output a drive current to the light-emitting unit based on the supply current, the transmission enable signal, and the comparison signal. The ramp signal is a first ramp signal during a first frame period, and a second ramp signal, different from the first ramp signal, during a second frame period following the first frame. The transmission control unit is configured to operate in a first mode based on the first ramp signal, and the transmission control unit is configured to operate in a second mode, different from the first mode, based on the second ramp signal.

[0006] The electronic device disclosed herein includes a pixel array. The pixel array includes a plurality of pixel units. The plurality of pixel units are divided into a plurality of first pixel units and a plurality of second pixel units. The plurality of first pixel units and the plurality of second pixel units are staggered. The plurality of pixel units are configured to receive a plurality of transmit enable signals, a plurality of voltage data, and a common ramp signal, respectively, and are configured to be illuminated during a plurality of transmit cycles according to the plurality of transmit enable signals, the plurality of voltage data, and the ramp signal. Each of the plurality of first pixel units includes a first transmit control unit, and each of the plurality of second pixel units includes a second transmit control unit. The first transmit control unit is configured to receive a first comparison signal, and the second transmit control unit is configured to receive a second comparison signal, wherein the second comparison signal is inverted compared to the first comparison signal. The first transmit control unit is configured to operate in a first mode based on the common ramp signal, and the second transmit control unit is configured to operate in a second mode different from the first mode based on the common ramp signal.

[0007] Based on the foregoing, the electronic device according to this disclosure improves the quality of the displayed image.

[0008] To make the foregoing easier to understand, several embodiments with figures are described in detail below. Attached Figure Description

[0009] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and form a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

[0010] Figure 1 A schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0011] Figure 2 In accordance with this disclosure Figure 1 A schematic diagram of the signals in an embodiment;

[0012] Figure 3 A schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0013] Figure 4 In accordance with this disclosure Figure 3 A schematic diagram of the signals in an embodiment;

[0014] Figure 5A In accordance with this disclosure Figure 3 A schematic diagram of the signals in an embodiment;

[0015] Figure 5B In accordance with this disclosure Figure 3 A schematic diagram of the signals in an embodiment;

[0016] Figure 5C In accordance with this disclosure Figure 3 A schematic diagram of the signals in an embodiment;

[0017] Figure 5D In accordance with this disclosure Figure 3 A schematic diagram of the signals in an embodiment;

[0018] Figure 6 A schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0019] Figure 7 In accordance with this disclosure Figure 6 A schematic diagram of the signals in an embodiment;

[0020] Figure 8A In accordance with this disclosure Figure 6 A schematic diagram of the signals in an embodiment;

[0021] Figure 8B In accordance with this disclosure Figure 6 A schematic diagram of the signals in an embodiment;

[0022] Figure 8C In accordance with this disclosure Figure 6 A schematic diagram of the signals in an embodiment;

[0023] Figure 8D In accordance with this disclosure Figure 6 A schematic diagram of the signals in an embodiment;

[0024] Figure 9A This is a schematic diagram of a pixel array in an electronic device according to an embodiment of the present disclosure;

[0025] Figure 9B In accordance with this disclosure Figure 9A A schematic diagram of the signals in an embodiment;

[0026] Figure 10A This is a schematic diagram of a pixel array in an electronic device according to an embodiment of the present disclosure;

[0027] Figure 10B In accordance with this disclosure Figure 10A A schematic diagram of the signals in an embodiment;

[0028] Figure 11A This is a schematic diagram of a pixel array in an electronic device according to an embodiment of the present disclosure;

[0029] Figure 11B In accordance with this disclosure Figure 11A A schematic diagram of the signals in an embodiment;

[0030] Figure 11C In accordance with this disclosure Figure 11AA schematic diagram of the signals in an embodiment;

[0031] Figure 11D In accordance with this disclosure Figure 11A A schematic diagram of the signal in an embodiment.

[0032] Explanation of icon numbers

[0033] 100, 300, 600: Electronic devices;

[0034] 110, 310, 610: Current source;

[0035] 120, 320, 620: Voltage comparators;

[0036] 130, 330, 630: Transmission control unit;

[0037] 140, 340, 640: Light-emitting units;

[0038] 311, 312, 321, 322, 325, 331, 332, 333, 334, 335, 611, 612, 621, 622, 625, 631, 632, 633, 634, 635, 3241, 3242, 6241, 6242, 6261, 6262: Transistors;

[0039] 313, 323, 613, 623: Capacitors;

[0040] 324, 624, 625, 626: Inverter circuits;

[0041] 900, 1000, 1100: Pixel array;

[0042] 910, 1010, 1110, 1120, 1130: Timing diagram;

[0043] CS: Comparison signal;

[0044] DI: Drive current;

[0045] DL: Data cable;

[0046] EM: Transmit enable signal;

[0047] EP: Activation Period;

[0048] F901, F1001, F1101B, F1101C, F1101D: First frame;

[0049] F902, F1002, F1102B, F1102C, F1102D: Second frame;

[0050] M401, M501_EM, M501_SS, M701, M801_EM, M801_SS: First mode;

[0051] M402, M502_EM, M502_SS, M702, M802_EM, M802_SS: Second mode;

[0052] N1, N2: Node voltages;

[0053] P1: Connection cycle;

[0054] P1', P1_5A, P1_5C, P1_8A, P1_8C: First connection cycle;

[0055] P1'', P1_5B, P1_5D, P1_8B, P1_8D: Second connection cycle;

[0056] P2: Disconnection cycle;

[0057] P2': First disconnection cycle;

[0058] P2'': Second disconnection cycle;

[0059] P901, P1101: First pixel unit;

[0060] P1002, P1102: Second pixel unit;

[0061] RL: Signal line;

[0062] SI: Supply current;

[0063] SPAM: Pulse Amplitude Modulated Scan Signal;

[0064] SPWM: Pulse Width Modulation Scan Signal;

[0065] SS: Ramp signal;

[0066] SS1: First ramp signal;

[0067] SS2: Second ramp signal;

[0068] T1: Type 1;

[0069] T2: Type II;

[0070] t201, t202, t203, t400, t401, t402, t403, t404, t405, t501A, t501A', t501B, t501C, t501D, t501D', t502A, t502B, t502B', t502C, t502C', t502D, t700, t701, t702, t703, t704, t705, t801A, t801A', t801B, t801C, t801D, t801D', t802A, t802B, t802B', t802C, t802C', t802D: Time;

[0071] VD: Voltage data;

[0072] VDD_LEU: Operating voltage;

[0073] VSS, VSS_LEU: Voltage;

[0074] Vth: Threshold voltage. Detailed Implementation

[0075] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or similar components.

[0076] Throughout this disclosure and the appended claims, certain terms are used to refer to specific components. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same component. This document is not intended to distinguish between components that have the same function but different names. In the following description and claims, words such as “comprising” and “including” are open-ended terms and should be interpreted as “including but not limited to…”.

[0077] The term "coupled (or connected)" as used throughout the specification (including the appended claims) of this application may refer to any direct or indirect connecting element. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device via other devices or certain connecting elements. The terms "first," "second," and similar terms used throughout the specification (including the appended claims) of this application are used only to name discrete elements or to distinguish different embodiments or scopes. Therefore, the terms should not be considered as upper or lower limits on the number of elements or should not be used to limit the order of arrangement of elements. Additionally, where possible, elements / components / steps using the same reference numerals in the drawings and embodiments denote the same or similar parts. The use of the same reference numerals or the same terms in different embodiments may refer to the related descriptions of elements / components / steps.

[0078] The electronic device disclosed herein may include a display device, an antenna device, a sensing device, or a splicing device, but this disclosure is not limited thereto. The electronic device disclosed herein may be a flexible or bendable electronic device. In some embodiments of this disclosure, the electronic device may be suitable, for example, for liquid crystals, light-emitting diodes (LEDs), quantum dots (QDs), phosphors, phosphors, other suitable display media, or combinations of the foregoing materials, but this disclosure is not limited thereto. Light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), sub-millimeter light-emitting diodes (microLEDs), micro light-emitting diodes (microLEDs), or quantum dot light-emitting diodes (QLEDs or QDLEDs), or other suitable materials. Materials may be arranged and combined arbitrarily, but this disclosure is not limited thereto. Antenna devices may be liquid crystal antenna devices or non-liquid crystal antenna devices, but this disclosure is not limited thereto. Splicing devices may be, for example, display splicing devices or antenna splicing devices, but this disclosure is not limited thereto. It should be noted that the electronic device may be any combination of the foregoing, but this disclosure is not limited thereto. In the following text, a display device will be used as an electronic device or a splicing device to illustrate the contents of this disclosure, but this disclosure is not limited thereto.

[0079] It should be noted that in the following embodiments, technical features of several different embodiments may be replaced, rearranged, and combined to complete other embodiments without departing from the spirit of this disclosure. Features of each embodiment may be arbitrarily mixed and used together, provided that they do not violate the spirit of this disclosure or conflict with each other.

[0080] Figure 1 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure. (See reference...) Figure 1 The electronic device 100 includes a pixel array, and the pixel array includes a plurality of pixel units. In one embodiment, the electronic device 100 may be a pixel unit, but this disclosure is not limited thereto. Each of the plurality of pixel units may include, for example, Figure 1The circuit architecture shown is illustrated. In embodiments of this disclosure, electronic device 100 includes a current source 110, a voltage comparator 120, a transmit control unit 130, and a light-emitting unit 140. The current source 110 is coupled between an operating voltage VDD_LEU and the transmit control unit 130. The transmit control unit 130 is further coupled to the voltage comparator 120 and the light-emitting unit 140, and receives a transmit enable signal EM. The light-emitting unit 140 is coupled between the transmit control unit 130 and a voltage VSS_LEU. The voltage VSS_LEU is lower than the operating voltage VDD_LEU. In embodiments of this disclosure, the current source 110 is configured to output a supply current SI to the transmit control unit 130. The voltage comparator 120 is configured to receive voltage data VD and a ramp signal SS. The voltage comparator 120 outputs a comparison signal CS to the transmit control unit 130 based on the voltage data VD and the ramp signal SS, and the transmit control unit 130 outputs a drive current DI to the light-emitting unit 140 based on the supply current SI, the transmit enable signal EM, and the comparison signal CS. In embodiments of this disclosure, the transmit enable signal EM, voltage data VD, and ramp signal SS can be provided via data lines and / or scan lines from multiple drive circuits respectively arranged outside or inside the active area of ​​the electronic device 100.

[0081] Figure 2 In accordance with this disclosure Figure 1 A schematic diagram of the signal in an embodiment. (See reference) Figure 1 and Figure 2 Voltage comparator 120 receives voltage data VD and a ramp signal SS. At time t201, the voltage of ramp signal SS begins to rise to form a ramp waveform. Since the voltage of ramp signal SS is lower than the voltage of voltage data VD, voltage comparator 120 outputs a comparison signal CS with a high voltage level. During the enable cycle EP from time t201 to time t203, transmit control unit 130 receives a transmit enable signal EM with a low voltage level. After time t202, since the voltage of ramp signal SS is higher than the voltage of voltage data VD, voltage comparator 120 outputs a comparison signal CS with a low voltage level. Therefore, during the turn-on (transmit / illuminate) period P1 of the enable cycle EP from time t201 to time t202, transmit control unit 130 outputs a drive current DI to drive the light-emitting unit 140. During the off cycle P2 of the enable cycle EP from time t202 to time t203, transmit control unit 130 does not output a drive current DI to drive the light-emitting unit 140.

[0082] In embodiments of this disclosure, voltage comparator 120 may further receive a pulse width modulation (PWM) scan signal and perform voltage programming on voltage data VD according to the PWM scan signal. Electronic device 100 can determine the on-cycle P1 by controlling the voltage level of voltage data VD. If the voltage level of voltage data VD is high, the duration of on-cycle P1 is long. If the voltage level of voltage data VD is low, the duration of on-cycle P1 is short. Furthermore, if the transmit enable signal EM changes to a low voltage level earlier, the enable cycle EP starts earlier, and therefore the duration of on-cycle P1 is long. If the transmit enable signal EM changes to a low voltage level later, the enable cycle EP starts later, and therefore the duration of on-cycle P1 is short. In other words, the duration of the on-cycle P1 of the drive current DI is determined by the transmit enable signal EM, voltage data VD, and ramp signal SS. In other words, the pixel unit can be dimmed by voltage data VD to determine the duration of the pixel unit's turning light cycle. However, if there is a delay due to the propagation delay and signal distortion of the transmit enable signal EM and / or the ramp signal SS, then the duration of the turn-on period P1 can be affected by the delay of the transmit enable signal EM and / or the ramp signal SS, which can be regarded as non-uniformity in the displayed image.

[0083] Additionally, in embodiments of this disclosure, the ramp signal SS is a ramp-up signal, but this disclosure is not limited thereto. In one embodiment of this disclosure, the ramp signal SS may be a ramp-down signal. Furthermore, in embodiments of this disclosure, the transmit enable signal EM is at a low voltage level from time t201 to time t203, and a drive current DI is generated from time t201 to time t202 based on the high voltage level of the comparison signal CS and the low voltage level of the transmit enable signal EM, but this disclosure is not limited thereto. In one embodiment of this disclosure, the transmit enable signal EM is at a high voltage level from time t201 to time t203, and a drive current DI is generated from time t201 to time t202 based on the high voltage level of the comparison signal CS and the high voltage level of the transmit enable signal EM, but this disclosure is not limited thereto.

[0084] Figure 3 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure. (See reference...) Figure 3 The electronic device 300 includes a pixel array, and the pixel array includes a plurality of pixel units. In one embodiment, the electronic device 300 may be a pixel unit, but this disclosure is not limited thereto. Each of the plurality of pixel units may include, for example: Figure 3The circuit architecture shown is illustrated. In embodiments of this disclosure, electronic device 300 includes a current source 310, a voltage comparator 320, a transmit control unit 330, and a light-emitting unit 340. The current source 310 is coupled between the operating voltage VDD_LEU and the transmit control unit 330. The transmit control unit 330 is further coupled to the voltage comparator 320 and the light-emitting unit 340, and receives a transmit enable signal EM. The light-emitting unit 340 is coupled between the transmit control unit 330 and the voltage VSS_LEU. The voltage VSS_LEU is lower than the operating voltage VDD_LEU. In embodiments of this disclosure, the current source 310 is configured to output a supply current to the transmit control unit 330. The voltage comparator 320 is configured to receive voltage data VD via a data line DL and a ramp signal SS via a signal line RL. The voltage comparator 320 outputs a comparison signal CS to the transmit control unit 330 based on the voltage data VD and the ramp signal SS, and the transmit control unit 330 outputs a drive current to the light-emitting unit 340 based on the supply current, the transmit enable signal EM, and the comparison signal CS. In embodiments of this disclosure, the transmit enable signal EM, voltage data VD, and ramp signal SS can be provided from multiple drive circuits respectively arranged outside or inside the active region of the electronic device 300.

[0085] In embodiments of this disclosure, current source 310 includes transistor 311, transistor 312, and capacitor 313. A first terminal of transistor 311 is coupled to data line DL and receives voltage data VD, and a control terminal of transistor 311 receives a pulse-amplitude modulation (PAM) scan signal (SPAM). A first terminal of transistor 312 receives an operating voltage VDD_LEU, and a control terminal of transistor 312 is coupled to a second terminal of transistor 311, and the second terminal of transistor 312 is coupled to transmit control unit 330. A first terminal of capacitor 313 is coupled to the second terminal of transistor 311, and the second terminal of capacitor 313 is coupled to the first terminal of transistor 312. In embodiments of this disclosure, transistors 311 and 312 are P-type transistors. In embodiments of this disclosure, current source 310 receives the PAM scan signal for voltage programming of the voltage at the control terminal of transistor 312, so as to modulate the current supplied through the second terminal of transistor 312.

[0086] In embodiments of this disclosure, voltage comparator 320 includes a plurality of transistors 321, 322, and 325, a capacitor 323, and an inverter circuit 324. A first terminal of transistor 321 is coupled to a data line DL and receives voltage data VD, and a control terminal of transistor 321 receives a pulse width modulation scan signal SPWM. A first terminal of transistor 322 receives a ramp signal SS, a control terminal of transistor 322 receives a transmit enable signal EM, and a second terminal of transistor 322 is coupled to a second terminal of transistor 321. A first terminal of capacitor 323 is coupled to the second terminals of transistors 322 and 321. An input terminal of inverter circuit 324 is coupled to the second terminal of capacitor 323, and an output terminal of inverter circuit 324 is coupled to a transmit control unit 330. A first terminal of transistor 325 is coupled to the input terminal of inverter circuit 324, a control terminal of transistor 325 receives the pulse width modulation scan signal SPWM, and a second terminal of transistor 325 is coupled to the output terminal of inverter circuit 324. The voltage at the second terminal of capacitor 323 is defined as node voltage N1. In embodiments of this disclosure, transistors 321, 322, and 325 are P-type transistors. Voltage comparator 320 performs voltage programming on voltage data VD according to a pulse width modulation scan signal SPWM, such that the second terminal of transistor 321 can output a pulse width modulation voltage.

[0087] In embodiments of this disclosure, inverter circuit 324 includes transistors 3241 and 3242. A first terminal of transistor 3241 receives an operating voltage VDD, a control terminal of transistor 3241 is coupled to an input terminal of inverter circuit 324, and a second terminal of transistor 3241 is coupled to an output terminal of inverter circuit 324. A second terminal of transistor 3242 receives a voltage VSS, a control terminal of transistor 3242 is coupled to an input terminal of inverter circuit 324, and a first terminal of transistor 3242 is coupled to an output terminal of inverter circuit 324. Voltage VSS is lower than the operating voltage VDD. In one embodiment, voltage VSS may be 0 volts, and the operating voltage VDD may be the working voltage. In embodiments of this disclosure, transistor 3241 is a P-type transistor, and transistor 3242 is an N-type transistor.

[0088] In embodiments of this disclosure, the transmit control unit 330 includes a plurality of transistors 331 to 335. The control terminal of transistor 331 is coupled to a voltage comparator 320. A first terminal of transistor 332 is coupled to an operating voltage VDD, the control terminal of transistor 332 receives a transmit enable signal EM, and a second terminal of transistor 332 is coupled to the first terminal of transistor 331. A first terminal of transistor 333 is coupled to the second terminal of transistor 331, the control terminal of transistor 333 is coupled to the voltage comparator 320, and a second terminal of transistor 333 is coupled to a voltage VSS. The voltage VSS is lower than the operating voltage VDD. A first terminal of transistor 334 is coupled to the second terminal of transistor 331, the control terminal of transistor 334 receives the transmit enable signal EM, and a second terminal of transistor 334 is coupled to the voltage VSS. A first terminal of transistor 335 is coupled to a current source 310, the control terminal of transistor 335 is coupled to the second terminal of transistor 331, and the second terminal of transistor 335 is coupled to a light-emitting unit 340. The voltage at the control terminal of transistor 335 is defined as node voltage N2. In embodiments of this disclosure, transistors 331 and 332 are P-type transistors, and transistors 333, 334 and 335 are N-type transistors.

[0089] Figure 4 In accordance with this disclosure Figure 3 A schematic diagram of the signal in an embodiment. (See reference) Figure 3 and Figure 4 During the period from time t400 to time t401, the voltage of the pulse width modulation scan signal SPWM changes from a high voltage level to a low voltage level to turn on transistors 321 and 325. Data line DL transmits voltage data VD containing pulse width modulation data. During the period from time t401 to time t402, the voltage of the pulse amplitude modulation scan signal SPAM changes from a high voltage level to a low voltage level to turn on transistor 311. Data line DL transmits voltage data VD containing pulse amplitude modulation data. During the data setting period from time t400 to time t402, the voltage of the transmit enable signal EM changes from a low voltage level to a high voltage level to turn off transistors 322 and 332 and turn on transistor 334. During the enable period from time t402 to time t405, the voltage of the transmit enable signal EM changes from a high voltage level to a low voltage level to turn on transistors 322 and 332 and turn off transistor 334.

[0090] In this embodiment, the transmit control unit 330 operates in the first mode M401 and determines the end time (time t404) of the first turn-on period (transmit period / illumination period) P1' based on the fact that the ramp signal SS, which is the first ramp signal SS1, is less than the threshold voltage of the comparator 320 set by the voltage data VD with pulse width modulation data. That is, the node voltage N1 coupled to the ramp signal SS via the capacitor is less than the threshold voltage Vth of the inverter 324. In one embodiment, the first ramp signal SS1 is a ramp-down signal. That is, the voltage comparator 320 can receive the first ramp signal SS1 via the capacitor 323. During the data setting period from time t400 to time t402, the first ramp signal SS1 has a high voltage level, and the node voltage N1 changes from a relatively high voltage level to the threshold voltage Vth of the inverter 324 through the connection between the input and output of the inverter 324 when the transistor 325 is turned on with the pulse width modulation signal SPWM. During the data setting period from time t400 to time t402, node voltage N2 remains at a low voltage level (e.g., voltage VSS) due to transistor 334 being turned on. At time t402, the first ramp signal SS1 (ramp signal) begins to drop, the transmit enable signal EM goes low, transistor 322 turns on, and node voltage N1 changes from a low voltage level (threshold voltage Vth) to a relatively high voltage level through capacitive coupling with capacitor 323, while node voltage N2 changes from a low voltage level (voltage VSS) to a high voltage level (e.g., operating voltage VDD), causing transistor 335 to turn on to provide drive current to the light-emitting unit 340. At time t402, the light-emitting unit 340 illuminates. During the enable period from time t402 to time t405, the voltage of the first ramp signal SS1 drops, and node voltage N1 drops synchronously through capacitive coupling with capacitor 323. After time t404, since node voltage N1 is lower than the threshold voltage Vth of inverter 324, transistor 331 is turned off and transistor 333 is turned on after the voltage is inverted. Therefore, node voltage N2 changes from a high voltage level (operating voltage VDD) to a low voltage level (voltage VSS), causing transistor 335 to turn off and the light-emitting unit 340 to also turn off. Thus, the display device 300 can perform effective dimming of the light-emitting unit 340.

[0091] It should be noted that the light-emitting unit 340 first illuminates during the first on-cycle (illumination cycle) P1' (all light-emitting units 340 are illuminated), and then the light-emitting unit 340 is de-illuminated during the first off-cycle (dimming cycle) P2' to perform data setting (all light-emitting units 340 are de-illuminated sequentially or simultaneously). It is noteworthy that the duration of the first on-cycle P1' of the drive current DI is determined by the transmit enable signal EM, the voltage data VD, and the first ramp signal SS1. If there is a delay due to the propagation delay and / or signal distortion of the transmit enable signal EM and / or the first ramp signal SS1, then the duration of the first on-cycle P1' and the duration of the first off-cycle P2' can be adjusted (affected) by the first delay of the transmit enable signal EM and / or the second delay of the first ramp signal SS1, which can be considered as non-uniformity in the displayed image.

[0092] In this embodiment, the transmit control unit 330 operates in the second mode M402, determining the start time (time t403) of the second turn-on period (transmit period / illumination period) P1'' based on the fact that the ramp signal SS, which is the second ramp signal SS2, is greater than the threshold voltage of the comparator 320 set by the voltage data VD with pulse width modulation data. That is, the node voltage N1, which is capacitively coupled to the ramp signal SS, is greater than the threshold voltage Vth of the inverter 324. In one embodiment, the second ramp signal SS2 is a ramp-up signal. That is, the voltage comparator 320 can receive the second ramp signal SS2 through the capacitor 323. During the data setting period from time t400 to time t402, the second ramp signal SS2 has a low voltage level, and the node voltage N1 changes from a relatively low voltage level to the threshold voltage Vth of the inverter 324 through the connection between the input and output of the inverter 324 when the transistor 325 is turned on with the pulse width modulation signal SPWM. During the data setting period from time t400 to time t402, node voltage N2 remains at a low voltage level (voltage VSS) because transistor 334 is turned on. At time t402, the second ramp signal SS2 (ramp signal) begins to rise, the transmit enable signal EM goes low, transistor 323 turns on, and node voltage N1 changes from the threshold voltage Vth of inverter circuit 324 to a relatively low voltage level through capacitive coupling with capacitor 323, causing transistor 335 to turn off and the light-emitting unit 340 to also turn off. During the period from time t402 to time t403, the voltage of the second ramp signal SS2 rises, and node voltage N1 rises synchronously through capacitive coupling with capacitor 323. After time t403, because node voltage N1 is higher than the threshold voltage Vth of inverter circuit 324, after the voltage is inverted, node voltage N2 changes from a low voltage level (voltage VSS) to a high voltage level (operating voltage VDD), causing transistor 331 to turn on and transistor 333 to turn off. Therefore, transistor 335 is turned on, and light-emitting unit 340 is illuminated. Thus, electronic device 300 can perform effective dimming function on light-emitting unit 340.

[0093] It should be noted that the light-emitting unit 340 is first disconnected during the second off-cycle (dimming cycle) P2'' to perform data setting (all light-emitting units 340 are disconnected), and then the light-emitting unit 340 is illuminated during the second on-cycle (illumination cycle) P1'' (all light-emitting units 340 illuminate sequentially or simultaneously). It is noteworthy that the duration of the second on-cycle P1'' of the drive current DI is determined by the transmit enable signal EM, the voltage data VD, and the second ramp signal SS2. If a delay exists due to the propagation delay and / or signal distortion of the transmit enable signal EM and / or the second ramp signal SS2, then the duration of the second off-cycle P2'' and the duration of the second on-cycle P1'' can be adjusted (affected) by the first delay of the transmit enable signal EM and / or the second delay of the second ramp signal SS2, which can be considered as non-uniformity in the displayed image.

[0094] Figure 5A In accordance with this disclosure Figure 3 A schematic diagram of the signal in an embodiment. Figure 5B In accordance with this disclosure Figure 3 A schematic diagram of the signal in an embodiment. Figure 5C In accordance with this disclosure Figure 3 A schematic diagram of the signal in an embodiment. Figure 5D In accordance with this disclosure Figure 3 A schematic diagram of the signal in an embodiment. (See reference) Figures 3 to 5D To address the errors in the duration of the first turn-on period P1' and the second turn-on period P1'' caused by the propagation delay and signal distortion of the transmit enable signal EM and / or the ramp signals SS (first ramp signal SS1 and second ramp signal SS2), the following measures are provided: Figures 5A to 5D The arrangement of signals.

[0095] refer to Figure 5A In this embodiment, the transmit control unit 330 operates in the first mode M501_EM and determines the end time (time t502A) of the first turn-on cycle P1_5A based on the fact that the first ramp signal SS1 (ramp signal) is less than the threshold voltage of the comparator 320. That is, the node voltage N1 is less than the threshold voltage Vth of the inverter 324. In this embodiment, the transmit enable signal EM is delayed, and therefore the start time of the first turn-on cycle P1_5A is delayed from time t501A to time t501A'. Compared with the period from time t501A to time t502A, the duration of the first turn-on cycle P1_5A from time t501A' to time t502A is shorter. In other words, the duration of the period of the light-emitting unit 340 of the illuminated pixel unit is shorter, and therefore the displayed image of the pixel unit is darker.

[0096] refer to Figure 5B In this embodiment, the transmit control unit 330 operates in the second mode M502_EM and determines the start time (t501B) of the second turn-on cycle P1_5B based on the fact that the second ramp signal SS2 (ramp signal) is greater than the threshold voltage of the comparator 320. That is, the node voltage N1 is greater than the threshold voltage Vth of the inverter 324. In this embodiment, the transmit enable signal EM is delayed, and therefore the end time of the second turn-on cycle P1_5B is delayed from time t502B to time t502B'. Compared with the period from time t501B to time t502B, the duration of the second turn-on cycle P1_5B from time t501B to time t502B' is longer. In other words, the duration of the period of the light-emitting unit 340 of the illuminated pixel unit is longer, and therefore the displayed image of the pixel unit is brighter.

[0097] It should be noted that when the transmission control unit 330 operates in the first mode M501_EM (end adjustment mode), the displayed image is darker due to the delay of the transmission enable signal EM. Conversely, when the transmission control unit 330 operates in the second mode M502_EM (start adjustment mode), the displayed image is brighter due to the delay of the transmission enable signal EM. In other words, when the transmission control unit 330 operates in the first mode M501_EM and the second mode M502_EM, the delay of the transmission enable signal EM has opposite effects on the displayed image. Specifically, the time length deduction of the first time length of the first on-state period P1_5A in the first mode M501_EM is equal to the time length increment of the second time length of the second on-state period P1_5B in the second mode M502_EM. In other words, the brightness deduction of the first mode M501_EM is equal to the brightness increment of the second mode M502_EM.

[0098] In this way, if the transmission control unit 330 operates first in the first frame in the first mode M501_EM, and then operates in the second mode M502_EM in the second frame immediately following the first frame, the displayed images of the first and second frames will compensate for each other, thus eliminating the inhomogeneity in the displayed image caused by the propagation delay and / or signal distortion of the transmission enable signal EM. As a result, the quality of the displayed image is improved.

[0099] refer to Figure 5CIn this embodiment, the transmit control unit 330 operates in the first mode M501_SS and determines the end time of the first turn-on period P1_5C based on the fact that the first ramp signal SS1 (ramp signal) is less than the threshold voltage of the comparator 320. That is, the node voltage N1 is less than the threshold voltage Vth of the inverter 324. In this embodiment, the first ramp signal SS1 is delayed, and therefore the end time of the first turn-on period P1_5C is delayed from time t502C to time t502C'. Compared with the period from time t501C to time t502C, the duration of the first turn-on period P1_5C from time t501C to time t502C' is longer. In other words, the duration of the period of the light-emitting unit 340 of the illuminated pixel unit is longer, and therefore the displayed image of the pixel unit is brighter.

[0100] refer to Figure 5D In this embodiment, the transmit control unit 330 operates in the second mode M502_SS and determines the start time of the second turn-on cycle P1_5D based on the fact that the second ramp signal SS2 (ramp signal) is greater than the threshold voltage Vth of the comparator 320. That is, the node voltage N1 is greater than the threshold voltage Vth of the inverter 324. In this embodiment, the second ramp signal SS2 is delayed, and therefore the start time of the second turn-on cycle P1_5D is delayed from time t501D to time t501D'. Compared with the period from time t501D to time t502D, the duration of the second turn-on cycle P1_5D from time t501D' to time t502D is shorter. In other words, the duration of the period of the light-emitting unit 340 of the illuminated pixel unit is shorter, and therefore the displayed image of the pixel unit is darker.

[0101] It should be noted that when the transmission control unit 330 operates in the first mode M501_SS (end adjustment mode), the displayed image is brighter due to the delay of the first ramp signal SS1. Conversely, when the transmission control unit 330 operates in the second mode M502_SS (start adjustment mode), the displayed image is darker due to the delay of the second ramp signal SS2. In other words, when the transmission control unit 330 operates in both the first mode M501_SS and the second mode M502_SS, the delay of the ramp signals SS (first ramp signal SS1 and second ramp signal SS2) has opposite effects on the displayed image. Specifically, the time increment of the first time length of the first on-cycle P1_5C in the first mode M501_SS is equal to the time subtraction of the second time length of the second on-cycle P1_5D in the second mode M502_SS. In other words, the brightness increment of the first mode M501_SS is equal to the brightness subtraction of the second mode M502_SS.

[0102] In this way, if the transmission control unit 330 operates first in the first frame in the first mode M501_SS, and then operates in the second mode M502_SS in the second frame immediately following the first frame, the displayed images of the first and second frames will compensate for each other, thus eliminating the inhomogeneity in the displayed image caused by the propagation delay and / or signal distortion of the first ramp signal SS1. As a result, the quality of the displayed image is improved.

[0103] Figure 6 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure. (See reference...) Figure 6 The electronic device 600 includes a pixel array, and the pixel array includes a plurality of pixel units. In one embodiment, the electronic device 600 may be a pixel unit, but this disclosure is not limited thereto. Each of the plurality of pixel units may include, for example, Figure 6 The circuit architecture shown is illustrated. In embodiments of this disclosure, electronic device 600 includes a current source 610, a voltage comparator 620, a transmit control unit 630, and a light-emitting unit 640. The current source 610 is coupled between the operating voltage VDD_LEU and the transmit control unit 630. The transmit control unit 630 is further coupled to the voltage comparator 620 and the light-emitting unit 640, and receives a transmit enable signal EM. The light-emitting unit 640 is coupled between the transmit control unit 630 and the voltage VSS_LEU. The voltage VSS_LEU is lower than the operating voltage VDD_LEU. In embodiments of this disclosure, the current source 610 is configured to output a supply current to the transmit control unit 630. The voltage comparator 620 is configured to receive voltage data VD via a data line DL and a ramp signal SS via a signal line RL. The voltage comparator 620 outputs a comparison signal CS to the transmit control unit 630 based on the voltage data VD and the ramp signal SS, and the transmit control unit 630 outputs a drive current to the light-emitting unit 640 based on the supply current, the transmit enable signal EM, and the comparison signal CS. In embodiments of this disclosure, the transmit enable signal EM, voltage data VD, and ramp signal SS can be provided from multiple drive circuits respectively arranged outside or inside the active region of the electronic device 600.

[0104] In embodiments of this disclosure, current source 610 includes transistor 611, transistor 612, and capacitor 613. A first terminal of transistor 611 is coupled to data line DL and receives voltage data VD, and a control terminal of transistor 611 receives a pulse amplitude modulation scan signal SPAM. A first terminal of transistor 612 receives an operating voltage VDD_LEU, and a control terminal of transistor 612 is coupled to a second terminal of transistor 611, and the second terminal of transistor 612 is coupled to transmit control unit 630. A first terminal of capacitor 613 is coupled to the second terminal of transistor 611, and the second terminal of capacitor 613 is coupled to the first terminal of transistor 612. In embodiments of this disclosure, transistors 611 and 612 are P-type transistors. In embodiments of this disclosure, current source 610 receives the pulse amplitude modulation scan signal SPAM for voltage programming of the voltage at the control terminal of transistor 612, so as to modulate the current supplied through the second terminal of transistor 612.

[0105] In embodiments of this disclosure, voltage comparator 620 includes a plurality of transistors 621, 622, and 625, a capacitor 623, an inverter circuit 624, and an inverter circuit 626. A first terminal of transistor 621 is coupled to a data line DL and receives voltage data VD, and a control terminal of transistor 621 receives a pulse width modulation scan signal SPWM. A first terminal of transistor 622 receives a ramp signal SS, a control terminal of transistor 622 receives a transmit enable signal EM, and a second terminal of transistor 622 is coupled to a second terminal of transistor 621. A first terminal of capacitor 623 is coupled to the second terminals of transistors 622 and 621. An input terminal of inverter circuit 624 is coupled to the second terminal of capacitor 623, and an output terminal of inverter circuit 624 is coupled to inverter circuit 626. A first terminal of transistor 625 is coupled to the input terminal of inverter circuit 624, a control terminal of transistor 625 receives the pulse width modulation scan signal SPWM, and a second terminal of transistor 625 is coupled to the output terminal of inverter circuit 624. The input terminal of inverter circuit 626 is coupled to the output terminal of inverter circuit 624, and the output terminal of inverter circuit 626 is coupled to transmit control unit 630. The voltage at the second terminal of capacitor 623 is defined as node voltage N1. In embodiments of this disclosure, transistors 621, 622, and 625 are P-type transistors. Voltage comparator 620 performs voltage programming on voltage data VD according to pulse width modulation scan signal SPWM, such that the second terminal of transistor 621 can output pulse width modulation voltage.

[0106] In embodiments of this disclosure, inverter circuit 624 includes transistors 6241 and 6242. A first terminal of transistor 6241 receives an operating voltage VDD, a control terminal of transistor 6241 is coupled to an input terminal of inverter circuit 624, and a second terminal of transistor 6241 is coupled to an output terminal of inverter circuit 624. A second terminal of transistor 6242 receives a voltage VSS, a control terminal of transistor 6242 is coupled to an input terminal of inverter circuit 624, and a first terminal of transistor 6242 is coupled to an output terminal of inverter circuit 624. Voltage VSS is lower than the operating voltage VDD. In embodiments of this disclosure, transistor 6241 is a P-type transistor, and transistor 6242 is an N-type transistor.

[0107] In embodiments of this disclosure, inverter circuit 626 includes transistors 6261 and 6262. A first terminal of transistor 6261 receives an operating voltage VDD, a control terminal of transistor 6261 is coupled to an input terminal of inverter circuit 626, and a second terminal of transistor 6261 is coupled to an output terminal of inverter circuit 626. A second terminal of transistor 6262 receives a voltage VSS, a control terminal of transistor 6262 is coupled to an input terminal of inverter circuit 626, and a first terminal of transistor 6262 is coupled to an output terminal of inverter circuit 626. In embodiments of this disclosure, transistor 6261 is a P-type transistor, and transistor 6262 is an N-type transistor.

[0108] In embodiments of this disclosure, the transmit control unit 630 includes a plurality of transistors 631 to 635. The control terminal of transistor 631 is coupled to a voltage comparator 620. A first terminal of transistor 632 is coupled to an operating voltage VDD, the control terminal of transistor 632 receives a transmit enable signal EM, and a second terminal of transistor 632 is coupled to the first terminal of transistor 631. A first terminal of transistor 633 is coupled to the second terminal of transistor 631, the control terminal of transistor 633 is coupled to the voltage comparator 620, and the second terminal of transistor 633 is coupled to a voltage VSS. Voltage VSS is lower than the operating voltage VDD. A first terminal of transistor 634 is coupled to the second terminal of transistor 631, the control terminal of transistor 634 receives the transmit enable signal EM, and the second terminal of transistor 634 is coupled to the voltage VSS. A first terminal of transistor 635 is coupled to a current source 610, the control terminal of transistor 635 is coupled to the second terminal of transistor 631, and the second terminal of transistor 635 is coupled to a light-emitting unit 640. The voltage at the control terminal of transistor 635 is defined as node voltage N2. In embodiments of this disclosure, transistors 631 and 632 are P-type transistors, and transistors 633, 634 and 635 are N-type transistors.

[0109] Figure 7 In accordance with this disclosure Figure 6 A schematic diagram of the signal in an embodiment. (See reference) Figure 6 and Figure 7 During the period from time t700 to time t701, the voltage of the pulse width modulation scan signal SPWM changes from a high voltage level to a low voltage level to turn on transistors 621 and 625. Data line DL transmits voltage data VD containing pulse width modulation data. During the period from time t701 to time t702, the voltage of the pulse amplitude modulation scan signal SPAM changes from a high voltage level to a low voltage level to turn on transistor 611. Data line DL transmits voltage data VD containing pulse amplitude modulation data. During the data setting period from time t700 to time t702, the voltage of the transmit enable signal EM changes from a low voltage level to a high voltage level to turn off transistors 622 and 632 and turn on transistor 634. During the enable period from time t702 to time t705, the voltage of the transmit enable signal EM changes from a high voltage level to a low voltage level to turn on transistors 622 and 632 and turn off transistor 634.

[0110] In this embodiment, the transmit control unit 630 operates in the first mode M701 and determines the end time (time t704) of the first turn-on period (transmit period / illumination period) P1' based on the fact that the ramp signal SS, which is the second ramp signal SS2, is greater than the threshold voltage of the comparator 620 set by the voltage data VD with pulse width modulation data. That is, the node voltage N1 is greater than the threshold voltage Vth of the inverter 624. In one embodiment, the second ramp signal SS2 is a ramp-up signal. That is, the voltage comparator 620 can receive the second ramp signal SS2. During the data setting period from time t700 to time t702, the second ramp signal SS2 has a low voltage level, and the node voltage N1 changes from a relatively low voltage level to the threshold voltage Vth of the inverter circuit 624. During the data setting period from time t700 to time t702, the node voltage N2 is maintained at a low voltage level (voltage VSS) because the transistor 634 is turned on. At time t702, the second ramp signal SS2 (ramp signal) begins to rise, and the node voltage N1 changes from the threshold voltage Vth of the inverter circuit 624 to a relatively low voltage level through capacitive coupling with capacitor 623, while the node voltage N2 changes from a low voltage level (voltage VSS) to a high voltage level (e.g., operating voltage VDD), causing transistor 635 to turn on to provide drive current to the light-emitting unit 640. At time t702, the light-emitting unit 640 is illuminated. During the enable cycle from time t702 to time t705, the voltage of the second ramp signal SS2 rises, and the node voltage N1 rises synchronously through capacitive coupling with capacitor 623. After time t704, since the node voltage N1 is lower than the threshold voltage Vth of the inverter circuit 624, transistor 631 turns off and transistor 633 turns on. Therefore, the node voltage N2 changes from a high voltage level (operating voltage VDD) to a low voltage level (voltage VSS), causing transistor 635 to turn off and the light-emitting unit 640 to turn off as well. Therefore, the electronic device 600 can perform an effective dimming function on the light-emitting unit 640.

[0111] It should be noted that the light-emitting unit 640 first illuminates during the first on-cycle (illumination cycle) P1' from time t702 to time t704 (all light-emitting units 640 are illuminated), and then the light-emitting unit 640 is de-illuminated during the first off-cycle (dimming cycle) P2' from time t704 to time t705 to perform data setting (all light-emitting units 640 are de-illuminated sequentially or simultaneously). It is noteworthy that the duration of the first on-cycle P1' of the drive current DI is determined by the transmit enable signal EM, the voltage data VD, and the second ramp signal SS2. If there is a delay due to the propagation delay and / or signal distortion of the transmit enable signal EM and / or the second ramp signal SS2, then the duration of the first on-cycle P1' and the duration of the first off-cycle P2' can be adjusted (affected) by the first delay of the transmit enable signal EM and / or the second delay of the second ramp signal SS2, which can be considered as non-uniformity in the displayed image.

[0112] In this embodiment, the transmit control unit 630 operates in the second mode M702 and determines the start time (time t702) of the second turn-on cycle (transmit cycle / illumination cycle) P1'' based on the fact that the ramp signal SS, which is the first ramp signal SS1, is less than the threshold voltage of the comparator 620 set by the voltage data VD with pulse width modulation data. That is, the node voltage N1, which is capacitively coupled to the ramp signal SS, is less than the threshold voltage Vth of the inverter 624. In one embodiment, the first ramp signal SS1 is a ramp-down signal. That is, the voltage comparator 620 can receive the first ramp signal SS1. During the data setting cycle from time t700 to time t702, the first ramp signal SS1 has a high voltage level, and the node voltage N1 changes from a relatively high voltage level to the threshold voltage Vth of the inverter circuit 624. During the data setting cycle from time t700 to time t702, the node voltage N2 is maintained at a low voltage level (voltage VSS) because the transistor 634 is turned on. At time t702, the first ramp signal SS1 (ramp signal) begins to decrease, and the node voltage N1 changes from the threshold voltage Vth of the inverter circuit 624 to a relatively high voltage level through capacitive coupling with capacitor 623. The node voltage N2 is maintained at a low voltage level (voltage VSS), causing transistor 635 to turn off, and the light-emitting unit 640 also turns off. During the second off-cycle (dimming cycle) P2'' from time t702 to time t703, the voltage of the first ramp signal SS1 decreases, and the node voltage N1 decreases synchronously through capacitive coupling with capacitor 623. After time t703, since the node voltage N1 is lower than the threshold voltage Vth of the inverter circuit 624, the node voltage N2 changes from a low voltage level (voltage VSS) to a high voltage level (operating voltage VDD), inverting the voltage. After this, transistor 631 turns on and transistor 633 turns off. Therefore, transistor 635 turns on, and the light-emitting unit 640 illuminates. Therefore, the electronic device 600 can perform an effective dimming function on the light-emitting unit 640.

[0113] It should be noted that the light-emitting unit 640 is first disconnected during the second off-cycle (dimming cycle) P2'' to perform data setting (all light-emitting units 640 are disconnected), and then the light-emitting unit 640 is illuminated during the second on-cycle (illumination cycle) P1'' from time t703 to time t705 (all light-emitting units 640 are illuminated sequentially or simultaneously). It is noteworthy that the duration of the second on-cycle P1'' of the drive current DI is determined by the transmit enable signal EM, the voltage data VD, and the first ramp signal SS1. If there is a delay due to the propagation delay and / or signal distortion of the transmit enable signal EM and / or the first ramp signal SS1, then the duration of the second off-cycle P2'' and the duration of the second on-cycle P1'' can be adjusted (affected) by the first delay of the transmit enable signal EM and / or the second delay of the second ramp signal SS2, which can be considered as non-uniformity in the displayed image.

[0114] Figure 8A In accordance with this disclosure Figure 6 A schematic diagram of the signal in an embodiment. Figure 8B In accordance with this disclosure Figure 6 A schematic diagram of the signal in an embodiment. Figure 8C In accordance with this disclosure Figure 6 A schematic diagram of the signal in an embodiment. Figure 8D In accordance with this disclosure Figure 6 A schematic diagram of the signal in an embodiment. (See reference) Figures 6 to 8D To address the errors in the duration of the first turn-on period P1' and the second turn-on period P1'' caused by the propagation delay and signal distortion of the transmit enable signal EM and / or the ramp signals SS (first ramp signal SS1 and second ramp signal SS2), the following measures are provided: Figures 8A to 8D The arrangement of signals.

[0115] refer to Figure 8A In this embodiment, the transmit control unit 630 operates in the first mode M801_EM and determines the end time (time t802A) of the first turn-on cycle P1_8A based on the fact that the second ramp signal SS2 (ramp signal) is greater than the threshold voltage of the comparator 620. That is, the node voltage N1 is greater than the threshold voltage Vth of the inverter 624. In this embodiment, the transmit enable signal EM is delayed, and therefore the start time of the first turn-on cycle P1_8A is delayed from time t801A to time t801A'. Compared with the period from time t801A to time t802A, the duration of the first turn-on cycle P1_8A from time t801A' to time t802A is shorter. In other words, the duration of the period of the light-emitting unit 640 of the illuminated pixel unit is shorter, and therefore the displayed image of the pixel unit is darker.

[0116] refer to Figure 8B In this embodiment, the transmit control unit 630 operates in the second mode M802_EM and determines the start time (t801B) of the second turn-on cycle P1_8B based on the fact that the first ramp signal SS1 (ramp signal) is less than the threshold voltage of the comparator 620. That is, the node voltage N1 is less than the threshold voltage Vth of the inverter 624. In this embodiment, the transmit enable signal EM is delayed, and therefore the end time of the second turn-on cycle P1_8B is delayed from time t802B to time t802B'. Compared with the period from time t801B to time t802B, the duration of the second turn-on cycle P1_8B from time t801B to time t802B' is longer. In other words, the duration of the period of the light-emitting unit 640 of the illuminated pixel unit is longer, and therefore the displayed image of the pixel unit is brighter.

[0117] It should be noted that when the transmission control unit 630 operates in the first mode M801_EM (end adjustment mode), the displayed image is darker due to the delay of the transmission enable signal EM. Conversely, when the transmission control unit 630 operates in the second mode M802_EM (start adjustment mode), the displayed image is brighter due to the delay of the transmission enable signal EM. In other words, when the transmission control unit 630 operates in the first mode M801_EM and the second mode M802_EM, the delay of the transmission enable signal EM has opposite effects on the displayed image. Specifically, the duration of the first time length of the first on-state period P1_8A in the first mode M801_EM is subtracted from the duration of the second time length of the second on-state period P1_8B in the second mode M802_EM. In other words, the brightness subtraction in the first mode M801_EM is equal to the brightness increment in the second mode M802_EM.

[0118] In this way, if the transmission control unit 630 operates first in the first frame in the first mode M801_EM, and then operates in the second mode M802_EM in the second frame immediately following the first frame, the displayed images of the first and second frames will compensate for each other, thus eliminating the inhomogeneity in the displayed image caused by the propagation delay and / or signal distortion of the transmission enable signal EM. As a result, the quality of the displayed image is improved.

[0119] refer to Figure 8CIn this embodiment, the transmit control unit 630 operates in the first mode M801_SS and determines the end time of the first turn-on period P1_8C based on the fact that the second ramp signal SS2 (ramp signal) is greater than the threshold voltage of the comparator 620. That is, the node voltage N1 is greater than the threshold voltage Vth of the inverter 324. In this embodiment, the second ramp signal SS2 is delayed, and therefore the end time of the first turn-on period P1_8C is delayed from time t802C to time t802C'. Compared with the period from time t801C to time t802C, the duration of the first turn-on period P1_8C from time t801C to time t802C' is longer. In other words, the duration of the period of the light-emitting unit 640 of the illuminated pixel unit is longer, and therefore the displayed image of the pixel unit is brighter.

[0120] refer to Figure 8D In this embodiment, the transmit control unit 630 operates in the second mode M802_SS, and determines the start time of the second turn-on cycle P1_8D based on the fact that the first ramp signal SS1 (ramp signal) is less than the threshold voltage of the comparator 620. That is, the node voltage N1 is less than the threshold voltage Vth of the inverter 624. In this embodiment, the delay of the first ramp signal SS1 occurs, and therefore the start time of the second turn-on cycle P1_8D is delayed from time t801D to time t801D'. Compared with the period from time t801D to time t802D, the duration of the second turn-on cycle P1_8D from time t801D' to time t802D is shorter. In other words, the duration of the period of the light-emitting unit 640 of the illuminated pixel unit is shorter, and therefore the displayed image of the pixel unit is darker.

[0121] It should be noted that when the transmission control unit 630 operates in the first mode M801_SS (end adjustment mode), the displayed image is brighter due to the delay of the second ramp signal SS2. Conversely, when the transmission control unit 630 operates in the second mode M802_SS (start adjustment mode), the displayed image is darker due to the delay of the first ramp signal SS1. In other words, when the transmission control unit 630 operates in both the first mode M801_SS and the second mode M802_SS, the delay of the ramp signals SS (first ramp signal SS1 and second ramp signal SS2) has opposite effects on the displayed image. Specifically, the time increment of the first time length of the first on-cycle P1_8C in the first mode M801_SS is equal to the time subtraction of the second time length of the second on-cycle P1_8D in the second mode M802_SS. In other words, the brightness increment of the first mode M801_SS is equal to the brightness subtraction of the second mode M802_SS.

[0122] In this way, if the transmission control unit 630 operates first in the first frame in the first mode M801_SS, and then operates in the second mode M802_SS in the second frame immediately following the first frame, the displayed images of the first and second frames will compensate for each other, thus eliminating the inhomogeneity in the displayed image caused by the propagation delay and / or signal distortion of the ramp signal SS. As a result, the quality of the displayed image is improved.

[0123] Figure 9A This is a schematic diagram of a pixel array of an electronic device according to an embodiment of the present disclosure. Figure 9B In accordance with this disclosure Figure 9A A schematic diagram of the signal in an embodiment. (See reference) Figures 3 to 5D , Figure 9A and Figure 9B The electronic device includes a pixel array 900, and the pixel array 900 includes a plurality of first pixel units P901. Each of the plurality of first pixel units P901 may include the circuit architecture shown in FIG3, and the pixel array may be as follows: Figure 9A The arrangement shown is such that the signal of the first pixel unit P901 can be as follows: Figure 9B The timing diagram 910 shown is arranged as shown.

[0124] refer to Figure 3 Inverter 324 is arranged in voltage comparator 320, thus inverting the comparison signal before it is provided to transmission control unit 330. In other words, transmission control unit 330 is configured to receive the inverted comparison signal. Therefore, the pixel unit P901 of the electronic device can be called an inverted type pixel unit, which is described as follows: Figure 9A The first type T1 in the series.

[0125] refer to Figures 5A to 5D and Figure 9B When the transmission control unit 330 operates in the first mode M501_EM and the second mode M502_EM, the delay of the transmission enable signal EM has opposite effects on the displayed image. Furthermore, when the transmission control unit 330 operates in the first mode M501_SS and the second mode M502_SS, the delay of the ramp signals SS (first ramp signal SS1 and second ramp signal SS2) has opposite effects on the displayed image.

[0126] In this manner, the first mode M501_EM / M501_SS (end adjustment mode) and the second mode M502_EM / M502_SS (start adjustment mode) of the transmission control unit 330 of the first pixel unit P901 can be alternately arranged in time to eliminate the effect of the delay of the transmission enable signal EM and / or the ramp signal SS (first ramp signal SS1 and second ramp signal SS2). In one embodiment, the transmission control unit 330 operates in the second mode M502_EM / M502_SS (start adjustment mode) based on the second ramp signal SS2 (ramp signal) in the first frame F901, and the transmission control unit 330 operates in the first mode M501_EM / M501_SS (end adjustment mode) based on the first ramp signal SS1 (ramp signal) in the second frame F902 after the first frame F901, so that the displayed images of the first frame F901 and the second frame F902 will compensate for each other. Therefore, it eliminates the non-uniformity in the displayed image caused by the propagation delay and / or signal distortion of the transmit enable signal EM and / or ramp signal SS, and improves the quality of the displayed image.

[0127] Figure 10A This is a schematic diagram of a pixel array of an electronic device according to an embodiment of the present disclosure. Figure 10B In accordance with this disclosure Figure 10A A schematic diagram of the signal in an embodiment. (See reference) Figures 6 to 8D , Figure 10A and Figure 10B The electronic device includes a pixel array 1000, and the pixel array 1000 includes a plurality of second pixel units P1002. Each of the plurality of second pixel units P1002 may include, for example: Figure 6 The circuit architecture shown can be used as follows: the pixel array can be Figure 10A The arrangement shown is such that the signal of the second pixel unit P1002 can be as follows: Figure 10B The timing diagram 1010 shown is arranged as shown.

[0128] refer to Figure 6 Inverters 624 and 626 are arranged in voltage comparator 620, and therefore the comparison signal is not inverted (inverted twice) before being provided to the transmit control unit 630. In other words, the transmit control unit 630 is configured to receive the non-inverted comparison signal. Therefore, the pixel unit P1002 of the electronic device can be referred to as a non-inverted type pixel unit, which is described as follows: Figure 10A The second type, T2.

[0129] refer to Figures 8A to 8D and Figure 10BWhen the transmission control unit 630 operates in the first mode M801_EM and the second mode M802_EM, the delay of the transmission enable signal EM has opposite effects on the displayed image. Furthermore, when the transmission control unit 630 operates in the first mode M801_SS and the second mode M802_SS, the delay of the ramp signals SS (first ramp signal SS1 and second ramp signal SS2) has opposite effects on the displayed image.

[0130] In this manner, the first mode M801_EM / M801_SS (end adjustment mode) and the second mode M802_EM / M802_SS (start adjustment mode) of the transmission control unit 630 of the second pixel unit P1002 can be alternately arranged in time to eliminate the effect of the delay of the transmission enable signal EM and / or the ramp signal SS (first ramp signal SS1 and second ramp signal SS2). In one embodiment, the transmission control unit 630 operates in the first mode M801_EM / M801_SS (end adjustment mode) based on the second ramp signal SS2 (ramp signal) in the first frame F1001, and the transmission control unit 630 operates in the second mode M802_EM / M802_SS (start adjustment mode) based on the first ramp signal SS1 (ramp signal) in the second frame F1002 after the first frame F1001, so that the displayed images of the first frame F1001 and the second frame F1002 will compensate for each other. Therefore, it eliminates the non-uniformity in the displayed image caused by the propagation delay and / or signal distortion of the transmit enable signal EM and / or ramp signal SS, and improves the quality of the displayed image.

[0131] Figure 11A This is a schematic diagram of a pixel array of an electronic device according to an embodiment of the present disclosure. Figure 11B In accordance with this disclosure Figure 11A A schematic diagram of the signal in an embodiment. Figure 11C In accordance with this disclosure Figure 11A A schematic diagram of the signal in an embodiment. Figure 11D In accordance with this disclosure Figure 11A A schematic diagram of the signal in an embodiment. (See reference) Figures 9A to 11D The electronic device includes a pixel array 1100, and the pixel array 1100 includes a plurality of pixel units. The plurality of pixel units are divided into a plurality of first pixel units P1101 and a plurality of second pixel units P1102, and the plurality of first pixel units P1101 and the plurality of second pixel units are interleaved. (Reference) Figure 9A The pixel unit P1101 of the electronic device can be called an inverted type pixel unit, and it is described as follows: Figure 11A The first type, T1, is referenced. Figure 10A The pixel unit P1102 of the electronic device can be called a non-inverting type pixel unit, and it is described as follows: Figure 11AThe second type, T2, is described. Details of the first pixel unit P1101 and the second pixel unit P1102 can be found in [reference needed]. Figure 9A Description of the first pixel unit P901 and Figure 10A The description of the second pixel unit P1002 is omitted here, and details are not described continuously without redundancy. Furthermore, the signals of the first pixel unit P1101 and the second pixel unit P1102 can be described as follows: Figure 11B , Figure 11C and Figure 11D The timing diagrams 1110, 1120 and 1130 shown are arranged as follows.

[0132] In one embodiment, a plurality of pixel units (first pixel unit P1101 and second pixel unit P1102) are configured to receive a plurality of transmit enable signals, a plurality of voltage data, and a common ramp signal, respectively, and the plurality of pixel units are configured to be illuminated during a plurality of transmit cycles according to the plurality of transmit enable signals, the plurality of voltage data, and the ramp signal. In embodiments of this disclosure, the plurality of transmit enable signals, voltage data, and common ramp signal may be provided from a plurality of driving circuits respectively arranged outside or inside the active region of the electronic device via data lines and / or scan lines.

[0133] Furthermore, each of the plurality of first pixel units P1101 includes a first transmission control unit, and each of the plurality of second pixel units P1102 includes a second transmission control unit. Since the first pixel unit P1101 is an inverted type pixel unit (first type T1), the first transmission control unit is configured to receive a first comparison signal (inverted). Similarly, since the first pixel unit P1102 is a non-inverted type pixel unit (second type T2), the second transmission control unit is configured to receive a second comparison signal (non-inverted). That is, the second comparison signal has inverted logic compared to the first comparison signal.

[0134] Furthermore, the first transmission control unit of the first pixel unit P1101 is configured to operate in a first mode based on a common ramp signal, and the second transmission control unit of the second pixel unit P1102 is configured to operate in a second mode different from the first mode based on the common ramp signal. In the embodiment, reference is made to... Figures 5A to 5D as well as Figures 8A to 8DWhen the first pixel unit P1101 (inverting type pixel unit) and the second pixel unit P1102 (non-inverting type pixel unit) operate in different modes (end adjustment mode and start adjustment mode) based on the same ramp signal (common ramp signal), the delay in transmitting the enable signal has opposite effects on the displayed image. Similarly, when the first pixel unit P1101 (inverting type pixel unit) and the second pixel unit P1102 (non-inverting type pixel unit) operate in different modes (end adjustment mode and start adjustment mode) based on the same ramp signal (common ramp signal), the delay in the common ramp signal has opposite effects on the displayed image.

[0135] In this way, the first pixel unit P1101 (inverted type pixel unit) and the second pixel unit P1102 (non-inverted type pixel unit) can be arranged to be spatially staggered to eliminate the effects of the delay of the transmit enable signal and / or common ramp signal.

[0136] In one embodiment, reference Figure 11B During the first frame F1101B and the second frame F1102B following the first frame F1101B, the common ramp signal is the second ramp signal (ramp signal), and therefore the first mode is the start adjustment mode, and the second mode is the end adjustment mode. When the first transmission control unit of the first pixel unit P1101 operates in the first mode (start adjustment mode), the start time of the first turn-on cycle of the first pixel unit is determined based on the common ramp signal being greater than the threshold voltage of the comparator. When the second transmission control unit of the second pixel unit P1102 operates in the second mode (end adjustment mode), the end time of the second turn-on cycle of the second pixel unit is determined based on the common ramp signal being greater than the threshold voltage of the comparator. Therefore, spatial non-uniformity in the displayed image caused by propagation delay and / or signal distortion of the transmission enable signal and / or common ramp signal is eliminated, and the quality of the displayed image is improved.

[0137] In one embodiment, reference Figure 11CDuring the first frame F1101C and the second frame F1102C following the first frame F1101C, the common ramp signal is the first ramp signal (ramp signal), and therefore the first mode is the end adjustment mode, and the second mode is the start adjustment mode. When the first transmission control unit of the first pixel unit P1101 operates in the first mode (end adjustment mode), the end time of the first turn-on cycle of the first pixel unit is determined based on the common ramp signal being less than the threshold voltage of the comparator. When the second transmission control unit of the second pixel unit P1102 operates in the second mode (start adjustment mode), the start time of the second turn-on cycle of the second pixel unit is determined based on the common ramp signal being less than the threshold voltage of the comparator. Therefore, spatial non-uniformity in the displayed image caused by propagation delay and / or signal distortion of the transmission enable signal and / or common ramp signal is eliminated, and the quality of the displayed image is improved.

[0138] Additionally, elimination can be achieved in both time and space. In one embodiment, reference... Figure 11D During the first frame F1101D, the common ramp signal is the second ramp signal (ramp signal), and therefore the first transmit control unit operates in the start adjustment mode (i.e., the first mode is the start adjustment mode), and the second transmit control unit operates in the end adjustment mode (i.e., the second mode is the end adjustment mode). During the second frame F1102D following the first frame F1101D, the common ramp signal is the first ramp signal (ramp signal), and therefore the first transmit control unit operates in the end adjustment mode (i.e., the first mode is the end adjustment mode), and the second transmit control unit operates in the start adjustment mode (i.e., the second mode is the start adjustment mode). Therefore, the non-uniformity in the displayed image caused by the propagation delay and / or signal distortion of the transmit enable signal and / or the common ramp signal is eliminated in both time and space, and the quality of the displayed image is improved.

[0139] It should be noted that the arrangement of the pixel array 1100 is only an exemplary embodiment in which the first pixel unit P1101 and the second pixel unit P1102 are interleaved by pixel units, but this disclosure is not limited thereto. In one embodiment, the first pixel unit P1101 and the second pixel unit P1102 may be interleaved by less than one pixel unit (e.g., half a pixel unit). In one embodiment, the first pixel unit P1101 and the second pixel unit P1102 may be interleaved by two or more pixel units.

[0140] In summary, the electronic device of this disclosure can eliminate non-uniformity in the displayed image caused by propagation delay and / or signal distortion by using temporal and / or spatial compensation for signal arrangement and / or pixel arrangement. As a result, the quality of the displayed image is improved.

[0141] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of this disclosure. In view of the foregoing, it is intended that this disclosure cover modifications and variations, provided that such modifications and variations are within the scope of the appended claims and their equivalents.

Claims

1. An electronic device, characterized in that, include: Light-emitting unit; A current source, configured to output supply current; A voltage comparator configured to receive voltage data and a ramp signal and output a comparison signal based on the voltage data and the ramp signal; as well as A transmission control unit, coupled to the light-emitting unit, the current source, and the voltage comparator, wherein the transmission control unit is configured to receive a transmission enable signal and the comparison signal, and to output a drive current to the light-emitting unit according to the supply current, the transmission enable signal, and the comparison signal. The ramp signal is a first ramp signal during the first frame, and the ramp signal is a second ramp signal during the second frame following the first frame, which is different from the first ramp signal. The transmit control unit is configured to operate in a first mode based on the first ramp signal, and the transmit control unit is configured to operate in a second mode different from the first mode based on the second ramp signal.

2. The electronic device according to claim 1, characterized in that, The duration of the drive current's on-time is determined by the transmit enable signal, voltage data, and the ramp signal.

3. The electronic device according to claim 2, characterized in that, When the transmission control unit operates in the first mode The first ramp signal is a descent signal, and the connection period is the first connection period. The start time of the first connection cycle is determined by the transmit enable signal. The end time of the first turn-on cycle is determined based on the fact that the first ramp signal is less than the threshold voltage of the voltage comparator set using the voltage data.

4. The electronic device according to claim 3, characterized in that, When the transmission control unit operates in the second mode The second ramp signal is a ramp-up signal, and the connection period is the second connection period. The start time of the second turn-on cycle is determined based on the fact that the second ramp signal is greater than the threshold voltage of the voltage comparator set using the voltage data. The end time of the second connection cycle is determined by the transmission enable signal.

5. The electronic device according to claim 4, characterized in that, in The first duration of the first turn-on cycle is adjusted by the first delay of the transmit enable signal and / or the second delay of the first ramp signal. The second duration of the second turn-on cycle is adjusted by the first delay of the transmit enable signal and / or the second delay of the second ramp signal, and The time length of the first time length minus the time length increment of the second time length, or the time length increment of the first time length equals the time length minus the second time length.

6. The electronic device according to claim 1, characterized in that, The voltage comparator further receives a pulse width modulation scan signal and performs voltage programming on the voltage data based on the pulse width modulation scan signal.

7. The electronic device according to claim 6, characterized in that, The voltage comparator includes: A first transistor, wherein a first terminal of the first transistor is coupled to a data line and receives the voltage data, and a control terminal of the first transistor receives the pulse width modulation scan signal; The second transistor, wherein the first terminal of the second transistor receives the ramp signal, the control terminal of the second transistor receives the transmit enable signal, and the second terminal of the second transistor is coupled to the second terminal of the first transistor; A first capacitor, wherein a first terminal of the first capacitor is coupled to a second terminal of the second transistor and a second terminal of the first transistor; A first inverter circuit, wherein the input terminal of the first inverter circuit is coupled to the second terminal of the first capacitor, and the output terminal of the first inverter circuit is coupled to the transmit control unit; and A third transistor, wherein a first terminal of the third transistor is coupled to the input terminal of the first inverter circuit, a control terminal of the third transistor receives the pulse width modulation scan signal, and a second terminal of the third transistor is coupled to the output terminal of the first inverter circuit.

8. The electronic device according to claim 7, characterized in that, The first inverter circuit includes: A fourth transistor, wherein a first terminal of the fourth transistor receives an operating voltage, a control terminal of the fourth transistor is coupled to the input terminal of the first inverter circuit, and a second terminal of the fourth transistor is coupled to the output terminal of the first inverter circuit; and A fifth transistor, wherein the second terminal of the fifth transistor receives a voltage, the control terminal of the fifth transistor is coupled to the input terminal of the first inverter circuit, and the first terminal of the fifth transistor is coupled to the output terminal of the first inverter circuit.

9. The electronic device according to claim 7, characterized in that, The voltage comparator further includes: A second inverter circuit, wherein the input terminal of the second inverter circuit is coupled to the output terminal of the first inverter circuit, and the output terminal of the second inverter circuit is coupled to the transmit control unit.

10. The electronic device according to claim 9, characterized in that, When the transmission control unit operates in the first mode The first ramp signal is a ramp-up signal, and the on-time of the drive current is the first on-time. The start time of the first connection cycle is determined by the transmit enable signal. The end time of the first turn-on cycle is determined based on the fact that the first ramp signal is greater than the threshold voltage of the voltage comparator set using the voltage data.

11. The electronic device according to claim 10, characterized in that, When the transmission control unit operates in the second mode The second ramp signal is a descent signal, and the connection period is the second connection period. The start time of the second turn-on cycle is determined based on the fact that the second ramp signal is less than the threshold voltage of the voltage comparator set using the voltage data. The end time of the second connection cycle is determined by the transmission enable signal.

12. The electronic device according to claim 1, characterized in that, The launch control unit includes: A sixth transistor, wherein the control terminal of the sixth transistor is coupled to the voltage comparator; A seventh transistor, wherein a first terminal of the seventh transistor is coupled to an operating voltage, a control terminal of the seventh transistor receives the transmit enable signal, and a second terminal of the seventh transistor is coupled to a first terminal of the sixth transistor; An eighth transistor, wherein a first terminal of the eighth transistor is coupled to a second terminal of the sixth transistor, a control terminal of the eighth transistor is coupled to the voltage comparator, and a second terminal of the eighth transistor is coupled to a voltage. A ninth transistor, wherein a first terminal of the ninth transistor is coupled to a second terminal of the sixth transistor, a control terminal of the ninth transistor receives the transmit enable signal, and a second terminal of the ninth transistor is coupled to the voltage; and A tenth transistor, wherein a first terminal of the tenth transistor is coupled to the current source, a control terminal of the tenth transistor is coupled to the second terminal of the sixth transistor, and the second terminal of the tenth transistor is coupled to the light-emitting unit.

13. The electronic device according to claim 1, characterized in that, The current source further receives a pulse amplitude modulated scan signal for voltage programming.

14. The electronic device according to claim 13, characterized in that, The current source mentioned above includes: The eleventh transistor, wherein the first terminal of the eleventh transistor is coupled to the data line and receives the voltage data, and the control terminal of the eleventh transistor receives the pulse amplitude modulation scan signal; A twelfth transistor, wherein a first terminal of the twelfth transistor receives an operating voltage, a control terminal of the twelfth transistor is coupled to a second terminal of the eleventh transistor, and the second terminal of the twelfth transistor is coupled to the transmit control unit; and A second capacitor, wherein a first terminal of the second capacitor is coupled to a second terminal of the eleventh transistor, and a second terminal of the second capacitor is coupled to a first terminal of the twelfth transistor.

15. The electronic device according to claim 11, characterized in that, in The first duration of the first turn-on cycle is adjusted by the first delay of the transmit enable signal and / or the second delay of the first ramp signal. The second duration of the second turn-on cycle is adjusted by the first delay of the transmit enable signal and / or the second delay of the second ramp signal, and The time length of the first time length minus the time length increment of the second time length, or the time length increment of the first time length equals the time length minus the second time length.

16. An electronic device, characterized in that, include: A pixel array includes multiple pixel units, wherein the multiple pixel units are divided into multiple first pixel units and multiple second pixel units, and the multiple first pixel units and the multiple second pixel units are interleaved. The plurality of pixel units are configured to receive a plurality of transmit enable signals, a plurality of voltage data, and a common ramp signal, respectively, and the plurality of pixel units are configured to be illuminated during a plurality of transmit cycles according to the plurality of transmit enable signals, the plurality of voltage data, and the common ramp signal. Each of the plurality of first pixel units includes a first emission control unit, and each of the plurality of second pixel units includes a second emission control unit. The first transmission control unit is configured to receive a first comparison signal, and the second transmission control unit is configured to receive a second comparison signal, wherein the second comparison signal has inverse logic to the first comparison signal. The first transmit control unit is configured to operate in a first mode based on the common ramp signal, and the second transmit control unit is configured to operate in a second mode different from the first mode based on the common ramp signal.

17. The electronic device according to claim 16, characterized in that, in The common ramp signal is an ascending ramp signal, the first mode is the start adjustment mode, and the second mode is the end adjustment mode. When the first transmission control unit operates in the first mode, the start time of the first turn-on cycle of the first pixel unit is determined based on the common ramp signal being greater than the threshold voltage of the voltage comparator set using the voltage data, and the end time of the first turn-on cycle is determined by the transmission enable signal. When the second transmission control unit operates in the second mode, the end time of the second turn-on cycle of the second pixel unit is determined based on the common ramp signal being greater than the threshold voltage, and the start time of the second turn-on cycle is determined by the transmission enable signal.

18. The electronic device according to claim 16, characterized in that, in The common slope signal is a descent signal, the first mode is the end of adjustment mode, and the second mode is the start of adjustment mode. When the first transmission control unit operates in the first mode, the start time of the first turn-on cycle of the first pixel unit is determined by the transmission enable signal, and the end time of the first turn-on cycle of the first pixel unit is determined based on the fact that the common ramp signal is less than the threshold voltage of the voltage comparator set by the voltage data. When the second transmission control unit operates in the second mode, the start time of the second turn-on cycle of the second pixel unit is determined based on the common ramp signal being less than the threshold voltage, and the end time of the second turn-on cycle is determined by the transmission enable signal.

19. The electronic device according to claim 16, characterized in that, in During the first frame, the common ramp signal is a ramp-up signal, the first mode is the start adjustment mode, and the second mode is the end adjustment mode. During the second frame following the first frame, the common ramp signal is a descent signal, the first mode is the end adjustment mode, and the second mode is the start adjustment mode.

Images