Narrow frame array circuit, driving method and display device

Abstract

The present invention provides a narrow-border array circuit, a driving method, and a display device. The narrow-border array circuit includes a display circuit including pixel units arranged in an array; a control circuit including a GIA unit, multiple scan lines, and multiple data lines, wherein the intersections of the multiple scan lines and the multiple data lines connect the pixel units of the display circuit. Multiple data lines are provided between adjacent pixel units in the same row of the array, each data line intersecting with a different scan line. The data lines connect at least one pixel unit in the same row, and adjacent pixel units in the same row are connected to different data lines. In the narrow-border array circuit, driving method, and display device of the present invention, even if a scan line is disconnected for some reason, the corresponding display unit can still be activated via another data line and the remaining scan line portion, thereby ensuring the operational stability of the entire display device.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a narrow-frame array circuit, a driving method, and a display device. Background Art

[0002] With the development of display technology, flat-panel display devices such as liquid crystal displays (LCDs) have been widely used in various consumer electronic products such as mobile phones, televisions, personal digital assistants, digital cameras, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream display device.

[0003] Display devices currently on the market are typically triple-gate products. Due to pixel layout limitations, the GIA units in triple-gate products are typically arranged horizontally, leaving little vertical space but occupying more horizontal space. This increases the distance between the left and right sides of the substrate, and consequently, the bezel area. This type of display device is clearly unsuitable for the development of narrow-bezel products. Furthermore, if the gate breaks first, triple-gate products are unable to self-repair, resulting in malfunction. Summary of the Invention

[0004] The purpose of the present invention includes providing a narrow-border array circuit to solve the problem in the prior art that narrow-border products are difficult to operate normally after a single gate line is broken.

[0005] The present invention provides a narrow-frame array circuit, comprising a display circuit and pixel units distributed in an array;

[0006] A control circuit comprising a GIA unit, a plurality of scan lines, and a plurality of data lines, wherein intersections of the plurality of scan lines and the plurality of data lines are connected to the pixel units of the display circuit;

[0007] Among them, multiple data lines are arranged between adjacent pixel units in the same row distributed in an array, each data line intersects with a different scan line, the data line connects at least one pixel unit in the same row, and adjacent pixel units in the same row are connected to different data lines.

[0008] Furthermore, the scan line includes two scan sub-lines, and the scan sub-lines are cross-connected with the data line; two adjacent scan sub-lines belong to two different scan lines.

[0009] Furthermore, the scan line includes two scan sub-lines, and the scan sub-lines are cross-connected with the data line; the two scan sub-lines belonging to the same scan line are adjacent.

[0010] Furthermore, the scan line is disconnected between adjacent target positions, and the target positions are intersections between the plurality of data lines and the scan line between the adjacent pixel units; and one scan line is only allowed to be disconnected at one position.

[0011] Furthermore, the scan line includes two scan sub-lines, the scan sub-lines are cross-connected with the data line, and the scan sub-lines are disconnected between adjacent target positions to form a connection point;

[0012] connecting in series the connection points corresponding to the plurality of scanning sub-lines belonging to the same scanning line;

[0013] The target position is an intersection between a plurality of the data lines and the scan lines between adjacent pixel units; and one scan sub-line is allowed to be disconnected at only one point.

[0014] Furthermore, for the connection points in the scan sub-lines belonging to the same scan line, two connection points on the same side are selected for series connection.

[0015] Furthermore, the number of the data lines between adjacent pixel units is 2, and the scan line is connected to the GIA unit.

[0016] Furthermore, the distance between the two data lines passing through the two connection points on the same scanning sub-line is greater than the distance between the two data lines between other adjacent pixel units.

[0017] The present invention further provides a driving method, which is used for any of the above-mentioned narrow-border array circuits;

[0018] When a scan line is broken, the signal will automatically be transmitted from another parallel scan line to the pixel unit when entering the narrow-border array circuit.

[0019] The present invention further provides a display device, comprising any one of the above-mentioned narrow-border array circuits.

[0020] Beneficial effects of the present invention:

[0021] In this case, multiple data lines are set up between pixel units to ensure that if one data line fails, another data line can still work; if a scan line is disconnected for some reason, the corresponding display unit can still be activated through another data line and the remaining scan line part, ensuring the operational stability of the entire display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a schematic structural diagram of a narrow-border array circuit according to a first embodiment of the present invention;

[0023] Figure 2 2 is a schematic structural diagram of an existing narrow-border array circuit in a first embodiment of the present invention;

[0024] Figure 3 This is a schematic structural diagram of a narrow-border array circuit in a second embodiment of the present invention;

[0025] Figure 4 This is a schematic structural diagram of a narrow-border array circuit in which only the G1 line is disconnected according to a third embodiment of the present invention;

[0026] Figure 5 This is a schematic structural diagram of a narrow-border array circuit in which G lines are completely disconnected in a third embodiment of the present invention;

[0027] Figure 6 2 is a schematic structural diagram of another narrow-border array circuit with all G lines disconnected in the third embodiment of the present invention. DETAILED DESCRIPTION

[0028] To further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the following, in conjunction with the accompanying drawings and preferred embodiments, describes in detail the specific implementation methods, methods, steps, structures, features and effects of a narrow-border array circuit and display device proposed in accordance with the present invention.

[0029] The aforementioned and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the accompanying drawings. Through the description of the specific embodiments, a deeper and more detailed understanding of the technical means and effects adopted by the present invention to achieve the intended objectives can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the present invention.

[0030] A first embodiment of the present invention provides a narrow-border array circuit. Figure 1 FIG. 1 is a schematic structural diagram of a narrow-border array circuit according to a first embodiment of the present invention. Figure 1 As shown, it includes: a display circuit 10, including pixel units 101 distributed in an array; a control circuit 20, including a GIA unit 201, multiple scan lines G, and multiple data lines S, wherein the intersections of the multiple scan lines G and the multiple data lines S are connected to the pixel units of the display circuit 10; wherein, multiple data lines S are arranged between adjacent pixel units 101 in the same row distributed in an array, each data line intersects with a different scan line, and the data lines are connected to at least one pixel unit in the same row, and adjacent pixel units in the same row are connected to different data lines.

[0031] Figure 1 In the embodiment, all pixel units 101 are distributed in an array, and the specific classification of the pixel units 101 can be one or more ( Figure 1 In the figure, a and b are each a pixel unit. The control circuit 20 includes a GIA unit, multiple scan lines, and multiple data lines. The GIA unit 201 is generally disposed on both sides of the display circuit 10. Multiple scan lines (i.e., G lines, gate lines) intersect with multiple data lines (i.e., S lines, source lines). The pixel units 101 in the display circuit 10 are connected to the intersections.

[0032] Refer to the common Figure 2 The array circuit diagram shown is Figure 2 FIG. 1 is a schematic structural diagram of an existing narrow-border array circuit in the first embodiment of the present invention. Figure 2 As shown, it can be seen that in this case Figure 1 In the pixel units 101 distributed in an array, multiple data lines (ie, S lines, source lines) are additionally provided between two adjacent pixel units 101 in the same row. Preferably, two data lines (ie, S lines, source lines) are provided.

[0033] Then in actual applications, each data line intersects with different scan lines, each scan line connects all different data lines, each data line connects at least one pixel unit in the same row, and the adjacent pixel units 101 in the same row are connected to different data lines. For example, two data lines linα and linβ are set between pixel unit a and pixel unit b, pixel point a is connected to linα, pixel point b is connected to linβ, and linα and linβ are connected to the same scan line; at this time, if linα fails, then the pixel unit originally connected to linα will be automatically regarded as connected to linβ through the scan line. In other words, when linα fails, linβ can directly connect pixel point a (newly added) and pixel point b, and assume the work content of linα; corresponding to this case, pixel unit a is equivalent to Figure 1 The first pixel unit a in the first row and pixel unit b are equivalent to Figure 1 For the second pixel unit a in the first row, linα is equivalent to S2, and linβ is equivalent to S3. Even if one of the two data lines between the two pixel units 101 fails, the other data line can still perform this step.

[0034] Moreover, if a scan line is broken, that is, the Gate line is broken, then the signal will not be Figure 2 When the circuit shown in the figure is used, the signal cannot be transmitted to the corresponding pixel unit. Figure 1 When the circuit shown is used, the signal will be automatically transmitted to the pixel unit 101 through another interface, thereby ensuring the normal operation of the pixel unit 101 and improving the stability of the array circuit in the implementation process.

[0035] In some examples, the array distribution of the pixel units 101 of the display circuit 10 follows a pixel arrangement rule.

[0036] Specifically, based on the existing triple-gate product, the pixel units 101 of the display circuit 10 are arranged vertically. The corresponding triple-gate product is reordered using the pixel rule, reducing the number of vertical source lines from three to one, saving two-thirds of the gate ICs. This increases the space for the GIA layout within the narrow-frame array circuit, making it more conducive to narrow-frame designs. The addition of source lines also increases the charging time of a single GIA gate row, improving the vulnerability of insufficient charging in low temperatures.

[0037] In some examples, such as Figure 1 As shown, the scan line includes two scan sub-lines, and the scan sub-lines are cross-connected with the data line; two adjacent scan sub-lines belong to two different scan lines.

[0038] Specifically, scan lines are typically configured as gate lines. In this case, the same gate line is split into two branches (i.e., scan sub-lines). For example, G1 is divided into a sub-line G1a below the first row of pixel cells a in the figure, and another sub-line G1a' below the third row of pixel cells a. Thus, the GIA unit on the left can transmit signals to the pixel cells via the upper G1a or the lower G1a'. Similarly, the GIA unit on the right can transmit signals to the pixel cells via the upper G1a or the lower G1a'. The upper G1a and lower G1a' are then connected to the G1 line at both ends, thereby enabling the gate line G1 to circulate within the display circuit area.

[0039] For the G line arrangement, there are the following situations: two adjacent scanning sub-lines belong to two different scanning lines, for example Figure 1 From top to bottom, the scan lines G connected to each row of pixel units are: G1-G2-G1-G2-G3-G4-G3-G4. This allows the pixel units of the display unit to be fed with the same signal every other row, saving space and facilitating the design of narrow-edge products.

[0040] A second embodiment of the present invention provides a narrow-border array circuit. The difference between the narrow-border array circuit in this embodiment and the first embodiment lies in the arrangement of G lines.

[0041] Figure 3 FIG. 1 is a schematic structural diagram of a narrow-border array circuit in a second embodiment of the present invention. Figure 3As shown, the scan line G includes two scan sub-lines, and the scan sub-line G is cross-connected with the data line S; the two scan sub-lines belonging to the same scan line are adjacent.

[0042] Specifically, scan lines are usually configured as gate lines. In this case, the same gate line is divided into two branches. For example, G1 is divided into a sub-line G1a under the first row of pixel units a and another sub-line G1a' under the second row of pixel units a.

[0043] In this way, the GIA unit on the left can transmit signals to the pixel unit through the upper G1a or the lower GIa'. Similarly, the GIA unit on the right can transmit signals to the pixel unit through the upper G1a or the lower GIa'. The upper G1a and the lower GIa' are connected to the G1 line at both ends, thus looping the gate line G1 within the display circuit area. Even if a scan sub-line accidentally breaks, in this case, the signal can still be transmitted to the pixel unit by looping around another scan sub-line belonging to the same scan line.

[0044] In this case, two scanning sub-lines originating from the same G line are set to be adjacent. Figure 3 In the figure, from top to bottom, the scan lines G connected to each row of pixel units are: G1-G1-G2-G2-G3-G3-G4-G4. The pixel units of the display unit can be used to provide different signals to every other row, and two identical signals can appear in adjacent rows.

[0045] A third embodiment of the present invention provides a narrow-border array circuit. The narrow-border array circuit in this embodiment differs from that in the first embodiment in the arrangement of G lines.

[0046] Figure 4 FIG. 1 is a schematic structural diagram of a narrow-border array circuit in which only the G1 line is disconnected in the third embodiment of the present invention. Figure 4 As shown, the scan line G includes two scan sub-lines, which are cross-connected with the data line S. The scan sub-lines are disconnected between target positions, which are intersections between multiple data lines between adjacent pixel units and two scan sub-lines belonging to the same scan line; and only one disconnection is allowed in the same row for one scan sub-line.

[0047] Preferably, there are two parallel data lines between adjacent pixel units in the same row.

[0048] Specifically, multiple data lines (i.e., S lines) are set between two adjacent pixel units, and the intersections of the data lines between adjacent pixel units and two scanning sub-lines belonging to the same scanning line are set as connection points. The target position for disconnecting the scanning sub-lines must be between the connection points.

[0049] Therefore, each row of G lines can be split into left and right sides by the target position. The G lines in the left area can form a loop and connect to the GIA unit on the left, ensuring the normal operation of the pixel units in the left area. The G lines in the right area can form a loop and connect to the GIA unit on the right, ensuring the normal operation of the pixel units in the left area. This achieves separate control of the left and right areas of the target position, realizing a two-split screen.

[0050] It is worth mentioning that the two scanning sub-lines belonging to the same scanning line are disconnected synchronously, so that the pixel units on the left and right sides of the target position can be controlled separately.

[0051] For example, there are two data lines S2 and S3 between the first row, first column, and second column pixel units. The intersections of data lines S2 and S3 with the first row G1 are two connection points, and the intersections of data lines S2 and S3 with the second row G1 are also two connection points. The G1 line is disconnected between the two connection points in the first row, and at the same time, the G1 line is also disconnected between the two connection points in the second row. In this way, the left part of the G1 line is the left loop of the G1 line in the bold part, and the right part of the G1 line is the right loop of the G1 line. In this case, the switching states of the pixel units in the first row can be different, that is, in the pixel units in the first row, the switching states of the first pixel unit are different from those of the second, third, and fourth pixel units, presenting a separate display effect.

[0052] Since only one scanning sub-line in the same row is allowed to be disconnected, two scanning sub-lines belonging to the same scanning line are disconnected synchronously. Therefore, in actual application, a two-screen display is adopted for the application display of the display device.

[0053] Figure 5 Schematic diagram of a narrow-border array circuit with all G lines disconnected in the third embodiment of the present invention. In some examples, such as Figure 5 As shown, the target positions where each scan line is disconnected can be arranged in a row.

[0054] That is, each scan line is disconnected between the same data lines; Figure 5As shown, the two scan sub-lines of G1 are disconnected between the connection point of S4 and S5. The two scan lines of G2 are also disconnected between the connection point of S4 and S5. The two scan lines of G3 are also disconnected between the connection point of S4 and S5. The two scan lines of G4 are also disconnected between the connection point of S4 and S5. This achieves the G line disconnection in the same column of this narrow-border array circuit, realizing a two-part screen split between the left and right halves. In this embodiment, the preferred arrangement is to disconnect different G lines between the same two data lines, and these two data lines are located between adjacent pixel modules. To this end, this embodiment saves space as much as possible, reduces the complexity of the newly added circuits, and facilitates circuit layout.

[0055] The present application also discloses a driving method for driving the narrow-border array circuit described above; when a scan line G line is broken, the signal will automatically be transmitted from another parallel scan line G line to the pixel unit when entering the narrow-border array circuit.

[0056] In some examples, Figure 6 FIG. 1 is a schematic structural diagram of another narrow-border array circuit in which the G lines are all disconnected in the third embodiment of the present invention. Figure 6 As shown, the scan line includes two scan sub-lines, which are cross-connected with the data line. The scan sub-lines are disconnected between adjacent target positions to form connection points. The connection points corresponding to multiple scan sub-lines belonging to the same scan line are connected in series.

[0057] The target position is an intersection between a plurality of data lines and the scan line between the adjacent pixel units; and one scan sub-line is only allowed to be disconnected at one point.

[0058] For example, Figure 6 As shown, there are two data lines S4 and S5 between the second and third pixel units in the first row, and the two scanning sub-lines of the G1 line form two connection points with S4 and S5 respectively. The scanning sub-line is disconnected between these two connection points, that is, the upper half of the scanning sub-line of G1 is disconnected between S4 and S5, and the lower half of the scanning sub-line of G1 is also disconnected synchronously between S4 and S5.

[0059] In addition, the four connection points belonging to the G1 line are connected in series according to the data lines. Specifically, if the two left segments of the scan sub-lines where the connection points are located intersect with S4, the two connection points are connected in series vertically; if the two right segments of the scan sub-lines where the connection points are located intersect with S5, the two connection points are connected in series vertically.

[0060] This solution effectively adds two source line segments between S4 and S5, increasing the space between them. Consequently, the distance between two data lines passing through two connection points on the same scan sub-line is larger than the distance between two data lines between other adjacent pixel units. This increases the width of the gap between S4 and S5 to reduce interference between the data lines.

[0061] A fourth embodiment of the present invention provides a display device, which includes any one of the above-mentioned narrow-border array circuits.

[0062] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any technician familiar with this profession can make some changes or modifications using the technical content disclosed above without departing from the scope of the technical solution of the present invention. Any modifications, equivalent replacements or improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A narrow-frame array circuit, characterized in that: include: A display circuit including pixel units distributed in an array; A control circuit comprising a GIA unit, a plurality of scan lines, and a plurality of data lines, wherein intersections of the plurality of scan lines and the plurality of data lines are connected to the pixel units of the display circuit; Wherein, a plurality of data lines are arranged between adjacent pixel units in the same row distributed in an array, each data line intersects with a different scan line, the data lines connect at least one pixel unit in the same row, and adjacent pixel units in the same row are connected to different data lines; The scan line includes a plurality of scan sub-lines, the scan sub-lines are cross-connected with the data lines, and the scan sub-lines are disconnected between adjacent target positions to form connection points; Connecting in series the connection points corresponding to a plurality of scanning sub-lines belonging to the same scanning line; The target position is an intersection between a plurality of the data lines and the scan lines between adjacent pixel units; and one scan sub-line is allowed to be disconnected at only one point.

2. The narrow-border array circuit according to claim 1, wherein: The scan line includes two scan sub-lines, and the scan sub-lines are cross-connected with the data line; two adjacent scan sub-lines belong to two different scan lines.

3. The narrow-border array circuit according to claim 1, wherein: The scan line includes two scan sub-lines, and the scan sub-lines are cross-connected with the data line; the two scan sub-lines belonging to the same scan line are adjacent to each other.

4. The narrow-border array circuit according to claim 1, wherein: The scanning line includes two scanning sub-lines, and the connection points of the scanning sub-lines belonging to the same scanning line are selected to be connected in series at two connection points on the same side.

5. The narrow-border array circuit according to any one of claims 1 to 4, characterized in that: The number of the data lines between adjacent pixel units is 2, and the scan line is connected to the GIA unit.

6. The narrow-border array circuit according to claim 4, wherein: The distance between the two data lines passing through two connection points on the same scanning sub-line is greater than the distance between the two data lines between other adjacent pixel units.

7. A driving method, characterized in that: The driving method is used to drive the narrow-border array circuit according to any one of claims 1 to 6; When a scan line is broken, the signal will automatically be transmitted from another parallel scan line to the pixel unit when entering the narrow-border array circuit.

8. A display device, characterized in that: The display device includes a narrow-border array circuit according to any one of claims 1 to 6.

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