Transmission method using ldpc code of row orthogonal structure and device therefor

Abstract

The present invention relates to a transmission method using LDPC codes with row-orthogonal structure and a device therefor. A method for encoding a quasi-cyclic low density parity check (LDPC) code according to an embodiment of the present invention can include the steps of generating a multi-edge LDPC code matrix including a high-rate code matrix and a single parity check code matrix; and encoding a signal using the multi-edge LDPC code matrix, wherein the single parity check code matrix is formed by concatenating a first matrix having a non-row-orthogonal structure matrix and a second matrix having a pure row-orthogonal structure.

Description

[0001] This application is a divisional application of patent application No. 201880002810.7 (PCT / KR2018 / 001505), filed with the China Patent Office on January 11, 2019, with an international application date of February 5, 2018, entitled "A method for transmitting LDPC codes using row orthogonal structures and an apparatus for the same". Technical Field

[0002] This invention relates to wireless local area network (LAN) systems, and more particularly to a method for transmitting LDPC codes using a row orthogonal structure in a system supporting low-density parity-check (LDPC) codes, and an apparatus for supporting such transmission. Background Technology

[0003] Wireless access systems have been widely deployed to provide a wide variety of communication services, such as voice and data communication services. Typically, a wireless access system is a multiple access system capable of supporting communication with multiple users by sharing available system resources (e.g., bandwidth, transmission power). For example, multiple access systems can include one of the following: Code Division Multiple Access (CDMA), Frequency Division Multiple Access (FDMA), Time Division Multiple Access (TDMA), Orthogonal Frequency Division Multiple Access (OFDMA), Single-Carrier Frequency Division Multiple Access (SC-FDMA), and Multi-Carrier Frequency Division Multiple Access (MC-FDMA).

[0004] In broadcast systems and the communication systems described above, channel codes must be used. As an example of a general configuration method for channel codes, a transmitter can encode input symbols using an encoder and transmit the encoded symbols. A receiver, for example, can receive the encoded symbols and decode them to recover the input symbols. In this case, the size of the input symbols and the size of the encoded symbols can be defined differently depending on the communication system. For example, in the turbo codes used for data transmission in the 3GPP Long Term Evolution (LTE) communication system, the size of the input symbols is up to 6144 bits, while the size of the encoded symbols is 18432 (6144 * 3) bits. For turbo coding in LTE communication systems, refer to 3GPP Technical Specification 36.212.

[0005] However, even with increased signal-to-noise ratio (SNR), LTE turbo codes, due to their structure, are characterized by performance improvements that do not significantly deviate from the predetermined range. While using codes with low error rates could address this issue, it would increase complexity.

[0006] In communication systems, high bit error rates can necessitate unnecessary data retransmissions and lead to channel reception failures. Furthermore, excessively complex codes increase the overhead of base stations (BS) and user equipment (UE), and cause transmission and reception delays. These problems need to be addressed, especially in future-generation communication systems that require faster data transmission and reception. Therefore, a coding method with low complexity while reducing bit error rates is needed.

[0007] Specifically, regarding fifth-generation (5G) mobile communication technology, the technology being discussed is Ultra-Reliable and Low-Latency Communication (URLLC). URLLC requires the error rate plane to be 10... -5 Or a lower block error rate (BLER) may occur. Here, error flooring means a point where the error rate decreases slightly despite an increase in information volume. In LTE turbo codes, error flooring increases with information volume by 10... -4 Or even lower BLERs may occur. Therefore, LDPC codes can be used as an alternative to turbo codes. LDPC codes can achieve low bit error rates with relatively low complexity. To use LDPC codes effectively, a method for selecting the basic code from a variety of LDPC codes needs to be determined. Summary of the Invention

[0008] Technical issues

[0009] The technical objective of this invention is to provide a method for transmitting LDPC codes suitable for a given communication environment in a wireless LAN system using LDPC codes.

[0010] Another technical objective of this invention is to provide a method for generating row orthogonal LDPC code structures that can be used in wireless LAN systems employing multiple LDPC codes.

[0011] This invention is not limited to the content specifically described above, and other technical objectives can be derived from the embodiments of this invention.

[0012] Technical solution

[0013] According to one aspect of the invention, the above and other objectives can be achieved by providing a method for encoding using quasi-cyclic low-density parity-check (LDPC) codes. The method includes generating a polygonal LDPC code matrix comprising a high-ratio code matrix and a single parity-check code matrix; and encoding a signal using the polygonal LDPC code matrix, wherein the single parity-check code matrix is ​​formed by concatenating a first matrix configured with a non-row orthogonal structure matrix and a second matrix configured with a pure row orthogonal structure matrix.

[0014] According to another aspect of the invention, an apparatus is provided for encoding using quasi-cyclic low-density parity-check (LDPC) codes. The apparatus includes a transceiver and a processor. The processor is configured to generate a polygonal LDPC code matrix comprising a high-ratio code matrix and a single parity-check code matrix, and to encode a signal using the polygonal LDPC code matrix, wherein the single parity-check code matrix is ​​formed by concatenating a first matrix configured with a non-row orthogonal structure matrix and a second matrix configured with a pure row orthogonal structure matrix.

[0015] The following contents can be applied together to the methods and apparatus described above for encoding LDPC codes.

[0016] The first matrix may include edges with the same column values ​​for consecutive rows, and the second matrix may not include edges with the same column values ​​for consecutive rows.

[0017] The first matrix may include a number of rows having a first value, and the second matrix may include a number of rows having a second value. The first and second values ​​may be determined based on the total number of rows in the single parity check code matrix and the minimum code rate of the multilateral LDPC code.

[0018] The first value can be determined by the product of the total number of rows in the single parity check matrix and the minimum code rate, and the second value can be determined by subtracting the first value from the total number of rows in the single parity check matrix.

[0019] The first matrix may include a number of rows having a first value, and the second matrix may include a number of rows having a second value. The first and second values ​​may be determined to assign the second matrix to rows starting from the row with a preset code rate in the single parity check matrix.

[0020] The first matrix can be configured with 22 rows and the second matrix can be configured with 20 rows.

[0021] The high bitrate matrix can be configured with a 7×17 matrix structure, and the high bitrate matrix can include a 4×4 structure of a double diagonal parity matrix.

[0022] Beneficial effects

[0023] According to one embodiment of the present invention, LDPC codes can be generated using LDPC codes suitable for various communication environments.

[0024] According to another embodiment of the present invention, LDPC codes can be transmitted without system performance degradation using a partially row orthogonal LDPC code structure.

[0025] Other technical effects besides those described above can be derived from the embodiments of the present invention. Attached Figure Description

[0026] Figure 1 This is a flowchart illustrating an exemplary encoding process.

[0027] Figure 2 This is a diagram illustrating an exemplary transport block (TB) encoding process.

[0028] Figure 3 This is a diagram illustrating an exemplary recursive system convolutional (RSC) encoder.

[0029] Figure 4 This is a diagram illustrating the LTE turbo encoder.

[0030] Figure 5 This is a diagram illustrating an exemplary grid (trellis) based on an RSC encoder.

[0031] Figure 6 This is a diagram illustrating an exemplary grid structure.

[0032] Figure 7 This is a diagram illustrating an exemplary structured parity check matrix.

[0033] Figure 8 This is a diagram illustrating an exemplary model matrix.

[0034] Figure 9 It is a diagram used to explain matrix transformations based on the number of shifts.

[0035] Figure 10 This is a flowchart illustrating an exemplary LDPC code decoding method.

[0036] Figure 11 This is an example diagram of a bipartite graph.

[0037] Figure 12 This is a diagram illustrating the structure of an LDPC code according to an embodiment of the present invention.

[0038] Figure 13 This is a diagram illustrating an exemplary rate matching process.

[0039] Figure 14 This is a diagram used to explain the structure of LDPC codes that use row orthogonal structures.

[0040] Figure 15 This is a diagram used to explain the partial row orthogonal LDPC code structure that can be used in some embodiments of the present invention.

[0041] Figure 16This is a diagram illustrating a partial row orthogonal LDPC code structure according to an embodiment of the present invention.

[0042] Figure 17 This is a diagram illustrating another partially row orthogonal LDPC code structure according to an embodiment of the present invention.

[0043] Figure 18 This is a diagram illustrating a partial row orthogonal LDPC code structure according to another embodiment of the present invention.

[0044] Figure 19 These are diagrams used to explain the apparatus according to embodiments of the present invention. Detailed Implementation

[0045] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. The detailed description given below in conjunction with the accompanying drawings is intended as a description of exemplary embodiments and is not intended to represent only embodiments through which the concepts explained in these embodiments can be practiced.

[0046] This detailed description includes details for the purpose of providing an understanding of the invention. However, it will be apparent to those skilled in the art that these teachings can be practiced and carried out without these specific details. In some instances, well-known structures and devices have been omitted to avoid obscuring the concept of the invention, and the essential functions of structures and devices are shown in block diagram form.

[0047] The following technologies can be applied to various radio access systems using Code Division Multiple Access (CDMA), Frequency Division Multiple Access (FDMA), Time Division Multiple Access (TDMA), Orthogonal Frequency Division Multiple Access (OFDMA), and Single Carrier Frequency Division Multiple Access (SC-FDMA). CDMA can be implemented using radio technologies such as Universal Terrestrial Radio Access (UTRA) and CDMA 2000. TDMA can be implemented using radio technologies such as Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), and Enhanced Data Rate GSM Evolution (EDGE). OFDMA can be implemented using radio technologies such as IEEE 802.11 (Wi-Fi), IEEE 802.16 (WiMAX), IEEE 802.20, and Evolved UTRA (E-UTRA). UTRA is part of the Universal Mobile Telecommunications System (UMTS). The 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) is the part of Evolved UMTS (E-UMTS) that uses E-UTRA. 3GPP LTE uses OFDMA in the downlink and SC-FDMA in the uplink. Advanced LTE (LTE-A) is an evolution of 3GPP LTE.

[0048] For clarity, the following description primarily relates to 3GPP LTE / LTE-A systems. However, the technical concept of the invention is not limited thereto. Specific terminology used in the following description is provided to aid in understanding the invention. These specific terms may be replaced by other terms within the spirit and scope of the invention.

[0049] Figure 1 This is a flowchart illustrating an exemplary encoding process.

[0050] like Figure 1 The encoding process shown can be applied to various channel codes, including turbo codes used in LTE communication systems. For ease of description, this encoding process will henceforth be described using terminology according to the standard specifications of LTE communication systems.

[0051] exist Figure 1 In the example, the transmitter can generate a transport block (TB) (step S101). The transmitter adds cyclic redundancy check (CRC) bits for the TB (step S102). The transmitter can generate code blocks from the TB with the CRC bits added (step S103). For example, the transmitter can divide the TB into code blocks based on the encoder's input size. The transmitter can add CRC bits to each divided code block (step S104). In this case, the size of the code block and the code block CRC bits can be 6144 bits. The transmitter can perform encoding and modulation with respect to each block consisting of the code block and the code block CRC bits (step S105). For example, turbo encoding can be applied as described previously.

[0052] The decoding process can be... Figure 1 The encoding process is performed in reverse order. For example, the receiver can use a decoder corresponding to each encoder to decode each code block, configure a final TB, and perform CRC verification on that TB.

[0053] For example, the size of the input symbol may differ from the size of the TB from the Media Access Control (MAC) layer. If the size of the TB is greater than the maximum size of the input symbol for the turbo code, the TB can be divided into multiple code blocks (CBs). According to the LTE communication system standard, the size of the CB can be equal to the value obtained by subtracting the CRC bits from 6144 bits. The input symbol for the turbo code can be defined as data including CB and CRC, or data including TB (e.g., the size of TB is less than 6144 bits) and CRC. The CRC bits are significantly smaller than 6144 bits (e.g., the maximum CRC bits are 24 bits). Therefore, in the following description, CB can refer to CB itself or CB and the corresponding CRC bits, and TB can refer to TB itself or TB and the corresponding CRC bits, unless otherwise defined.

[0054] Figure 2 This is a diagram illustrating an exemplary TB encoding process.

[0055] Figure 2 The diagram illustrates the above information. Figure 1 The described encoding process corresponds to the encoding process of TB 201. First, TB CRC 202 is added to TB 201. TB CRC 202 can be used to verify TB 201 during the decoding process. Next, TB 201 and TB CRC 202 are divided into three CBs 203. In this embodiment, although TB ​​201 and TB CRC 202 are divided into three CBs 203, TB 201 can be divided into multiple CBs based on the input size of encoder 205.

[0056] CB CRC 204 is added to the corresponding CB 203. CB CRC 204 can be used by the receiver to acknowledge CB 203. CB 203 and CB CRC 204 can be encoded by the corresponding encoder 205 and the corresponding modulator 205.

[0057] Figure 3 This is a diagram illustrating an exemplary recursive system convolutional (RSC) encoder.

[0058] Figure 3 The RSC encoder 300 can be used for turbo encoding. Figure 3 In this code, m represents the input data, C1 represents the system bitstream, and C2 represents the encoded bitstream. Here, the RSC encoder 300 has a bit rate of 1 / 2.

[0059] The RSC encoder 300 can be configured to feed the encoded output back to the input of a non-recursive, non-systematic convolutional encoder. Figure 3 In one embodiment, encoder 300 includes two delayers. The value D of each delayer can be determined according to the encoding scheme. The delayers can be configured by memory or shift registers.

[0060] Figure 4 This is a diagram illustrating the LTE turbo encoder.

[0061] The encoding scheme of the LTE turbo encoder 400 uses parallel concatenated convolutional codes (PCCC) implemented by two 8-state encoders 410 and 420 and a turbo code internal interleaver 430.

[0062] exist Figure 4In the turbo encoder 400, a first component encoder 410, a second component encoder 420, and a turbo code internal interleaver 430 are included. The first component encoder 410 and the second component encoder 420 are 8-state component encoders. Each of the first component encoder 410 and the second component encoder 420 has a similar... Figure 3 The structure of the RSC encoder. The first component encoder 410 and the second component encoder 420 respectively include three delay units 411, 412 and 413 and three delay units 421, 422 and 423.

[0063] exist Figure 4 In this context, D represents the value based on the encoding scheme. k This represents the input to the turbo encoder 400. The outputs from the first component encoder 410 and the second component encoder 420 are represented as z, respectively. k and z' k The output from the turbo code internal interleaver 430 is represented as c' k Typically, each of delay units 411, 412, 413, 421, 422, and 423 delays the input value by one clock cycle. However, each of delay units 411, 412, 413, 421, 422, and 423 can be configured to delay the input value by more than one clock cycle, depending on an internal configuration. Each of delay units 411, 412, 413, 421, 422, and 423 can consist of a shift register and can be configured to thereby delay the input bit by a preset clock cycle and subsequently output the input bit.

[0064] The turbo code internal interleaver 430 can reduce the impact of burst errors that may occur during signal transmission over a radio channel. For example, the turbo code internal interleaver 430 can be a quadratic polynomial permutation (QPP) interleaver.

[0065] Turbo codes are high-performance forward error correction (FEC) codes used in LTE communication systems. For example, a data block encoded with turbo codes can include three sub-blocks. One sub-block can correspond to m bits of payload data. Another sub-block can include n / 2 parity bits calculated using RSC codes for the payload. Furthermore, other sub-blocks can include n / 2 parity bits calculated using RSC codes for permutations of the payload data. For example, these permutations can be performed by an interleaver. Therefore, two distinct parity sub-blocks can be combined with the sub-block used for the payload to form a single block. As an example, when m equals n / 2, a block has a code rate of 1 / 3.

[0066] In the first encoder 410, where the input c k Reaching the encoding bit z kThe process can be divided into two paths. These two paths include a first path connecting the input stage to the output stage without feedback, and a second path feeding back from the input stage to the input stage.

[0067] On the first path, enter c k —The input c k After passing through delay unit 411, and the input c k The input stage is supplied to the output stage via delays 411, 412, and 413. The relationship between the input and output stages for the first path can be expressed as a polynomial. This polynomial for the first path is called the forward generator polynomial and can be expressed as g1 in the following equation.

[0068] Equation 1

[0069] g1(D) = 1 + D + D 3

[0070] Meanwhile, on the second path, enter c k —The input c k After passing through delay units 411 and 142, and the input c k After passing through delayers 411, 412, and 413, the polynomial is fed back to the input stage. The polynomial for the second path is called the recursive generator polynomial and can be expressed as g0 in the following equation.

[0071] Equation 2

[0072] g0(D)=1+D 2 +D 3

[0073] In equations 1 and 2, "+" indicates a mutually exclusive OR (XOR), and 1 indicates that the input is delayed zero times. Furthermore, D n This indicates that the input is delayed n times.

[0074] Figure 5 This is a diagram illustrating an exemplary grid based on an RSC encoder.

[0075] Figure 5 The diagram shows... Figure 3 The structure of the grid in the RSC encoder. Figure 5 In the middle, S i This represents the i-th input data. Figure 5In this grid, each circle represents a node. Lines between nodes represent branches. Solid lines indicate branches used for the input value 1, while dashed lines indicate branches used for the input value 0. The value on each branch is expressed as m / C1C2 (input value / system bit, encoded bit). This grid can have states that are exponentially proportional to the amount of memory in the encoder. For example, if the encoder includes 'a' memories, then the grid can include 2... a There are several states.

[0076] This grid is a state machine illustrating the state transitions of an encoder that allows for two states. Convolutional encoders, such as RSC encoders, can perform encoding based on the grid diagram. Codewords encoded by the RSC encoder can be decoded using algorithms based on the grid structure. For example, the Viterbi or Bahl, Cocke, Jelinek, and Raviv (BCJR) algorithms can be used.

[0077] Figure 6 This is a diagram illustrating an exemplary grid structure.

[0078] exist Figure 6 In this context, n represents the length of the codeword. Typically, additional bits are added to the end of the input sequence, thereby terminating the grid. A sequence consisting of 0s is usually called the tail portion. This tail portion terminates the grid by causing a node in a certain state to have a value of 0.

[0079] exist Figure 6 In this context, the codeword length can be determined by considering the length k of the input data and the length t of the tail portion. For example, when the code rate is R, the codeword length n can have a value of (k+t) / R. Typically, the tail portion length t can be determined as the length that can be used to reset all delays of the encoder (e.g., memory). As an example, Figure 3 The RSC encoder can use a total of two tail sections. Furthermore, as... Figure 4 The turbo encoder for LTE communication shown can use three tail sections.

[0080] The tail portion can have a relatively short length compared to the length of the input data. As described above, since the length of the codeword is related to the length of the tail portion, a code rate loss will occur due to the tail portion if the codeword length is finite. However, despite the code rate loss due to the tail portion, grid termination using the tail portion is widely used due to its low computational complexity and outstanding error correction performance.

[0081] Puncturing is a scheme that truncates a portion of a codeword. By truncating, a portion of the codeword is not transmitted because it is removed. For example, truncating can be used to reduce the rate loss caused by adding a tail. In this case, the receiver can perform decoding using a grid corresponding to the sum of the length k of the input data and the length t of the tail. That is, the receiver can perform decoding under the assumption that it has already received the untruncated codeword. In this case, the receiver can treat the branch from the node corresponding to the truncated bit (e.g., the bit not transmitted by the transmitter) as having no input value. That is, it assumes with equal probability that the input data of the branch corresponding to the node is 0 or 1.

[0082] As mentioned above Figure 1 As described, a CRC is added to the CB. The CRC can be determined as the remainder obtained after dividing the data to be transmitted by a preset checksum used as the divisor. Typically, the CRC can be added to the end of the transmitted data. The receiver can compare the remainder of the received data divided by the preset checksum with the CRC, or determine whether the remainder of the entire received data, including the CRC, divided by the checksum is 0.

[0083] If the size of TB is 6144 bits, then the size of CRC can be up to 24 bits. Therefore, the other bits besides the CRC bits can be used to determine the size of CB.

[0084] The receiver can perform decoding for each CB. Subsequently, the receiver can configure a TB from the CB and determine whether decoding has been successfully performed by checking the CRC against that TB. In current LTE systems, the CB CRC is used to terminate early decoding. For example, if the CRC for one CB fails, the receiver may not decode other CBs and send a negative acknowledgment (NACK) to the transmitter.

[0085] Upon receiving a NACK, the transmitter can retransmit at least a portion of the transmitted data. For example, the transmitter can retransmit a TB or one or more CBs. As an example, when the transmitter retransmits all TBs, the radio resources used for retransmission may be excessively consumed. Furthermore, for example, when the receiver generates a NACK due to a CB CRC failure, the receiver can send information (e.g., CB indicators) to the transmitter about the CBs that have experienced CRC failures. The transmitter can improve the efficiency of radio resources by using this information about the CBs to only transmit those that have experienced CRC failures. However, if the number of CBs increases, the amount of data used to feed back information about the CBs (e.g., CB indicators) increases.

[0086] In LTE communication systems, the receiver can use ACK / NACK signals to notify the transmitter whether data has been successfully received. In Frequency Division Duplex (FDD), the ACK / NACK for data received in the i-th subframe is sent in the (i+4)-th subframe. If a NACK is received in the (i+4)-th subframe, a retransmission can be performed in the (i+8)-th subframe. This is to account for the time required to process the TB (Transmission Tolerance) and generate the ACK / NACK, as channel code processing for TBs is time-consuming. In Time Division Duplex (TDD), the ACK / NACK and retransmission subframes can be determined based on the time used to process the TB, the time used to generate the ACK / NACK, and the uplink subframe allocation (e.g., TDD uplink / downlink configuration). Furthermore, ACK / NACK bundling and multiplexing can be used.

[0087] As described above, turbo codes exhibit limited improvement in bit error rate when the SNR exceeds a predetermined value. As an alternative to turbo codes, low-density parity-check (LDPC) codes have been proposed. LDPC codes are linear block codes and are used in IEEE 802.11n and 802.11ac, as well as Digital Video Broadcasting (DVB). LDPC codes can include a generator matrix and a parity-check matrix. In LDPC codes, data can be encoded by multiplying message bits with the generator matrix. Typically, in communication specifications using LDPC codes, the parity-check matrix can be used instead of the generator matrix. For example, data can be encoded using a parity-check matrix.

[0088] The linear block code can be generated based on either the generator matrix G or the parity check matrix H. The linear block code is configured such that the product Hc of the transpose of the codeword c and the parity check matrix... t The entire codeword c has a value of 0. Decoding an LDPC code can be performed in the same way as other linear block codes by checking whether the product of the parity check matrix H and the codeword c is "0". For example, this can be done by checking the product of the transpose of the codeword c and the parity check matrix (i.e., Hc). t To perform LDPC code decoding, set the value to 0.

[0089] In LDPC codes, the majority of elements in the parity check matrix are 0, with a small number of elements having values ​​other than 0 relative to the block length. Therefore, LDPC codes can be used for iterative decoding based on probability. In the originally proposed LDPC codes, the parity check matrix was defined in a non-systematic form, and small weights were applied to the rows and columns of this parity check matrix in a non-uniform manner. The weights can represent the number of 1s included in a row or column.

[0090] As described above, the density of elements with values ​​other than 0 in the parity-check matrix H of LDPC codes is very low. Therefore, LDPC codes exhibit performance close to the limit of Shannon's theorem while maintaining low decoding complexity. Due to their high error-correcting performance and low decoding complexity, LDPC codes are suitable for high-speed wireless communication.

[0091] Structured LDPC code

[0092] As described earlier, the parity check matrix H can be used to generate LDPC codes. Matrix H consists of a large number of 0s and a small number of 1s. The size of matrix H can be 10. 5 Bits or more. A lot of memory may be needed to represent this H matrix.

[0093] Figure 7 This is a diagram illustrating an exemplary structured parity check matrix.

[0094] In this structured LDPC code, the elements of matrix H can be expressed as follows: Figure 7 The sub-blocks of a predetermined size are illustrated in the diagram. Figure 7 In this matrix, each element of H represents a sub-block.

[0095] In the IEEE 802.16e standard specification, subblocks are indicated by an integer index, which allows for a reduction in the size of the memory used to represent matrix H. Each subblock can, for example, be a permutation matrix of a predetermined size.

[0096] Figure 8 This is a diagram illustrating an exemplary model matrix.

[0097] For example, referring to the IEEE 802.16e standard specification, if the codeword size is 2^304 and the code rate is 2 / 3, then the model matrix used to encode / decode LDPC codes is as follows: Figure 8 As shown. This model matrix can represent a parity check matrix comprising at least one sub-block as described below. The sub-block may be referred to as the shift amount in the following description. This model matrix can be extended into a parity check matrix based on the method described subsequently. Therefore, encoding and decoding based on a specific model matrix means encoding and decoding based on a parity check matrix generated by extending the model matrix.

[0098] exist Figure 8 In this context, the indicator "-1" indicates a zero matrix of a preset size. The indicator "0" indicates an identity matrix of a preset size. Positive indicators other than "-1" and "0" indicate the number of shifts. For example, a sub-block expressed as indicator "1" could mean a matrix obtained by shifting the identity matrix once in a specific direction.

[0099] Figure 9 It is a diagram used to explain matrix transformations based on the number of shifts.

[0100] For example, Figure 9 The diagram illustrates a scenario where the sub-blocks are arranged in 4 rows and 4 columns. Figure 9 In this case, the sub-block is shifted three times to the right from the identity matrix. In the parity check matrix of the structured LDPC code, the sub-block can be represented by the integer index "3".

[0101] Typically, LDPC code encoding can be performed by generating a generator matrix G from a parity check matrix H and then using this generator matrix to encode the information bits. To generate this generator matrix G, Gaussian elimination is performed on the parity check matrix H such that [P...] T The matrix is ​​configured in the form of :I]. If the number of information bits is k and the size of the encoded codeword is n, then matrix P is a matrix with k rows and nk columns, and matrix I is an identity matrix with size k.

[0102] If the parity check matrix H has the form [P] T If :I], then the generating matrix G has the form [I:P] T If k information bits are encoded, the encoded information bits can be represented as a matrix x with 1 row and k columns. In this case, the codeword c is xG of the form [x:xP]. Here, x represents the information part (or system part) and xP represents the parity part.

[0103] Furthermore, by designing matrix H with a specific structure without using Gaussian elimination, information bits can be encoded directly from matrix H without deriving matrix G. For the structures of matrices H and G described above, the product of the transposes of matrices G and H has a value of 0. Using this property and the relationship between information bits and codewords, codewords can be obtained by adding parity bits to the end of the information bits.

[0104] Figure 10 This is a flowchart illustrating an exemplary LDPC code decoding method.

[0105] In a communication system, encoded data includes noise as it passes through the radio channel. Therefore, codeword c is represented in the receiver as a codeword c' that includes noise. The receiver performs demultiplexing and demodulation on the received signal (step S1000) and initializes the decoding parameters (step S1005). The receiver updates the check node and variable node (steps S1010 and S1015) and performs sydrome verification (step S1020). That is, the decoding process can be completed by verifying c'H. T Does it end if the value is 0? TIf c' is 0, then the first k bits from c' can be determined as information bits x. If c'H T If the value is not 0, then the information bit x can be searched for a solution satisfying c'H using a decoding scheme based on algorithms such as sum-product algorithms. T The condition c' is 0 and is restored.

[0106] Figure 11 This is an example diagram of a bipartite graph.

[0107] exist Figure 11 In the middle, the left nodes are v0, v1, ..., v 11 The first node represents the variable node, while the right-hand nodes c1, c2, ..., c6 represent the check nodes. Figure 11 In the example, for ease of description, a bipartite graph focusing on variable node v0 and check node c1 is illustrated. Figure 11 The connecting lines in a bipartite graph can be called edges. Figure 11 A bipartite graph can be obtained from Hc t Generate. Therefore, in Figure 11 In the parity check matrix H, the edge from variable node v0 corresponds to the first column of the parity check matrix H, and the edge from check node c1 corresponds to the first row of the matrix H.

[0108] As described above, for successful decoding, the product of the parity check matrix H and the transpose of the codeword matrix c should have a value of "0". Therefore, the value of the variable node connected to a parity check node should be 0. Thus, in Figure 11 In the context, the variable nodes v0, v1, v4, v6, v9, and v are connected to the verification node c1. 11 The value of the mutual exclusion OR (XOR) should be "0". Feature group verification means verifying whether the XOR value of the variable nodes connected to each verification node is 0.

[0109] Quasi-cyclic (QC) LDPC codes

[0110] The QC LDPC code will then be described.

[0111] To achieve outstanding performance in LDPC codes, the parity check matrix (or generator matrix) can be randomly configured. The performance of LDPC codes can improve with increasing block length. In decoding, the performance of LDPC codes can be improved using optimal decoding methods. However, due to the complexity of optimal decoding, the belief propagation algorithm is used to decode LDPC codes. Furthermore, while randomly generated parity check matrices for LDPC codes exhibit outstanding performance, their implementation and representation are very complex. Therefore, the structured LDPC codes described above are widely used. QC LDPC codes are widely used as structured LDPC codes.

[0112] QC LDPC codes consist of a zero matrix of size Q×Q and a cyclic permutation matrix (CPM) of size Q×Q. a It has the ability to circumlocate an identity matrix of size Q×Q by a value a (reference) Figure 9 The form obtained by shifting. For example, such as Figure 7 As shown, the parity check matrix H can include (mb+1)×(nb+1) CPMs. As previously described, a cyclic shift value of 0 represents the identity matrix, while a cyclic shift value of -1 represents the zero matrix. Furthermore, the parity check matrix can be expressed as follows: Figure 8 The matrix shown represents the cyclic shift values. Here, each cyclic shift value can be configured to be equal to or greater than -1 and equal to or less than Q⁻¹. (As shown in the image) Figure 8 The matrix showing the cyclic shift value configuration can be called a cyclic shift matrix or a characteristic matrix.

[0113] Figure 12 This is a diagram illustrating the structure of an LDPC code according to an embodiment of the present invention.

[0114] In the following embodiments, a multi-sided QC LDPC code can be used. For example, such as Figure 12 As shown, a multilateral QC LDPC code can have a structure in which a high-ratio code similar to a QC Irregular Repeated Accumulation (IRA) (QC-IRA) and a single parity check code are concatenated. For example, the parity check matrix H of a multilateral QC LDPC code can be defined as follows.

[0115] Equation 3

[0116]

[0117] In the above equations, A and B(Mb*(Kb+Mb)) represent high-ratio codes with a structure similar to QC-IRA, and C(Mb*Mc) represents the zero matrix. Furthermore, D(Mc*(Kb+Mb)) and E(Mc*Mc) represent the information part and parity part of a single parity-check code, respectively. In this case, E can be determined as a single diagonal structure.

[0118] exist Figure 12 In this code, Kb represents the size of the information to be encoded. Furthermore, Mb represents the parity size of the high-ratio code portion, while Mc represents the parity size of the single-parity check code portion. Pb represents the truncation size applied to the LDPC code.

[0119] In this case, the size of Pb can be determined by considering the maximum number of iterations that the LDPC decoder can perform. In some embodiments of the invention, the maximum number of iterations of the decoder can be 50, so the size of Pb can be 2Z. However, the invention is not limited to such a structure. Figure 12 In the high-ratio code portion A, the parity structure can be determined as a double diagonal structure by considering the coding scheme.

[0120] For the configuration of QC LDPC codes of the desired size, a lifting operation can be performed. The lifting is used to obtain a parity matrix of the desired size from a preset parity matrix. Various code lengths can be supported by changing the lifting size. For example, flat lifting or modulo lifting can be used. For example, the parity matrix based on modulo lifting can be obtained as indicated by the following equation:

[0121] Equation 4

[0122]

[0123] In the above equation, Q represents the lifting size and a ij This represents the shift value of the i-th row and j-th column of the preset parity check matrix (see reference). Figure 8 Furthermore, MOD Q represents modulo operation based on the value Q. That is, in a cyclic shift matrix with a predefined parity matrix, the value corresponding to the zero matrix is ​​retained, and a modulo operation with a boost size of Q is performed on the other cyclic shift values. Therefore, the boosted values ​​of the cyclic shift matrix are converted to values ​​equal to or greater than -1 and equal to or less than Q-1.

[0124] Figure 13 This is a diagram illustrating an exemplary rate matching process.

[0125] The length of data bits that can be substantially transmitted can be determined based on the size of available physical resources. Therefore, codewords with a code rate corresponding to the size of available physical resources can be generated through rate matching. For example, a shortening scheme can be performed by removing a portion of the information portion of the codeword. Since the information portion is reduced, this shortening scheme can reduce the code rate. For example, a truncating scheme can be performed by truncating at least a portion of the parity of the codeword. In truncating, the code rate increases because the ratio of information bits is increased. Therefore, theoretically, codewords corresponding to any code rate can be generated through a combination of shortening and truncating schemes.

[0126] The performance of shortening and truncation can be determined based on the order of the shortened or truncated bits. However, in QC LDPC codes, the order of bit truncation within a Q×Q block does not affect performance. Therefore, after interleaving in units of boost size Q for parity blocks, truncation can be performed from the last part of the parity bits. Furthermore, shortening can be performed from the last part of the information bits.

[0127] Meanwhile, if the size of the physical resource is greater than the length of the encoded LDPC code, rate matching can be performed through an iterative scheme.

[0128] refer to Figure 13 First, an information block containing the information bits to be sent is generated (step S1301). If the size of the CB is smaller than the length of the LDPC information portion, 0 bits can be added to the end of the information block before encoding. Figure 13 In the example, the 0-bit block is inserted at the end of the information block for subsequent shortening (step S1302). Next, encoding is performed on the information block and the 0-bit block based on the LDPC code, so that a codeword including the parity block can be generated (step S1303). In step S1303, the information block and the 0-bit block can correspond to the information part of the LDPC code, and the parity block can correspond to the parity part of the LDPC code.

[0129] As described above, the shortening scheme can be applied to rate matching. In this case, the already inserted 0-bit block can be removed (step S1304). Furthermore, for the truncation described later, interleaving with increasing size units can be performed with respect to parity blocks (truncation). In addition, for rate matching, the last part of the parity block can be truncated (step S1305).

[0130] 5G wireless LAN systems support transmission rates ranging from a maximum of 20Gbps to a minimum of tens of bps (up to 40bps in LTE). Therefore, 5G wireless LAN systems support diverse transmission environments. To effectively encode information in such diverse environments, the LDPC code used for encoding should support various code rates. However, when information is encoded using a single LDPC code as in conventional operations, inefficiencies arise in handling various communication environments.

[0131] This invention proposes that LDPC codes use multiple basic codes to provide efficient encoding in various communication environments.

[0132] The basic codes proposed in this invention can be basic codes that are advantageous for large TB (large blocks) and high throughput, or basic codes that are advantageous for small TB (small blocks) and short latency.

[0133] Unlike turbo codes, the drawback of LDPC codes is that the number of rows in the matrix to be processed increases as the code rate decreases. For example, when the LDPC code rate is 8 / 9, the number of rows to be processed by the encoder is 6, while when the code rate is reduced to 2 / 3 under the same conditions, the number of rows to be processed by the encoder increases by 18. Since the number of rows to be processed increases threefold, the delay also increases threefold.

[0134] To overcome these problems, this invention proposes introducing additional short blocks for encoding small TBs. By introducing such multiple basic codes, gains in decoding latency and power consumption can be achieved.

[0135] Data packets transmitted between the BS and UE exhibit different characteristics depending on whether they are transmitted on the uplink or downlink. When data packets are transmitted on the downlink, large terabytes (TB) account for the majority of the traffic because downlink data packets have a relatively higher bit rate compared to uplink data packets. Conversely, when data packets are transmitted on the uplink, relatively small terabytes (TB) account for the majority of the traffic.

[0136] Considering these characteristics, if the transmitter's encoder uses LDPC codes suitable for each communication environment to encode the information, latency can be effectively reduced.

[0137] This invention proposes a method for an encoder in a transmitter to generate LDPC codes using a partially row orthogonal structure. Here, a partially row orthogonal LDPC structure can refer to an LDPC structure in which only a portion of the different levels constituting the LDPC code have a row orthogonal structure. The row orthogonal structure and partially row orthogonal structure proposed in this invention will be described in detail below.

[0138] LDPC code structure using row orthogonal structure

[0139] Figure 14 This is a diagram used to explain the structure of LDPC codes that use row orthogonal structures.

[0140] In a row orthogonal structure, the edges within the hierarchy of the parity check matrix D constituting the LDPC are designed so that they do not overlap upwards or downwards with respect to consecutive rows, such as... Figure 14 As shown. Here, a hierarchy can represent a set of one or more rows.

[0141] Now refer to Figure 14 The example shown in the figure illustrates the row orthogonal structure in more detail. Figure 14 In the dashed partition shown, the first level in the upper part is configured such that two rows form a level, and the second level in the lower part is configured such that three rows form a level.

[0142] In this case, since the edges constituting the first level and the edges constituting the second level are configured not to overlap upwards and downwards between consecutive rows, both the first level and the second level can be defined as having a row orthogonal structure.

[0143] However, this structure is not effective for reducing latency because it can cause memory conflicts between the first and second levels. Furthermore, in a row orthogonal structure, the positions of edges within the matrix are restricted, causing edges to not overlap with respect to consecutive rows (different column values), as described previously, resulting in overall system performance degradation.

[0144] In the following, an LDPC code structure according to an embodiment of the present invention, proposed to solve the above-mentioned problems, will be described. In particular, a method for generating LDPC codes using a partially row orthogonal structure will be described, wherein only a portion of the levels of a single parity check matrix is ​​configured as a row orthogonal structure.

[0145] LDPC code structure using partially row orthogonal structure

[0146] Figure 15 This diagram is referenced to explain a partially row orthogonal LDPC code structure that can be used in some embodiments of the invention. The partially row orthogonal structure can be designed using the following properties of LDPC codes.

[0147] Since the number of lines to be processed increases as the bit rate decreases, a significant gain in decoding latency of LDPC codes can be achieved at low bit rates.

[0148] As the bitrate becomes lower Figure 15 The parity check matrix D shown increases the available space for edge positions. Therefore, it is possible to design row-orthogonal edge arrangements without the performance degradation described above.

[0149] To minimize memory conflicts between levels as described above, edges are designed not to overlap at the boundaries of different levels.

[0150] With this in mind, a partial row orthogonal structure can be involved, such that the edges between different rows in the high-bitrate portion of matrix D overlap, i.e., there is no row orthogonal structure, rather than all levels of matrix D being designed to be row orthogonal. In the low-bitrate portion of matrix D, the edges between different rows can be designed not to overlap, i.e., the edges between different rows can be designed to have a row orthogonal structure.

[0151] Therefore, when the row orthogonal structure is used only for the low-rate portion of the LDPC code by partitioning the parity check matrix, the row orthogonal performance degradation caused by edge selection and memory conflicts can be reduced. In other words, the high-rate portion provides a wide range of edge selection to offset latency degradation.

[0152] Figure 15 The X shown here signifies a period of overlapping edges (with the same column value) between consecutive rows in the region corresponding to the row above X in the parity check matrix D. In other words, this means that no row orthogonal structure was designed in the region corresponding to the row above X in the parity check matrix D.

[0153] In the region defined by rows X of matrix D, the edges between rows overlap, preventing the signal from being fully pipelined. Therefore, the delay during decoding increases. However, in the lower region defined by rows Y, the edges between rows do not overlap, allowing the signal to be fully pipelined. This reduces the delay during decoding. In other words, a delay gain can be achieved.

[0154] Quasi-row orthogonal structures can be used as a means to balance performance and latency in row orthogonal structures. A quasi-row orthogonal structure is one in which edges overlap only in truncated regions and not in other regions. Decoding quasi-row orthogonal structures may require additional logic beyond the conventional hierarchical decoding method.

[0155] The method for determining the values ​​X and Y described above will then be described.

[0156] Table 1 below shows the parameters that can be used as the basic diagram in embodiments of the present invention, and proposes several parameters for forming the first and second basic codes of the basic diagram. However, the features of the present invention are not limited to the parameters proposed in this table.

[0157] Table 1

[0158]

[0159] In the table above, Mb represents the parity of each basic code, and Nb represents the codeword size of each basic code. Additionally, Pb represents the truncated size of each basic code. Kb,max represents the maximum number of columns for each basic code, and Kb,min represents the minimum number of columns for each basic code.

[0160] First, X and Y can be determined based on the ratio of the total amount of the entire basic code (the total number of rows).

[0161] For example, assuming a basic chart as shown in Table 1 is provided, and the minimum code rate of the first basic code is 1 / 3, the number of rows can be set to 66. In this case, if the parity matrix is ​​produced starting from 1 / 3 of all rows using a row orthogonal structure, then X can be 22 (=66 / (1 / 3)) and Y can be 44 (=66-22).

[0162] Second, it requires that the code rate of the row orthogonal structure can be predetermined, and that the row orthogonal structure can be applied to rows starting from the row in the parity check matrix corresponding to the predetermined code rate.

[0163] For example, in the example above, if we expect to apply the row orthogonal structure to the matrix starting at 2 / 3 of the code rate, X could be 18 (=32 / (2 / 3)-(32-2)) and Y could be 48 (=66-18). In this case, consider the 2Z truncation.

[0164] Third, a method for determining the parity check matrix X and Y with a row orthogonal structure will now be described when the size of the basic code is small.

[0165] For example, consider a scenario where a basic graph as shown in Table 1 is provided and a second basic code is used. If LDPC codes support very low code rates even when the size of the basic code is very small, then a portion of the parity check matrix can have a row orthogonal structure to reduce decoding latency due to the large number of rows constituting the parity check matrix. In this case, the code rate at the start of the row orthogonal structure is lower than that in basic codes with a large size (the first basic code in the example above).

[0166] In the example above, assuming the maximum code rate of the second basic code is 1 / 5, the total number of rows can be 10 / (1 / 5) = 50. If the row orthogonal structure is applied to rows starting at approximately 1 / 2 code rate, then X can be 18 (= 10 / (1 / 2) - (10 - 2)) and Y can be 32 (= 50 - 18).

[0167] Recently, the 3GPP standard has provided a proposal for LDPC code structures with partial row orthogonal structures. Hereinafter, some embodiments of the present invention based on the above proposal will be described.

[0168] Figure 16 This is a diagram illustrating a partial row orthogonal LDPC code structure according to an embodiment of the present invention. Figure 17 This is a diagram illustrating another partially row orthogonal LDPC code structure according to an embodiment of the present invention.

[0169] After that, will be Figure 16 and 17 The LDPC code structure proposed according to an embodiment of the present invention is illustrated in the figure.

[0170] Regarding performance, the LDPC code structure according to embodiments of the present invention can be proposed as follows. The proposed LDPC code can be a structure used to ensure a code rate of 0.89 to 0.93. To satisfy a code rate of 0.89, matrices A and B are preferably configured to have a size of 5*27 (including two truncated columns). In the 5*27 matrix, the parity matrix with a double diagonal structure is preferably configured to have a size of 4*4. In the 5*27 matrix, 1-degree variable nodes can be included in the parity matrix. Furthermore, the two truncated columns can be configured adjacently as check nodes for 1-degree variable nodes (the last row in matrices A and B).

[0171] Regarding the matrix D of the LDPC code structure proposed according to the embodiment, up to X rows can be configured with quasi-row orthogonal, non-row orthogonal, and pure row orthogonal structures. Here, a non-row orthogonal structure means that the entire partition of a specific partition is configured with a structure other than a row orthogonal structure, while a pure row orthogonal structure means that the entire partition of a specific partition is configured with a row orthogonal structure. In this case, the other Y rows can be configured with a pure row orthogonal structure.

[0172] Regarding complexity, the structure according to embodiments of the present invention can be proposed as follows. The total number of edges included in the LDPC code structure can be limited to approximately 300 to 310. More specifically, in order for the LDPC structure to support a code rate of 1 / 3, the total number of edges included in the LDPC code structure can be limited to approximately 300 to 310. In this case, to ensure throughput at low code rates, it is desirable to use a pure LDPC code structure in the Y row. In some cases, X or Y can have a value of 0.

[0173] Figure 18 This is a diagram illustrating a partial row orthogonal LDPC code structure according to another embodiment of the present invention.

[0174] The following will describe Figure 18 The LDPC code structure proposed according to another embodiment of the present invention is shown.

[0175] Regarding performance, an LDPC code structure according to another embodiment of the present invention can be proposed as follows. The proposed LDPC code structure can be a structure used to ensure a code rate of 0.67 (=2 / 3). To satisfy a code rate of 0.89, matrices A and B are preferably configured to have a size of 7*17 (including 2 column cutoffs). In the 7*17 matrix, the parity matrix with a double diagonal structure is preferably configured to have a size of 4*4. In the 7*17 matrix, 1-degree variable nodes can be included in the parity matrix. If there are a large number of 1-degree nodes, the waterfall performance may be outstanding, but the error level performance may be reduced. According to another embodiment of the present invention, three 1-degree nodes can be proposed, and the three nodes constituting the lower right part of matrix B can be configured as 1-degree nodes. In addition, the 2 column cutoffs can be configured adjacently as check nodes of the 1-degree variable nodes (the last row in matrices A and B).

[0176] Regarding the matrix D of the LDPC code structure proposed according to another embodiment, up to X rows can be configured with quasi-row orthogonal, non-row orthogonal, and pure row orthogonal structures. Here, a non-row orthogonal structure means that the entire partition of a specific partition is configured with a structure other than a row orthogonal structure, while a pure row orthogonal structure means that the entire partition of a specific partition is configured with a row orthogonal structure. In this case, the other Y rows can be configured with a pure row orthogonal structure. In some cases, X or Y can have a value of 0.

[0177] Regarding complexity, the structure according to another embodiment of the invention can be proposed as follows. The total number of edges included in the LDPC code structure can be limited to approximately 190 to 195. More specifically, in order for the LDPC structure to support a code rate of 1 / 5, the total number of edges included in the LDPC code structure can be limited to approximately 190 to 195. In this case, to ensure throughput at low code rates, it is desirable to use a pure LDPC code structure in the Y row. In some cases, X or Y can have a value of 0.

[0178] According to the embodiments described above, when X and Y are configured with respect to each bitrate... Figure 18 The parameters and bitrate standards shown in the figure can be configured as indicated in Table 2.

[0179] Table 2

[0180]

[0181] also, Figure 18 The LDPC code structure illustrated in the figure, according to another embodiment of the present invention, can be proposed based on the parameters shown in Table 3.

[0182] Table 3

[0183] Kb Mb Mc Pb W X Y X+Y 10 7 42 2 7

[22]

[20] 42

[0184] Although the LDPC code structure according to embodiments of the present invention has been described, the scope of the invention is not limited to the numbers or illustrations described above. Various embodiments incorporating the features described above may fall within the scope of the invention.

[0185] Figure 19 These are diagrams used to explain the apparatus according to embodiments of the present invention.

[0186] refer to Figure 19 The BS 10 according to the present invention may include a receiving module 11, a transmitting module 12, a processor 13, a memory 14, and multiple antennas 15. The transmitting module 12 can transmit various signals, data, and information to an external device (e.g., a UE). The receiving module 11 can receive various signals, data, and information from an external device (e.g., a UE). The receiving module 11 and the transmitting module 12 may be referred to as a transceiver. The processor 13 can control the overall operation of the BS 10. The multiple antennas 15 may be configured, for example, according to a 2D antenna deployment configuration.

[0187] The processor 13 of the BS 10 according to an example of the invention can be configured to receive channel state information according to the example presented in the invention. The processor 13 of the BS 10 processes the information received by the BS 10 and the information to be transmitted outside the BS 10. The memory 14 can store the processed information for a predetermined time and can be replaced by a component such as a buffer (not shown).

[0188] refer to Figure 19 The UE 20 according to the present invention may include a receiving module 21, a transmitting module 22, a processor 23, a memory 24, and multiple antennas 25. Using multiple antennas 25 means that the UE 20 uses multiple antennas 25 to support multiple-input multiple-output (MIMO) transmission and reception. The transmitting module 22 can transmit various signals, data, and information to external devices (e.g., a BS). The receiving module 21 can receive various signals, data, and information from external devices (e.g., a BS). The receiving module 21 and the transmitting module 22 can be referred to as a transceiver. The processor 23 can control the overall operation of the BS 10.

[0189] The processor 23 of UE 10 according to an example of the present invention can be configured to transmit channel state information according to the example presented in the present invention. The processor 23 of UE 20 processes information received by UE 20 and information to be transmitted outside of UE 10. The memory 24 can store the processed information for a predetermined time and can be replaced by a component such as a buffer (not shown).

[0190] The detailed configuration of UE 10 can be implemented such that the various embodiments of the invention described above can be applied independently or two or more embodiments of the invention can be applied simultaneously. For clarity, unnecessary details will not be described here.

[0191] In the various embodiments of the invention described herein, although the BS has been primarily described as an example of a downlink transmitting entity or an uplink receiving entity, and the UE has been described as an example of a downlink receiving entity or an uplink transmitting entity, the scope of the invention is not limited thereto. For example, the description of the BS can also be applied when the cell, antenna port, antenna port group, remote radio head (RRH), transmitting point, receiving point, access point, or relay is a downlink transmitting entity to or from the UE. Furthermore, the principles of the invention described through the various embodiments of the invention can also be applied to relays acting as downlink transmitting entities to or from the UE, or as uplink receiving entities to or from the BS.

[0192] Embodiments of the present invention can be implemented by various means, such as hardware, firmware, software, or combinations thereof.

[0193] In a hardware configuration, the method according to embodiments of the present invention can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, etc.

[0194] In firmware or software configuration, the method according to embodiments of the present invention can be implemented in the form of modules, processes, functions, etc., that perform the functions or operations described above. Software code can be stored in a memory unit and executed by a processor. The memory unit can be located inside or outside the processor and can send data to and receive data from the processor via various known means.

[0195] The embodiments described above constitute combinations of components and features of the present invention in a specified form. Unless otherwise expressly stated, each component or feature is to be considered optional. Each component or feature may be implemented in a form that is not combined with other components or features. Additionally, some components and / or features may be combined to configure embodiments of the present invention. The order of operations described in the embodiments of the present invention may be changed. Some components or features of the embodiments may be included in another embodiment or may be replaced by corresponding components or features of the present invention. It will be apparent to those skilled in the art that claims not expressly referenced in each other in the appended claims may be presented as embodiments of the present invention in a combined form, or may be included as new claims by amendment after filing of the application.

[0196] It will be apparent to those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit and essential characteristics of the invention. Therefore, the above embodiments should be considered illustrative rather than restrictive in all respects. The scope of the invention should be determined by a reasonable interpretation of the appended claims, and all variations falling within the equivalent scope of the invention are within the scope of the invention.

[0197] Industrial applicability

[0198] Embodiments of the present invention can be applied to various wireless access systems and broadcast communication systems. Wireless access systems include, for example, 3GPP systems, 3GPP2 systems, and / or IEEE 802.xx systems. Embodiments of the present invention can be applied not only to wireless access systems, but also to all technical fields employing wireless access systems.

Claims

1. A method for transmitting a block of information using low-density parity-check (LDPC) codes in a wireless communication system by a transmission device, the method comprising: The transmission device encodes the information block based on the parity check matrix of the LDPC code; and The encoded information blocks are transmitted by the transmission device; The parity check matrix is ​​based on LDPC basic codes. Sure, Each element in the LDPC basic code represents a zero matrix of dimension Z*Z, or a cyclic permutation matrix of dimension Z*Z obtained by cyclically shifting the identity matrix of dimension Z*Z to the right by non-negative integer times. Where "[AB]" is dimension M b *(K b +M b The matrix M, where M is... b and K b They are positive integers. Where "B" is dimension M b *M b A double diagonal structure matrix, where M is located on the first main diagonal of "B". b The element, the second diagonal directly above the first main diagonal of "B" (M) b -1) Apart from the elements and the two elements below the leftmost element of the first main diagonal of "B", each element of "B" represents a zero matrix of dimension Z*Z. Where "C" represents dimension M b *M c The matrix is ​​given by the expression, where each element of "C" represents a zero matrix of dimension Z*Z, and Mc is a positive integer. Where "E" is dimension M c *M c A single diagonal structure matrix, where M is located on the diagonal excluding "E". c Apart from the elements, each element of "E" represents a zero matrix of dimension Z*Z. Where "D" is dimension M c *(K b +M b The matrix of ) and Wherein, "D" represents a quasi-row orthogonal structure, where: i) Each pair of consecutive rows of "D" has at most one element representing a Z*Z cyclic permutation matrix in each column except the leftmost two columns, and ii) At least two consecutive rows of "D" have more than one element in at least one of the leftmost two columns of a cyclic permutation matrix representing dimension Z*Z.

2. The method according to claim 1, wherein, "[AB]" is not a row orthogonal structure.

3. A transmitting device for transmitting information blocks using low-density parity-check (LDPC) codes in a wireless communication system, the transmitting device comprising: An encoder configured to encode the information block based on the parity check matrix of the LDPC code; and The sending module is configured to send encoded information blocks; The parity check matrix is ​​based on LDPC basic codes. Sure, Each element in the LDPC basic code represents a zero matrix of dimension Z*Z, or a cyclic permutation matrix of dimension Z*Z obtained by cyclically shifting the identity matrix of dimension Z*Z to the right by non-negative integer times. Where "[AB]" is dimension M b *(K b +M b The matrix M, where M is... b and K b They are positive integers. Where "B" is dimension M b *M b A double diagonal structure matrix, where M is located on the first main diagonal of "B". b The element, the second diagonal directly above the first main diagonal of "B" (M) b -1) Apart from the elements and the two elements below the leftmost element of the first main diagonal of "B", each element of "B" represents a zero matrix of dimension Z*Z. Where "C" represents dimension M b *M c The matrix is ​​given by the expression, where each element of "C" represents a zero matrix of dimension Z*Z, and Mc is a positive integer. Where "E" is dimension M c *M c A single diagonal structure matrix, where M is located on the diagonal excluding "E". c Apart from the elements, each element of "E" represents a zero matrix of dimension Z*Z. Where "D" is dimension M c *(K b +M b ) matrix, Wherein, "D" is a quasi-row orthogonal structure, wherein: i) Each pair of consecutive rows of "D" has at most one element representing a Z*Z cyclic permutation matrix in each column except the leftmost two columns, and ii) At least two consecutive rows of "D" have more than one element in at least one of the leftmost two columns of a cyclic permutation matrix representing dimension Z*Z.

4. The transmitting device according to claim 3, wherein, "[AB]" is not a row orthogonal structure.

5. A method for a receiving device to receive an information block in a wireless communication system using a low-density parity-check (LDPC) code, the method comprising: The receiving device receives the encoded information block; The receiving device decodes the encoded information block based on the parity check matrix of the LDPC code to generate an information block; The parity check matrix is ​​based on LDPC basic codes. Sure, Each element in the LDPC basic code represents a zero matrix of dimension Z*Z, or a cyclic permutation matrix of dimension Z*Z obtained by cyclically shifting the identity matrix of dimension Z*Z to the right by non-negative integer times. Where "[AB]" is dimension M b *(K b +M b The matrix M, where M is... b and K b They are positive integers. Where "B" is dimension M b *M b A double diagonal structure matrix, where M is located on the first main diagonal of "B". b The element, the second diagonal directly above the first main diagonal of "B" (M) b -1) Apart from the elements and the two elements below the leftmost element of the first main diagonal of "B", each element of "B" represents a zero matrix of the stated dimension Z*Z. Where "C" is M b *M c A matrix, where each element of "C" represents a zero matrix of dimension Z*Z, where Mc is a positive integer. Where "E" is dimension M c *M c A single diagonal structure matrix, where M is located on the diagonal excluding "E". c Apart from the elements, each element of "E" represents a zero matrix of dimension Z*Z. Where "D" is dimension M c *(K b +M b The matrix of ) and Wherein, "D" is a quasi-row orthogonal structure, wherein: i) Each pair of consecutive rows of "D" has at most one element representing a Z*Z cyclic permutation matrix in each column except the leftmost two columns, and ii) At least two consecutive rows of "D" have more than one element in at least one of the leftmost two columns of a cyclic permutation matrix representing dimension Z*Z.

6. The method according to claim 5, wherein, "[AB]" is not a row orthogonal structure.

7. A receiving device for receiving information blocks using low-density parity-check (LDPC) codes in a wireless communication system, the receiving device comprising: A receiving module configured to receive encoded information blocks; A decoder configured to decode the encoded information block based on the parity check matrix of the LDPC code to generate an information block; The parity check matrix is ​​based on LDPC basic codes. Sure, Each element in the LDPC basic code represents a zero matrix of dimension Z*Z, or a cyclic permutation matrix of dimension Z*Z obtained by cyclically shifting the identity matrix of dimension Z*Z to the right by non-negative integer times. Where "[AB]" is dimension M b *(K b +M b The matrix M, where M is... b and K b They are positive integers. Where "B" is dimension M b *M b A double diagonal structure matrix, where M is located on the first main diagonal of "B". b The element, the second diagonal directly above the first main diagonal of "B" (M) b -1) Apart from the elements and the two elements below the leftmost element of the first main diagonal of "B", each element of "B" represents a zero matrix of dimension Z*Z. Where "C" represents dimension M b *M c The matrix is ​​given by the expression, where each element of "C" represents a zero matrix of dimension Z*Z, and Mc is a positive integer. Where "E" is dimension M c *M c A single diagonal structure matrix, where M is located on the diagonal excluding "E". c Apart from the elements, each element of "E" represents a zero matrix of dimension Z*Z. Where "D" is dimension M c *(K b +M b ) matrix, Wherein, "D" represents a quasi-row orthogonal structure, where: i) Each pair of consecutive rows of "D" has at most one element representing a Z*Z cyclic permutation matrix in each column except the leftmost two columns, and ii) At least two consecutive rows of "D" have at least one element in at least one of the leftmost two columns representing a cyclic permutation matrix of dimension Z*Z.

8. The receiving device according to claim 7, wherein, "[AB]" is not a row orthogonal structure.

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