Epitaxial nitride device monolithic heterogeneous integrated circuit and its fabrication method

Abstract

This invention discloses a monolithic heterogeneous integrated circuit for epitaxial nitride devices, primarily addressing the challenges of controlling the operating frequency band of existing surface acoustic wave (SAW) devices and their difficulty in epitaxial heterogeneous integration with high electron mobility transistors (HEP transistors). From bottom to top, it comprises a substrate, a nucleation layer, a channel layer, an insertion layer, a barrier layer, and a polarization layer. Interdigitated electrodes and their corresponding polarization layers below them constitute the SAW device. The source and drain electrodes, along with the channel layer, insertion layer, barrier layer, gate electrode, and the corresponding polarization layer below the gate electrode, constitute the HEP transistor. The SAW device is located in the gate-source conduction region of the transistor, sharing a polarization layer and isolated by a passivation layer between the interdigitated electrodes and the gate and source electrodes. This invention controls the operating frequency band and bandwidth of the SAW device by adjusting the two-dimensional electron gas concentration of the HEP transistor, facilitating monolithic epitaxial integration and heterogeneous ferroelectric integration of nitride devices, and can be used in filter-microwave RF front-end systems.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and specifically relates to an epitaxial nitride device monolithic heterogeneous integrated circuit that can be used in a filter-microwave amplifier RF front-end system. Background Technology

[0002] Radio frequency (RF) integrated circuits are widely used in electronic warfare, smart weapons, aerospace equipment, radar detection, and wireless communication, performing analog signal processing at the RF front-end of receivers and transmitters. RF RF integrated circuits typically consist of microwave power amplifier devices and passive filter devices, working together to remove signal noise and amplify the signal. The development trend of microwave power amplifier devices is based on wide-bandgap semiconductor gallium nitride (GaN) material technology. This is mainly due to the high electron saturation velocity and high breakdown field strength of this material, enabling high operating frequencies, output power, and power conversion efficiency. Passive filter devices are typically fabricated from magnetron sputtered polycrystalline aluminum nitride (ALT) material, primarily benefiting from the material's large piezoelectric coefficient, electromechanical coupling coefficient, and high quality factor.

[0003] Conventional GaN high electron mobility transistor device structures, such as Figure 1 As shown, from bottom to top, it includes a substrate, a nucleation layer, a GaN channel layer, an AlN insertion layer, and an AlGaN barrier layer. A gate electrode is disposed on the AlGaN barrier layer, and source and drain electrodes are disposed on the ohmic contacts of the source and drain regions. The structure of a surface acoustic wave device fabricated from conventional polycrystalline AlN material is as follows: Figure 2 As shown, from bottom to top, it includes a substrate, a polycrystalline AlN piezoelectric layer, and interdigitated electrodes on the polycrystalline AlN piezoelectric layer as transducers. Integrating passive AlN surface acoustic wave devices with active GaN high electron mobility transistors can realize higher-performance filter-microwave amplifier monolithic heterogeneous integrated circuits for use in RF front-end systems, enabling miniaturization and improved integration of RF front-end systems. However, in current RF front-end power amplifier modules, because surface acoustic wave devices and microwave power amplifier devices are mostly discrete devices, and the two devices are grown in different ways, the following drawbacks exist:

[0004] 1. The operating frequency band, bandwidth and sideband rejection ratio of surface acoustic wave devices cannot be flexibly adjusted. If a variable capacitor is used to adjust the surface acoustic wave device, the circuit complexity will be increased.

[0005] 2. Discrete packaging of surface acoustic wave devices and microwave power amplifier devices introduces additional parasitic inductance and mutual inductance, which degrades the device performance at high frequencies. Furthermore, the isolation between devices leads to an increase in chip integration area, and the additional wiring is not conducive to the miniaturization of RF integrated circuits.

[0006] 3. Conventional AlN surface acoustic wave devices are fabricated from polycrystalline materials grown by magnetron sputtering, while conventional GaN high electron mobility transistors are fabricated from single-crystal materials grown by metal-organic chemical vapor deposition or molecular beam epitaxy. The different epitaxial growth methods of these two devices lead to a significant difference in the crystal quality of the materials, making it difficult to achieve continuous growth of the materials and epitaxial monolithic integration of the two devices.

[0007] 4. Conventional AlN surface acoustic wave devices are mostly made of polycrystalline AlN material. Their filters have low electromechanical coupling coefficient, piezoelectric coefficient, sound velocity and power handling capability, as well as low quality factor, which limits the operating frequency and output power of surface acoustic wave devices, and the operating frequency band cannot be adjusted.

[0008] 5. The ferroelectric modulation layer below the gate of conventional GaN high electron mobility transistors is a polycrystalline material grown in situ, which introduces additional interface states and limits the monolithic ferroelectric integration of the device. Summary of the Invention

[0009] The purpose of this invention is to propose a monolithic heterogeneous integrated circuit for epitaxial nitride devices and its fabrication method, in order to solve the problems of existing surface acoustic wave devices having difficulty in controlling the operating frequency band, difficulty in epitaxial heterogeneous integration with high electron mobility transistors, and large package size.

[0010] The technical solution to achieve the objective of this invention is as follows:

[0011] 1. A monolithic heterogeneous integrated circuit for epitaxial nitride devices, characterized in that: from bottom to top, it includes a substrate, a nucleation layer, a channel layer, an insertion layer, a barrier layer, and a polarization layer, with a gate electrode and an interdigitated electrode disposed on the upper part of the polarization layer;

[0012] The interdigitated electrodes and their corresponding polarization layers below them constitute a nitride surface acoustic wave device.

[0013] A source electrode and a drain electrode are disposed on the ohmic contact region from the channel layer to the barrier layer. The source and drain electrodes, together with the channel layer, the insertion layer, the barrier layer, the gate electrode, and the polarization layer below the gate electrode, constitute a nitride high electron mobility transistor.

[0014] The nitride surface acoustic wave device is disposed on the barrier layer of the gate-source conduction region of the nitride high electron mobility transistor, and the interdigitated electrodes are filled with passivation layers between the gate electrode and the source electrode to achieve isolation between the two devices. The operating frequency band, bandwidth and sideband suppression ratio of the surface acoustic wave device can be controlled by adjusting the two-dimensional electron gas concentration of the high electron mobility transistor.

[0015] Furthermore, the polarization layer has a thickness of 500nm-1500nm and is constructed using Sc. m Al nN material, where the component 0 < m < 0.35, and m + n = 1;

[0016] Further, the barrier layer has a thickness of 6 nm to 30 nm and is made of Sc x In y Al z Ga w N material, where the components 0 ≤ x ≤ 0.3, 0 ≤ y ≤ 0.3, 0 ≤ z < 1, 0 ≤ w < 1 and x + y + z + w = 1;

[0017] Further, the substrate is made of any one of sapphire material, silicon material, silicon carbide material, diamond material, gallium nitride material, aluminum nitride material, boron nitride material, gallium oxide material;

[0018] Further, the passivation layer is made of any one of SiN material, Al2O3 material, HfO2 material;

[0019] Further, the channel layer is made of GaN material with a thickness of 500 nm - 4000 nm;

[0020] Further, the nucleation layer is made of AlN material with a thickness of 3 nm - 1000 nm;

[0021] Further, the insertion layer is made of AlN material with a thickness of 1 nm - 2 nm.

[0022] 2. A manufacturing method for a monolithic heterogeneous integrated circuit of an epitaxial nitride device, characterized by comprising the following steps:

[0023] 1) Using metalorganic chemical vapor deposition technology or molecular beam epitaxy technology, grow an AlN nucleation layer with a thickness of 3 nm - 1000 nm on a substrate wafer;

[0024] 2) Using metalorganic chemical vapor deposition method or molecular beam epitaxy technology, grow a GaN channel layer with a thickness of 500 nm - 4000 nm on the AlN nucleation layer;

[0025] 3) Using metalorganic chemical vapor deposition method or molecular beam epitaxy technology, grow an AlN insertion layer with a thickness of 1 nm - 2 nm on the GaN channel layer;

[0026] 4) Using metalorganic chemical vapor deposition method or molecular beam epitaxy technology, grow a barrier layer with a thickness of 6 nm - 30 nm on the AlN insertion layer;

[0027] 5) Using metalorganic chemical vapor deposition method or molecular beam epitaxy technology, grow a polarization layer with a thickness of 500 nm - 1500 nm on the barrier layer;

[0028] 6) Using photoresist as a mask on the polarization layer, select the source-drain ohmic contact region of the nitride high electron mobility transistor, and use dry etching to etch the polarization layer to the upper part of the channel layer to form a groove for the source-drain ohmic contact region.

[0029] 7) A Si-doped n-type GaN layer is grown in the groove of the source-drain ohmic contact region using metal-organic chemical vapor deposition or molecular beam epitaxy, with a Si dosage of (0.5-5)×10⁻⁶. 20 cm -3 This forms an ohmic contact region;

[0030] 8) Using photoresist as a mask, define the gate electrode region of the nitride high electron mobility transistor and the fabrication region of the nitride surface acoustic wave device. Use inductively coupled plasma etching method with BCl3 / Cl2 gas source to completely etch the polarization layer outside the fabrication region of the surface acoustic wave device and the gate electrode region of the high electron mobility transistor.

[0031] 9) Using photoresist as a mask, a dry etching process is used to thin the polarization layer of the gate electrode region of the nitride high electron mobility transistor to 30nm~80nm;

[0032] 10) Using photoresist as a mask, electron beam evaporation is used to first deposit ohmic contact metal Ti / Al / Ni / Au in the ohmic contact region, and then annealing is carried out at 830℃ in a nitrogen atmosphere to form the source electrode and drain electrode; then, using photoresist as a mask, the surface acoustic wave device fabrication area is selected, and electron beam evaporation is used to deposit metal Ti / Au on the polarization layer of the surface acoustic wave device fabrication area to form the interdigitated electrode of the surface acoustic wave device;

[0033] 11) Using photoresist as a mask and employing electron beam evaporation, Ni / Au metal is deposited on the polarization layer thinned in the gate electrode region of a high electron mobility transistor to form a gate electrode;

[0034] 12) A passivation layer with a thickness of 50nm-200nm is deposited on the entire surface of the device using plasma-enhanced chemical vapor deposition or atomic layer deposition.

[0035] 13) Using photoresist as a mask, reactive ion etching is employed with SF6 gas source to etch the passivation layer to form gate electrode vias, source electrode vias, drain electrode vias and interdigitated electrode vias;

[0036] 14) Using traditional optical lithography, gate electrode, source electrode, drain electrode and interdigitated electrode Pad patterns are formed on the device surface. Using photoresist as a mask, an Au metal layer is evaporated on each electrode Pad pattern using electron beam evaporation method to form leads between each electrode Pad pattern and each electrode, thus completing the fabrication of a monolithic heterogeneous radio frequency integrated circuit.

[0037] Compared with the prior art, the present invention has the following advantages:

[0038] 1. This invention integrates surface acoustic wave devices and high electron mobility transistors at the epitaxial level on a monolithic heterogeneous basis, which simplifies the integration and fabrication process of discrete devices, reduces parasitic inductance introduced during packaging, and is conducive to reducing chip area and system miniaturization, and improving the performance of radio frequency front-end circuits.

[0039] 2. The surface acoustic wave device of the present invention is located in the gate-source conduction region of a high electron mobility transistor. The operating frequency band, output power and filtering capability of the surface acoustic wave device can be changed by adjusting the two-dimensional electron gas concentration in the conductive channel of the high electron mobility transistor.

[0040] 3. This invention uses metal-organic chemical vapor deposition or molecular beam epitaxy to achieve the growth of surface acoustic wave devices and high electron mobility transistor materials in one step, solving the problem that polycrystalline material filters and single-crystal material high electron mobility transistors are difficult to integrate on a single wafer due to the inconsistency of material growth methods.

[0041] 4. The polarization layer in this invention uses a continuously epitaxially grown single-crystal ScAlN material. Due to the strong ferroelectric properties of this material, it can not only increase the gate control capability of the device and reduce the subthreshold swing of the device, but also positively increase the threshold voltage of the device, reducing the difficulty of gallium nitride integrated circuit integration design. At the same time, compared with the polycrystalline (Sc)AlN material grown by traditional magnetron sputtering, this material has a consistent crystal phase and higher piezoelectric coefficient, sound velocity and electromechanical coupling coefficient, thus improving the operating frequency, quality factor and power handling capability of surface acoustic wave devices, realizing the monolithic integration of piezoelectric material filter passive devices and single-crystal RF active devices. Attached Figure Description

[0042] Figure 1 This is a structural diagram of a traditional polycrystalline AlN surface acoustic wave device;

[0043] Figure 2 This is a structural diagram of a traditional AlGaN / GaN high electron mobility transistor;

[0044] Figure 3 This is a structural diagram of the monolithic heterogeneous integrated circuit of the epitaxial nitride device of the present invention;

[0045] Figure 4 This is a schematic diagram of the process for fabricating a monolithic heterogeneous integrated circuit with epitaxial nitride devices according to the present invention. Detailed Implementation

[0046] The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0047] Reference Figure 3 , the monolithic heterogeneous integrated circuit of the epitaxial nitride device in this example includes a substrate 1, a nucleation layer 2, a channel layer 3, an insertion layer 4, a barrier layer 5, a polarization layer 6, and a passivation layer 7, where:

[0048] The substrate 1 is made of any one of sapphire material, silicon material, silicon carbide material, diamond material, gallium nitride material, aluminum nitride material, boron nitride material, and gallium oxide material;

[0049] The nucleation layer 2 is located above the substrate 1, made of AlN material, with a thickness of 3 nm - 1000 nm;

[0050] The channel layer 3 is located above the nucleation layer 2, made of GaN material, with a thickness of 500 nm - 4000 nm;

[0051] The insertion layer 4 is located above the channel layer 3, made of AlN material, with a thickness of 1 nm - 2 nm;

[0052] The barrier layer 5 is located above the insertion layer 4, made of Sc x In y Al z Ga w N material with a composition of 0 ≤ x ≤ 0.3, 0 ≤ y ≤ 0.3, 0 ≤ z < 1, 0 ≤ w < 1 and x + y + z + w = 1, and a thickness of 6 nm - 30 nm;

[0053] The polarization layer 6 is located above the barrier layer 5, made of continuous epitaxial single crystal Sc m Al n N material with a composition of 0 < m < 0.35 and m + n = 1, and a thickness of 500 nm - 1500 nm. Interdigital electrodes and gate electrodes are provided on the polarization layer 6;

[0054] The channel layer 3 to the barrier layer 5 is an ohmic contact region, and source electrodes and drain electrodes are provided on the ohmic contact region;

[0055] The passivation layer 7 is filled between the interdigital electrodes and the gate electrodes, and between the source electrodes, the gate electrodes and the drain electrodes

[0056] The passivation layer 7 is made of any one of SiN material, Al2O3 material, and HfO2 material;

[0057] The interdigital electrode and the polarization layer 6 below it form a nitride surface acoustic wave device, and the source and drain electrodes, the channel layer 3, the insertion layer 4, the barrier layer 5, the gate electrode, and the polarization layer 6 corresponding to the lower part of the gate electrode form a nitride high electron mobility transistor. [[ID=H]]

[0058] Refer to Figure 4The following three embodiments are given as methods for fabricating the above-mentioned epitaxial nitride device monolithic heterogeneous integrated circuit.

[0059] Example 1: Fabrication of Sc on a gallium nitride substrate using molecular beam epitaxy. 0.18 Al 0.82 N-barrier layer, Sc 0.18 Al 0.82 N-polarized nitride devices are monolithic heterogeneous integrated circuits.

[0060] Step 1: Use molecular beam epitaxy (MBE) to epitaxially form AlN nucleation layers, such as... Figure 4 (a).

[0061] The set temperature is 600℃, the nitrogen flow rate is 0.6 sccm, and the aluminum beam equilibrium vapor pressure is 0.6 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 350W, uses molecular beam epitaxy to epitaxially form a 3nm thick AlN nucleation layer on a gallium nitride substrate.

[0062] Step two, use molecular beam epitaxy (MBE) to epitaxially grow the GaN channel layer, such as... Figure 4 (b)

[0063] The set temperature is 600℃, the nitrogen flow rate is 0.6 sccm, and the gallium beam equilibrium vapor pressure is 3.5 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 350W, uses molecular beam epitaxy to epitaxially form a GaN channel layer with a thickness of 500nm on an AlN nucleation layer.

[0064] Step 3: Use molecular beam epitaxy (MBE) to epitaxially grow an AlN insertion layer, such as... Figure 4 (c)

[0065] The set temperature is 600℃, the nitrogen flow rate is 0.6 sccm, and the aluminum beam equilibrium vapor pressure is 0.6 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 350W, uses molecular beam epitaxy to epitaxially grow a 1nm thick AlN insertion layer on the GaN channel layer.

[0066] Step four: Use molecular beam epitaxy to epitaxially grow Sc 0.18 Al 0.82 N-barrier layer, such as Figure 4 (d)

[0067] The set temperature is 650℃, the nitrogen flow rate is 0.6 sccm, and the scandium beam equilibrium vapor pressure is 0.5 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the aluminum beam is 0.6 × 10⁻⁶. -7Torr, using a nitrogen RF source with a power of 350W, molecular beam epitaxy was employed to epitaxially grow a 6nm thick Sc on an AlN insertion layer. 0.18 Al 0.82 N-barrier layer.

[0068] Step 5: Use molecular beam epitaxy to epitaxially grow Sc 0.18 Al 0.82 N-polarization layer, such as Figure 4 (e).

[0069] The set temperature is 650℃, the nitrogen flow rate is 0.6 sccm, and the scandium beam equilibrium vapor pressure is 0.5 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the aluminum beam is 0.6 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 350W, uses molecular beam epitaxy on Sc 0.18 Al 0.82 500nm Sc epitaxial layer on N-barrier layer 0.18 Al 0.82 N-polarization layer.

[0070] Step six: Using dry etching technology, fabricate grooves in the source-drain ohmic contact area, such as... Figure 4 (f).

[0071] In Sc 0.18 Al 0.82 Using photoresist as a mask on the N-polarized layer, the source-drain ohmic contact region of the nitride high electron mobility transistor was selected. Process conditions were set: Cl2 flow rate of 20 sccm, reaction chamber pressure of 15 mTorr, and electrode power of 220 W. The Sc in the source-drain ohmic contact region was then removed. 0.18 Al 0.82 N-polarization layer, Sc 0.18 Al 0.82 An N-barrier layer, an AlN insertion layer, and a partial GaN channel layer form a groove in the source-drain ohmic contact region.

[0072] Step 7: Use molecular beam epitaxy (MBE) to epitaxially grow a Si-doped n-type GaN layer to form source-drain ohmic contact regions, such as... Figure 4 (g)

[0073] The set temperature is 600℃, the nitrogen flow rate is 0.6 sccm, and the gallium beam equilibrium vapor pressure is 3.5 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the silicon beam is 1.6 × 10⁻⁶. -8 Torr, with a nitrogen RF source power of 350W, uses molecular beam epitaxy to deposit 60nm thick Si with a doping concentration of 0.5×10⁻⁶ in the source-drain ohmic contact region trenches. 20 cm -3n-type GaN layer.

[0074] Step eight involves using inductively coupled plasma etching (ICP-C) to form the gate electrode region of the nitride high electron mobility transistor and the fabrication area of ​​the nitride surface acoustic wave device, such as... Figure 4 (h).

[0075] Using photoresist as a mask, an inductively coupled plasma etching process was employed, with a Cl2 gas flow rate of 10 sccm, a BCl3 gas flow rate of 25 sccm, and an etching time of 50 s. This completely etched the Sc2 layer outside the fabrication area of ​​the surface acoustic wave device and the gate electrode area of ​​the high electron mobility transistor. 0.18 Al 0.82 N-polarization layer.

[0076] Step 9: Use dry etching technology to thin the Sc in the gate electrode region of the nitride high electron mobility transistor. 0.18 Al 0.82 N-polarization layer, such as Figure 4 (i).

[0077] Using photoresist as a mask on the device surface, and setting process conditions of Cl2 flow rate of 20 sccm, reaction chamber pressure of 15 mTorr, and electrode power of 220 W, the Sc2 in the gate electrode region of the nitride high electron mobility transistor was synthesized. 0.18 Al 0.82 The N-polarization layer was thinned to 50 nm.

[0078] Step 10: Fabricate the source electrode, drain electrode, and interdigitated electrode using electron beam evaporation technology, such as... Figure 4 (j).

[0079] 10.1) Using photoresist as a mask, select the source / drain ohmic contact region and set the vacuum level to less than 1.4 × 10⁻⁶. -3 Pa, power range of 400-800W, evaporation rate of The process conditions were as follows: first, Ti / Al / Ni / Au metal combinations were deposited on the source and drain ohmic contact regions, with metal thicknesses of 0.05μm / 0.12μm / 0.08μm / 0.08μm respectively; then, rapid thermal annealing was performed in a nitrogen atmosphere at a temperature of 830℃ for 30s to fabricate the source and drain electrodes of the nitride high electron mobility transistor.

[0080] 10.2) Using photoresist as a mask, select the fabrication area for the surface acoustic wave device and set the vacuum level to less than 1.4 × 10⁻⁶. - 3 Pa, power range of 400-800W, evaporation rate of The process conditions in the Surface Acoustic Wave (SAW) device fabrication area Sc 0.18 Al 0.82Ti / Au metal composites with thicknesses of 0.05 μm / 0.08 μm are deposited on the N-polarized layer to form the interdigitated electrodes of the nitride surface acoustic wave device.

[0081] Step eleven: Fabricate the gate electrode using electron beam evaporation technology, such as... Figure 4 (k).

[0082] Thinning of Sc in the gate electrode region of nitride high electron mobility transistors 0.18 Al 0.82 A mask is fabricated on the N-polarized layer, with a vacuum level set to less than 1.4 × 10⁻⁶. -3 Pa, power range of 400-800W, evaporation rate of The process conditions for thinning Sc 0.18 Al 0.82 Ni / Au metal composites with metal thicknesses of 0.04 μm / 0.5 μm were deposited on the N-polarized layer to complete the fabrication of the gate electrode.

[0083] Step 12: Deposit a 50nm Al2O3 passivation layer using atomic layer deposition (ALD) technology, such as... Figure 4 (l).

[0084] The process conditions were set as follows: time 40s, pressure 2000mTorr, temperature 300℃, Al(CH3)3 flow rate 850sccm, H2O flow rate 350sccm, and N2 flow rate 1000sccm. An Al2O3 passivation layer with a thickness of 50nm was deposited on the entire surface of the device using atomic layer deposition.

[0085] Step thirteen: Fabricate gate electrode vias, source electrode vias, drain electrode vias, and interdigitated electrode vias on the Al2O3 passivation layer, such as... Figure 4 (m).

[0086] Using photoresist as a mask, reactive ion etching was employed with process conditions set at a pressure of 1500 mTorr, a power of 200 W, an SF6 flow rate of 8 sccm, a CHF3 flow rate of 10 sccm, and a He flow rate of 150 sccm. The Al2O3 passivation layer was etched to the metal surfaces of each electrode to form gate electrode vias, source electrode vias, drain electrode vias, and interdigitated electrode vias, respectively.

[0087] Step fourteen: Using optical lithography and electron beam evaporation, each electrode pad is brought out on each electrode via to complete the fabrication of the monolithic integrated circuit, such as... Figure 4 (n).

[0088] 14.1) Using traditional optical lithography, each electrode pad pattern is formed on each electrode via;

[0089] 14.2) Using electron beam evaporation technology to The rate of evaporation of Au metal with a thickness of 80 nm is achieved on each electrode pad pattern to complete the fabrication of a monolithic integrated circuit.

[0090] Example 2: Al was fabricated on an aluminum nitride substrate using metal-organic chemical vapor deposition (MOCVD). 0.25 Ga 0.75 N-barrier layer, Sc 0.3 Al 0.7 N-polarized nitride devices are monolithic heterogeneous integrated circuits.

[0091] Step 1, deposit an AlN nucleation layer, such as Figure 4 (a).

[0092] Using metal-organic chemical vapor deposition (MOCVD), an AlN nucleation layer with a thickness of 1000 nm was epitaxially formed on an aluminum nitride substrate under the following process conditions: epitaxial temperature of 1200℃, pressure of 45 Torr, aluminum source flow rate of 18.0 sccm, ammonia flow rate of 3500 sccm, and hydrogen flow rate of 2500 sccm.

[0093] Step 2, deposit the GaN channel layer, such as Figure 4 (b)

[0094] Using metal-organic chemical vapor deposition (MOCVD), a GaN channel layer with a thickness of 4000 nm was deposited on an AlN nucleation layer under the following process conditions: temperature 1200℃, pressure 45 Torr, ammonia flow rate 3500 sccm, gallium source flow rate 180 sccm, and hydrogen flow rate 2500 sccm.

[0095] Step 3, deposit the AlN insertion layer, such as Figure 4 (c)

[0096] Using metal-organic chemical vapor deposition (MOCVD), with process conditions of 1200℃, 45 Torr, 18 sccm aluminum source flow rate, 3500 sccm ammonia flow rate, and 2500 sccm hydrogen flow rate, an AlN insertion layer with a thickness of 2 nm was deposited on the GaN channel layer.

[0097] Step 4, Al deposition 0.25 Ga 0.75 N-barrier layer, such as Figure 4 (d)

[0098] Using metal-organic chemical vapor deposition (MOCVD), with process conditions of 1200℃, 45 Torr, aluminum source flow rate of 10 sccm, gallium source flow rate of 80 sccm, ammonia flow rate of 3500 sccm, and hydrogen flow rate of 2500 sccm, a 30 nm thick Al layer was deposited on the AlN insertion layer. 0.25 Ga 0.75 N-barrier layer.

[0099] Step 5, Deposition of Sc 0.3 Al 0.7 N-polarization layer, such as Figure 4 (e).

[0100] Using metal-organic chemical vapor deposition (MOCVD), with process conditions of 1200℃, 80 Torr, aluminum source flow rate of 10 sccm, scandium source flow rate of 3000 sccm, ammonia flow rate of 3500 sccm, and hydrogen flow rate of 2500 sccm, the Al... 0.25 Ga 0.75 A Sc layer with a thickness of 1500 nm is deposited on the N-barrier layer. 0.3 Al 0.7 N-polarization layer.

[0101] Step 6: Dry etching to create grooves in the source-drain ohmic contact area, such as... Figure 4 (f).

[0102] In Sc 0.3 Al 0.7 Using photoresist as a mask on the N-polarized layer, the source-drain ohmic contact regions of the nitride high electron mobility transistor were selected. Dry etching was employed with process conditions of 18 sccm Cl2 flow rate, 12 mTorr reaction chamber pressure, and 160 W electrode power to remove Sc. 0.3 Al 0.7 N polarization layer, Al 0.25 Ga 0.75 An N-barrier layer, an AlN insertion layer, and a partial GaN channel layer form a groove in the source-drain ohmic contact region.

[0103] Step 7: Deposit a Si-doped n-type GaN layer to form the source / drain ohmic contact region, such as... Figure 4 (g)

[0104] Under process conditions of 1200℃, 45 Torr, gallium source flow rate of 60 sccm, silicon source flow rate of 800 sccm, ammonia flow rate of 3500 sccm, and hydrogen flow rate of 2500 sccm, a 120 nm thick Si layer with a doping concentration of 5 × 10⁻⁶ was deposited in the source-drain ohmic contact region trench. 20 cm -3 n-type GaN layer.

[0105] Step 8: Etch to form the fabrication area of ​​the nitride surface acoustic wave device and the gate electrode area of ​​the nitride high electron mobility transistor, such as... Figure 4 (h).

[0106] Using photoresist as a mask, an inductively coupled plasma etching process was employed with a Cl2 gas flow rate of 10 sccm, a BCl3 gas flow rate of 25 sccm, and an etching time of 200 s to completely etch the Sc2 surface acoustic wave device fabrication area and the area outside the gate electrode region of the high electron mobility transistor. 0.3 Al 0.7 N-polarization layer.

[0107] Step 9: Use dry etching technology to thin the Sc in the gate electrode region of the nitride high electron mobility transistor. 0.3 Al 0.7 N-polarization layer, such as Figure 4 (i).

[0108] In Sc 0.3 Al 0.7 Using photoresist as a mask on the N-polarized layer, and employing process conditions of 18 sccm Cl2 flow rate, 12 mTorr reaction chamber pressure, and 160 W electrode power, the Sc2 in the gate electrode region of a nitride high electron mobility transistor was applied. 0.3 Al 0.7 The N-polarization layer was thinned to 80 nm.

[0109] Step 10: Fabricate the source electrode, drain electrode, and interdigitated electrode, as follows: Figure 4 (j).

[0110] 10a) Using photoresist as a mask, select the source-drain ohmic contact region, and employ electron beam evaporation technology at a vacuum level of less than 1.6 × 10⁻⁶. -3 Pa, power range of 600-900W, evaporation rate of Under the specified process conditions, Ti / Al / Ni / Au metal combinations were deposited on the source and drain ohmic contact regions, with metal thicknesses of 0.02μm / 0.2μm / 0.05μm / 0.05μm, respectively, to complete the fabrication of the source and drain electrodes of the nitride high electron mobility transistor.

[0111] 10b) Using photoresist as a mask, select the fabrication area for the surface acoustic wave device, and perform electron beam evaporation with a vacuum degree of less than 1.6 × 10⁻⁶. -3 Pa, power range of 600-900W, evaporation rate of The process conditions in the fabrication area of ​​acoustic surface wave devices (Sc) 0.3 Al 0.7Ti / Au metal composites with metal thicknesses of 0.02 μm / 0.05 μm were deposited on the N-polarized layer to complete the fabrication of interdigitated electrodes for the nitride surface acoustic wave device.

[0112] Step 11, fabricate the gate electrode, such as Figure 4 (k).

[0113] Thinning of Sc in the gate electrode region of nitride high electron mobility transistors 0.3 Al 0.7 A mask was fabricated on the N-polarized layer using electron beam evaporation technology at a vacuum level of less than 1.5 × 10⁻⁶. -3 Pa, power range of 300-800W, evaporation rate of The process conditions in Sc 0.3 Al 0.7 Ni / Au metal composites with metal thicknesses of 0.03 μm / 0.4 μm were deposited on the N-polarized layer to complete the fabrication of the gate electrode.

[0114] Step 12, deposit an HfO2 passivation layer, such as Figure 4 (l).

[0115] Using atomic layer deposition (ALD), a 100 nm thick HfO2 passivation layer was deposited on the entire upper surface of the device under the following conditions: time 70 s, temperature 280 °C, ethyl methylamino hafnium flow rate 1200 sccm, H2O flow rate 110 sccm, and N2 flow rate 1000 sccm.

[0116] Step 13: Etch to form gate electrode vias, source electrode vias, drain electrode vias, and interdigitated electrode vias on the HfO2 passivation layer, such as... Figure 4 (m).

[0117] Using photoresist as a mask, reactive ion etching was employed under the following process conditions: pressure of 1500 mTorr, power of 200 W, SF6 flow rate of 8 sccm, CHF3 flow rate of 10 sccm, and He flow rate of 150 sccm. The HfO2 passivation layer was etched to the metal surfaces of the gate electrode, source electrode, drain electrode, and interdigitated electrode, forming gate electrode vias, source electrode vias, drain electrode vias, and interdigitated electrode vias, respectively.

[0118] Step 14: Lead out each electrode pad from each electrode via to complete the fabrication of the monolithic integrated circuit, such as... Figure 4 (n).

[0119] First, traditional optical lithography is used to photolithographically form metal pad patterns on the gate electrode, source electrode, drain electrode, and interdigitated electrode; then, electron beam evaporation technology is used on each electrode pad pattern to... Au metal with a thickness of 80nm was evaporated at a high speed to complete the fabrication of a monolithic integrated circuit.

[0120] Example 3: In was fabricated on a silicon carbide substrate using molecular beam epitaxy. 0.17 Al 0.83 N-barrier layer, Sc 0.1 Al 0.9 N-polarized nitride devices are monolithic heterogeneous integrated circuits.

[0121] Step A, epitaxial AlN nucleation layer, such as Figure 4 (a).

[0122] Molecular beam epitaxy was used to epitaxially form a 200 nm thick AlN nucleation layer on a silicon carbide substrate.

[0123] The process conditions for molecular beam epitaxy were: temperature 750℃, nitrogen flow rate 3.0 sccm, and aluminum beam equilibrium vapor pressure 3.2 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 350W.

[0124] Step B, epitaxial GaN channel layer, such as Figure 4 (b)

[0125] A GaN channel layer with a thickness of 2000 nm was epitaxially formed on an AlN nucleation layer using molecular beam epitaxy.

[0126] The process conditions for molecular beam epitaxy were: temperature 750℃, nitrogen flow rate 3.0 sccm, and gallium beam equilibrium vapor pressure 9.5 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 350W.

[0127] Step C, epitaxial AlN insertion layer, such as Figure 4 (c)

[0128] Molecular beam epitaxy was used to deposit an AlN insertion layer with a thickness of 1.5 nm on the GaN channel layer.

[0129] The process conditions for molecular beam epitaxy were: temperature 750℃, nitrogen flow rate 3.0 sccm, and aluminum beam equilibrium vapor pressure 3.2 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 350W.

[0130] Step D, Deposition of In 0.17 Al 0.83 N-barrier layer, such as Figure 4 (d)

[0131] Molecular beam epitaxy was used to epitaxially grow an In layer with a thickness of 15 nm on the AlN insertion layer. 0.17 Al 0.83 N-barrier layer.

[0132] The process conditions for molecular beam epitaxy were: temperature 600℃, nitrogen flow rate 3.0 sccm, and indium beam equilibrium vapor pressure 2.1 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the aluminum beam is 1.2 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 350W.

[0133] Step E, Deposition of Sc 0.1 Al 0.9 N-polarization layer, such as Figure 4 (e).

[0134] Using molecular beam epitaxy, in In 0.17 Al 0.83 On the N-barrier layer, an epitaxial Sc layer with a thickness of 1000 nm is formed. 0.1 Al 0.9 N-polarization layer.

[0135] The process conditions for molecular beam epitaxy were: temperature 680℃, nitrogen flow rate 3.0 sccm, and scandium beam equilibrium vapor pressure 0.5 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the aluminum beam is 3.2 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 350W.

[0136] Step F: Dry etching to create grooves in the source-drain ohmic contact area, such as... Figure 4 (f).

[0137] In Sc 0.1 Al 0.9 A mask is fabricated on the N-polarized layer, and photoresist is used as the mask. The drain-ohm contact region of the nitride high electron mobility transistor is selected, and a dry etching method is used to remove the Sc from the source-drain ohm contact region. 0.1 Al 0.9 N polarization layer, In 0.17 Al 0.83 An N-barrier layer, an AlN insertion layer, and a partial GaN channel layer form a groove in the source-drain ohmic contact region.

[0138] The etching process conditions were: Cl2 flow rate of 15 sccm, reaction chamber pressure of 11 mTorr, and electrode power of 180 W.

[0139] Step G: Deposit a Si-doped n-type GaN layer to form the source / drain ohmic contact region, such as... Figure 4 (g)

[0140] A 50 nm thick Si-doped n-type GaN layer with a Si doping concentration of 1.0 × 10⁻⁶ was deposited in the groove of the source-drain ohmic contact region using molecular beam epitaxy. 20 cm -3 .

[0141] The process conditions for molecular beam epitaxy were: temperature 750℃, nitrogen flow rate 3.0 sccm, and gallium beam equilibrium vapor pressure 9.5 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the silicon beam is 2.8 × 10⁻⁶. -8 Torr, with a nitrogen RF source power of 350W.

[0142] Step H involves etching to form the fabrication area for the nitride surface acoustic wave device and the gate electrode area for the nitride high electron mobility transistor, such as... Figure 4 (h).

[0143] Using photoresist as a mask, an inductively coupled plasma etching process was employed, with a Cl2 gas flow rate of 10 sccm, a BCl3 gas flow rate of 25 sccm, and an etching time of 150 s. This process completely etched the Sc2 layer outside the fabrication area of ​​the surface acoustic wave device and the gate electrode area of ​​the high electron mobility transistor. 0.1 Al 0.9 N-polarization layer.

[0144] Step I: Thinning the Sc in the gate electrode region of the nitride high electron mobility transistor 0.1 Al 0.9 N-polarization layer, such as Figure 4 (i).

[0145] In Sc 0.1 Al 0.9 Using photoresist as a mask, a dry etching process is employed to thin the Sc region of the gate electrode area of ​​the nitride high electron mobility transistor on the N-polarization layer. 0.1 Al 0.9 The N-polarization layer reaches 30nm.

[0146] The etching process conditions were: Cl2 flow rate of 15 sccm, reaction chamber pressure of 11 mTorr, and electrode power of 180 W.

[0147] Step J: Fabricate the source electrode, drain electrode, and interdigitated electrode, as follows... Figure 4 (j).

[0148] J.1) Using photoresist as a mask, the source and drain ohmic contact regions were selected. Electron beam evaporation was used to deposit Ti / Al / Ni / Au metal combinations with metal thicknesses of 0.02μm / 0.05μm / 0.04μm / 0.04μm on the source and drain ohmic contact regions, respectively. Then, rapid thermal annealing was performed in a nitrogen atmosphere at 830℃ to fabricate the source and drain electrodes.

[0149] J.2) Using photoresist as a mask, the area for fabricating the surface acoustic wave (SAW) device is selected, and electron beam evaporation is used to deposit Sk on the Sk of the SAW device fabrication area. 0.1 Al 0.9A metal composite Ti / Au with a thickness of 0.02 μm / 0.04 μm is deposited on the N-polarized layer to form interdigitated electrodes.

[0150] The process conditions used for metal deposition are: vacuum degree less than 1.5 × 10⁻⁶. -3 Pa, power range of 500-800W, evaporation rate of The process conditions for rapid hot annealing are: temperature 830℃ and time 30s.

[0151] Step K: Fabricate the gate electrode, such as... Figure 4 (k).

[0152] Using photoresist as a mask, thinning of Sc in the gate electrode region of a nitride high electron mobility transistor. 0.1 Al 0.9 A mask is fabricated on the N-polarized layer, and electron beam evaporation is used to fabricate the mask on the thinned Sc layer. 0.1 Al 0.9 The gate electrode is fabricated by depositing metal on the N-polarized layer, wherein the deposited metal is a Ni / Au metal combination with a thickness of 0.02μm / 0.3μm.

[0153] The process conditions used for metal deposition are: vacuum degree less than 1.4 × 10⁻⁶. -3 Pa, power range of 400-800W, evaporation rate of

[0154] Step L, deposit a SiN passivation layer, such as Figure 4 (l).

[0155] A 200 nm thick SiN passivation layer was deposited on the entire upper surface of the device using plasma-enhanced chemical vapor deposition.

[0156] The process conditions used in the plasma-enhanced chemical vapor deposition method were as follows: time 60 s, pressure 2200 mTorr, temperature 350 ℃, SiH4 flow rate 13.5 sccm, NH3 flow rate 10 sccm, and N2 flow rate 1000 sccm.

[0157] Step M involves fabricating gate electrode vias, source electrode vias, drain electrode vias, and interdigitated electrode vias on the SiN passivation layer, such as... Figure 4 (m).

[0158] Using photoresist as a mask, reactive ion etching is employed to etch the SiN passivation layer to the metal surfaces of the gate electrode, source electrode, drain electrode, and interdigitated electrode, forming gate electrode vias, source electrode vias, drain electrode vias, and interdigitated electrode vias.

[0159] The process conditions adopted by the reactive ion etching method are as follows: the pressure is 1500 mTorr, the power is 200 W, the flow rate of SF6 is 8 sccm, the flow rate of CHF3 is 10 sccm, and the flow rate of He is 150 sccm.

[0160] Step N, lead out each electrode Pad on each electrode through hole to complete the production of a monolithic integrated circuit, such as Figure 4 (n).

[0161] Adopt the traditional optical lithography process to lithographically form the metal Pad patterns of the gate electrode, source electrode, drain electrode and interdigital electrode on each electrode through hole; use the electron beam evaporation method, according to the rate to evaporate Au metal with a thickness of 80 nm on each electrode Pad to complete the production of a monolithic integrated circuit.

[0162] The above description is only three specific examples of the present invention and does not constitute any limitation to the present invention. Obviously, for professionals in this field, after understanding the content and principle of the present invention, various modifications and changes in form and details may be made without departing from the principle and structure of the present invention. For example, in addition to the gallium nitride material, aluminum nitride material, and silicon carbide material that have been used for the substrate, sapphire material, silicon material, diamond material, boron nitride material, and gallium oxide material can also be used; in addition to the Sc 0.18 Al 0.82 N, Al 0.25 Ga 0.75 N, In 0.17 Al 0.83 N used for the barrier layer, Sc x In y Al z Ga w N materials with components of 0≤x≤0.3, 0≤y≤0.3, 0≤z<1, 0≤w<1 and x + y + z + w = 1 and a thickness of 6 nm to 30 nm can also be used; in addition to the Sc 0.18 Al 0.82 N, Sc 0.3 Al 0.7 N, Sc 0.1 Al 0.9 N used for the polarization layer, single crystal Sc m Al n [ N materials with components of 0 < m < 0.35 and m + n = 1 and a continuously epitaxial thickness of 500 nm - 1500 nm can also be adopted; however, these corrections and changes based on the idea of the present invention are still within the scope of the claims of the present invention.

Claims

1. A monolithic heterogeneous integrated circuit for epitaxial nitride devices, characterized in that: From bottom to top, it includes a substrate (1), a nucleation layer (2), a channel layer (3), an insertion layer (4), a barrier layer (5), and a polarization layer (6). A gate electrode and an interdigitated electrode are disposed on the upper part of the polarization layer (6). The interdigitated electrodes and their corresponding polarization layer (6) below them constitute a nitride surface acoustic wave device; Source and drain electrodes are disposed on the ohmic contact region from the channel layer (3) to the barrier layer (5). The source and drain electrodes, together with the channel layer (3), the insertion layer (4), the barrier layer (5), the gate electrode, and the polarization layer (6) below the gate electrode, constitute a nitride high electron mobility transistor. The nitride surface acoustic wave device is disposed on the barrier layer (5) of the gate-source conduction region of the nitride high electron mobility transistor, and the interdigitated electrodes are filled with passivation layers (7) between the gate electrode and the source electrode, respectively, to achieve isolation between the two devices. The operating frequency band, bandwidth and sideband suppression ratio of the nitride surface acoustic wave device can be controlled by adjusting the two-dimensional electron gas concentration of the nitride high electron mobility transistor.

2. The integrated circuit as described in claim 1, characterized in that: The polarization layer (6) has a thickness of 500 nm - 1500 nm and is made of Sc m Al n N material, where 0 < m < 0.35 and m + n = 1.

3. The integrated circuit as described in claim 1, characterized in that: The barrier layer (5) has a thickness of 6 nm to 30 nm and is constructed using Sc. x In y Al z Ga w Material N, wherein the composition is 0≤x≤0.3, 0≤y≤0.3, 0≤z<1, 0≤w<1 and x+y+z+w=1.

4. The integrated circuit as described in claim 1, characterized in that: The substrate (1) is made of any one of the following materials: sapphire, silicon, silicon carbide, diamond, gallium nitride, aluminum nitride, boron nitride, and gallium oxide. The passivation layer (7) is made of any one of SiN, Al2O3, or HfO2 materials.

5. The integrated circuit as described in claim 1, characterized in that: The channel layer (3) is made of GaN material and has a thickness of 500 nm-4000 nm; The nucleation layer (2) is made of AlN material and has a thickness of 3 nm-1000 nm. The insertion layer (4) is made of AlN material and has a thickness of 1 nm-2 nm.

6. A method for fabricating a monolithic heterogeneous integrated circuit with epitaxial nitride devices, comprising the following steps: 1) Using metal-organic chemical vapor deposition or molecular beam epitaxy, an AlN nucleation layer (2) of 3 nm-1000 nm is grown on a substrate (1). 2) Using metal-organic chemical vapor deposition or molecular beam epitaxy, a GaN channel layer (3) of 500 nm-4000 nm is grown on the AlN nucleation layer (2). 3) Using metal-organic chemical vapor deposition or molecular beam epitaxy, an AlN insertion layer (4) with a thickness of 1 nm-2 nm is grown on the GaN channel layer (3). 4) Using metal-organic chemical vapor deposition or molecular beam epitaxy, a barrier layer (5) with a thickness of 6 nm-30 nm is grown on the AlN insertion layer (4). 5) Using metal-organic chemical vapor deposition or molecular beam epitaxy, a polarization layer (6) with a thickness of 500 nm-1500 nm is grown on the barrier layer (5). 6) Using photoresist as a mask on the polarization layer (6), select the source-drain ohmic contact region of the nitride high electron mobility transistor, and use dry etching to etch the polarization layer (6) to the upper part of the channel layer (3) to form a groove for the source-drain ohmic contact region. 7) A Si-doped n-type GaN layer is grown in the groove of the source-drain ohmic contact region using metal-organic chemical vapor deposition or molecular beam epitaxy, with a Si dosage of (0.5-5)×10⁻⁶. 20 cm -3 This forms an ohmic contact region; 8) Using photoresist as a mask, define the gate electrode region of the nitride high electron mobility transistor and the fabrication region of the nitride surface acoustic wave device. Using inductively coupled plasma etching method and BCl3 / Cl2 gas source, completely etch the polarization layer outside the fabrication region of the surface acoustic wave device and the gate electrode region of the high electron mobility transistor (6). 9) Using photoresist as a mask, the polarization layer (6) of the gate electrode region of the nitride high electron mobility transistor is thinned to 30 nm~80 nm using a dry etching process; 10) Using photoresist as a mask, electron beam evaporation process is used to first deposit ohmic contact metal Ti / Al / Ni / Au in the ohmic contact area, and then annealing is carried out at 830 °C in a nitrogen atmosphere to form source and drain electrodes; then using photoresist as a mask, the surface acoustic wave device fabrication area is selected, and electron beam evaporation process is used to deposit metal Ti / Au on the polarization layer (6) of the surface acoustic wave device fabrication area to form interdigitated electrodes of the surface acoustic wave device; 11) Using photoresist as a mask and employing electron beam evaporation, Ni / Au metal is deposited on the polarization layer (6) thinned in the gate electrode region of the high electron mobility transistor to form the gate electrode; 12) A passivation layer with a thickness of 50 nm-200 nm is deposited on the entire surface of the device using plasma-enhanced chemical vapor deposition or atomic layer deposition (7). 13) Using photoresist as a mask, reactive ion etching is used with SF6 gas source to etch the passivation layer (7) to form gate electrode vias, source electrode vias, drain electrode vias and interdigitated electrode vias; 14) Using traditional optical lithography, gate electrode, source electrode, drain electrode and interdigitated electrode Pad patterns are formed on the device surface. Using photoresist as a mask, an Au metal layer is evaporated on each electrode Pad pattern using electron beam evaporation method to form leads between each electrode Pad pattern and each electrode, thus completing the fabrication of a monolithic heterogeneous integrated circuit.

7. The manufacturing method as described in claim 6, characterized in that: The process conditions for the organometallic chemical vapor deposition method described in steps 1) to 3) are as follows: The temperature is 950 o C-1250 o C, pressure is 40 Torr-50 Torr, aluminum source flow rate is 3 sccm-20 sccm, gallium source flow rate is 60 sccm-200 sccm, ammonia flow rate is 3500 sccm, and hydrogen flow rate is 2500 sccm.

8. The manufacturing method as described in claim 6, characterized in that: The molecular beam epitaxy technique described in steps 1) to 3) has the following process conditions: The temperature is 600 o C-750 o C, nitrogen flow rate is 0.6 sccm - 3.0 sccm, aluminum beam equilibrium vapor pressure is 0.6 × 10⁻⁶. -7 Torr-3.2×10 -7 Torr, the equilibrium vapor pressure of the gallium beam is 3.5 × 10⁻⁶. -7 Torr-9.5×10 -7 Torr, with a nitrogen RF source power of 350 W.

9. The manufacturing method as described in claim 6, characterized in that: The process conditions for the organometallic chemical vapor deposition method described in step 4) are as follows: The temperature is 950 o C-1250 o C, pressure is 40 Torr-100 Torr, scandium source flow rate is 2000 sccm-5000 sccm, aluminum source flow rate is 3 sccm-20 sccm, gallium source flow rate is 60 sccm-200 sccm, indium source flow rate is 50 sccm-120 sccm, ammonia flow rate is 3500 sccm, and hydrogen flow rate is 2500 sccm; The process conditions for the organometallic chemical vapor deposition method described in step 5) are as follows: The temperature is 950 o C-1250 o C, pressure is 40 Torr-100 Torr, scandium source flow rate is 2000 sccm-5000 sccm, aluminum source flow rate is 3 sccm-20 sccm, ammonia flow rate is 3500 sccm, and hydrogen flow rate is 2500 sccm.

10. The manufacturing method as described in claim 6, characterized in that: The molecular beam epitaxy technique described in step 4) has the following process conditions: The temperature is 600 o At C-750 ℃, the nitrogen flow rate is 0.6 sccm-3.0 sccm, and the aluminum beam equilibrium vapor pressure is 0.6×10⁻⁶. -7 Torr-3.2×10 -7 Torr, the equilibrium vapor pressure of the gallium beam is 3.5 × 10⁻⁶. -7 Torr-9.5×10 -7 Torr, the equilibrium vapor pressure of the scandium beam is 0.2 × 10⁻⁶. -7 Torr-0.5×10 -7 Torr, the equilibrium vapor pressure of the indium beam is 0.8 × 10⁻⁶. -7 Torr-2.1×10 -7 Torr, with a nitrogen-based radio frequency source power of 350 W; The molecular beam epitaxy technique described in step 5) has the following process conditions: The temperature is 600 o At C-750 ℃, the nitrogen flow rate is 0.6 sccm-3.0 sccm, and the aluminum beam equilibrium vapor pressure is 0.6×10⁻⁶. -7 Torr-3.2×10 -7 Torr, the equilibrium vapor pressure of the scandium beam is 0.2 × 10⁻⁶. -7 Torr-0.5×10 -7 Torr, with a nitrogen RF source power of 350 W.

Images