Pixel circuit and driving method thereof, and display device

Abstract

A pixel circuit and a driving method thereof, and a display device, wherein the pixel circuit includes a driving subcircuit, a writing subcircuit, a first resetting subcircuit and a light-emitting element, wherein: the driving subcircuit is configured to provide a driving current between a first pole and a second pole of the driving subcircuit in response to a control signal of a first node; the writing subcircuit is configured to write a data voltage signal to the first pole of the driving subcircuit in response to a control signal of a first scanning signal line; the first resetting subcircuit is configured to reset the anode terminal of the light-emitting element in response to a control signal of a second scanning signal line; in a low-frequency display mode, the input frequency of the control signal of the first scanning signal line is the same as the data refresh frequency, and the input frequency of the control signal of the second scanning signal line is greater than the data refresh frequency.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a pixel circuit and a driving method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] An embodiment of the present disclosure provides a pixel circuit, including a driving subcircuit, a writing subcircuit, a first reset subcircuit and a light-emitting element, wherein: the driving subcircuit is configured to provide a driving current between a first pole and a second pole of the driving subcircuit in response to a control signal of a first node; the writing subcircuit is configured to write a data voltage signal to the first pole of the driving subcircuit in response to a control signal of a first scanning signal line; the first reset subcircuit is configured to reset the anode terminal of the light-emitting element in response to a control signal of a second scanning signal line; in a low-frequency display mode, the input frequency of the control signal of the first scanning signal line is the same as the data refresh frequency, and the input frequency of the control signal of the second scanning signal line is greater than the data refresh frequency.

[0005] An embodiment of the present disclosure further provides a display device, comprising a pixel circuit as described in any of the preceding items.

[0006] The disclosed embodiment also provides a method for driving a pixel circuit, which is used to drive a pixel circuit as described in any of the above, and the driving method includes: in a reset stage, a first reset subcircuit responds to a control signal of a second scan signal line to reset the anode terminal of a light-emitting element; in a data writing stage, a writing subcircuit responds to a control signal of a first scan signal line to write a data voltage signal to a first pole of a driving subcircuit; in a light-emitting stage, a driving subcircuit responds to a control signal of a first node to provide a driving current between a first pole and a second pole of the driving subcircuit; in a low-frequency display mode, an input frequency of a control signal of the first scan signal line is the same as a data refresh frequency, and an input frequency of a control signal of the second scan signal line is greater than the data refresh frequency.

[0007] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0009] Figure 1 It is a structural schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

[0010] Figure 2 An equivalent circuit diagram of a first reset sub-circuit, a drive sub-circuit and a write sub-circuit according to an embodiment of the present disclosure;

[0011] Figure 3 An equivalent circuit diagram of a second reset sub-circuit, a compensation sub-circuit, a storage sub-circuit and an anti-leakage electronic circuit according to an embodiment of the present disclosure;

[0012] Figure 4 An equivalent circuit diagram of a first light-emitting control subcircuit and a second light-emitting control subcircuit according to an embodiment of the present disclosure;

[0013] Figure 5 is a schematic diagram of an equivalent circuit of a pixel circuit according to an embodiment of the present disclosure;

[0014] Figure 6 for Figure 5 The working timing diagram of the pixel circuit shown in the normal mode;

[0015] Figure 7 is a schematic diagram of an equivalent circuit of another pixel circuit according to an embodiment of the present disclosure;

[0016] Figure 8 for Figure 7The working timing diagram of the pixel circuit shown in the normal mode;

[0017] Fig. 9 for Figure 7 The working timing diagram of the pixel circuit shown in the low frequency mode;

[0018] Fig.10 is a schematic diagram of an equivalent circuit of another pixel circuit according to an embodiment of the present disclosure;

[0019] Fig.11A A schematic diagram of a planar structure of a pixel circuit according to an embodiment of the present disclosure;

[0020] Fig. 11B A schematic diagram of a light shielding layer pattern in a pixel circuit according to an embodiment of the present disclosure;

[0021] Fig. 11C A schematic diagram of a first semiconductor layer pattern in a pixel circuit according to an embodiment of the present disclosure;

[0022] Fig.11D It is a schematic diagram of a first conductive layer pattern in a pixel circuit according to an embodiment of the present disclosure;

[0023] Fig.11E A schematic diagram of a second conductive layer pattern in a pixel circuit according to an embodiment of the present disclosure;

[0024] Fig.11F A schematic diagram of a second semiconductor layer pattern in a pixel circuit according to an embodiment of the present disclosure;

[0025] Fig.11G It is a schematic diagram of a third conductive layer pattern in a pixel circuit according to an embodiment of the present disclosure;

[0026] Fig.11H A schematic diagram of a polysilicon via pattern formed in a pixel circuit according to an embodiment of the present disclosure;

[0027] Fig.11I A schematic diagram of an oxide via pattern formed in a pixel circuit according to an embodiment of the present disclosure;

[0028] Fig.11J It is a schematic diagram of a fourth conductive layer pattern in a pixel circuit according to an embodiment of the present disclosure;

[0029] Figure 11K A schematic diagram of a first planar layer pattern in a pixel circuit according to an embodiment of the present disclosure;

[0030] Fig.11L It is a schematic diagram of a fifth conductive layer pattern in a pixel circuit according to an embodiment of the present disclosure;

[0031] Fig.11M It is a schematic diagram of a second planar layer pattern in a pixel circuit according to an embodiment of the present disclosure;

[0032] Fig.11N A schematic diagram of an anode pattern in a pixel circuit according to an embodiment of the present disclosure;

[0033] Fig.11O A schematic diagram of a pixel definition layer pattern in a pixel circuit according to an embodiment of the present disclosure;

[0034] Fig. 12A for Fig.11A A cross-sectional view along the A-A' direction;

[0035] Fig. 12B for Fig.11A A cross-sectional view taken along the B-B' direction;

[0036] Fig. 12C for Fig.11A Sectional view along the C-C' direction;

[0037] Fig.12D for Fig.11A A cross-sectional view along the D-D' direction;

[0038] Fig.12E for Fig.11A Sectional view along E-E' direction;

[0039] Figures 13 to 17 Five structural schematic diagrams of display devices provided in embodiments of the present disclosure. DETAILED DESCRIPTION

[0040] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. Note that the embodiments can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0041] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprising" and similar words always cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0042] In the embodiments of the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0043] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0044] In this specification, "connection" includes the case where components are connected together through an element having some kind of electrical function. There is no particular limitation on the "element having some kind of electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some kind of electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0045] OLED display devices have many advantages such as self-luminescence, low driving voltage, high luminous efficiency, short response time and wide operating temperature range, and are recognized as the display devices with the most development potential. OLEDs are divided into passive organic electroluminescent diodes (Passive matrix OLED, PMOLED) and active matrix organic light-emitting diodes (ActiveMatrix OLED, AMOLED) according to the driving method. The AMOLED display device has multiple pixels arranged in an array, and each pixel is driven to emit light through a pixel circuit. For dynamic pictures, the display quality can be improved by increasing the refresh frequency of the picture. For some relatively static pictures, since there is no need for high-frequency refresh, the power consumption of the display device can be saved by reducing the refresh frequency of the picture. In order to make the AMOLED display device compatible with the characteristics of high-frequency refresh and low power consumption, the AMOLED display device needs to support dynamic frequency refresh.

[0046] Currently, Always On Display (AOD) has become a must-have feature for many portable devices such as smartphones and smart watches. In AOD mode, the screen displays time and simple information, and there is no need for high-speed refresh. Since AOD occupies a long period of user time, low-frequency refresh is conducive to saving power consumption of the device and extending battery life.

[0047] In the pixel circuit using low temperature polycrystalline oxide (LTPO) technology, the switch transistor (Thin Film Transistor, TFT) connected to the control electrode of the drive transistor (Drive Thin Film Transistor, DTFT) is replaced with a low leakage oxide transistor (Oxide TFT). Due to the low leakage of Oxide TFT, the brightness of the OLED changes slightly over a long period of time (>0.1s, or even more than 1s), thus achieving low frame rate display and high brightness retention rate.

[0048] Assume that in low-frequency mode, the data refresh frequency of the pixel circuit is 60Hz, that is, the pixel circuit refreshes and writes data at a frequency of 60Hz, and the subsequent time is maintained. In order to better eliminate the flicker phenomenon, the OLED display device simulates a 60Hz drive, that is, the control signal of the light-emitting control signal line EM is refreshed at a frequency of 60Hz (if there is a PWM dimming setting, the refresh frequency of the control signal of the light-emitting control signal line EM can be 240Hz or higher). However, at this time, the actual screen effect is that the flicker is still visible to the naked eye. The main reason is that in the refresh stage, since the reset subcircuit resets the anode end of the light-emitting element, it takes a certain amount of time to charge the capacitor of the light-emitting element after the control signal of the light-emitting control signal line EM is turned on, resulting in a slow rise in the brightness of the light-emitting element, especially in low grayscale, the brightness stability takes about several milliseconds (ms). In the retention stage, although there is a periodic black insertion of the light-emitting control signal line EM, the anode end of the light-emitting element is not reset, so the brightness of the light-emitting element can quickly reach a stable state. Therefore, in the refresh stage and the retention stage, the brightness waveform of the light-emitting element is inconsistent, resulting in visible screen flickering.

[0049] In some pixel circuit design schemes, the control signal of the first scanning signal line is also designed to be driven at high frequency, that is, in the refresh stage and the hold stage, the anode terminal of the light-emitting element is reset, so that in the refresh stage and the hold stage, the time for the brightness of the light-emitting element to reach a stable state remains consistent, so the low-frequency component in the brightness waveform is eliminated, and the screen flicker is significantly improved. However, after the control signal of the first scanning signal line is designed to be driven at high frequency, not only the anode terminal of the light-emitting element is reset at high frequency, but also the source terminal of the driving transistor will repeatedly write the data voltage signal and the voltage signal of the first power line, and through the parasitic capacitance, jump coupling to the gate terminal of the driving transistor, affecting the current stability; in addition, in the refresh stage and the hold stage, the potential of the first pole of the anti-leakage transistor will be different (in the refresh stage, the potential of the first pole of the anti-leakage transistor is Vdata+Vth, in the hold stage, the potential of the first pole of the anti-leakage transistor is Vdata-Vds, where Vdata is the data voltage, Vth is the threshold voltage of the driving transistor, and Vds is the source-drain voltage difference of the driving transistor), which will also affect the current stability.

[0050] The present disclosure provides a pixel circuit. Figure 1 A schematic diagram of the structure of a pixel circuit provided in an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the pixel circuit includes: a driving sub-circuit 101, a writing sub-circuit 102, a first resetting sub-circuit 103 and a light emitting element EL.

[0051] Among them, the driving subcircuit 101 is connected to the first node N1, the second node N2 and the third node N3 respectively, and is configured to provide a driving current between the first pole (i.e., the second node N2) and the second pole (i.e., the third node N3) of the driving subcircuit 101 in response to the control signal of the first node N1.

[0052] The writing subcircuit 102 is connected to the first scanning signal line Pgate, the data signal line Data and the second node N2 respectively, and is configured to write the signal of the data signal line Data into the first pole (ie, the second node N2) of the driving subcircuit 101 in response to the control signal of the first scanning signal line Pgate.

[0053] The first reset subcircuit 103 is respectively connected to the second scan signal line Scan, the initial signal line INIT and the anode end (i.e., the fourth node N4) of the light emitting element EL, and is configured to reset the anode end (i.e., the fourth node N4) of the light emitting element EL in response to the control signal of the second scan signal line Scan.

[0054] In the low-frequency display mode, the frequency of the control signal of the first scan signal line Pgate is a first frequency, the frequency of the control signal of the second scan signal line Scan is a second frequency, and the second frequency is greater than the first frequency.

[0055] The pixel circuit of the disclosed embodiment includes a low-frequency display mode and a normal display mode. The low-frequency display mode includes multiple first display cycles. The first display cycle includes a refresh phase and a hold phase. In the low-frequency display mode, the control signal of the first scan signal line Pgate is input only in the refresh phase and not in the hold phase; the control signal of the second scan signal line Scan is periodically input throughout the first display cycle (refresh phase and hold phase).

[0056] The pixel circuit provided by the embodiment of the present disclosure connects the write subcircuit 102 to the first scan signal line Pgate, and connects the first reset subcircuit 103 to the second scan signal line Scan. In the low-frequency display mode, the frequency of the control signal of the first scan signal line Pgate is a first frequency, and the frequency of the control signal of the second scan signal line Scan is a second frequency, and the second frequency is greater than the first frequency, thereby eliminating the charge on the anode end surface of the light-emitting element EL, and making the time for the brightness of the light-emitting element EL to reach a stable state remain consistent in the low-frequency display mode, and the screen flicker is significantly improved. In addition, the write subcircuit 102 will not repeatedly write the data voltage and the voltage signal of the first power line, thereby ensuring the current stability.

[0057] In some exemplary embodiments, Figure 2 An equivalent circuit diagram of the driving sub-circuit 101, the writing sub-circuit 102 and the first resetting sub-circuit 103 provided in the embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the driving sub-circuit 101 includes a driving transistor Td, the writing sub-circuit 102 includes a first transistor T1, and the first reset sub-circuit 103 includes a second reset transistor Tr2;

[0058] The control electrode of the driving transistor Td is connected to the first node N1, the first electrode of the driving transistor Td is connected to the second node N2, and the second electrode of the driving transistor Td is connected to the third node N3;

[0059] The control electrode of the first transistor T1 is connected to the first scanning signal line Pgate, the first electrode of the first transistor T1 is connected to the data signal line Data, and the second electrode of the first transistor T1 is connected to the second node N2;

[0060] The control electrode of the second reset transistor Tr2 is connected to the second scan signal line Scan, the first electrode of the second reset transistor Tr2 is connected to the initial signal line INIT, and the second electrode of the second reset transistor Tr2 is connected to the anode terminal of the light emitting element EL (ie, the fourth node N4).

[0061] Figure 21 shows an exemplary structure of the driving subcircuit 101, the writing subcircuit 102 and the first resetting subcircuit 103. It is easy for those skilled in the art to understand that the implementation of the driving subcircuit 101, the writing subcircuit 102 and the first resetting subcircuit 103 is not limited thereto, as long as their respective functions can be achieved.

[0062] In some exemplary embodiments, Figure 1 As shown, the pixel circuit further includes a compensation sub-circuit 104 , a storage sub-circuit 105 , an anti-leakage electronic circuit 106 and a second reset sub-circuit 107 .

[0063] Among them, the compensation sub-circuit 104 is respectively connected to the first scan signal line Pgate, the third node N3 and the fifth node N5, and is configured to write the signal of the third node N3 into the fifth node N5 in response to the control signal of the first scan signal line Pgate, and is also configured to compensate the fifth node N5 in response to the control signal of the first scan signal line Pgate.

[0064] The leakage prevention circuit 106 is connected to the third scan signal line Ngate, the first node N1 and the fifth node N5 respectively, and is configured to write the signal of the fifth node N5 into the first node N1 in response to the control signal of the third scan signal line Ngate.

[0065] The storage sub-circuit 105 is respectively connected to the first power line VDD and the first node N1 , and is configured to store a signal of the first node N1 .

[0066] The second reset sub-circuit 107 is respectively connected to the initial signal line INIT and the fifth node N5, and is also connected to the second scan signal line Scan or the reset control signal line Reset, and is configured to write the reset voltage signal of the initial signal line INIT into the fifth node N5 in response to the control signal of the second scan signal line Scan or the reset control signal line Reset.

[0067] The pixel circuit of the embodiment of the present disclosure avoids the influence of the threshold voltage drift of the driving subcircuit 101 on the driving current of the light emitting element EL, thereby improving the uniformity of the displayed image and the display quality of the display panel. In addition, the pixel circuit of the embodiment of the present disclosure has fewer leakage channels, thereby improving the screen flickering problem under low frequency and low brightness.

[0068] In some exemplary embodiments, Figure 3 An equivalent circuit diagram of the compensation sub-circuit 104, the storage sub-circuit 105, the leakage prevention electronic circuit 106 and the second reset sub-circuit 107 provided in the embodiment of the present disclosure is shown in FIG. Figure 3As shown, the compensation sub-circuit 104 includes a second transistor T2, the storage sub-circuit 105 includes a first capacitor Cst, the anti-leakage electronic circuit 106 includes an anti-leakage transistor Tlp, and the second reset sub-circuit 107 includes a first reset transistor Tr1;

[0069] The control electrode of the second transistor T2 is connected to the first scanning signal line Pgate, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the fifth node N5;

[0070] One end of the first capacitor Cst is connected to the first power line VDD, and the other end of the first capacitor Cst is connected to the first node N1;

[0071] The control electrode of the anti-leakage transistor Tlp is connected to the third scanning signal line Ngate, the first electrode of the anti-leakage transistor Tlp is connected to the fifth node N5, and the second electrode of the anti-leakage transistor Tlp is connected to the first node N1;

[0072] A control electrode of the first reset transistor Tr1 is connected to the second scan signal line Scan or the reset control signal line Reset, a first electrode of the first reset transistor Tr1 is connected to the initial signal line INIT, and a second electrode of the first reset transistor Tr1 is connected to the fifth node N5.

[0073] Figure 3 FIG. 1 shows an exemplary structure of the compensation subcircuit 104, the storage subcircuit 105, the leakage prevention electronic circuit 106, and the second reset subcircuit 107. It is easy for those skilled in the art to understand that the implementation of the compensation subcircuit 104, the storage subcircuit 105, the leakage prevention electronic circuit 106, and the second reset subcircuit 107 is not limited thereto, as long as their respective functions can be achieved.

[0074] In some exemplary embodiments, Figure 1 As shown, the pixel circuit further includes a first light emitting control subcircuit 108 and a second light emitting control subcircuit 109 .

[0075] The first light emitting control sub-circuit 108 is respectively connected to the first power line VDD, the light emitting control signal line EM and the second node N2, and is configured to write the voltage signal of the first power line VDD into the second node N2 under the control of the signal of the light emitting control signal line EM;

[0076] The second light emitting control subcircuit 109 is connected to the light emitting control signal line EM, the third node N3 and the fourth node N4 respectively, and is configured to form a path between the third node N3 and the fourth node N4 under the control of the signal of the light emitting control signal line EM.

[0077] In some exemplary embodiments, Figure 1As shown, one end of the light emitting element is connected to the fourth node N4, and the other end is connected to the second power line VSS.

[0078] In some exemplary embodiments, Figure 4 An equivalent circuit diagram of the first light-emitting control subcircuit 108 and the second light-emitting control subcircuit 109 provided in the embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the first light emitting control subcircuit 108 includes a third transistor T3, and the second light emitting control subcircuit includes a fourth transistor T4;

[0079] The control electrode of the third transistor T3 is connected to the light emitting control signal line EM, the first electrode of the third transistor T3 is connected to the first power line VDD, and the second electrode of the third transistor T3 is connected to the second node N2;

[0080] A control electrode of the fourth transistor T4 is connected to the light emission control signal line EM, a first electrode of the fourth transistor T4 is connected to the third node N3, and a second electrode of the fourth transistor T4 is connected to the anode terminal of the light emitting element EL.

[0081] In some exemplary embodiments, Figure 5 The equivalent circuit diagram of the pixel circuit provided by the embodiment of the present disclosure is as follows: Figure 5 As shown, in the pixel circuit provided by the present disclosure, the driving subcircuit 101 includes a driving transistor Td, the writing subcircuit 102 includes a first transistor T1, the first reset subcircuit 103 includes a second reset transistor Tr2, the compensation subcircuit 104 includes a second transistor T2, the storage subcircuit 105 includes a first capacitor Cst, the anti-leakage electronic circuit 106 includes an anti-leakage transistor Tlp, the second reset subcircuit 107 includes a first reset transistor Tr1, the first light-emitting control subcircuit 108 includes a third transistor T3, and the second light-emitting control subcircuit 109 includes a fourth transistor T4;

[0082] The control electrode of the driving transistor Td is connected to the first node N1, the first electrode of the driving transistor Td is connected to the second node N2, and the second electrode of the driving transistor Td is connected to the third node N3;

[0083] The control electrode of the first transistor T1 is connected to the first scanning signal line Pgate, the first electrode of the first transistor T1 is connected to the data signal line Data, and the second electrode of the first transistor T1 is connected to the second node N2;

[0084] The control electrode of the second reset transistor Tr2 is connected to the second scan signal line Scan, the first electrode of the second reset transistor Tr2 is connected to the initial signal line INIT, and the second electrode of the second reset transistor Tr2 is connected to the anode terminal of the light emitting element EL;

[0085] The control electrode of the second transistor T2 is connected to the first scanning signal line Pgate, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the fifth node N5;

[0086] One end of the first capacitor Cst is connected to the first power line VDD, and the other end of the first capacitor Cst is connected to the first node N1;

[0087] The control electrode of the anti-leakage transistor Tlp is connected to the third scanning signal line Ngate, the first electrode of the anti-leakage transistor Tlp is connected to the fifth node N5, and the second electrode of the anti-leakage transistor Tlp is connected to the first node N1;

[0088] A control electrode of the first reset transistor Tr1 is connected to the second scan signal line Scan, a first electrode of the first reset transistor Tr1 is connected to the initial signal line INIT, and a second electrode of the first reset transistor Tr1 is connected to the fifth node N5;

[0089] The control electrode of the third transistor T3 is connected to the light emitting control signal line EM, the first electrode of the third transistor T3 is connected to the first power line VDD, and the second electrode of the third transistor T3 is connected to the second node N2;

[0090] A control electrode of the fourth transistor T4 is connected to the light emission control signal line EM, a first electrode of the fourth transistor T4 is connected to the third node N3, and a second electrode of the fourth transistor T4 is connected to the anode terminal of the light emitting element EL.

[0091] In some exemplary embodiments, the driving transistor Td, the first reset transistor Tr1, the second reset transistor Tr2, and the first to fourth transistors T1 to T4 may be low temperature polysilicon (LTPS) thin film transistors (TFT), and the leakage protection transistor Tlp may be an indium gallium zinc oxide (IGZO) thin film transistor.

[0092] In this embodiment, the indium gallium zinc oxide thin film transistor generates less leakage current than the low temperature polysilicon thin film transistor. Therefore, setting the anti-leakage transistor Tlp as an indium gallium zinc oxide thin film transistor can significantly reduce the generation of leakage current. In addition, the first reset transistor Tr1 and the second transistor T2 do not need to be set as an indium gallium zinc oxide thin film transistor. Since the size of the low temperature polysilicon thin film transistor is generally smaller than that of the indium gallium zinc oxide thin film transistor, the pixel circuit of the embodiment of the present disclosure will occupy a relatively small space, which is conducive to improving the resolution of the display panel.

[0093] The pixel circuit of the disclosed embodiment combines the good switching characteristics of LTPS-TFT and the low leakage characteristics of oxide-TFT, and can achieve low-frequency driving (1 Hz to 60 Hz), thereby significantly reducing the power consumption of the display screen.

[0094] In some exemplary embodiments, the second electrode of the light emitting element EL is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously provided high level signal. The first scanning signal line Pgate is a scanning signal line in the pixel circuit of the current display row, and the reset control signal line Reset is a scanning signal line in the pixel circuit of the previous display row, that is, for the nth display row, the first scanning signal line Pgate is PGate(n), and the reset control signal line Reset is PGate(n-1), and the reset control signal line Reset of the current display row and the first scanning signal line Pgate in the pixel circuit of the previous display row can be the same signal line, so as to reduce the signal lines of the display panel and realize the narrow frame of the display panel.

[0095] In some exemplary embodiments, the light emitting element EL may be an organic electroluminescent diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0096] In some exemplary embodiments, the first capacitor Cst may be a liquid crystal capacitor formed by a pixel electrode and a common electrode, or an equivalent capacitor formed by a liquid crystal capacitor formed by a pixel electrode and a common electrode and a storage capacitor, which is not limited in the present disclosure.

[0097] Figure 6 for Figure 5 The working timing diagram of the pixel circuit is shown below. Figure 6 The operation process of the pixel circuit of the example is described in detail with reference to the exemplary embodiment of the present disclosure. Figure 5 The pixel circuit includes 8 transistors (Tr1, Tr2, Td, T1-T4, Tlp), 1 storage capacitor Cst and 9 signal lines (data signal line Data, first scan signal line Pgate, reset control signal line Reset, third scan signal line Ngate, second scan signal line Scan, initial signal line INIT, first power line VDD, second power line VSS and light-emitting control signal line EM), the driving transistor Td, the first reset transistor Tr1, the second reset transistor Tr2, the first transistor T1 to the fourth transistor T4 are P-type transistors, and the anti-leakage transistor Tlp is an N-type transistor.

[0098] In an exemplary embodiment, the operation process of the pixel circuit may include:

[0099] The first stage t1 is called the reset stage. The signals of the first scanning signal line Pgate, the second scanning signal line Scan, the third scanning signal line Ngate and the light-emitting control signal line EM are all high-level signals, and the signal of the reset control signal line Reset is a low-level signal. The high-level signal of the light-emitting control signal line EM turns off the third transistor T3 and the fourth transistor T4, the high-level signal of the third scanning signal line Ngate turns on the anti-leakage transistor Tlp, and the low-level signal of the reset control signal line Reset turns on the first reset transistor Tr1. Therefore, the voltage of the first node N1 is reset to the initial voltage Vinit provided by the initial signal line INIT, and then the voltage of the reset control signal line Reset is high, and the first reset transistor Tr1 is turned off. Since the third transistor T3 and the fourth transistor T4 are turned off, the light-emitting element EL does not emit light in this stage.

[0100] The second stage t2 is called the data writing stage. The signals of the first scanning signal line Pgate and the second scanning signal line Scan are low-level signals. The first transistor T1, the second transistor T2 and the second reset transistor Tr2 are turned on. The data signal line Data outputs the data voltage. The voltage of the fourth node N4 is reset to the initial voltage Vinit provided by the initial voltage line INIT, and the initialization is completed. In this stage, since the first node N1 is at a low level, the driving transistor Td is turned on. The first transistor T1 and the second transistor T2 are turned on so that the data voltage output by the data signal line Data passes through the turned-on first transistor T1, the second node N2, the turned-on driving transistor Td, the third node N3, the turned-on second transistor T2 and the anti-leakage transistor Tlp to provide to the first node N1, and the sum of the data voltage output by the data signal line Data and the threshold voltage of the driving transistor Td is charged into the storage capacitor C1. The voltage of the second end (first node N1) of the storage capacitor C1 is Vdata+Vth, Vdata is the data voltage output by the data signal line Data, and Vth is the threshold voltage of the driving transistor Td. The signal of the light emitting control signal line EM is a high level signal, and the third transistor T3 and the fourth transistor T4 are turned off to ensure that the light emitting element EL does not emit light.

[0101] The third stage t3 is called the light-emitting stage, the signals of the first scanning signal line Pgate and the second scanning signal line Scan are high-level signals, and the signals of the light-emitting control signal line EM and the third scanning signal line Ngate are low-level signals. The high-level signal of the second scanning signal line Scan turns off the second reset transistor Tr2, and the low-level signal of the light-emitting control signal line EM turns on the third transistor T3 and the fourth transistor T4. The power supply voltage output by the first power supply terminal VDD provides a driving voltage to the first electrode (i.e., the fourth node N4) of the light-emitting element EL through the turned-on third transistor T3, the driving transistor Td, and the fourth transistor T4, driving the light-emitting element EL to emit light.

[0102] During the pixel circuit driving process, the driving current flowing through the driving transistor Td (ie, the driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata+Vth, the driving current of the driving transistor Td is:

[0103] I=K*(Vgs-Vth) 2 =K*[(Vdata+Vth-Vdd)-Vth] 2 =K*[(Vdata-Vdd)] 2

[0104] Among them, I is the driving current flowing through the driving transistor Td, that is, the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the driving transistor Td, Vth is the threshold voltage of the driving transistor Td, Vdata is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply terminal VDD.

[0105] It can be seen from the above formula that the current I flowing through the light emitting element EL has nothing to do with the threshold voltage Vth of the driving transistor Td, thereby eliminating the influence of the threshold voltage Vth of the driving transistor Td on the current I and ensuring the uniformity of brightness.

[0106] Based on the above working timing, the pixel circuit eliminates the residual positive charge of the light-emitting element EL after the last light emission, realizes compensation for the gate voltage of the driving transistor, avoids the influence of the threshold voltage drift of the driving transistor on the driving current of the light-emitting element EL, and improves the uniformity of the displayed image and the display quality of the display panel.

[0107] In some exemplary embodiments, Figure 7 As shown, the pixel circuit of the embodiment of the present disclosure is Figure 5On the basis of the pixel circuit shown, the signals of the second scanning signal line Scan and the reset control signal line Reset are merged, that is, the gate of the driving transistor Td (DTFT) and the anode reset of the light-emitting element EL share the second scanning signal line Scan control output, which can save a horizontal signal line on the layout and improve space utilization.

[0108] Figure 8 for Figure 7 The working timing diagram of the pixel circuit in normal mode is shown below. Figure 8 The operation process of the pixel circuit of the example is described in detail with reference to the exemplary embodiment of the present disclosure. Figure 7 The pixel circuit includes 8 transistors (Tr1, Tr2, Td, T1-T4, Tlp), 1 storage capacitor Cst and 8 signal lines (data signal line Data, first scan signal line Pgate, third scan signal line Ngate, second scan signal line Scan, initial signal line INIT, first power line VDD, second power line VSS and light-emitting control signal line EM), the driving transistor Td, the first reset transistor Tr1, the second reset transistor Tr2, the first transistor T1 to the fourth transistor T4 are P-type transistors, and the anti-leakage transistor Tlp is an N-type transistor.

[0109] In an exemplary embodiment, if Figure 8 As shown, the working process of the pixel circuit may include:

[0110] The first stage A1 is called the reset stage. The signals of the first scanning signal line Pgate, the third scanning signal line Ngate and the light-emitting control signal line EM are all high-level signals, and the signal of the second scanning signal line Scan is a low-level signal. The high-level signal of the light-emitting control signal line EM turns off the third transistor T3 and the fourth transistor T4, the high-level signal of the third scanning signal line Ngate turns on the anti-leakage transistor Tlp, and the low-level signal of the second scanning signal line Scan turns on the first reset transistor Tr1 and the second reset transistor Tr2. Therefore, the voltage of the first node N1 and the fourth node N4 is reset to the initial voltage Vinit provided by the initial signal line INIT, and the initialization is completed. Then the voltage of the second scanning signal line Scan is high, and the first reset transistor Tr1 and the second reset transistor Tr2 are turned off. Since the third transistor T3 and the fourth transistor T4 are turned off, the light-emitting element EL does not emit light in this stage.

[0111] The second stage A2 is called the data writing stage. The signal of the first scanning signal line Pgate is a low level signal. The signals of the third scanning signal line Ngate, the second scanning signal line Scan and the light emitting control signal line EM are all high level signals. The high level signal of the second scanning signal line Scan turns off the second reset transistor Tr2. The low level signal of the first scanning signal line Pgate turns on the first transistor T1 and the second transistor T2. The data signal line Data outputs the data voltage. In this stage, since the first node N1 is at a low level, the driving transistor Td is turned on. The first transistor T1 and the second transistor T2 are turned on so that the data voltage output by the data signal line Data is provided to the first node N1 through the turned-on first transistor T1, the second node N2, the turned-on driving transistor Td, the third node N3, the turned-on second transistor T2 and the anti-leakage transistor Tlp, and the sum of the data voltage output by the data signal line Data and the threshold voltage of the driving transistor Td is charged into the storage capacitor C1, and the voltage of the second end (first node N1) of the storage capacitor C1 is Vdata+Vth, Vdata is the data voltage output by the data signal line Data, and Vth is the threshold voltage of the driving transistor Td. The signal of the light-emitting control signal line EM is a high-level signal, and the third transistor T3 and the fourth transistor T4 are turned off to ensure that the light-emitting element EL does not emit light.

[0112] The third stage A3 is called the light-emitting stage, the signals of the first scanning signal line Pgate and the second scanning signal line Scan are high-level signals, and the signals of the light-emitting control signal line EM and the third scanning signal line Ngate are low-level signals. The low-level signal of the light-emitting control signal line EM turns on the third transistor T3 and the fourth transistor T4, and the power supply voltage output by the first power supply terminal VDD provides a driving voltage to the first electrode (i.e., the fourth node N4) of the light-emitting element EL through the turned-on third transistor T3, the driving transistor Td, and the fourth transistor T4, driving the light-emitting element EL to emit light.

[0113] The pixel circuit of the disclosed embodiment can save one horizontal signal line on the layout by merging the signal of the second scanning signal line Scan with the signal of the reset control signal line Reset, that is, the gate of the driving transistor Td (DTFT) and the anode reset of the light-emitting element EL share the output of the second scanning signal line Scan, thereby improving space utilization.

[0114] Fig. 9 for Figure 7 The control signal diagram of each control signal line of the pixel circuit shown in FIG. Fig. 9As shown, exemplarily, assuming that the display frequency is 60Hz, taking the data refresh frequency of 1Hz in the low-frequency mode as an example, in the low-frequency mode, a display cycle is 1s, wherein the refresh phase is 1 / 60s, that is, 1 / 60s can be used to update the data (the timing of this phase includes the aforementioned reset phase, data writing phase and light-emitting phase), and the holding phase is 59 / 60s, that is, the remaining 59 / 60s data is held (the timing includes the light-emitting phase and the extinguishing phase that are repeated in sequence). In the holding phase, the first scanning signal line Pgate and the third scanning signal line Ngate do not input control signals, and the second scanning signal line Scan and the light-emitting control signal line EM periodically input control signals. By using this method, the picture is updated once every 1 second, the low-frequency component in the brightness waveform is eliminated, and the flicker is significantly improved. In addition, by separating the gate signal of the transistor that resets the anode of the light-emitting element EL from the control signal of the first scanning signal Pgate, the source stability of the driving transistor Td in the low-frequency mode is maintained, and the anode of the light-emitting element EL can be reset at high frequency.

[0115] In some exemplary embodiments, Figure 5 and Figure 6 As shown, the first reset sub-circuit 103 and the second reset sub-circuit 107 are both connected to the initial signal line INIT, and the initial signal line INIT provides a reset voltage to the anode terminal of the light emitting element EL and the fifth node N5 respectively.

[0116] In other exemplary embodiments, Fig.10 As shown, the initial signal line INIT includes a first initial signal line INIT1 and a second initial signal line INIT2, wherein the first reset sub-circuit 103 is connected to the first initial signal line INIT1, the second reset sub-circuit 107 is connected to the second initial signal line INIT2, the first initial signal line INIT1 provides a first reset voltage to the anode end of the light emitting element EL, and the second initial signal line INIT2 provides a second reset voltage to the fifth node N5.

[0117] The pixel circuit of the embodiment of the present disclosure can adjust the reset voltage of the light-emitting element EL and the reset voltage of the first node N1 respectively by initializing the fifth node N5 to the signal of the first initial signal line INIT1 and by initializing the fourth node N4 to the signal of the second initial signal line INIT2, thereby achieving a better display effect and improving problems such as low-frequency flicker.

[0118] The following is an exemplary description of the preparation process of the pixel circuit. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating, and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made of a certain material on a substrate by deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. "The orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0119] In an exemplary embodiment, the preparation process of the pixel circuit may include the following operations:

[0120] (11) Forming a light shielding layer pattern. In an exemplary embodiment, forming the light shielding layer pattern may include: depositing a light shielding film on a substrate (BS); coating a layer of photoresist on the light shielding film, exposing and developing the photoresist using a single-tone mask, forming an unexposed area at the light shielding layer pattern position, retaining the photoresist, forming a fully exposed area at other positions, without the photoresist, exposing the light shielding film; etching the light shielding film in the fully exposed area and stripping off the remaining photoresist, forming a light shielding layer pattern on the substrate, such as Fig. 11B The light shielding film may be made of one of the metals such as silver Ag, molybdenum Mo, aluminum Al, copper Cu, etc., or a composite layer structure of multiple metals, such as Mo / Cu / Mo.

[0121] In an exemplary embodiment, if Fig. 11B As shown, the light shielding layer of each sub-pixel may include a first light shielding layer LS01 and a second light shielding layer LS02. The first light shielding layer LS01 extends in a first direction X; the second light shielding layer LS02 extends along a second direction Y. The first direction X and the second direction Y intersect.

[0122] In an exemplary embodiment, the first light shielding layer LS01 and the second light shielding layer LS02 may be an integral structure connected to each other.

[0123] (12) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: depositing a first insulating film and a first active layer film in sequence on a substrate on which the aforementioned pattern is formed; coating a layer of photoresist on the first active layer film, exposing and developing the photoresist using a single-tone mask, forming an unexposed area at the position of the first active layer pattern, retaining the photoresist, and forming a fully exposed area without photoresist at other positions; etching the first active layer film in the fully exposed area and stripping off the remaining photoresist to form a first insulating layer and a first semiconductor layer pattern. The first insulating layer is used to block the influence of ions in the substrate on the thin film transistor, and may be a composite film of silicon nitride SiNx, silicon oxide SiOx, or SiNx / SiOx. The first active layer film may be made of silicon material, and the silicon material includes amorphous silicon and polycrystalline silicon. The first active layer film may also be made of amorphous silicon a-Si, and may be formed into polycrystalline silicon through crystallization or laser annealing, such as Fig. 11C shown.

[0124] like Fig. 11C As shown, the first semiconductor layer of each sub-pixel may include a first active layer ACT1 of a first transistor T1, a second active layer ACT2 of a second transistor T2, a third active layer ACT3 of a third transistor T3, a fourth active layer ACT4 of a fourth transistor T4, a driving active layer ACTd of a driving transistor Td, a first reset active layer ACTr1 of a first reset transistor Tr1, and a second reset active layer ACTr2 of a second reset transistor Tr2, and the first active layer ACT1, the second active layer ACT2, the third active layer ACT3, the fourth active layer ACT4, the driving active layer ACTd, the first reset active layer ACTr1, and the second reset active layer ACTr2 are an interconnected integrated structure.

[0125] In an exemplary embodiment, the driving active layer ACTd may be shaped like a "J", the first active layer ACT1 and the second active layer ACT2 may be shaped like a "1", and the third active layer ACT3, the fourth active layer ACT4, the first reset active layer ACTr1 and the second reset active layer ACTr2 may be shaped like an "L".

[0126] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the second region Dr1 of the first reset active layer ACTr1 also serves as the first region S2 of the second active layer ACT2, that is, the second region Dr1 of the first reset active layer ACTr1 and the first region S2 of the second active layer ACT2 are connected to each other. The first region Sd of the driving active layer ACTd also serves as the second region D1 of the first active layer ACT1 and the second region D3 of the third active layer ACT3, that is, the first region Sd of the driving active layer ACTd, the second region D1 of the first active layer ACT1, and the second region D3 of the third active layer ACT3 are connected to each other. The second region Dd of the driving active layer ACTd also serves as the first region S4 of the fourth active layer ACT4 and the second region D2 of the second active layer ACT2, that is, the second region Dd of the driving active layer ACTd, the first region S4 of the fourth active layer ACT4, and the second region D2 of the second active layer ACT2 are connected to each other. The second region D4 of the fourth active layer ACT4 also serves as the second region Dr2 of the second reset active layer ACTr2, that is, the second region D4 of the fourth active layer ACT4 and the second region Dr2 of the second reset active layer ACTr2 are connected to each other. The first region Sr1 of the first reset active layer ACTr1, the first region S1 of the first active layer ACT1, the first region S3 of the third active layer ACT3, and the first region Sr2 of the second reset active layer ACTr2 are separately provided.

[0127] Combination Fig.11A and Fig. 11C In an exemplary embodiment, the first light shielding layer LS01 is provided with a first light shielding protrusion protruding in a direction perpendicular to the extension direction of the first light shielding layer LS01, and the orthographic projection of the first light shielding protrusion on the substrate covers the orthographic projection of the driving active layer ACTd on the substrate. The second light shielding layer LS02 is provided with a second light shielding protrusion protruding in a direction perpendicular to the extension direction of the second light shielding layer LS02, and the orthographic projection of the second light shielding protrusion on the substrate covers the orthographic projection of the first area S2 of the second active layer ACT2 on the substrate.

[0128] In an exemplary embodiment, the first semiconductor layer may be made of polysilicon (p-Si), that is, the first reset transistor, the second transistor, the driving transistor, the first transistor, the third transistor, the fourth transistor and the second reset transistor are LTPS thin film transistors.

[0129] After this process, the display substrate includes a first insulating layer disposed on the base and a first semiconductor layer disposed on the first insulating layer, and the first semiconductor layer may include an active layer of a plurality of transistors.

[0130] (13) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first metal film in sequence on a substrate having the aforementioned pattern, patterning the first metal film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, wherein the first conductive layer pattern at least includes: a first scanning signal line Pgate, a second scanning signal line Scan, a light emitting control signal line EM, and a first electrode Ce1 of a first capacitor, such as Fig.11D In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE 1) layer.

[0131] In an exemplary embodiment, the first scan signal line Pgate, the second scan signal line Scan, and the light emitting control signal line EM extend along the first direction X. The second scan signal line Scan is located at a side of the first scan signal line Pgate away from the light emitting control signal line EM, and the first electrode Ce1 of the storage capacitor is disposed between the first scan signal line Pgate and the light emitting control signal line EM.

[0132] In an exemplary embodiment, the first electrode plate Ce1 may be rectangular, and the corners of the rectangle may be chamfered, and the orthographic projection of the first electrode plate Ce1 on the substrate overlaps with the orthographic projection of the driving active layer of the driving transistor Td on the substrate. In an exemplary embodiment, the first electrode plate Ce1 also serves as the gate electrode of the driving transistor Td, and the area where the driving active layer of the driving transistor Td overlaps with the first electrode plate Ce1 serves as the channel region of the driving transistor Td, and one end of the channel region is connected to the first area of ​​the driving active layer, and the other end is connected to the second area of ​​the driving active layer. The second scanning signal line Scan is provided with a gate block protruding toward one side of the first scanning signal line Pgate, and the orthographic projection of the gate block on the substrate overlaps with the orthographic projection of the first reset active layer of the first reset transistor Tr1 on the substrate, and the area where the gate block overlaps with the first active layer of the first reset transistor Tr1 serves as the gate electrode of the first reset transistor Tr1. The area where the first scan signal line Pgate overlaps with the second active layer of the second transistor T2 serves as the gate electrode of the second transistor T2, the area where the first scan signal line Pgate overlaps with the first active layer of the first transistor T1 serves as the gate electrode of the first transistor T1, the area where the first electrode plate Ce1 overlaps with the driving active layer of the driving transistor Td serves as the gate electrode of the driving transistor Td, the area where the light emitting control signal line EM overlaps with the third active layer of the third transistor T3 serves as the gate electrode of the third transistor T3, the area where the light emitting control signal line EM overlaps with the fourth active layer of the fourth transistor T4 serves as the gate electrode of the fourth transistor T4, and the area where the second scan signal line Scan overlaps with the second reset active layer of the second reset transistor Tr2 serves as the gate electrode of the second reset transistor Tr2.

[0133] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of each transistor, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​each active layer are both conductorized.

[0134] In an exemplary embodiment, in combination with Fig.11A and Fig.11D , the orthographic projection of the first light-shielding protrusion on the substrate covers the orthographic projection of the first electrode plate Ce1 on the substrate.

[0135] After this process, the display substrate includes a light-shielding layer arranged on the base, a first insulating layer arranged on the light-shielding layer, a first semiconductor layer arranged on the first insulating layer, a second insulating layer covering the first semiconductor layer and a first conductive layer arranged on the second insulating layer, and the first conductive layer may include a first scanning signal line Pgate, a second scanning signal line Scan, a light-emitting control signal line EM and a first electrode Ce1 of the storage capacitor.

[0136] (14) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a third insulating film and a second metal film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second metal film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, wherein the second conductive layer pattern at least includes: a first connecting electrode ace, a second electrode plate Ce2 of the storage capacitor, and a first branch Ngate_B1 of the third scanning signal line Ngate, such as Fig.11E In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE 2) layer.

[0137] Combination Fig.11A and 11E As shown, in an exemplary embodiment, the orthographic projection of the first connection electrode ace on the substrate and the orthographic projection of the first scanning signal line Pgate on the substrate include an overlapping area. The first connection electrode ace is configured to be connected to the fourth connection electrode Cln formed subsequently through a fifth via hole V5 formed subsequently, and the fourth connection electrode Cln is connected to the first electrode plate Ce1 through a fourth via hole V4 formed subsequently, and the first electrode plate Ce1 also serves as the gate electrode of the driving transistor Td, so that the gate electrode of the driving transistor and the first scanning signal line Pgate form an adjustment capacitor, and the data voltage can be adjusted later through the adjustment capacitor.

[0138] In an exemplary embodiment, the first branch Ngate_B1 extends along the first direction X. The second plate Ce2 of the storage capacitor is located between the first branch Ngate_B1 and the light emitting control signal line EM.

[0139] In an exemplary embodiment, the contour of the second electrode plate Ce2 may be rectangular, and the corners of the rectangle may be chamfered, and there is an overlapping area between the orthographic projection of the second electrode plate Ce2 on the substrate and the orthographic projection of the first electrode plate Ce1 on the substrate. An opening H is provided on the second electrode plate Ce2, and the opening H may be located in the middle of the second electrode plate Ce2. The opening H may be a regular hexagon, so that the second electrode plate Ce2 forms a ring structure. The opening H exposes the third insulating layer covering the first electrode plate Ce1, and the orthographic projection of the first electrode plate Ce1 on the substrate includes the orthographic projection of the opening H on the substrate. In an exemplary embodiment, the opening H is configured to accommodate a first via hole formed subsequently, and the first via hole is located in the opening H and exposes the first electrode plate Ce1, so that the second pole of the leakage-proof transistor Tlp formed subsequently is connected to the first electrode plate Ce1.

[0140] After this process, the display substrate includes a light-shielding layer arranged on the base, a first insulating layer arranged on the light-shielding layer, a first semiconductor layer arranged on the first insulating layer, a second insulating layer covering the first semiconductor layer, a first conductive layer arranged on the second insulating layer, a third insulating layer covering the first conductive layer and a second conductive layer arranged on the third insulating layer, the second conductive layer at least includes a second electrode Ce2 of the storage capacitor and a first branch Ngate_B1 of the third scanning signal line Ngate.

[0141] (15) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: depositing a fourth insulating film and a second semiconductor film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second semiconductor film through a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer disposed on the fourth insulating layer, such as Fig.11F shown.

[0142] like Fig.11F As shown, the second semiconductor layer of each sub-pixel may include an anti-leakage active layer ACTlp of the anti-leakage transistor Tlp. In an exemplary embodiment, the anti-leakage active layer ACTlp extends along the second direction Y, and the shape of the anti-leakage active layer ACTlp may be a dumbbell shape.

[0143] In an exemplary embodiment, the second region Dlp of the leakage prevention active layer ACTlp is adjacent to the first reset active layer of the first reset transistor Tr1, and the first region Slp of the leakage prevention active layer ACTlp is adjacent to the first capacitor Cst.

[0144] In an exemplary embodiment, the second semiconductor layer may be made of oxide, that is, the leakage protection transistor is an oxide thin film transistor.

[0145] After this process, the display substrate includes a light-shielding layer arranged on the base, a first insulating layer arranged on the light-shielding layer, a first semiconductor layer arranged on the first insulating layer, a second insulating layer covering the first semiconductor layer, a first conductive layer arranged on the second insulating layer, a third insulating layer covering the first conductive layer, a second conductive layer arranged on the third insulating layer, a fourth insulating layer covering the second conductive layer, and a second semiconductor layer arranged on the fourth insulating layer, and the second semiconductor layer includes at least an anti-leakage active layer ACTlp.

[0146] (16) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a fifth insulating film and a third metal film in sequence on the substrate on which the aforementioned pattern is formed, patterning the fifth insulating film and the third metal film using a patterning process to form a fifth insulating layer disposed on the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, wherein the third conductive layer pattern at least includes: a second branch Ngate_B2 of the third scanning signal line Ngate and a first initial signal line INIT1, such as Fig.11G In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0147] like Fig.11G As shown, in an exemplary embodiment, the second branch Ngate_B2 and the first initial signal line INIT1 extend along the first direction X, the second branch Ngate_B2 is close to the first scan signal line Pgate, and the first initial signal line INIT1 is close to the second scan signal line Scan. In an exemplary embodiment, the area where the second branch Ngate_B2 overlaps with the anti-leakage active layer serves as the gate electrode of the anti-leakage transistor.

[0148] After this process, the display substrate includes a light-shielding layer arranged on the base, a first insulating layer arranged on the light-shielding layer, a first semiconductor layer arranged on the first insulating layer, a second insulating layer covering the first semiconductor layer, a first conductive layer arranged on the second insulating layer, a third insulating layer covering the first conductive layer, a second conductive layer arranged on the third insulating layer, a fourth insulating layer covering the second conductive layer and a second semiconductor layer arranged on the fourth insulating layer, a fifth insulating layer covering the second semiconductor layer and a third conductive layer arranged on the fifth insulating layer, and the third conductive layer includes at least a second branch Ngate_B2 of the third scan signal line Ngate and the first initial signal line INIT1.

[0149] (17) Forming a polysilicon via pattern. In an exemplary embodiment, forming the polysilicon via pattern may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed, patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein the sixth insulating layer is provided with a plurality of vias, and the plurality of vias at least include: a second via V2, a fourth via V4, a fifth via V5, a seventh via V7, an eighth via V8, a ninth via V9, an eleventh via V11, and a thirteenth via V13, such as Fig.11H shown.

[0150] Combination Fig.11H and Fig. 12AAs shown, in an exemplary embodiment, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the first region of the second active layer (also the second region of the first reset active layer). The second via hole V2 is configured to connect the first electrode of the second transistor T2 formed subsequently to the second active layer through the via hole, and to connect the second electrode of the first reset transistor Tr1 formed subsequently to the first reset active layer through the via hole.

[0151] Combination Fig.11H and Fig. 12A As shown, in an exemplary embodiment, the fourth via hole V4 is located in the opening H of the second electrode plate Ce2, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the opening H on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the fourth via hole V4 are etched away to expose the surface of the first electrode plate Ce1. The fourth via hole V4 is configured to connect the subsequently formed connection electrode Cln to the first electrode plate Ce1 through the via hole.

[0152] Combination Fig.11H and Fig. 12A As shown, in an exemplary embodiment, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the fifth via hole V5 are etched away to expose the surface of the first connection electrode ace.

[0153] Combination Fig.11H and Fig. 12C As shown, in an exemplary embodiment, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the first region of the first reset active layer. The seventh via hole V7 is configured to connect the first electrode of the first reset transistor Tr1 formed subsequently to the first reset active layer through the via hole.

[0154] Combination Fig.11H , Fig.11A and Fig.12E As shown, in an exemplary embodiment, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighth via hole V8 are etched away to expose the surface of the first region of the second reset active layer. The eighth via hole V8 is configured to connect the subsequently formed second initial signal line to the second reset active layer through the via hole.

[0155] Combination Fig.11H and Fig.12DAs shown, in an exemplary embodiment, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via hole V9 are etched away to expose the surface of the second region of the fourth active layer (also the second region of the second reset active layer). The ninth via hole V9 is configured to connect the second electrode of the subsequently formed fourth transistor T4 to the fourth active layer through the via hole, and to connect the second electrode of the subsequently formed second reset transistor Tr2 to the second reset active layer through the via hole.

[0156] Combination Fig.11H and Fig. 12B As shown, in an exemplary embodiment, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first region of the third active layer. The eleventh via hole V11 is configured to connect the subsequently formed connection electrode VCP to the third active layer through the via hole.

[0157] Combination Fig.11H and Fig. 12B As shown, in an exemplary embodiment, the thirteenth via hole V13 is located in the area where the second electrode plate Ce2 is located, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the second electrode plate Ce2 on the substrate, and the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the second electrode plate Ce2. The thirteenth via hole V13 is configured to connect the subsequently formed connection electrode VCP to the second electrode plate Ce2 through the via hole.

[0158] Combination Fig.11H and Fig.11A As shown, in an exemplary embodiment, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourteenth via hole V14 are etched away to expose the surface of the first region of the first active layer. The fourteenth via hole V14 is configured to connect the subsequently formed data connection electrode to the first active layer through the via hole.

[0159] (18) Forming an oxide via pattern. In an exemplary embodiment, forming the oxide via pattern may include: on the substrate having the aforementioned pattern formed, forming a plurality of vias using a patterning process, the plurality of vias including at least: a first via V1, a third via V3, and a sixth via V6, such as Fig.11I shown.

[0160] Combination Fig.11H , Fig. 12A and Fig. 12CAs shown, in an exemplary embodiment, the sixth insulating layer and the fifth insulating layer in the first via hole V1 are etched away to expose the surface of the second region of the anti-leakage active layer. The sixth insulating layer and the fifth insulating layer in the third via hole V3 are etched away to expose the surface of the first region of the anti-leakage active layer. The sixth insulating layer in the sixth via hole V6 is etched away to expose the surface of the first initial signal line INIT1.

[0161] (19) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth metal film on the substrate on which the aforementioned pattern is formed, patterning the fourth metal film using a patterning process, and forming a fourth conductive layer disposed on the sixth insulating layer, wherein the fourth conductive layer at least includes: a second initial signal line INIT2, a second connection electrode cp1, a third connection electrode cp2, a fourth connection electrode Cln, a fifth connection electrode VCP, a sixth connection electrode RE, and a seventh connection electrode cd, such as Fig.11J In an exemplary embodiment, the fourth conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0162] In an exemplary embodiment, the second initial signal line INIT2 extends along the first direction X and is connected to the first region of the second reset active layer through the eighth via hole V8 so that the first electrode of the second reset transistor Tr2 has the same potential as the second initial signal line INIT2.

[0163] In an exemplary embodiment, the second connection electrode cp1 may be in the shape of a letter "1", one end of which is connected to the second region of the anti-leakage active layer through the first via hole V1, and the other end of which is connected to the first region of the second active layer (or the second region of the first reset active layer) through the second via hole V2. In an exemplary embodiment, the second connection electrode cp1 may serve as the second electrode of the anti-leakage transistor Tlp, the first electrode of the second transistor, and the second electrode of the first reset transistor.

[0164] In an exemplary embodiment, the third connection electrode cp2 may be rectangular, and the third connection electrode cp2 is connected to the first initial signal line INIT1 through the sixth via hole V6 on the one hand, and is connected to the first region of the first reset active layer through the seventh via hole V7 on the other hand. In an exemplary embodiment, the third connection electrode cp2 may serve as the first electrode of the first reset transistor Tr1.

[0165] In an exemplary embodiment, the fourth connection electrode Cln is connected to the first region of the anti-leakage active layer through the third via hole V3, and is connected to the first electrode plate Ce1 through the fourth via hole V4, and is also connected to the first connection electrode ace through the fifth via hole V5. In an exemplary embodiment, the fourth connection electrode Cln can serve as the first electrode of the anti-leakage transistor Tlp.

[0166] In an exemplary embodiment, the zigzag-line shaped fifth connection electrode VCP (power connection electrode) is connected to the second electrode plate Ce2 through the thirteenth via hole V13 on the one hand, and is connected to the third active layer through the eleventh via hole V11 on the other hand. The fifth connection electrode VCP is configured to be connected to the first power line formed subsequently through the twelfth via hole formed subsequently.

[0167] In an exemplary embodiment, the sixth connection electrode RE may be in a folded shape, and the sixth connection electrode RE is connected to the second region of the fourth active layer (or the second region of the second reset active layer) through the ninth via hole V9 on the one hand, and is connected to the connection electrode ACP through the tenth via hole V10 formed subsequently on the other hand. In an exemplary embodiment, the sixth connection electrode RE may serve as the second electrode of the fourth transistor T4 and the second electrode of the second reset transistor Tr2.

[0168] In an exemplary embodiment, the seventh connection electrode cd (data connection electrode) may be rectangular, and the seventh connection electrode cd is connected to the first region of the first active layer through the fourteenth via hole V14 on the one hand, and is connected to the subsequently formed data signal line through the subsequently formed sixteenth via hole V16 on the other hand. In an exemplary embodiment, the seventh connection electrode cd may serve as the first electrode of the first transistor T1.

[0169] (20) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a first flat film and a fifth metal film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first flat film and the fifth metal film using a patterning process to form a first flat layer disposed on the fourth conductive layer, and a fifth conductive layer pattern disposed on the first flat layer, wherein the first flat layer at least includes: a tenth via hole V10, a twelfth via hole V12, and a sixteenth via hole V16, and the fifth conductive layer at least includes: a data signal line Data, a first power line VDD, and an eighth connection electrode ACP, such as Figure 11K and Fig.11L In an exemplary embodiment, the fifth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0170] In an exemplary embodiment, the data signal line Data extends along the second direction Y, and the data signal line Data is connected to the data connection electrode cd through the sixteenth via hole V16. Since the data connection electrode cd is connected to the first area of ​​the first active layer through the fourteenth via hole V14, the data signal line is connected to the first electrode of the first transistor, so that the data signal transmitted by the data signal line can be written into the first transistor.

[0171] In an exemplary embodiment, the first power line VDD is connected to the fifth connection electrode VCP through the twelfth via hole V12 .

[0172] In an exemplary embodiment, the eighth connection electrode ACP may be rectangular in shape, and the eighth connection electrode ACP (anode connection electrode) is connected to the sixth connection electrode RE through a tenth via hole V10.

[0173] (21) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate formed with the aforementioned pattern, patterning the second planar film using a patterning process to form a second planar layer covering the fifth conductive layer, wherein at least the seventeenth via hole V17 is disposed on the second planar layer, such as Fig.11M shown.

[0174] In an exemplary embodiment, the seventeenth via hole V17 is located in the area where the eighth connection electrode ACP is located, the second flat layer in the seventeenth via hole V17 is removed to expose the surface of the eighth connection electrode ACP, and the seventeenth via hole V17 is configured to connect the subsequently formed anode to the eighth connection electrode ACP through the via hole.

[0175] (25) Forming an anode pattern. In an exemplary embodiment, forming the anode pattern may include: depositing a transparent conductive film on the substrate on which the aforementioned pattern is formed, patterning the transparent conductive film using a patterning process, and forming an anode disposed on the second planar layer, such as Fig.11N shown.

[0176] In an exemplary embodiment, the anode is connected to the eighth connection electrode ACP through the seventeenth via hole V17. Since the eighth connection electrode ACP is connected to the sixth connection electrode RE through the tenth via hole V10, and the sixth connection electrode RE is connected to the second area of ​​the fourth active layer (or the second area of ​​the second reset active layer) through the ninth via hole V9, the pixel circuit can drive the light emitting element to emit light.

[0177] In an exemplary embodiment, the subsequent preparation process may include: coating a pixel definition film, patterning the pixel definition film through a patterning process to form a pixel definition layer (PDL), the pixel definition layer of each sub-pixel is provided with a sub-pixel aperture (SA), and the sub-pixel aperture exposes the anode, such as Fig.11O As shown. An organic light-emitting layer is formed by evaporation or inkjet printing process, and a cathode is formed on the organic light-emitting layer. An encapsulation layer is formed, and the encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.

[0178] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked, and the materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer may be amorphous silicon (a-si).

[0179] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer. The first insulating layer is called a buffer (BUF) layer, which is used to improve the water and oxygen resistance of the substrate, the second insulating layer is called a first gate insulating (GI1) layer, the third insulating layer is called a second gate insulating (GI2) layer, the fourth insulating layer is called a first interlayer insulating (ILD1) layer, the fifth insulating layer is called a second interlayer insulating (ILD2) layer, and the sixth insulating layer is called a passivation (PVX) layer. The first flat layer (PLN1) and the second flat layer (PLN2) can be made of organic materials, the transparent conductive film can be made of indium tin oxide ITO or indium zinc oxide IZO. The first semiconductor layer (SML1) can be made of polysilicon (p-Si), and the second semiconductor layer (SML2) can be made of oxide.

[0180] The display substrate of the disclosed embodiment connects the write subcircuit to the first scan signal line Pgate and the first reset subcircuit to the second scan signal line Scan. In the low-frequency display mode, the frequency of the control signal of the first scan signal line Pgate is a first frequency, and the frequency of the control signal of the second scan signal line Scan is a second frequency, and the second frequency is greater than the first frequency, thereby eliminating the charge on the surface of the anode end of the light-emitting element EL, and ensuring that in the low-frequency display mode, the time for the brightness of the light-emitting element EL to reach a stable state remains consistent, the screen flicker is significantly improved, and the write subcircuit will not repeatedly write the data voltage and the voltage signal of the first power line, thereby ensuring current stability.

[0181] The structure of the display substrate and its preparation process shown in the present disclosure are merely exemplary. In an exemplary embodiment, the corresponding structure can be changed and the composition process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0182] The exemplary embodiment of the present disclosure further provides a driving method of a pixel circuit, which is used to drive the pixel circuit as described above. In an exemplary embodiment, the driving method may include:

[0183] In the reset stage, the first reset subcircuit resets the anode terminal of the light emitting element in response to the control signal of the second scanning signal line;

[0184] In the data writing phase, the writing subcircuit writes a data voltage signal to the first electrode of the driving subcircuit in response to a control signal of the first scanning signal line;

[0185] In the light emitting stage, the driving sub-circuit provides a driving current between the first electrode and the second electrode of the driving sub-circuit in response to the control signal of the first node;

[0186] In the low-frequency display mode, the input frequency of the control signal of the first scan signal line is the same as the data refresh frequency, and the input frequency of the control signal of the second scan signal line is greater than the data refresh frequency.

[0187] The exemplary embodiment of the present disclosure also provides a display device, including a display area and a peripheral area around the display area, wherein the peripheral area includes a first frame area and a second frame area arranged opposite to each other on the left and right sides of the display area. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, an advertising panel, a watch phone, an e-book portable multimedia player, or a display screen of various Internet of Things products. In an exemplary embodiment, the display device can be a wearable display device that can be worn on a human body in some way, such as a smart watch, a smart bracelet, etc.

[0188] like Figures 13 to 17As shown, the display area includes the pixel circuit as described in any of the previous items, and the peripheral area includes a first scan signal line driving circuit, a second scan signal line driving circuit, a third scan signal line driving circuit and a light-emitting control signal line driving circuit, the first scan signal line driving circuit includes a plurality of cascaded first scan signal line shift registers; the second scan signal line driving circuit includes a plurality of cascaded second scan signal line shift registers; the third scan signal line driving circuit includes a plurality of cascaded third scan signal line shift registers; the light-emitting control signal line driving circuit includes a plurality of cascaded light-emitting control signal line shift registers.

[0189] like Figures 13 to 15 As shown, a plurality of first scan signal line shift registers PgateGOA are divided into two groups, one of which is distributed in the first frame area, and the other is distributed in the second frame area, and each first scan signal line shift register PgateGOA is connected to a pixel circuit in a row of sub-pixels;

[0190] A plurality of second scan signal line shift registers Scan GOA are divided into two groups, one of which is distributed in the first frame area, and the other is distributed in the second frame area, and each second scan signal line shift register Scan GOA is connected to a pixel circuit in one or two rows of sub-pixels;

[0191] A plurality of third scanning signal line shift registers Ngate GOA are divided into two groups, one of which is distributed in the first frame area, and the other is distributed in the second frame area, and each third scanning signal line shift register Ngate GOA is connected to a pixel circuit in one or two rows of sub-pixels;

[0192] Multiple light control signal line shift registers EM GOA are divided into two groups, one of which is distributed in the first frame area, and the other is distributed in the second frame area. Each light control signal line shift register EM GOA is connected to the pixel circuits in one or two rows of sub-pixels.

[0193] like Fig.13 As shown, the display device of the embodiment of the present disclosure adopts bilateral driving, and four groups of GOA of the first scanning signal line Pgate, the third scanning signal line Ngate, the second scanning signal line Scan and the light-emitting control signal line EM are arranged on both sides of the display area, and each group of GOA units drives a row of sub-pixels. The advantages are strong driving capability and small output signal delay (Tr / Tf), and the disadvantage is that the space is large, and it is mainly used in products with low requirements for the frame, such as laptops, tablets, etc.

[0194] like Figure 14 to Figure 15As shown, the display device of the embodiment of the present disclosure still adopts bilateral driving, and the first scan signal line shift register Pgate GOA still adopts one GOA unit to drive one row of sub-pixels. The third scan signal line shift register Ngate GOA, the light control signal line shift register EM GOA and the second scan signal line shift register Scan GOA are mainly changed to one GOA unit to drive two rows of sub-pixels, and the vertical space is exchanged for the horizontal space to reduce the size of the left and right borders. Since the first scan signal line Pgate outputs the shortest effective level time during the timing setting, the key to determining the pixel charging and Vth compensation time is the control signal of the first scan signal line Pgate, so the delay time (Tr / Tf) of the Ngate, EM, and Scan output signals is increased to a certain extent, which has almost no effect on the pixel operation and display effect. This solution is mainly used for products that have certain requirements for the border (about 1mm), such as mobile phones.

[0195] like Fig.16 As shown, a plurality of first scan signal line shift registers Pgate GOA are divided into two groups, one of which is distributed in the first frame area, and the other is distributed in the second frame area, and each first scan signal line shift register Pgate GOA is connected to a pixel circuit in a row of sub-pixels;

[0196] A plurality of second scan signal line shift registers Scan GOA are distributed in the first frame area or the second frame area, and each second scan signal line shift register Scan GOA is connected to a pixel circuit in one or two rows of sub-pixels;

[0197] A plurality of third scanning signal line shift registers Ngate GOA are distributed in the first frame area or the second frame area, and each third scanning signal line shift register Ngate GOA is connected to a pixel circuit in one or two rows of sub-pixels;

[0198] A plurality of light emitting control signal line shift registers EM GOA are distributed in the first frame area or the second frame area, and each light emitting control signal line shift register EM GOA is connected to pixel circuits in one or two rows of sub-pixels.

[0199] like Fig.16 As shown, in the display device of the embodiment of the present disclosure, the third scan signal line shift register Ngate GOA, the light emitting control signal line shift register EM GOA, and the second scan signal line shift register Scan GOA adopt a unilateral drive mode and are distributed on both sides of the display area to further reduce the left and right borders. This solution is mainly used for products with extremely narrow borders (<0.8mm).

[0200] like Fig.17As shown, a plurality of first scan signal line shift registers Pgate GOA are distributed in the first frame area or the second frame area, and each first scan signal line shift register Pgate GOA is connected to a pixel circuit in a row of sub-pixels;

[0201] A plurality of second scan signal line shift registers Scan GOA are distributed in the first frame area or the second frame area, and each second scan signal line shift register Scan GOA is connected to a pixel circuit in one or two rows of sub-pixels;

[0202] A plurality of third scanning signal line shift registers Ngate GOA are distributed in the first frame area or the second frame area, and each third scanning signal line shift register Ngate GOA is connected to a pixel circuit in one or two rows of sub-pixels;

[0203] A plurality of light emitting control signal line shift registers EM GOA are distributed in the first frame area or the second frame area, and each light emitting control signal line shift register EM GOA is connected to pixel circuits in one or two rows of sub-pixels.

[0204] like Fig.17 As shown, in the display device of the embodiment of the present disclosure, the first scan signal line shift register Pgate GOA also becomes a single-sided drive. This solution is mainly used in small-sized wearable products.

[0205] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments.

[0206] Those skilled in the art should understand that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure.

Claims

1. A pixel circuit, comprising a driving subcircuit, a writing subcircuit, a first resetting subcircuit and a light-emitting element, wherein: The driving subcircuit is configured to provide a driving current between a first pole and a second pole of the driving subcircuit in response to a control signal of a first node; The writing subcircuit is configured to write a data voltage signal to a first electrode of the driving subcircuit in response to a control signal of a first scanning signal line; The first reset subcircuit is configured to reset the anode terminal of the light emitting element in response to a control signal of the second scanning signal line; In the low-frequency display mode, the input frequency of the control signal of the first scanning signal line is the same as the data refresh frequency, and the input frequency of the control signal of the second scanning signal line is greater than the data refresh frequency; In a direction perpendicular to the display substrate, the pixel circuit includes a substrate and a driving circuit layer arranged on the substrate, the driving circuit layer includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer; the driving subcircuit includes a driving transistor; The first conductive layer includes a first scanning signal line and a first electrode plate of a storage capacitor, the first electrode plate of the storage capacitor also serves as a control electrode of the driving transistor, the second conductive layer includes a first connecting electrode and a second electrode plate of the storage capacitor, the third conductive layer includes an initial signal line, the fourth conductive layer includes a fourth connecting electrode, the fourth connecting electrode is respectively connected to the first electrode plate of the storage capacitor and the first connecting electrode through a via hole, and the orthographic projection of the first connecting electrode on the substrate and the orthographic projection of the first scanning signal line on the substrate include an overlapping area.

2. The pixel circuit according to claim 1, wherein: The driving subcircuit includes a driving transistor, the writing subcircuit includes a first transistor, and the first resetting subcircuit includes a second resetting transistor; The control electrode of the driving transistor is connected to the first node, the first electrode of the driving transistor is connected to the second node, and the second electrode of the driving transistor is connected to the third node; The control electrode of the first transistor is connected to the first scanning signal line, the first electrode of the first transistor is connected to the data signal line, and the second electrode of the first transistor is connected to the second node; The control electrode of the second reset transistor is connected to the second scanning signal line, the first electrode of the second reset transistor is connected to the initial signal line, and the second electrode of the second reset transistor is connected to the anode terminal of the light emitting element.

3. The pixel circuit according to claim 1, further comprising a compensation subcircuit, a storage subcircuit, an anti-leakage electronic circuit and a second reset subcircuit; The compensation sub-circuit is configured to compensate the fifth node in response to the control signal of the first scan signal line; The storage sub-circuit is respectively connected to the first power line and the first node; The leakage prevention electronic circuit is configured to write the signal of the fifth node into the first node in response to a control signal of a third scanning signal line; The second reset sub-circuit is configured to reset the fifth node in response to a control signal of the second scan signal line or a reset control signal line.

4. The pixel circuit according to claim 3, wherein: The compensation subcircuit includes a second transistor, the storage subcircuit includes a storage capacitor, the leakage prevention electronic circuit includes a leakage prevention transistor, and the second reset subcircuit includes a first reset transistor; The control electrode of the second transistor is connected to the first scanning signal line, the first electrode of the second transistor is connected to the third node, and the second electrode of the second transistor is connected to the fifth node; One end of the storage capacitor is connected to the first power line, and the other end of the storage capacitor is connected to the first node; The control electrode of the leakage prevention transistor is connected to the third scanning signal line, the first electrode of the leakage prevention transistor is connected to the fifth node, and the second electrode of the leakage prevention transistor is connected to the first node; A control electrode of the first reset transistor is connected to the second scanning signal line, a first electrode of the first reset transistor is connected to the initial signal line, and a second electrode of the first reset transistor is connected to the fifth node.

5. The pixel circuit according to claim 3, wherein: The first reset subcircuit is connected to a first initial signal line, the second reset subcircuit is connected to a second initial signal line, the first initial signal line provides a first reset voltage to the anode end of the light emitting element, and the second initial signal line provides a second reset voltage to the fifth node; or, The first reset subcircuit and the second reset subcircuit are both connected to an initial signal line, and the initial signal line provides a reset voltage to the anode terminal of the light emitting element and the fifth node respectively.

6. The pixel circuit according to claim 3, further comprising a first light emission control subcircuit and a second light emission control subcircuit; The first light-emitting control subcircuit is configured to write the voltage signal of the first power line into the first electrode of the driving subcircuit in response to the control signal of the light-emitting control signal line; The second light emission control sub-circuit is configured to form a path between the second electrode of the driving sub-circuit and the anode terminal of the light emitting element in response to a control signal of the light emission control signal line.

7. The pixel circuit according to claim 6, wherein: The first light emission control subcircuit includes a third transistor, and the second light emission control subcircuit includes a fourth transistor; The control electrode of the third transistor is connected to the light emitting control signal line, the first electrode of the third transistor is connected to the first power line, and the second electrode of the third transistor is connected to the second node; The control electrode of the fourth transistor is connected to the light emission control signal line, the first electrode of the fourth transistor is connected to the third node, and the second electrode of the fourth transistor is connected to the anode terminal of the light emitting element.

8. The pixel circuit according to claim 6, wherein: The driving subcircuit includes a driving transistor, the writing subcircuit includes a first transistor, the first resetting subcircuit includes a second resetting transistor, the compensating subcircuit includes a second transistor, the storage subcircuit includes a storage capacitor, the anti-leakage electronic circuit includes an anti-leakage transistor, the second resetting subcircuit includes a first resetting transistor, the first light emitting control subcircuit includes a third transistor, and the second light emitting control subcircuit includes a fourth transistor; The control electrode of the driving transistor is connected to the first node, the first electrode of the driving transistor is connected to the second node, and the second electrode of the driving transistor is connected to the third node; The control electrode of the first transistor is connected to the first scanning signal line, the first electrode of the first transistor is connected to the data signal line, and the second electrode of the first transistor is connected to the second node; The control electrode of the second reset transistor is connected to the second scanning signal line, the first electrode of the second reset transistor is connected to the initial signal line, and the second electrode of the second reset transistor is connected to the anode terminal of the light emitting element; The control electrode of the second transistor is connected to the first scanning signal line, the first electrode of the second transistor is connected to the third node, and the second electrode of the second transistor is connected to the fifth node; One end of the storage capacitor is connected to the first power line, and the other end of the storage capacitor is connected to the first node; The control electrode of the leakage prevention transistor is connected to the third scanning signal line, the first electrode of the leakage prevention transistor is connected to the fifth node, and the second electrode of the leakage prevention transistor is connected to the first node; The control electrode of the first reset transistor is connected to the second scanning signal line, the first electrode of the first reset transistor is connected to the initial signal line, and the second electrode of the first reset transistor is connected to the fifth node; The control electrode of the third transistor is connected to the light emitting control signal line, the first electrode of the third transistor is connected to the first power line, and the second electrode of the third transistor is connected to the second node; The control electrode of the fourth transistor is connected to the light emission control signal line, the first electrode of the fourth transistor is connected to the third node, and the second electrode of the fourth transistor is connected to the anode terminal of the light emitting element.

9. The pixel circuit according to claim 8, wherein: The first reset transistor to the second reset transistor are all low-temperature polysilicon thin film transistors, and the leakage prevention transistor is an indium gallium zinc oxide thin film transistor.

10. The pixel circuit according to claim 9, wherein: In a direction perpendicular to the display substrate, the pixel circuit further comprises a light emitting structure layer arranged on a side of the driving circuit layer away from the substrate, and the driving circuit layer further comprises a light shielding layer, a first semiconductor layer, a second semiconductor layer and a fifth conductive layer; The first semiconductor layer includes an active layer of multiple low-temperature polysilicon thin film transistors, the first conductive layer also includes a second scanning signal line and a light-emitting control signal line, the second conductive layer includes a first branch of a third scanning signal line, the second semiconductor layer includes an active layer of an oxide thin film transistor, the third conductive layer also includes a second branch of the third scanning signal line and a first initial signal line, the fourth conductive layer includes a plurality of connecting electrodes and a second initial signal line, and the fifth conductive layer includes a first power line, a data signal line and an anode connecting electrode.

11. A display device, comprising a display area and a peripheral area located around the display area, wherein the display area comprises the pixel circuit according to any one of claims 1 to 10, and the peripheral area comprises a first scanning signal line driving circuit, a second scanning signal line driving circuit, a third scanning signal line driving circuit and a light emission control signal line driving circuit, The first scanning signal line driving circuit includes a plurality of cascaded first scanning signal line shift registers; The second scanning signal line driving circuit includes a plurality of cascaded second scanning signal line shift registers; The third scanning signal line driving circuit includes a plurality of cascaded third scanning signal line shift registers; The light emission control signal line driving circuit includes a plurality of cascaded light emission control signal line shift registers.

12. The display device according to claim 11, wherein: The peripheral area includes a first frame area and a second frame area which are arranged opposite to each other on the left and right sides of the display area; The plurality of first scanning signal line shift registers are divided into two groups, one of which is distributed in the first frame area, and the other is distributed in the second frame area, and each first scanning signal line shift register is connected to a pixel circuit in a row of sub-pixels; The plurality of second scanning signal line shift registers are divided into two groups, one of which is distributed in the first frame area, and the other is distributed in the second frame area, and each second scanning signal line shift register is connected to a pixel circuit in one or two rows of sub-pixels; The plurality of third scan signal line shift registers are divided into two groups, one of which is distributed in the first frame area, and the other is distributed in the second frame area, and each third scan signal line shift register is connected to a pixel circuit in one or two rows of sub-pixels; The multiple light emitting control signal line shift registers are divided into two groups, one of which is distributed in the first frame area, and the other is distributed in the second frame area. Each light emitting control signal line shift register is connected to the pixel circuit in one or two rows of sub-pixels.

13. The display device according to claim 11, wherein: The peripheral area includes a first frame area and a second frame area which are arranged opposite to each other on the left and right sides of the display area; The plurality of first scanning signal line shift registers are divided into two groups, one of which is distributed in the first frame area, and the other is distributed in the second frame area, and each first scanning signal line shift register is connected to a pixel circuit in a row of sub-pixels; The plurality of second scanning signal line shift registers are distributed in the first frame area or the second frame area, and each second scanning signal line shift register is connected to a pixel circuit in one or two rows of sub-pixels; The plurality of third scan signal line shift registers are distributed in the first frame area or the second frame area, and each third scan signal line shift register is connected to a pixel circuit in one or two rows of sub-pixels; The plurality of light emitting control signal line shift registers are distributed in the first frame area or the second frame area, and each light emitting control signal line shift register is connected to a pixel circuit in one or two rows of sub-pixels.

14. The display device according to claim 11, wherein: The peripheral area includes a first frame area and a second frame area which are arranged opposite to each other on the left and right sides of the display area; The plurality of first scan signal line shift registers are distributed in the first frame area or the second frame area, and each first scan signal line shift register is connected to a pixel circuit in a row of sub-pixels; The plurality of second scanning signal line shift registers are distributed in the first frame area or the second frame area, and each second scanning signal line shift register is connected to a pixel circuit in one or two rows of sub-pixels; The plurality of third scan signal line shift registers are distributed in the first frame area or the second frame area, and each third scan signal line shift register is connected to a pixel circuit in one or two rows of sub-pixels; The plurality of light emitting control signal line shift registers are distributed in the first frame area or the second frame area, and each light emitting control signal line shift register is connected to a pixel circuit in one or two rows of sub-pixels.

15. A method for driving a pixel circuit, for driving the pixel circuit according to any one of claims 1 to 10, the driving method comprising: In the reset stage, the first reset subcircuit resets the anode terminal of the light emitting element in response to the control signal of the second scanning signal line; In the data writing phase, the writing subcircuit writes a data voltage signal to the first electrode of the driving subcircuit in response to a control signal of the first scanning signal line; In the light emitting stage, the driving sub-circuit provides a driving current between the first electrode and the second electrode of the driving sub-circuit in response to the control signal of the first node; In the low-frequency display mode, the input frequency of the control signal of the first scan signal line is the same as the data refresh frequency, and the input frequency of the control signal of the second scan signal line is greater than the data refresh frequency.

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