Multi-functional gate position indicator

Abstract

The application discloses a multifunctional gate opening table, which adopts a FPGA+ARM system architecture, wherein the FPGA system processes external high-speed SSI signal communication, and the ARM system processes man-machine configuration and peripheral output control; the FPGA system comprises a PLL module, an USR sending module, a signal monitoring module, a signal detecting module, an input configuration module and an output state relay module; the ARM system comprises an USR receiving module, a keyboard input module, an LCD display module, a relay output module and an output configuration module; the signal monitoring module is used for monitoring SSI communication between the FPGA system and a gate opening instrument; and the signal detecting module is used for directly detecting high-speed SSI communication of the gate opening instrument by the FPGA system. The application has the advantages of being capable of monitoring and detecting the states of two gate opening instruments, and realizing high-speed monitoring and detection of a SSI signal interface with a maximum working frequency of 2MHz.

Description

Technical Field

[0001] This invention relates to the field of gate opening gauge technology, and more specifically, to a multifunctional gate opening gauge. More specifically, it is a multifunctional gate opening gauge applicable to multiple fields (such as water conservancy and hydropower, industrial automation, chemical and petroleum industries). Background Technology

[0002] In the water conservancy and hydropower industry, gate opening display and control play a crucial role. Gate opening detection is typically performed by gate opening meters. Most water conservancy and hydropower gate control requires signals from two or more gate opening meters. These meters not only detect the gate opening but also reflect the gate's status. The gate status is fed back to the PLC system, which then controls the hydraulic hoist to adjust the cylinders, thereby adjusting the gate's posture to achieve safe gate opening control. Currently, gate opening meters commonly use a single MCU system, which can connect to gate opening meters with various signal formats. The communication interface signal formats are typically RS485, analog, and SSI. The opening meter transmits the read data to the PLC automation system via analog and RS485 signals. Due to the increasingly stringent requirements for gate opening in water conservancy and hydropower, the most commonly used gate opening meter in the industry currently uses the SSI communication interface.

[0003] With the widespread application of technology, the requirements for gate opening control in water conservancy and hydropower are becoming increasingly stringent, leading to the following new situations: Situation 1: The gate opening meter is required to have the function of "locally" displaying the changes in two opening values ​​and the opening difference. Because the existing gate opening meter MCU technology cannot achieve high-speed monitoring of the SSI bus in terms of processing speed (the existing gate opening meter is applicable to an SSI communication rate of about 200kHz or less, which cannot meet the requirements of high-speed SSI communication (the high-speed communication rate is generally 500kHz)), they often use another method: first connect the SSI gate opening meter to the opening meter, and then convert the opening meter into analog or RS485 signals and input them into the PLC system. This approach is functionally feasible, but it has a major problem: if the opening meter fails, the entire system will crash. Scenario 2: The gate opening meter needs to display data from both the PLC system and the gate opening instrument normally. In the event of a PLC system crash, the gate opening meter should switch to detection mode, operating independently of the PLC system and working with the gate opening instrument. Existing gate opening instruments, mostly using single-MCU technology, cannot achieve this dual functionality. Scenario 3: Gate opening data is crucial for security, importance, and reliability. A single hydraulic cylinder may require two to three gate opening instruments. In this case, a gate opening meter is needed for one-to-one or one-to-multiple backup management. If the primary instrument fails, the backup can be immediately activated, meeting redundancy requirements. However, most existing gate opening instruments are single-MCU designs, using single-MCU I / O pins or SPI-simulated SSI communication, resulting in poor compatibility with SSI devices and failing to meet the real-time high-speed data requirements of a one-to-one backup system.

[0004] Therefore, it is necessary to develop a multi-functional gate opening meter that can achieve high-speed monitoring and detection of SSI signal interfaces, can directly communicate with the PLC automation system via SSI, can disconnect from the PLC automation system communication line as needed, and can meet the real-time requirements of high-speed SSI data for both use and backup. Summary of the Invention

[0005] The purpose of this invention is to provide a multifunctional gate opening meter that meets the real-time requirements of high-speed SSI data for both active and standby operation. It can monitor and detect the status of two gate opening meters. In monitoring mode, the gate opening meters monitoring the two SSI signals communicate normally with the PLC system and display the meter position information directly on the LCD. In detection mode, the communication lines between the gate opening meters and the PLC automation system are disconnected, and the two SSI signal gate opening meters communicate directly with the gate opening meter, displaying the meter position information directly on the LCD. This invention enables high-speed monitoring and detection of the SSI signal interface at a working frequency of up to 2MHz. It ensures reliable delivery of gate opening meter sensor travel data to users in any environment, meeting the high reliability and high performance requirements of various users of SSI signal interfaces for water conservancy and hydropower gate opening meters.

[0006] To achieve the above objectives, the technical solution of the present invention is as follows: a multifunctional gate opening meter, characterized in that: it adopts an FPGA+ARM system architecture, the FPGA system processes external high-speed SSI signal communication, and the present invention achieves high-speed SSI communication through the high-speed concurrent acquisition of SSI signals by the FPGA system; the ARM system processes human-machine configuration and peripheral output control.

[0007] Both the FPGA system and the ARM system are connected to the power management module;

[0008] The FPGA system includes a PLL module, a USR transmitting module, a signal monitoring module, a signal detection module, an input configuration module, and an output status relay module;

[0009] The ARM system includes a USR receiver module, a keyboard input module, an LCD display module, a relay output module, and an output configuration module, etc.

[0010] The PLL module connects to an external clock and is used to manage the clock. The 8MHz generated by the external active crystal oscillator generates two clock signals through the PLL module: one is the 100MHz internal clock of the FPGA, and the other is the 8MHz clock required by the ARM.

[0011] The USR transmitting module is used to transmit the SSI high-speed signal data captured by the FPGA system to the serial port of the ARM system through the TX terminal of the module at a baud rate of 115200BPS. Other interfaces such as SPI, I2C, and FMC may also be used for communication.

[0012] The signal monitoring module is used by the FPGA system to monitor the SSI communication between the PLC and the gate opening instrument.

[0013] The signal detection module is used for direct SSI high-speed communication between the FPGA system and the gate opening meter.

[0014] The input configuration module is used to read ARM system instructions and change the operating state of the FPGA system.

[0015] The LCD display module is used to display the gate opening meter signal data and table configuration parameters on the LCD.

[0016] The keyboard input module is used to input table configuration parameters;

[0017] The relay output module is used to convert the gate opening instrument signal into switching quantities such as upper and lower limit and over-tolerance.

[0018] The output configuration module is used to convert the table configuration parameters into instructions and send them to the input configuration module of the FPGA system.

[0019] The USR receiver module is used to receive SSI high-speed signal data captured by the USR transmitter module;

[0020] The output status relay module is connected to the status relay; in the monitoring state, the output status relay module does not output, the status relay does not engage, and the PLC automation system is directly connected to the gate opening meter SSI bus; in the detection state, the output status relay module outputs, the status relay engages, the PLC automation system is disconnected from the gate opening meter SSI bus, and the gate opening meter is directly connected to the gate opening meter.

[0021] In monitoring mode, when the multifunctional gate opening meter of the present invention malfunctions, it will not affect the normal SSI communication between the original PLC automation system and the gate opening meter. This ensures that the stroke data of the gate opening meter sensor can be reliably provided to the user in any environment, resulting in high reliability. It overcomes the shortcomings of the prior art, which, when the opening meter malfunctions, causes the original PLC automation system and the gate opening meter to lose normal SSI communication, leading to the collapse of the entire PLC automation system and the inability to provide the stroke data of the gate opening meter sensor to the user, resulting in low reliability.

[0022] This invention enables the monitoring of gate opening instrument data in the water conservancy and hydropower industry without modifying the existing PLC system and the normal SSI communication line between the gate opening instrument and the gate opening instrument.

[0023] In achieving the real-time requirement of high-speed SSI data with one active and one standby function, this invention provides a one-to-one standby configuration for both monitoring and detection functions. "Active" refers to the monitoring function, meaning the PLC automation system and the gate opening meter are in normal SSI communication, monitoring data. "Standby" refers to the detection function, meaning the PLC automation system is disconnected from the gate opening meter's SSI bus, but the gate opening meter is directly connected to the gate opening meter, detecting the position data of both gate opening meters. The "active" and "standby" functions in this invention automatically switch in real-time according to usage requirements.

[0024] In the above technical solution, the FPGA system is connected to the detection differential drive through the signal detection module; the detection differential drive is connected to the PLC automation system and the two-way gate opening meter through the status relay and SSI bus.

[0025] The signal monitoring module is connected to the monitoring differential drive; the monitoring differential drive is connected to the PLC automation system and the two-way gate opening meter through status relays and SSI bus.

[0026] The output status relay module is connected to the status relay.

[0027] In the above technical solution, the multifunctional gate opening meter of the present invention includes two working modes: listening and detection.

[0028] When in monitoring mode, the gate opening meter communicates normally with the PLC automation system. The multi-functional gate opening meter monitors and reflects the status of the two gate opening meters and displays it in real time. The SSI communication data between the PLC automation system and the gate opening meter is directly displayed on the instrument's LCD screen. At the same time, the gate opening meter has IO output control capability.

[0029] When in detection mode, the PLC automation system disconnects from the gate opening meter's SSI communication line, and the multi-functional gate opening meter acts as the host, communicating directly with the gate opening meter. The gate opening meter can detect the status of both gate opening meters and display it in real time. The detection data is displayed on the instrument's LCD screen. The gate opening meter also has output IO control capability in detection mode.

[0030] Users determine the working status of the gate opening meter based on the relay outputs of the monitoring and detection statuses. Both the monitoring and detection statuses can output relay values ​​as needed on site, making it convenient for users to determine the working status of the gate opening meter and meeting the stringent requirements of water conservancy and hydropower for gate opening control.

[0031] In the above technical solution, the FPGA used is the Gowin Semiconductor GW1N series FPGA.

[0032] In the above technical solution, ARM uses the EZ Innovation M3 series MCU.

[0033] In the above technical solution, the power management module is divided into three levels:

[0034] The first-level power management module uses the MP2403 synchronous buck regulator to step down the external input DC24V to the internal DC5V. Other buck regulator power chips may also be used. The DC5V is mainly used as the input for the second and third levels, and also powers the relays and bus chips.

[0035] The second-level power management module uses an AMS1117-3.3LDO three-terminal regulator to step down the internal input DC5V to an internal DC3.3V, which powers the MCU and MCU peripherals.

[0036] The third-level power management module uses an AMS1117-3.3LDO three-terminal regulator to step down the internal input DC5V to an internal DC1.2V, which is the FPGA core voltage.

[0037] The present invention has the following advantages:

[0038] (1) This invention can take into account the real-time requirements of high-speed SSI data with one for use and one for backup. It can monitor and detect the status of two gate opening meters. In the monitoring mode, the gate opening meter of this invention can communicate normally with the PLC system and display the position information of the opening meter directly on the LCD. In the detection mode, the gate opening meter is disconnected from the PLC automation system communication line, and the gate opening meter of the two SSI signals can communicate normally with the gate opening meter directly. The position information of the opening meter is displayed directly on the LCD.

[0039] (2) The monitoring function in this invention is a brand-new application on the gate opening meter. This invention achieves high-speed monitoring and detection of the SSI signal interface with a working frequency of up to 2MHz by using FPGA system for high-speed parallel processing, ARM system for high-speed peripheral management, and state relay signal switching. Through this invention, the travel data of the gate opening meter sensor can be reliably provided to the user in any environment, meeting the requirements of various users of the SSI signal interface of water conservancy and hydropower gate opening meter for high reliability and high performance of gate opening. Attached Figure Description

[0040] Figure 1 This is a system design block diagram of the present invention.

[0041] Figure 2 This is a schematic diagram of the FPGA working principle in this invention.

[0042] Figure 3 This is a timing waveform diagram of SSI in this invention.

[0043] Figure 4 This is a pin diagram of the multifunctional gate opening meter in this invention.

[0044] Figure 5 This is a differential signal diagram of the SSI signal in this invention.

[0045] Figure 6 This is a diagram of the state relay in this invention. Detailed Implementation

[0046] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, these descriptions do not constitute a limitation of the present invention and are merely illustrative. The advantages of the present invention will become clearer and easier to understand through this description.

[0047] As shown in the attached figure, a new type of multifunctional gate opening meter adopts an FPGA+ARM system architecture. The FPGA is a Gowin Semiconductor GW1N series FPGA, which has the characteristics of low power consumption, low cost, instant start-up, non-volatility, high security, rich packaging types, and convenient and flexible use. The device uses model GW1NZ-LV1QN48C6 / I5.

[0048] The FPGA system functions were developed using Verilog HDL in the Gowin_V1.9.8.07 IDE environment. It consists of PLL module, USR module, signal monitoring module, signal detection module, input configuration module, output status relay module, etc.

[0049] The ARM uses the EZ Innovation M3 series MCU, which features domestic production, high clock frequency, low power consumption, and Arm Cortex-M3 core. This device uses model GD32F103C8T6.

[0050] The ARM system is developed in the Keil 5 IDE environment using the C language. It consists of a USR receiver module, a keyboard input module, an LCD display module, an output relay module, and an output configuration module.

[0051] Figure 1 The power management module is divided into three levels. The first level uses an MP2403 synchronous buck regulator to step down the external input DC24V to an internal DC5V. Other buck regulator power chips may also be used. The DC5V is mainly used as the input for the second and third levels, and also powers the relays and bus chips. The second level uses an AMS1117-3.3LDO three-terminal regulator to step down the internal input DC5V to an internal DC3.3V, which powers the MCU and MCU peripherals. The third level uses an AMS1117-3.3LDO three-terminal regulator to step down the internal input DC5V to an internal DC1.2V, which is the FPGA core voltage.

[0052] Figure 4 The diagram shows the back wiring terminals for one application of this device. The terminal diagram includes a DC24V power input, a gate opening meter with two signal interfaces (SSI), and a PLC module with two signal interfaces (SSI).

[0053] Figure 5The differential drive module is divided into two groups of SSI signal differential drives. Each group has the same function. The SSI data differential drive direction is the input, and the SSI clock differential drive direction is the input during listening and the output during detection.

[0054] Figure 6 There are 4 groups of state relays, which are divided into two states. In the first state, the state relays are inactive and in the listening state. In the second state, all 4 groups of state relays are activated simultaneously and the state relays are in the detection state.

[0055] The core function of the FPGA system in this device is to convert the SSI signal into a USR signal. First, the FPGA system clock is provided by an external 8MHz active crystal oscillator. The external clock is used as the input of the PLL module. The PLL generates an internal main frequency clock of 100MHz by frequency multiplication, and generates an ARM system clock of 8MHz at the same frequency with the same phase. After receiving the ARM system configuration instruction, the FPGA system input configuration module changes the working state of the signal listening module and the signal detection module according to the instruction.

[0056] when Figure 2 When the Config directive is set to signal listening, the W_start function block issues a state change, while the output_relay function block has no output. Figure 6 The output status relay module is not activated.

[0057] SSI_Conduct_1 and SSI_Conduct_2 are working, while SSI_Host_1 and SSI_Host_2 are not working. Switch function block states change and control... Figure 5 The differential signal drive states of U11, U12, U13, and U14 are all in receive mode.

[0058] List the engineering model of the signal monitoring module in Verilog HDL:

[0059]

[0060]

[0061] The signal monitoring module's engineering model has input ports clk, rst_n, ssi_clk, ssi_data, and ssi_start, and output ports ssi_signal and ssi_datahex. The engineering model will use the ssi_clk signal to convert and process the ssi_data signal, and the processing result will be written into ssi_datahex. Once completed, it will be output to ssi_signal.

[0062] Figure 2When the Config instruction is used for signal detection, the W_start function block issues a state change, and the output_relay function block outputs. Figure 6 When the output status relay module activates, the PLC disconnects from the gate opening meter's SSI bus. SSI_Conduct_1 and SSI_Conduct_2 become inactive, while SSI_Host_1 and SSI_Host_2 become active. The Switch (clock) function block's state changes. Figure 5 The differential signals U11 and U12 are driven in the receiving state, while the differential signals U13 and U14 are driven in the transmitting state.

[0063] List the engineering model of the signal detection module in Verilog HDL:

[0064]

[0065] The signal detection module's engineering model has input ports clk, rst_n, ssi_data, and ssi_start, and output ports ssi_clk, ssi_signal, and ssi_datahex. The engineering model will convert and process the input ssi_data signal by outputting the ssi_clk signal, and the processing result will be written into ssi_datahex and then output to ssi_signal.

[0066] When the output is complete and the ssi_signal signal is 1, it indicates that the output has passed. Figure 3 The SSI timing diagram module reads one word of data, and the other channel does the same; the data from the two SSIs are transmitted through... Figure 2 The state machine of the Two_choose module is encoded into a custom protocol code. Figure 2 The Usr_Tx module sends the data to the ARM at a baud rate of 115200 BPS.

[0067] Two_choose module custom protocol code state machine model:

[0068] case(ramoutaddress)

[0069] 4'd1:begin txd_data<=8'ha5; end4'd2:begin txd_data<=ssi_datahex_0[15:8]; end4'd3:begin txd_data<=ssi_datahex_0[7:0]; end4'd4:begin txd_data<=ssi_datahex_1[15:8]; end4'd5:begin txd_data<=ssi_datahex_1[7:0]; end4'd6:begintxd_data<=8'h0d; end

[0070] defau lt:;

[0071] Endcase

[0072] Figure 1 After receiving the protocol code, the ARM system in the middle decodes the two sets of gate opening meter data required and displays them on the LCD through the LCD display module.

[0073] When the keyboard input module and the LCD display module form a human-machine interface, the working state can be manually switched, and various protection parameters can be input. These protection parameters generally include A-mode, B-mode, AB-mode, AB positioning, upper and lower limits, etc. The multi-functional gate opening instrument of this invention can work autonomously completely independent of the PLC system.

[0074] Therefore, the multifunctional gate opening meter of this invention has two-channel SSI gate opening meter monitoring and detection functions. Utilizing the FPGA concurrency mechanism and ARM multi-peripheral interface features, this multifunctional gate opening meter meets the high reliability and high performance requirements of various users of the SSI signal interface for water conservancy and hydropower gate opening meters. This invention can achieve high-speed monitoring and detection of the SSI signal interface at a working frequency of up to 2MHz. Through the multifunctional gate opening meter described in this invention, water conservancy and hydropower, or industrial fields, can reliably provide users with the stroke data of the gate opening meter sensor regardless of the environment.

[0075] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0076] All other unspecified parts belong to the prior art.

Claims

1. A multifunctional gate opening gauge, characterized in that: The system adopts an FPGA+ARM architecture, with the FPGA system handling external high-speed SSI signal communication and the ARM system handling human-machine configuration and peripheral output control. Both the FPGA system and the ARM system are connected to the power management module; The FPGA system includes a PLL module, a USR transmitting module, a signal monitoring module, a signal detection module, an input configuration module, and an output status relay module; The ARM system includes a USR receiver module, a keyboard input module, an LCD display module, a relay output module, and an output configuration module; The PLL module connects to an external clock and is used to manage the clock. The USR transmitting module is used to send the SSI high-speed signal data captured by the FPGA system to the serial port of the ARM system; The signal monitoring module is used to monitor the SSI communication between the PLC and the gate opening instrument; The signal detection module is used for direct SSI high-speed communication between the FPGA system and the gate opening meter; The input configuration module is used to read ARM system instructions and change the operating state of the FPGA system. The LCD display module is used to display the gate opening meter signal data and table configuration parameters on the LCD. The keyboard input module is used to input table configuration parameters; The relay output module is used to convert the gate opening indicator signal into a switching signal; The output configuration module is used to convert the table configuration parameters into instructions and send them to the input configuration module of the FPGA system. The USR receiver module is used to receive SSI high-speed signal data captured by the USR transmitter module; The output status relay module is connected to the status relay; in the monitoring state, the output status relay module does not output, the status relay does not engage, and the PLC automation system is directly connected to the gate opening meter SSI bus. In the detection state, the output status relay module outputs, the status relay is activated, the PLC automation system is disconnected from the gate opening meter SSI bus, and the gate opening meter is directly connected to the gate opening meter.

2. The multifunctional gate opening meter according to claim 1, characterized in that: The signal detection module is connected to the detection differential drive; the detection differential drive is connected to the PLC automation system and the two-way gate opening meter through status relays and SSI bus. The signal monitoring module is connected to the monitoring differential driver; The monitoring differential drive is connected to the PLC automation system and the two-way gate opening meter via status relays and SSI bus.

3. The multifunctional gate opening table according to claim 1 or 2, characterized in that: It includes two working modes: listening and detection; When in monitoring mode, the gate opening meter communicates normally with the PLC automation system. The multi-functional gate opening meter monitors and reflects the status of the two gate opening meters and displays it in real time. The SSI communication data between the PLC automation system and the gate opening meter is directly displayed on the instrument's LCD screen. When in detection mode, the PLC automation system disconnects from the gate opening meter SSI communication line, and the multi-functional gate opening meter acts as the host to communicate directly with the gate opening meter. The gate opening meter detects the status of the two gate opening meters and displays it in real time. The detection data is displayed on the instrument's LCD screen. Users determine the working status of the gate opening device based on the relay outputs of the monitoring and detection status.

4. The multifunctional gate opening meter according to claim 3, characterized in that: The FPGA used is the Gowin Semiconductor GW1N series FPGA.

5. The multifunctional gate opening meter according to claim 4, characterized in that: ARM uses the EZ Innovation M3 series MCU.

6. The multifunctional gate opening meter according to claim 5, characterized in that: The power management module is divided into three levels: The first-stage power management module uses the MP2403 synchronous buck regulator to step down the external input DC24V to the internal DC5V. The DC5V is used as the input for the second and third stages, and also powers the relays and bus chips. The second-level power management module uses an AMS1117-3.3LDO three-terminal regulator to step down the internal input DC5V to an internal DC3.3V, which powers the MCU and MCU peripherals. The third-level power management module uses an AMS1117-3.3LDO three-terminal regulator to step down the internal input DC5V to an internal DC1.2V, which is the FPGA core voltage.

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