Enhanced twisted pair copper transmission system and method of implementation

Abstract

The application discloses an enhanced twisted copper line transmission system and an implementation method thereof, which comprises an FPGA and an analog front end matched with the FPGA, the FPGA is configured to comprise a framing / de-framing unit, which is connected with network equipment at a public network or a local area network end through an interface unit; a digital front end unit connected with the analog front end, used for realizing PAM and CAP modulation and demodulation; a SOC subsystem connected with the framing / de-framing unit and the digital front end unit respectively, used for completing link building and state management; and the SOC subsystem adopts an embedded kernel, and a UART serial port of the embedded kernel is a management channel under SDSL technology and SHDSL technology. The application provides an enhanced twisted copper line transmission system and an implementation method thereof, adopts a channel compatibility and algorithm function module multiplexing method, supports two transmission technologies of SDSL and SHDSL, adopts a spread spectrum method, breaks through the limitation of an ITU-G.991.2 SHDSL standard, makes the highest transmission rate not less than 20480 kbit / s, and meets the application requirements of low-speed long-distance and short-distance high-bandwidth of users.

Description

Technical Field

[0001] This invention relates to the field of twisted-pair copper wire transmission technology. More specifically, this invention relates to an enhanced twisted-pair copper wire transmission system and its implementation method. Background Technology

[0002] Currently, the main transmission technologies based on twisted-pair copper wires both domestically and internationally include SDSL, SHDSL, ADSL2+, VDSL2, G.hn, and G.fast.

[0003] In 1998, the ITU-T approved the HDSL standard (G.991.1), which supports symmetrical transmission. It uses CAP modulation, which led to the development of SDSL transmission technology, supporting speeds of 2048 kbit / s. It is typically used for data transmission over a range of 12 kilometers, and chips based on this technology are no longer in production.

[0004] In 2001, the ITU-T approved the SHDSL standard (G.991.2), supporting symmetrical transmission. Because SHDSL uses the superior TC-PAM modulation method, it compresses the transmission spectrum, improves noise immunity, and extends transmission distance, thus offering a significant distance advantage compared to ADSL and HDSL technologies. Currently, SHDSL access technology using G.991.2 can achieve a maximum symmetrical data transmission rate of 15 Mbit / s, typically used for data transmission within a 12-kilometer range. Chips based on this technology are about to be discontinued.

[0005] In 2003, the ITU-T approved the new generation ADSL2+ standard (G.992.5), supporting asymmetric transmission. ADSL2+ uses DMT modulation, supports all ADSL2 technologies, widens the line bandwidth to 2.2MHz, increases the maximum number of subcarriers to 512, and raises the maximum downstream speed to 24Mbit / s, while maintaining full compatibility with both ADSL and ADSL2 standards. The ADSL2+ standard includes Annex M, which increases upstream bandwidth through dynamic frequency adjustment, theoretically providing a maximum upstream speed of 3.5Mbit / s. It is typically used for data transmission within a 3km range.

[0006] In 2005, the ITU-T adopted the VDSL2 standard (G.993.2), supporting both symmetrical and asymmetrical transmission modes. VDSL2 uses DMT as the sole modulation method, enabling interoperability between VDSL2 equipment from different manufacturers. It also extends the line bandwidth to 30MHz, achieving maximum uplink and downlink rates of 100Mbit / s each. Furthermore, it incorporates technologies such as Time Domain Equalization (TEQ), Echo Cancellation (EC), Frequency Notch, and Uplink Power Downgrade (UPBO), enhancing transmission performance and interference immunity. It is typically used for data transmission within a 1-kilometer range.

[0007] In 2010, the ITU-T published the G.hn standard (G.9960), which uses OFDM modulation, has a line bandwidth of 100MHz, supports 4096-QAM modulation, and has a maximum bidirectional transmission rate of 1Gbit / s. G.hn supports three transmission media: telephone line, power line, and coaxial cable. It is a home networking technology standard and is typically used for data transmission within a 1-kilometer range.

[0008] In 2020, the ITU-T published the G.fast standard (G.9701), which allows for on-demand allocation of uplink and downlink rates. G.fast uses DMT modulation, extends the line bandwidth to 106MHz, and may further extend to 212MHz. It is technically compatible with ADSL2+ and VDSL2, and can provide bidirectional transmission rates up to 1Gbit / s, typically used for data transmission within a 200-meter range.

[0009] Due to their unique advantages such as symmetrical services, long communication distance, and strong anti-interference capabilities, SDSL and SHDSL are more suitable for long-distance communication and some private network communication than ADSL2+, VDSL2, G.hn, and G.fast technologies. Moreover, SDSL and SHDSL technologies have a long-term sustainability in the use of private network communication. However, SDSL chips are facing discontinuation and SHDSL chips are about to be discontinued, which cannot meet the continuous order demand. Summary of the Invention

[0010] One object of the present invention is to solve at least the above-mentioned problems and / or defects, and to provide at least the advantages described below.

[0011] The purpose of this invention is to propose an enhanced twisted-pair copper wire transmission system and its implementation method. By establishing a reconfigurable FPGA + analog front-end hardware system and designing CAP and PAM integrated software code, it supports both SDSL and SHDSL technologies, further expands the line spectrum, and realizes the transmission of service data with a maximum rate of not less than 20480kbit / s on a pair of twisted-pair copper wires.

[0012] To achieve these objectives and other advantages of the present invention, an enhanced twisted-pair copper wire transmission system is provided, including an FPGA and an analog front-end cooperating therewith, the FPGA being configured to include:

[0013] The framing / deframing unit connects to network devices on the public network or local area network via the interface unit.

[0014] A digital front-end unit connected to the analog front-end to implement PAM and CAP modulation and demodulation;

[0015] It is a SOC subsystem that connects to the framing / deframing unit and the digital front-end unit respectively to complete link establishment and status management;

[0016] The simulation front end is configured to include:

[0017] A receiving unit and a transmitting unit that communicate with twisted-pair copper wires;

[0018] The FPGA is also connected to a configuration chip for storing FPGA software code and a clock unit for providing clock signals.

[0019] The analog front end is connected to a twisted-pair copper wire via a matching transformer;

[0020] The SOC subsystem is configured to use an embedded kernel, and the UART serial port of the embedded kernel is a management channel under SDSL and SHDSL technologies.

[0021] Preferably, the receiving unit is configured to include:

[0022] A receiving amplifier circuit connected to the transformer side;

[0023] The receiving amplifier circuit is connected to convert the amplified signal into an analog-to-digital converter (ADC) in the digital front-end unit.

[0024] The transmitting unit is configured to include:

[0025] Digital-to-analog converter (DAC) connected to the digital front-end unit;

[0026] The signal received from the DAC is sent to the line drive module on the transformer side;

[0027] Among them, a matching low-pass filter is provided between the amplifier circuit and the ADC, and between the DAC and the line drive module;

[0028] A resistor is provided between the line drive module and the transformer, and the output terminal of the line drive module is connected to the receiving amplifier circuit.

[0029] Preferably, the signal bandwidth of the ADC, DAC, and low-pass filter is configured to be greater than the bandwidth required for 20480 kbit / s, and the signal-to-noise ratio is greater than the signal-to-noise ratio required for MTC-PAM.

[0030] The transmission power of the analog front end is ≤14.5dBm.

[0031] A use case for an enhanced twisted-pair copper wire transmission system is as follows: the process of establishing a link and communication between user A and user B through the enhanced twisted-pair copper wire transmission system is configured to include:

[0032] Step 1: The FPGA on user A side receives the service data sent by user A through the interface unit, and frames, encodes and modulates the received signal before sending it to the analog front-end on the local side.

[0033] Step 2: User A's analog front-end performs digital-to-analog conversion, shaping and filtering, and signal amplification on the signal received from the FPGA before sending it into the twisted-pair copper wire.

[0034] Step 3: User B's analog front end receives messages from the twisted pair copper wire. The local echo signal is canceled and the received signal is amplified through the receiving amplifier circuit to amplify the amplitude of the received signal to the range of the ADC's receiving level. After the low-pass filter filters out the sampling clock outside the first Nyquist interval of the received signal, the received signal is converted from digital to analog by the ADC and then sent to User B's FPGA.

[0035] Step four: User B's FPGA demodulates and deframes the received signal and then sends it back to User B.

[0036] Step 5: User B sends its own service data to User A simultaneously using the same method, and User A receives the service data.

[0037] Step Six: Before User A and User B send and receive service data, the SOC subsystem of the enhanced twisted-pair copper wire transmission system switches the communication channels under SDSL and SHDSL technologies through the management of configuration parameters and the functional modules corresponding to the digital front-end multiplexing algorithm, and completes data communication or handshake link establishment through Steps One to Five.

[0038] Preferably, the management of configuration parameters during communication channel switching includes:

[0039] Based on the choice between SDSL and SHDSL technologies, the corresponding parameters of the functional modules are adjusted through the digital headend;

[0040] Different transmission powers are preset for SDSL and SHDSL technologies respectively. The FPGA matches the corresponding transmission power based on the selection of SDSL and SHDSL technologies, thereby completing the adaptation of transmission power when switching communication channels.

[0041] Preferably, the functional modules after digital front-end algorithm reuse are configured to include:

[0042] Common scrambling / descrambling modules, encoding / decoding modules, precoding modules, echo cancellation modules, equalizer modules, interpolation filtering, and noise shaping filtering modules used in SDSL and SHDSL technologies;

[0043] In addition, SDSL has its own unique IQ filter, which enables the reuse of functional modules under SDSL and SHDSL technologies through a relatively fixed structure.

[0044] Preferably, the digital front-end is configured to employ a DSP computing unit, and the multiplexing process of the equalizer module, interpolation filtering, and noise shaping filtering module in the digital front-end multiplexing algorithm is configured to include:

[0045] S1. The embedded kernel selects and controls the initial coefficients of the filter configuration of the DSP computing unit according to different modes and data rates.

[0046] S2, the DSP computing unit starts the error calculation program to perform iterative calculations based on the input data stream;

[0047] S3. When the error reaches the specified value, the DSP calculation unit writes the converged filter coefficients into the filter parameter configuration interface to complete the parameter configuration under different technical systems and realize the functional reuse of functional modules under different systems.

[0048] This invention offers at least the following advantages: It employs a flexible, programmable hardware architecture combining an FPGA and an analog front-end. The FPGA handles CAP and PAM modulation / demodulation algorithms, framing and deframing, interface functions, and system control. The analog front-end handles analog-to-digital conversion and interface adaptation between the FPGA and the twisted-pair copper wire. By utilizing a spread spectrum approach, it achieves a technological breakthrough in the ITU-G.991.2 SHDSL standard, resulting in a maximum transmission rate of at least 20480 kbit / s, meeting the application requirements for long-distance and high-bandwidth connections. Furthermore, by employing algorithm function module reuse and channel compatibility, it supports both SDSL and SHDSL technologies on the same hardware platform, realizing a fusion design of the two technologies and meeting the requirement of backward compatibility with existing twisted-pair copper wire transmission systems. Simultaneously, the system hardware circuitry supports, but is not limited to, CAP and PAM modulation / demodulation technologies and can also support the development of other technologies.

[0049] Other advantages, objectives and features of the present invention will become apparent in part from the following description, and in part from those skilled in the art through study and practice of the invention. Attached Figure Description

[0050] Figure 1 This is a schematic block diagram of an enhanced twisted-pair copper wire transmission system according to one embodiment of the present invention;

[0051] Figure 2 This is a schematic diagram illustrating the application of the enhanced twisted-pair copper wire transmission system of the present invention.

[0052] Figure 3 This is a schematic diagram of the processing flow for the reuse of algorithm function modules in the enhanced twisted-pair copper wire transmission system of the present invention. Detailed Implementation

[0053] The present invention will now be described in further detail with reference to the accompanying drawings, so that those skilled in the art can implement it based on the description.

[0054] It should be understood that terms such as “having,” “comprising,” and “including” as used herein do not imply the presence or addition of one or more other elements or combinations thereof.

[0055] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installed", "equipped", "sleeved / connected", "connected", etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.

[0056] This invention proposes an enhanced twisted-pair copper wire transmission system that addresses the discontinuation of SDSL and SHDSL chips and achieves a technological breakthrough in the ITU-G.991.2 SHDSL standard, enabling a maximum transmission rate of no less than 20480 kbit / s to meet users' needs for long-distance transmission and higher bandwidth. It supports both SDSL and SHDSL technologies on the same hardware platform, realizing a fusion design of the two technologies and meeting the requirement of backward compatibility with existing twisted-pair copper wire transmission systems.

[0057] The principle block diagram of the enhanced twisted-pair copper wire transmission system in this invention is as follows: Figure 1 The system mainly includes FPGA1, analog front-end2, and power supply unit3. The specific structure and function of each part of the system are described below:

[0058] 1. FPGA Unit

[0059] An FPGA, as a programmable unit, is used to implement modulation and demodulation algorithms, framing and deframing, interface, and system control functions in a twisted-pair copper wire transmission system. The FPGA section includes an embedded core (10), a framing and deframing unit (11), a digital front-end unit (12), an interface unit (13), a configuration chip (14), and a clock unit (15). The embedded core handles link establishment and state management, managing the framing and deframing unit, the digital front-end unit, and the interface unit; its UART serial port serves as the configuration management channel. The framing and deframing unit performs mapping, encapsulation, positioning, multiplexing, and demultiplexing; in quasi-synchronous mode, it also performs bit stuffing / removal operations. The digital front-end unit implements the relevant algorithms for PAM and CAP modulation and demodulation.

[0060] The FPGA's software code is stored in the configuration chip and installed inside the FPGA after power-on. The FPGA's clock source comes from an external crystal oscillator, which further generates high-frequency clocks for internal functional modules via an internal phase-locked loop, as well as sampling clocks for the ADC / DAC.

[0061] FPGA provides interface adaptations for external data, offering both TDM interfaces for synchronous data transmission and SerDes interfaces for asynchronous data packet transmission, allowing for flexible configuration as needed.

[0062] The FPGA controls parameters such as transmit power, receive gain, and filter bandwidth of the analog front end in real time according to the needs of its internal algorithm.

[0063] 2. Simulated front-end unit

[0064] The analog front-end's data interface rate needs to meet the requirement of 20480 kbit / s, which is much higher than the 2304 kbit / s data rate of similar SDSL and SHDSL analog front-ends such as the AFE1230. The analog front-end unit can be an integrated chip or a composite circuit composed of independent ADC, DAC, line driver, and filter chips. The analog front-end mainly performs analog-to-digital conversion and interface adaptation between the FPGA and the twisted-pair copper wire, and functionally can be divided into a transmitting section and a receiving section.

[0065] Transmitting section: The DAC210 performs the conversion from digital to analog signals, featuring high resolution and high linearity, which aids in echo cancellation. The transmitted signal undergoes further shaping and filtering through a low-pass filter I 211, removing noise outside the first Nyquist interval. The line drive module 212 amplifies the transmitted signal, featuring high current and low distortion, enabling the line transmission power to reach a maximum of 14.5 dBm.

[0066] The receiving section: The receiving amplifier circuit 221 cancels the local echo signal and amplifies the received signal, increasing the signal amplitude to the optimal receiving level range of the ADC. After receiving the signal, the low-pass filter II 222 filters out the sampling clock outside the first Nyquist interval of the received signal, providing anti-aliasing protection. The ADC 223 employs high-speed ADC oversampling technology; the high data rate helps improve the system's transmission rate, ensuring a maximum transmission rate of no less than 20480 kbit / s, and further extending the transmission distance.

[0067] 3. Power supply unit

[0068] The power supply unit consists of DC / DC power chips, which provide the required power voltages for the FPGA and analog front end.

[0069] Furthermore, the enhanced twisted-pair copper wire transmission system of the present invention achieves a speed improvement in SHDSL technology by designing a high-performance analog front-end circuit:

[0070] If MTC-PAM modulation level is used, the net load rate R and the analog signal bandwidth f 3db Relationship: f 3db = (R+8) / K / 2, where K is the number of loads per symbol.

[0071] Increasing the analog signal bandwidth can improve the net load rate. Therefore, the ADC, DAC, and filters of this system must meet the signal bandwidth processing requirements of greater than 20480 kbit / s, and the signal-to-noise ratio must meet the requirements of MTC-PAM. The digital processing unit should increase the data processing bandwidth.

[0072] Furthermore, the enhanced twisted-pair copper wire transmission system of the present invention achieves multi-system integration through the following means:

[0073] Specifically, the enhanced twisted-pair copper wire transmission system of this invention can support SDSL and SHDSL functions separately, or simultaneously, and can be selected through a management interface. Therefore, the specific solution is as follows:

[0074] 1. Design a compatible analog channel

[0075] The analog signal bandwidth 0-A of SDSL overlaps with that of SHDSL (0-B). When designing analog circuits, the processing capacity of the ADC / DAC and the passband bandwidth of the filters are designed according to the maximum signal bandwidth of SHDSL. The FPGA adjusts the bandwidth according to the algorithm requirements.

[0076] The FPGA performs different power back-offs based on the mode. Here, power back-off refers to presetting different transmit powers for SDSL and SHDSL technologies respectively. The FPGA matches the corresponding transmit power based on the selection of SDSL and SHDSL technologies, thereby completing the adaptation of transmit power when switching communication channels. That is, the transmit power of SDSL is set to 13dBm, and the transmit power of SHDSL is set to 14.5dBm. When SDSL technology is selected, the FPGA directly matches the transmit power to 13dBm, and when SHDSL technology is selected, the FPGA directly matches the transmit power to 14.5dBm, completing the adaptation of transmit power under different technologies and making the analog channel compatible.

[0077] 2. For modules with similar functions in SDSL and SHDSL, a relatively fixed structure is adopted, but the parameters can be flexibly configured according to the mode. The parameters are calculated iteratively through the DSP computing unit, and then the coefficients of the fixed unit are modified to achieve the reuse of corresponding functional modules by algorithm calls as much as possible and reduce code redundancy.

[0078] Specifically, the functional modules are configured to include:

[0079] Common scrambling / descrambling modules, encoding / decoding modules, precoding modules, echo cancellation modules, equalizer modules, interpolation filtering, and noise shaping filtering modules used in SDSL and SHDSL technologies;

[0080] In addition, SDSL features a unique IQ filter, which enables the reuse of functional modules under SDSL and SHDSL technologies through a relatively fixed structure.

[0081] In practical applications, based on the choice between SDSL and SHDSL technologies, the corresponding parameters of the functional modules are adjusted through the digital front end;

[0082] like Figure 3 As shown, the PAM / CAP_FILTER_1 and PAM / CAP_FILTER_2 modules perform digital filtering and equalization functions of the data stream, respectively, and have parameter configuration interfaces;

[0083] The DSP computing unit in the data front end is a computing unit that receives information from the data inflow and control commands from the embedded kernel.

[0084] The DSP computing unit can be configured with coefficients for the PAM / CAP_FILTER_1 and PAM / CAP_FILTER_2 modules.

[0085] Taking a typical digital filter as an example, both SDSL and SHDSL use filters with the same structure, and the data streams of both technologies can pass through the same filter unit. First, the embedded kernel controls the DSP to configure the initial coefficients of the filter according to different modes and data rates; then, the DSP starts the error calculation program to perform iterative calculations based on the input data stream; finally, when the error reaches a specified value, the DSP writes the converged filter coefficients into the filter's parameter configuration interface.

[0086] Furthermore, the enhanced twisted-pair copper wire transmission system of this invention is constructed using programmable devices and an analog front-end (AFE). Because programmable devices are used as the hardware to carry the modulation and demodulation algorithm, they have the characteristics of flexible and variable algorithms and software. The performance of the analog front-end circuit is superior to that of analog front-ends of similar SHDSL and SDSL chips, supporting higher data rates. Independent ADC, DAC, line driver, filter and other chip units also have the characteristics of flexible selection.

[0087] Furthermore, the hardware circuitry of the enhanced twisted-pair copper wire transmission system supports, but is not limited to, CAP and PAM modulation and demodulation technologies, and can also support the development of other modulation and demodulation technologies.

[0088] Example:

[0089] This invention proposes an enhanced twisted-pair copper wire transmission system and its implementation method. The system adopts a flexible and programmable hardware architecture of FPGA + analog front-end. The FPGA completes functions such as CAP and PAM modulation / demodulation algorithms, framing and deframing, interface, and system control. The analog front-end handles analog-to-digital conversion and interface adaptation between the FPGA and the twisted-pair copper wire. A spread spectrum approach is used to achieve a technological breakthrough in the ITU-G.991.2 SHDSL standard, enabling a maximum transmission rate of no less than 20480 kbit / s, meeting the application requirements of long-distance and high-bandwidth users. Algorithm function module reuse and channel compatibility methods are employed to support SDSL and SHDSL technologies on the same hardware platform, realizing a fusion design of the two technologies and meeting the requirement of backward compatibility with existing twisted-pair copper wire transmission systems. Simultaneously, the system hardware circuitry supports, but is not limited to, CAP and PAM modulation / demodulation technologies, and can also support the development of other technologies.

[0090] like Figure 2 A pair of enhanced twisted-pair copper wire transmission systems form a twisted-pair copper wire transmission network. It serves as the channel for information transmission between user A and user B. Devices connected to it can be routers, switches, network controllers, etc., and the interfaces used are E1 / E2, Ethernet, etc. It offers advantages such as flexible and diverse networking methods and convenient and quick system setup.

[0091] The above solution is merely an illustration of a preferred example and is not limited thereto. When implementing this invention, appropriate substitutions and / or modifications can be made according to the user's needs.

[0092] The number of devices and processing scale described herein are for the purpose of simplifying the description of the invention. Applications, modifications, and variations of the invention will be readily apparent to those skilled in the art.

[0093] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. It can be applied to various fields suitable for the present invention. Other modifications can be readily made by those skilled in the art. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and examples shown and described herein.

Claims

1. An enhanced twisted-pair copper wire transmission system, characterized in that, This includes an FPGA and an analog front-end that works with it, the FPGA being configured to include: The framing / deframing unit is connected to the user's network equipment via the interface unit; A digital front-end unit connected to the analog front-end to implement PAM and CAP modulation and demodulation; It is a SOC subsystem that connects to the framing / deframing unit and the digital front-end unit respectively to complete link establishment and status management; The simulation front end is configured to include: A receiving unit and a transmitting unit that communicate with twisted-pair copper wires; The FPGA is also connected to a configuration chip for storing FPGA software code and a clock unit for providing clock signals. The analog front end is connected to a twisted-pair copper wire via a matching transformer; The SOC subsystem is configured to use an embedded kernel, and the UART serial port of the embedded kernel is a management channel under SDSL and SHDSL technologies. The SOC subsystem of the enhanced twisted-pair copper wire transmission system achieves communication channel switching under SDSL and SHDSL technologies through the management of configuration parameters and the functional modules corresponding to the digital front-end multiplexing algorithm, thereby completing data communication or handshake link establishment. When switching communication channels, the management of configuration parameters includes: Based on the choice between SDSL and SHDSL technologies, the corresponding parameters of the functional modules are adjusted through the digital headend; Different transmission powers are preset for SDSL and SHDSL technologies respectively. The FPGA matches the corresponding transmission power based on the selection of SDSL and SHDSL technologies, thereby completing the adaptation of transmission power when switching communication channels. The digital front-end is configured to employ a DSP computing unit, and the multiplexing process of the equalizer module, interpolation filtering, and noise shaping filtering module in the digital front-end multiplexing algorithm is configured to include: S1. The embedded kernel selects and controls the initial coefficients of the filter configuration of the DSP computing unit according to different modes and data rates. S2, the DSP computing unit starts the error calculation program to perform iterative calculations based on the input data stream; S3. When the error reaches the specified value, the DSP calculation unit writes the converged filter parameters into the filter parameter configuration interface to complete the parameter configuration under different technical systems and realize the functional reuse of functional modules under different systems.

2. The enhanced twisted-pair copper wire transmission system as described in claim 1, characterized in that, The receiving unit is configured to include: A receiving amplifier circuit connected to the transformer side; The receiving amplifier circuit is connected to convert the amplified signal into an analog-to-digital converter (ADC) in the digital front-end unit. The transmitting unit is configured to include: Digital-to-analog converter (DAC) connected to the digital front-end unit; The signal received from the DAC is sent to the line drive module on the transformer side; Among them, a matching low-pass filter is provided between the amplifier circuit and the ADC, and between the DAC and the line drive module; A resistor is provided between the line drive module and the transformer, and the output terminal of the line drive module is connected to the receiving amplifier circuit.

3. The enhanced twisted-pair copper wire transmission system as described in claim 2, characterized in that, The signal bandwidth of the ADC, DAC, and low-pass filter is configured to be greater than the maximum analog bandwidth required for 20480 kbit / s, and the signal-to-noise ratio of the devices is greater than the signal-to-noise ratio required for MTC-PAM. The transmission power of the analog front end is ≤14.5dBm.

4. The enhanced twisted-pair copper wire transmission system as described in claim 1, characterized in that, The functional modules of the reused digital front-end algorithm are configured to include: Common scrambling / descrambling modules, encoding / decoding modules, precoding modules, echo cancellation modules, equalizer modules, interpolation filtering, and noise shaping filtering modules used in SDSL and SHDSL technologies; In addition, SDSL has its own unique IQ filter, which enables the reuse of functional modules under SDSL and SHDSL technologies through a relatively fixed structure.

5. A method for implementing the enhanced twisted-pair copper wire transmission system as described in claim 1, characterized in that, The process of establishing a link and communication between user A and user B through an enhanced twisted-pair copper wire transmission system is configured to include: Step 1: The FPGA on user A side receives the service data sent by user A through the interface unit, and frames, encodes and modulates the received signal before sending it to the analog front-end on the local side. Step 2: User A's analog front-end performs digital-to-analog conversion, shaping and filtering, and signal amplification on the signal received from the FPGA before sending it into the twisted-pair copper wire. Step 3: User B's analog front end receives messages from the twisted pair copper wire. The local echo signal is canceled and the received signal is amplified through the receiving amplifier circuit to amplify the amplitude of the received signal to the range of the ADC's receiving level. After the low-pass filter filters out the sampling clock outside the first Nyquist interval of the received signal, the received signal is converted from digital to analog by the ADC and then sent to User B's FPGA. Step four: User B's FPGA demodulates and deframes the received signal and then sends it back to User B. Step 5: User B sends its own service data to User A simultaneously using the same method, and User A receives the service data. Step Six: Before User A and User B send and receive service data, the SOC subsystem of the enhanced twisted-pair copper wire transmission system switches the communication channels under SDSL and SHDSL technologies through the management of configuration parameters and the functional modules corresponding to the digital front-end multiplexing algorithm, and completes data communication or handshake link establishment through Steps One to Five.

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