Data storage and verification method, device, equipment and storage medium

Abstract

The present application discloses a data storage verification method, device, equipment and storage medium, which relates to the field of data storage verification technology, including: performing a first round of verification on the data processed by the central processing unit through an external disk array unit to determine the abnormal data segment with error code; the external disk array unit is cascaded with the central processing unit through a SAS card; the abnormal data segment sent by the external disk array unit is received through a solid-state hard disk, and a second round of verification is performed on the abnormal data segment through the solid-state hard disk to locate the error code address in the abnormal data segment; the solid-state hard disk is directly connected to the central processing unit through an independent disk redundant array unit; the abnormal data segment is adjusted based on the error code address; and the abnormal data segment is replaced with the adjusted data segment. The present application uses a storage method of data interaction between the external disk array unit and the directly connected solid-state hard disk, so that the data verification and storage process are carried out simultaneously, thereby improving the efficiency of data storage and the accuracy of stored data.

Description

Technical Field

[0001] The present invention relates to the field of data storage verification technology, and in particular to a data storage verification method, device, equipment and storage medium. Background Art

[0002] The current era of big data places higher demands on the reliability of storage arrays, particularly on the accuracy of data storage in storage systems. As data volumes have increased exponentially, storage systems have gradually upgraded their data transmission capabilities to PCIE 5.0, significantly increasing storage speeds. Furthermore, storage space has evolved from integrated disk-controller systems to a large number of shared external disk array units for data storage. This increase in data transmission speed and data storage capacity has put pressure on the accuracy of the data transmission process. With increased transmission rates, the likelihood of bit errors during data storage increases, and as the total amount of stored data increases, the number of bit errors also increases. The current system's overall verification algorithm struggles to ensure verification accuracy, and the separation of verification from the storage process makes it difficult to increase the data verification rate. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a data storage verification method, device, equipment and storage medium, which can enable data verification and storage to be performed simultaneously, thereby improving the efficiency of data storage and ensuring the accuracy of stored data. The specific scheme is as follows:

[0004] In a first aspect, the present application discloses a data storage verification method, comprising:

[0005] Performing a first round of verification on the data processed by the central processing unit through an external disk array unit to determine abnormal data segments with bit errors; the external disk array unit is cascaded with the central processing unit through a SAS card;

[0006] The abnormal data segment sent by the external disk array unit is received by the solid-state disk unit, and the abnormal data segment is subjected to a second round of verification by the solid-state disk unit to locate an error address in the abnormal data segment; the solid-state disk unit is directly connected to the central processing unit through an independent disk redundant array unit;

[0007] Adjusting the abnormal data segment based on the error address by the solid state hard disk unit to obtain an adjusted data segment;

[0008] The abnormal data segment in the external disk array unit is replaced by the adjusted data segment.

[0009] Optionally, performing a first round of verification on the data processed by the central processing unit by the external disk array unit to determine abnormal data segments with bit errors includes:

[0010] The improved parity check algorithm is used by the external disk array unit to perform a first round of check on the data processed by the central processor to determine abnormal data segments with bit errors.

[0011] Optionally, performing a second round of verification on the abnormal data segment by the solid state drive unit to locate an error address in the abnormal data segment includes:

[0012] Extracting the start code and the end code of the abnormal data segment through the solid state hard disk unit;

[0013] Determine a corresponding normal data segment according to the start code and the end code received from the solid state drive unit;

[0014] sending the normal data segment to the solid state drive unit via a high-speed serial computer expansion bus switching device as a transmission medium;

[0015] The abnormal data segment is compared with the normal data segment one by one by the solid state hard disk unit to locate the error address and error value in the abnormal data segment.

[0016] Optionally, the sending of the normal data segment to the solid-state hard disk unit via a high-speed serial computer expansion bus switching device as a transmission medium includes:

[0017] The normal data segments are sent multiple times to the solid state hard disk unit via a high-speed serial computer expansion bus switching device as a transmission medium.

[0018] Optionally, after comparing the abnormal data segment with the normal data segment one by one by the solid state drive unit to locate the error address and error value in the abnormal data segment, the method further includes:

[0019] The error address and the error value fed back by the solid state hard disk unit are received through the high-speed serial computer expansion bus switching device.

[0020] Optionally, adjusting the abnormal data segment based on the error address by the solid state drive unit to obtain an adjusted data segment includes:

[0021] Determining a correct code value from the normal data segment according to the error code address;

[0022] Sending the correct code value and the error code address to the solid state drive;

[0023] The solid state drive uses the correct code value to adjust the abnormal data segment to obtain an adjusted data segment.

[0024] Optionally, replacing the abnormal data segment in the external disk array unit with the adjusted data segment includes:

[0025] The adjusted data segments are sent to the external disk array unit through the high-speed serial computer expansion bus switching device, and the adjusted data segments are used to replace the corresponding abnormal data segments in the external disk array unit.

[0026] In a second aspect, the present application discloses a data storage verification device, comprising:

[0027] A first verification module is configured to perform a first round of verification on the data processed by the central processing unit through an external disk array unit to determine abnormal data segments with bit errors; the external disk array unit is cascaded with the central processing unit through a SAS card;

[0028] a second verification module, configured to receive the abnormal data segment sent by the external disk array unit through a solid-state disk unit, and perform a second round of verification on the abnormal data segment through the solid-state disk unit to locate an error address in the abnormal data segment; the solid-state disk unit is directly connected to the central processing unit through an independent disk redundant array unit;

[0029] a data segment adjustment module, configured to adjust the abnormal data segment based on the error address by the solid state drive unit to obtain an adjusted data segment;

[0030] A data segment replacement module is configured to replace the abnormal data segment in the external disk array unit with the adjusted data segment.

[0031] In a third aspect, the present application discloses an electronic device, comprising:

[0032] Memory, used to store computer programs;

[0033] The processor is used to execute the computer program to implement the steps of the aforementioned disclosed data storage verification method.

[0034] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the aforementioned disclosed data storage verification method are implemented.

[0035] It can be seen that the present application provides a data storage verification method, including: performing a first round of verification on the data processed by the central processing unit through an external disk array unit to determine abnormal data segments with bit errors; the external disk array unit is cascaded with the central processing unit through a SAS card; receiving the abnormal data segments sent by the external disk array unit through a solid-state hard disk unit, and performing a second round of verification on the abnormal data segments through the solid-state hard disk unit to locate the bit error addresses in the abnormal data segments; the solid-state hard disk unit is directly connected to the central processing unit through an independent disk redundant array unit; adjusting the abnormal data segments based on the bit error addresses through the solid-state hard disk unit to obtain adjusted data segments; and replacing the abnormal data segments in the external disk array unit with the adjusted data segments. It can be seen from this that the present application performs a first round of verification through the external disk array unit to determine the abnormal data segment with bit errors, and performs a second round of verification on the abnormal data segment through the solid-state hard disk unit to locate the bit error address in the abnormal data segment. This data verification method is fast and efficient, that is, the storage method of data interaction between the external disk array unit and the directly connected solid-state hard disk can enable the data verification and storage processes to be carried out simultaneously, thereby improving the efficiency of data storage, and can improve the accuracy of stored data without affecting the data storage speed and the space occupancy rate of the external disk array unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0037] Figure 1 A schematic diagram of the hardware topology of a data interactive storage disclosed in this application;

[0038] Figure 2 This is a flow chart of a data storage verification method disclosed in this application;

[0039] Figure 3 This is an overall flow chart of a data dynamic interactive storage verification algorithm disclosed in this application;

[0040] Figure 4 This is a flow chart of a second round verification method disclosed in this application;

[0041] Figure 5 This is a flow chart of a specific data storage verification method disclosed in this application;

[0042] Figure 6A schematic diagram of an improved parity check data structure disclosed in this application;

[0043] Figure 7 This is a structural diagram of a data storage and verification device disclosed in this application;

[0044] Figure 8 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0045] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0046] Currently, in the era of big data, higher requirements are placed on the reliability of storage arrays, especially on the accuracy of data storage in storage systems. As the amount of data increases exponentially, the data transmission of storage systems has gradually been upgraded to PCIE5.0, the storage speed has been greatly improved, and the storage space has also been upgraded from the previous integrated disk controller to a large number of external shared external disk array units for data storage. This upgrade in data transmission rate and data storage capacity puts pressure on the accuracy of the data transmission process. As the transmission rate increases, the possibility of bit error rates occurring during data storage increases, and as the total capacity of stored data increases, the number of bit errors will also increase. The current system's overall verification algorithm is difficult to guarantee the accuracy of verification, and the verification is separated from the storage process, making it difficult to improve the data verification rate. To this end, the present application provides a new data storage verification scheme that enables data verification and storage processes to be performed simultaneously, thereby improving the efficiency of data storage and ensuring the accuracy of stored data.

[0047] It should be noted that the hardware topology structure of data interactive storage corresponding to the data storage verification method disclosed in this application is as follows: Figure 1As shown, the hardware topology of the data interactive storage uses PCIE SWITCH (i.e., a high-speed serial computer expansion bus switch) as the transmission medium, directly cascades the front-end CPU (Central Processing Unit), directly connects to the back-end SSD (Solid State Drives) through a RAID (Redundant Array of Independent Disks) card, and cascades the JBOD (Just a Bunch Of Disks) expansion cabinet storage unit through a SAS (Serial Attached SCSI) card, wherein the back-end SSD is used for data verification and the JBOD expansion cabinet storage unit is used for data storage, so that the data verification and storage processes are carried out simultaneously, thereby improving the efficiency of data storage. In addition, the hardware topology of the data interactive storage can be used for, but is not limited to, servers, military computers, and other devices that contain storage media and require data verification.

[0048] The embodiment of the present invention discloses a data storage verification method, see Figure 2 As shown, the method includes:

[0049] Step S11: performing a first round of verification on the data processed by the central processing unit through an external disk array unit to determine abnormal data segments with bit errors; the external disk array unit is cascaded with the central processing unit through a SAS card.

[0050] In this embodiment, a first round of verification is performed on the data processed by the central processing unit through an external disk array unit to determine abnormal data segments with bit errors; the external disk array unit is cascaded with the central processing unit via a SAS card. It can be understood that after the data is processed by the controller (i.e., the central processing unit), the processed data is stored in the back-end cascaded JBOD unit through the PCIE SWITCH bridge chip. The first round of verification is performed in the JBOD unit. The first round of verification is mainly used to locate the problem, that is, the first round of verification is only used to locate whether there are bit errors in the data, so it does not exist in large-scale computing scenarios.

[0051] Step S12: receiving the abnormal data segment sent by the external disk array unit through the solid-state hard disk unit, and performing a second round of verification on the abnormal data segment through the solid-state hard disk unit to locate the error address in the abnormal data segment; the solid-state hard disk unit is directly connected to the central processing unit through an independent disk redundant array unit.

[0052] In this embodiment, after the data processed by the central processing unit is subjected to a first round of verification by the external disk array unit to determine the abnormal data segment with a code error, the abnormal data segment sent by the external disk array unit is received by the solid state disk unit, and the abnormal data segment is subjected to a second round of verification by the solid state disk unit to locate the code error address in the abnormal data segment. It can be understood that when the first round of verification is carried out in the JBOD unit to determine the abnormal data segment with a code error, the abnormal data segment is simultaneously stored in the back-end SSD directly connected to the central processing unit through the RAID card, so that the storage space of the JBOD unit is not occupied. The JBOD unit is used for final data storage. The JBOD unit and the back-end SSD together form a new RAID verification disk array structure. That is, the data stored in the back-end SSD directly connected to the controller (i.e., the central processing unit) is the abnormal data end with a code error detected during the first round of verification in the JBOD unit. Since the back-end SSD is directly connected to the controller through the RAID card, it has a stronger RAID verification calculation function. That is, the back-end SSD is directly connected to the controller through the RAID card. The back-end SSD disk can provide sufficient computing power and storage space for data verification. That is, the second round of verification relies on the powerful computing power and storage space of the back-end SSD unit directly connected to the CPU through the RAID card. The abnormal data segment is temporarily stored in the back-end SSD directly connected to the central processing unit. Then, the error is located through the corresponding algorithm, and a second round of verification is performed in the back-end SSD. The purpose of the second round of verification is mainly to locate and correct the error problem, and to accurately correct the transmitted data while ensuring that the data correction rate reaches 100%. No other errors are introduced during the correction process. That is, the position of the error is specifically located, and the modified data is retransmitted to the JBOD unit. After the second round of verification is completed and the modified data is successfully transmitted to the JBOD unit, it means that the data exchange verification and storage process is completed. Through the data exchange storage method between the JBOD unit and the back-end SSD, the accuracy of the stored data can be improved without affecting the data storage speed and the space occupancy rate of the JBOD unit.

[0053] In this embodiment, the second round of verification of the abnormal data segment by the solid-state hard disk unit to locate the error address in the abnormal data segment can specifically include: extracting the start code and the end code of the abnormal data segment by the solid-state hard disk unit; determining the corresponding normal data segment based on the start code and the end code received as feedback from the solid-state hard disk unit; sending the normal data segment to the solid-state hard disk unit through a high-speed serial computer expansion bus switching device as a transmission medium; and comparing the abnormal data segment with the normal data segment one by one by the solid-state hard disk unit to locate the error address and error value in the abnormal data segment. It can be understood that the second round of verification starts after the abnormal data end of the first round of verification is transmitted to the back-end SSD, that is, the start code and the end code of the abnormal data end are first extracted, and after the extraction of the start code and the end code is completed, the start code and the end code are fed back to the PCIE SWITCH unit and the operating system. After reading the start code and the end code, the operating system re-sends the normal data segment corresponding to the start code and the end code to the back-end SSD through the PCIE SWITCH, and sends it multiple times, that is, the normal data segment is sent to the solid state drive unit multiple times through the high-speed serial computer expansion bus switching device as the transmission medium, so as to avoid problems during the sending process that cause the solid state drive unit to fail to receive the normal data segment. Then, the abnormal data segment is compared one by one with the normal data segment sent by the operating system to locate the error address, and the error adjustment is performed according to the normal data segment.

[0054] In this embodiment, after the abnormal data segment is compared with the normal data segment one by one by the solid-state drive unit to locate the error address and error value in the abnormal data segment, the process further includes: receiving the error address and error value fed back by the solid-state drive unit through the high-speed serial computer expansion bus switching device. In other words, a problem that may arise during the comparison process is that the code used for comparison has an error. Therefore, after the comparison is completed, the different code values ​​and the error address between the abnormal data segment and the normal data segment are fed back to the operating system again through the PCIE SWITCH, that is, the error address and error value fed back by the solid-state drive unit are received through the high-speed serial computer expansion bus switching device, and the operating system identifies the normal data segment based on the error address, and then resends the correct code value and the error address to the back-end SSD.

[0055] Step S13: adjusting the abnormal data segment based on the error address by the solid state hard disk unit to obtain an adjusted data segment.

[0056] In this embodiment, the solid-state hard disk unit adjusts the abnormal data segment based on the error code address to obtain an adjusted data segment. Specifically, the correct code value is determined from the normal data segment according to the error code address; the correct code value and the error code address are sent to the solid-state hard disk; and the solid-state hard disk uses the correct code value to adjust the abnormal data segment to obtain an adjusted data segment. It can be understood that when the back-end SSD receives the correct code value, it uses the correct code value to adjust the abnormal data segment to obtain an adjusted data segment. In other words, the operating system identifies the normal data segment according to the error code address, and then resends the correct code value and the error code address to the back-end SSD, and the back-end SSD uses the correct code value to adjust the abnormal data segment to obtain an adjusted data segment.

[0057] Step S14: using the adjusted data segment to replace the abnormal data segment in the external disk array unit.

[0058] In this embodiment, after the SSD unit completes the adjustment of the abnormal data segment, the adjusted data segment is sent to the external disk array unit via the high-speed serial computer expansion bus switch device, and the adjusted data segment replaces the corresponding abnormal data segment in the external disk array unit. In other words, the adjusted data segment is resent by the SSD unit to the PCIE SWITCH unit, and then sent to the JBOD unit via the PCIE link, and the adjusted data segment replaces the abnormal data segment in the external disk array unit.

[0059] It can be seen that in the embodiment of the present application, a first round of verification is performed by the external disk array unit to determine the abnormal data segment with bit errors, and a second round of verification is performed on the abnormal data segment by the solid-state hard disk unit to locate the bit error address in the abnormal data segment. This data verification method is fast and efficient, that is, the storage method of data interaction between the external disk array unit and the directly connected solid-state hard disk can enable the data verification and storage processes to be carried out simultaneously, thereby improving the efficiency of data storage and improving the accuracy of stored data without affecting the data storage speed and the space occupancy rate of the external disk array unit.

[0060] For example, Figure 3 As shown, data is transmitted to JBOD, a first round of verification is performed in JBOD to determine abnormal data segments, the abnormal data segments of the first round of verification are transmitted to the back-end SSD, a second round of verification is performed in the back-end SSD to locate the error position, and the abnormal data segments are modified. After the modification is completed, the modified data segments are uploaded to JBOD, wherein the second round of verification performed in the back-end SSD is as shown. Figure 4As shown, the back-end SSD receives the abnormal data segment of the first round of verification, preferentially extracts the start code and the end code of the abnormal data end, and after completing the extraction of the start code and the end code, feeds back the start code and the end code to the PCIE SWITCH unit and the operating system. After reading the start code and the end code, the operating system resends the normal data segment corresponding to the start code and the end code to the back-end SSD through the PCIE SWITCH, and sends it multiple times, thereby avoiding the situation where problems occur during the sending process and the solid-state drive unit does not receive the normal data segment. The abnormal data segment is then compared one by one with the normal data segment sent by the operating system to locate the error address and the error value, and the error address and the error value are fed back to the operating system. The operating system identifies the normal data segment according to the error address and the error value, and then resends the correct code value and the error address to the back-end SSD. The back-end SSD adjusts the abnormal data segment according to the correct code value and the error address. In other words, the technical solution for data storage verification in this application, through the combination of a fully digital control algorithm and the system hardware topology, abandons the traditional storage method of separating the data storage and verification processes. The hardware topology reserves a dedicated data verification space for storage, enabling data verification and storage processes to be performed simultaneously, thereby improving the reliability of data storage. The first round of monitoring algorithms is performed in the JBOD, and the second round of algorithms is performed in the directly connected SSD to solve the problem of error location. The storage method of data interaction between the JBOD and the directly connected SSD disks can improve the accuracy of stored data without affecting the data storage speed or the JBOD unit space occupancy rate.

[0061] See also Figure 5 As shown, the embodiment of the present invention discloses a specific data storage verification method. Compared with the previous embodiment, this embodiment further illustrates and optimizes the technical solution.

[0062] Step S21: performing a first round of check on the data processed by the central processing unit using an improved parity check algorithm through an external disk array unit to determine abnormal data segments with bit errors; the external disk array unit is cascaded with the central processing unit through a SAS card.

[0063] In this embodiment, the data is processed by the central processing unit. After the processing is completed, the processed data is stored in the back-end cascaded JBOD unit through the PCIE Switch bridge chip, and the first round of verification is performed in the JBOD unit. The first round of verification is mainly used to locate the problem, that is, the first round of verification is only used to locate whether there are bit errors in the data, so there is no large-scale computing scenario, and an improved parity check algorithm is used in the first round of verification. The improved parity check algorithm is used to diagnose whether there are bit errors in the processed data.

[0064] It should be noted that the improved parity check algorithm is based on error test data, and by adding a check code to ensure that any error situation is diagnosed, without increasing the computing power of the JBOD unit. After the check is completed, the abnormal data segment with the problem is sent to the back-end SSD unit for error location. In other words, the original parity check can diagnose single-bit errors or odd-bit errors, which account for 80% of the error rate, but cannot diagnose even-bit errors. The JBOD unit is mainly based on ordinary SAS SSD or HDD (Hard Disk Drive, mechanical hard disk), and cannot use complex RAID check algorithms such as Hamming check and CRC (Cyclic Redundancy Check) in RAID. In this application, the parity check algorithm and the overall data transmission process are improved, and the complex calculations are left to the back-end SSD for special verification and error location. The improved parity check algorithm is used in the JBOD unit to diagnose the problem without increasing the difficulty of calculation. The improved parity check algorithm is designed based on the actual bit error rate during binary transmission. A bit error rate tester is used to test the bit errors that occur in the PCIE link (i.e., a high-speed serial computer expansion bus) in actual work. During the test, the number of tests is adjusted according to the number of test channels. For the x1 transmission channel, three bit error tests are sufficient. For the x2 transmission channel, the number of tests is doubled, and so on to the x16 transmission channel. After the test is completed, the result with the highest bit error rate is selected as the basis for parity check improvement. Figure 6As shown, according to the bit error rate, the first check bit is added on the basis of the original parity check bit. To solve the problem that the parity check cannot check even-numbered bit errors, the original check bit is a parity check of the number of 1s in the binary sequence, and the newly added bit is a parity check of the number of two 1s in the binary sequence. The next added bit is a parity check of the number of four 1s in the binary sequence, and so on. That is, the newly added N bits are the parity check results of the number of 2N-power 1s in the binary sequence. The value of the N bits needs to be based on The error rate is determined by the test results of the bit error tester. The number of N bits must be greater than or equal to the number of bit errors in the tested binary data, and is generally an integer greater than the number of bit errors. For example, if the sender transmits 1 million bits (106 bits of data) and detects 243 bit errors at the receiver, there will be 2.43 bit errors for 10,000 bits of data, with a bit error rate of 2.43 per 10,000 bits. In this case, setting N to 3 before the 10,000 bits of data, that is, adding a 3-bit check code, ensures that all bit errors are covered. The improved parity check algorithm is based on the error test data and uses the added check code to ensure that any bit error is diagnosed without increasing the computing power of the JBOD unit. After the diagnosis is completed, the problematic abnormal data segment is sent to the back-end SSD to locate the bit error.

[0065] Step S22: receiving the abnormal data segment sent by the external disk array unit through the solid-state hard disk unit, and performing a second round of verification on the abnormal data segment through the solid-state hard disk unit to locate the error address in the abnormal data segment; the solid-state hard disk unit is directly connected to the central processing unit through an independent disk redundant array unit.

[0066] Step S23: adjusting the abnormal data segment based on the error address by the solid state drive unit to obtain an adjusted data segment.

[0067] Step S24: using the adjusted data segment to replace the abnormal data segment in the external disk array unit.

[0068] For the specific contents of the above steps S22 to S24, reference may be made to the corresponding contents disclosed in the above embodiments, which will not be repeated here.

[0069] It can be seen that in the embodiment of the present application, a first round of verification is performed by the external disk array unit to determine the abnormal data segment with bit errors, and a second round of verification is performed on the abnormal data segment by the solid-state hard disk unit to locate the bit error address in the abnormal data segment. This data verification method is fast and efficient, that is, the storage method of data interaction between the external disk array unit and the directly connected solid-state hard disk can enable the data verification and storage processes to be carried out simultaneously, thereby improving the efficiency of data storage and improving the accuracy of stored data without affecting the data storage speed and the space occupancy rate of the external disk array unit.

[0070] Accordingly, the present application also discloses a data storage verification device, see Figure 7 As shown, the device includes:

[0071] A first verification module 11 is configured to perform a first round of verification on the data processed by the central processing unit through an external disk array unit to determine abnormal data segments with bit errors; the external disk array unit is cascaded with the central processing unit through a SAS card;

[0072] a second verification module 12, configured to receive the abnormal data segment sent by the external disk array unit through a solid-state disk unit, and perform a second round of verification on the abnormal data segment through the solid-state disk unit to locate an error address in the abnormal data segment; the solid-state disk unit is directly connected to the central processing unit through an independent disk redundant array unit;

[0073] A data segment adjustment module 13, configured to adjust the abnormal data segment based on the error address by the solid state drive unit to obtain an adjusted data segment;

[0074] The data segment replacement module 14 is configured to replace the abnormal data segment in the external disk array unit with the adjusted data segment.

[0075] As can be seen from the above, in the embodiment of the present application, a first round of verification is performed by the external disk array unit to determine the abnormal data segment with bit errors, and a second round of verification is performed on the abnormal data segment by the solid-state hard disk unit to locate the bit error address in the abnormal data segment. This data verification method is fast and efficient, that is, the storage method of data interaction between the external disk array unit and the directly connected solid-state hard disk can enable the data verification and storage processes to be carried out simultaneously, thereby improving the efficiency of data storage and improving the accuracy of stored data without affecting the data storage speed and the space occupancy rate of the external disk array unit.

[0076] In some specific embodiments, the first verification module 11 may specifically include:

[0077] The abnormality check module is used to perform a first round of check on the data processed by the central processing unit using an improved parity check algorithm through an external disk array unit to determine abnormal data segments with bit errors.

[0078] In some specific embodiments, the second verification module 12 may specifically include:

[0079] An extraction module, configured to extract a start code and an end code of the abnormal data segment through the solid state hard disk unit;

[0080] a normal data segment determining module, configured to determine a corresponding normal data segment according to the start code and the end code received as feedback from the solid state drive unit;

[0081] a first sending module, configured to send the normal data segment to the solid state hard disk unit via a high-speed serial computer expansion bus switching device as a transmission medium;

[0082] The comparison module is used to compare the abnormal data segment with the normal data segment one by one through the solid state disk unit to locate the error address and error value in the abnormal data segment.

[0083] In some specific embodiments, the first sending module may specifically include:

[0084] The sending unit is used to send the normal data segment to the solid state hard disk unit multiple times through a high-speed serial computer expansion bus switching device as a transmission medium.

[0085] In some specific embodiments, the data storage verification device may specifically include:

[0086] A receiving module is used to receive the error address and the error value fed back by the solid state hard disk unit through the high-speed serial computer expansion bus switching device.

[0087] In some specific embodiments, the data segment adjustment module 13 may specifically include:

[0088] a correct code value determining unit, configured to determine a correct code value from the normal data segment according to the error code address;

[0089] A code value sending unit, configured to send the correct code value and the error code address to the solid state drive;

[0090] A data segment adjustment unit is configured to adjust the abnormal data segment using the correct code value via the solid state drive to obtain an adjusted data segment.

[0091] In some specific embodiments, the data segment replacement module 14 may specifically include:

[0092] The second sending module is used to send the adjusted data segment to the external disk array unit through the high-speed serial computer expansion bus switching device, and use the adjusted data segment to replace the corresponding abnormal data segment in the external disk array unit.

[0093] Furthermore, an embodiment of the present application also provides an electronic device. Figure 8 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram should not be considered as any limitation to the scope of application of the present application.

[0094] Figure 8 This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps of the data storage verification method disclosed in any of the aforementioned embodiments. Furthermore, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0095] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device. The communication protocol it follows is any communication protocol that can be applied to the technical solution of this application and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world. Its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0096] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0097] The operating system 221 is used to manage and control the hardware devices and computer program 222 on the electronic device 20, and can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of implementing the data storage verification method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program capable of implementing other specific tasks.

[0098] Furthermore, an embodiment of the present application also discloses a computer-readable storage medium, in which a computer program is stored. When the computer program is loaded and executed by a processor, the steps of the data storage verification method disclosed in any of the aforementioned embodiments are implemented.

[0099] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0100] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0101] The above is a detailed introduction to a data storage verification method, device, equipment and storage medium provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A data storage verification method, characterized in that: include: Performing a first round of verification on the data processed by the central processor through an external disk array unit to determine abnormal data segments with bit errors; The external disk array unit is cascaded with the central processing unit via a SAS card; The abnormal data segment sent by the external disk array unit is received by the solid-state disk unit, and the abnormal data segment is subjected to a second round of verification by the solid-state disk unit to locate an error address in the abnormal data segment; the solid-state disk unit is directly connected to the central processing unit through an independent disk redundant array unit; Adjusting the abnormal data segment based on the error address by the solid state hard disk unit to obtain an adjusted data segment; The abnormal data segment in the external disk array unit is replaced by the adjusted data segment.

2. The data storage verification method according to claim 1, characterized in that: The first round of verification of the data processed by the central processing unit by the external disk array unit to determine abnormal data segments with bit errors includes: The improved parity check algorithm is used by the external disk array unit to perform a first round of check on the data processed by the central processor to determine abnormal data segments with bit errors.

3. The data storage verification method according to claim 1, wherein: The performing a second round of verification on the abnormal data segment by the solid state hard disk unit to locate an error address in the abnormal data segment includes: Extracting the start code and the end code of the abnormal data segment through the solid state hard disk unit; Determine a corresponding normal data segment according to the start code and the end code received from the solid state drive unit; sending the normal data segment to the solid state drive unit via a high-speed serial computer expansion bus switching device as a transmission medium; The abnormal data segment is compared with the normal data segment one by one by the solid state hard disk unit to locate the error address and error value in the abnormal data segment.

4. The data storage verification method according to claim 3, characterized in that: The method of sending the normal data segment to the solid state drive unit via a high-speed serial computer expansion bus switching device as a transmission medium includes: The normal data segments are sent multiple times to the solid state hard disk unit via a high-speed serial computer expansion bus switching device as a transmission medium.

5. The data storage verification method according to claim 3, characterized in that: After comparing the abnormal data segments with the normal data segments one by one by the solid state hard disk unit to locate the error addresses and error values ​​in the abnormal data segments, the method further includes: The error address and the error value fed back by the solid state hard disk unit are received through the high-speed serial computer expansion bus switching device.

6. The data storage verification method according to any one of claims 3 to 5, characterized in that: The adjusting the abnormal data segment based on the error address by the solid state hard disk unit to obtain an adjusted data segment includes: Determining a correct code value from the normal data segment according to the error code address; Sending the correct code value and the error code address to the solid state drive unit; The solid state disk unit adjusts the abnormal data segment using the correct code value to obtain an adjusted data segment.

7. The data storage verification method according to claim 6, characterized in that: The replacing the abnormal data segment in the external disk array unit with the adjusted data segment includes: The adjusted data segments are sent to the external disk array unit through the high-speed serial computer expansion bus switching device, and the adjusted data segments are used to replace the corresponding abnormal data segments in the external disk array unit.

8. A data storage verification device, characterized in that: include: A first verification module is used to perform a first round of verification on the data processed by the central processing unit through an external disk array unit to determine abnormal data segments with bit errors; The external disk array unit is cascaded with the central processing unit via a SAS card; a second verification module, configured to receive the abnormal data segment sent by the external disk array unit through a solid-state disk unit, and perform a second round of verification on the abnormal data segment through the solid-state disk unit to locate an error address in the abnormal data segment; the solid-state disk unit is directly connected to the central processing unit through an independent disk redundant array unit; a data segment adjustment module, configured to adjust the abnormal data segment based on the error address by the solid state drive unit to obtain an adjusted data segment; A data segment replacement module is configured to replace the abnormal data segment in the external disk array unit with the adjusted data segment.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the steps of the data storage verification method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that Used to store computer programs; wherein, when the computer program is executed by a processor, the steps of the data storage verification method according to any one of claims 1 to 7 are implemented.

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