Capacitor assembly and method for manufacturing capacitor assembly

Abstract

This disclosure provides a capacitor assembly and a method for manufacturing the capacitor assembly. The capacitor assembly includes: a plurality of conductive nanowires spaced apart from each other; a first connecting conductive layer and a second connecting conductive layer respectively disposed on one end and the other end of the plurality of conductive nanowires and connected to the plurality of conductive nanowires; a conductive body surrounding the plurality of conductive nanowires; and a dielectric film disposed between the plurality of conductive nanowires and each of the first connecting conductive layer and the second connecting conductive layer and the conductive body.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2021-0143850, filed on October 26, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a capacitor assembly and a method for manufacturing the capacitor assembly. Background Technology

[0003] With the development of technology, the demand for surface-mount electronic components that achieve high capacitance while reducing size is constantly increasing.

[0004] As information technology (IT) products have become smaller and more multifunctional in recent years, the capacitors included in IT products also need to be smaller and have higher capacitance.

[0005] Based on this trend, a multilayer capacitor has been developed, which includes a dielectric layer with a high dielectric constant, as well as an internal electrode formed as an ultrathin dielectric layer.

[0006] However, due to the reduced breakdown voltage (BDV) caused by this thinning of the dielectric layer and the structural capacity limitations of the surface stacking method, the capacitance per unit volume of multilayer capacitors is currently approaching its limit.

[0007] To address this issue, a three-dimensional capacitor with high integration efficiency is provided, which includes electrode posts.

[0008] To achieve higher integration, three-dimensional capacitors are required to have an increased aspect ratio (or length / thickness) in their vertical pattern.

[0009] However, existing technologies have limitations in increasing the aspect ratio. This limitation is due to the capacitor manufacturing methods according to existing technologies.

[0010] Three-dimensional capacitors of the prior art can be manufactured using etching or growth methods.

[0011] In the case of etching methods among these approaches, because the capacitor has a higher aspect ratio, the time required to manufacture the capacitor can increase exponentially rather than linearly.

[0012] When the aspect ratio is greater than 30:1, it can generally be determined that the capacitor exceeds the threshold in terms of manufacturing time / cost.

[0013] In the case of growth methods, capacitors may encounter problems not only in terms of manufacturing time but also in terms of quality. The higher the aspect ratio of the capacitor, the more problems (such as pattern lifting, pattern misalignment, or pattern collapse) occur, thus significantly reducing its yield. Summary of the Invention

[0014] One aspect of this disclosure provides a capacitor assembly and a method for manufacturing the same, which overcomes the limitations of existing three-dimensional capacitors in achieving small size and high capacitance by including conductive nanowire bundles.

[0015] According to one aspect of this disclosure, a capacitor assembly may include: a plurality of conductive nanowires spaced apart from each other; a first connecting conductive layer and a second connecting conductive layer disposed on one end and the other end of the plurality of conductive nanowires, respectively, and connected to the plurality of conductive nanowires; a conductive body surrounding the plurality of conductive nanowires; and a dielectric film disposed between the plurality of conductive nanowires and each of the first connecting conductive layer and the second connecting conductive layer and the conductive body.

[0016] According to another aspect of this disclosure, a capacitor assembly may include: a first electrode portion including a plurality of conductive nanowires extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; a first connecting conductive layer and a second connecting conductive layer disposed on the upper and lower ends of the plurality of conductive nanowires, respectively, to connect the plurality of conductive nanowires to each other; a dielectric film surrounding a side surface of each of the plurality of conductive nanowires; and a second electrode portion filling the space between the plurality of conductive nanowires spaced apart between the first connecting conductive layer and the second connecting conductive layer, and surrounding a side surface of the dielectric film.

[0017] According to another aspect of this disclosure, a method for manufacturing a capacitor assembly includes: preparing a plurality of conductive nanowire bundles, each conductive nanowire being covered with glass; preparing a wafer by perpendicularly slicing the conductive nanowire bundles; forming a first connecting conductive layer and a second connecting conductive layer on one surface and another surface of the wafer, respectively, to connect the plurality of conductive nanowires to each other; forming a space in the wafer by removing the glass from the wafer; forming a dielectric film on the surface of each of the plurality of conductive nanowires and on the surface of each of the first connecting conductive layer and the second connecting conductive layer by depositing a dielectric in the wafer; and forming a second electrode portion by depositing a conductive material in the wafer.

[0018] According to another aspect of this disclosure, a capacitor assembly may include: a plurality of conductive nanowires spaced apart from each other; a dielectric film surrounding a side surface of each of the plurality of conductive nanowires; a barrier metal film surrounding the outer periphery of the dielectric film; a barrier dielectric film surrounding the outer periphery of the barrier metal film; a first connecting conductive layer and a second connecting conductive layer disposed at one end and the other end of the plurality of conductive nanowires, respectively, and connected to the plurality of conductive nanowires; and a conductive body filling the spaces between the plurality of conductive nanowires surrounded by the dielectric film, the barrier metal film, and the barrier dielectric film. Attached Figure Description

[0019] The above and other aspects, features and advantages of this disclosure will be more clearly understood by taking into account the accompanying drawings and the following detailed description, in which:

[0020] Figure 1 This is a schematic diagram illustrating a second connecting conductive layer, conductive nanowires, and dielectric film included in a capacitor assembly according to an exemplary embodiment of the present disclosure.

[0021] Figure 2 This is a schematic diagram showing a cross-section of a capacitor assembly according to an exemplary embodiment of the present disclosure;

[0022] Figure 3 It is along Figure 2 A cross-sectional view taken from line I-I';

[0023] Figures 4 to 7 Each is a diagram schematically illustrating the arrangement of conductive nanowire bundles in a capacitor assembly according to an exemplary embodiment of the present disclosure.

[0024] Figure 8 This is a partial cross-sectional view schematically illustrating a capacitor assembly according to another exemplary embodiment of the present disclosure;

[0025] Figures 9A to 11B These are diagrams illustrating the degrees of freedom in designing a capacitor assembly achieved through the manufacturing method of the capacitor assembly according to this disclosure; and

[0026] Figures 12 to 22 This is a diagram illustrating the manufacturing process of a capacitor assembly according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0027] In the following, exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0028] The X, Y, and Z directions shown in the figure indicate the length, width, and thickness directions of the capacitor assembly, respectively.

[0029] Figure 1This is a schematic diagram illustrating a second connecting conductive layer, conductive nanowires, and dielectric film included in a capacitor assembly according to an exemplary embodiment of the present disclosure. Figure 2 This is a schematic diagram showing a cross-section of a capacitor assembly according to an exemplary embodiment of the present disclosure; Figure 3 It is along Figure 2 A cross-sectional view taken from line I-I'; Figures 4 to 7 Each is a diagram schematically illustrating the arrangement of conductive nanowire bundles in a capacitor assembly according to an exemplary embodiment of the present disclosure.

[0030] Reference Figures 1 to 4 According to this embodiment, the capacitor assembly 1 may include a plurality of conductive nanowires 120 serving as a first electrode portion, a first connecting conductive layer 121 and a second connecting conductive layer 122, a dielectric film 110, a conductive body 130 serving as a second electrode portion, a first terminal 141 and a second terminal 142, and a protective layer 150.

[0031] The first electrode portion may include a plurality of conductive nanowires 120. Each of the plurality of conductive nanowires 120 may extend in the Z direction and is configured to be spaced apart from each other in the X direction and / or Y direction perpendicular to the Z direction. Furthermore, hereinafter, the first electrode portion is indicated as a plurality of conductive nanowires 120.

[0032] Multiple conductive nanowires 120 can be physically and electrically connected to each other via a first connecting conductive layer 121 and a second connecting conductive layer 122, as described below.

[0033] Each conductive nanowire 120 may be formed using a conductive material. As an example that does not limit this disclosure, each conductive nanowire 120 may include a metal, including at least one of nickel (Ni), cobalt (Co), titanium (Ti), tungsten (W), palladium (Pd), copper (Cu), and alloys thereof. Optionally, each conductive nanowire 120 may include a conductive ceramic material, such as titanium nitride (TiN) or tungsten nitride (WN).

[0034] Each conductive nanowire 120 may have a multiphase structure, for example, comprising crystalline alloys, amorphous alloys, or nanoscale grains. For example, the crystal structure of the conductive nanowire 120 can be controlled by controlling the environment in which the conductive nanowire 120 is drawn (e.g., cooling rate, drawing rate). However, this disclosure is not limited thereto.

[0035] The plurality of conductive nanowires 120 may be made of the same or different materials. For example, each of the plurality of conductive nanowires 120 may be a nickel (Ni) nanowire. In another example, some of the plurality of conductive nanowires 120 may be nickel (Ni) nanowires, and the remainder of the plurality of conductive nanowires 120 may be copper (Cu) nanowires. In yet another example, the plurality of conductive nanowires 120 may include metal nanowires, alloy nanowires, and conductive ceramic nanowires.

[0036] The plurality of conductive nanowires 120 may each have at least one shape, either cylindrical or polygonal. For example, each of the plurality of conductive nanowires 120 may have a cylindrical shape. In another example, each of the plurality of conductive nanowires 120 may have a polygonal shape. In yet another example, some of the plurality of conductive nanowires 120 may each have a cylindrical shape, and the remaining portions of the plurality of conductive nanowires 120 may each have a polygonal shape.

[0037] The average diameter of the plurality of conductive nanowires 120 may be less than or equal to 10 μm (optionally, less than or equal to 2 μm). For example, the average diameter of the plurality of conductive nanowires 120 may refer to an arithmetic mean obtained by performing multiple measurements along the Z direction on any one of the conductive nanowires 120 shown in the image, wherein the image is obtained by capturing an XZ section of the capacitor assembly 1 at the center in the Y direction using an optical microscope or a scanning electron microscope (SEM). Here, multiple measurements along the Z direction may refer to measurements performed at equal intervals along the Z direction, and are not limited thereto. Optionally, the average diameter may refer to a value obtained by measuring the diameters of at least three or more conductive nanowires 120 shown in the image separately using the method described above, and then taking an arithmetic mean of these diameters. For another example, the average diameter of the plurality of conductive nanowires 120 may refer to the arithmetic mean of the diameters of at least three or more conductive nanowires 120 shown in the image, wherein the image is obtained by capturing an XY section of the capacitor assembly 1 at the center in the Z direction using an optical microscope or a scanning electron microscope (SEM). In addition, when the shape of the conductive nanowire 120 shown in the XY cross-sectional image is not circular, the diameter of the conductive nanowire 120 can represent the equivalent circle diameter (assuming that the circle has the same area as the conductive nanowire in the XY cross-sectional image).

[0038] One end of multiple conductive nanowires 120 ( Figure 1 The average diameter of the upper end of the multiple conductive nanowires 120 is similar to that of the other end of the upper end. Figure 1The ratio of the difference between the average diameters of the lower ends of the conductive nanowires 120 and the average diameter of the plurality of conductive nanowires 120 can be less than or equal to 10%. Unlike general nanowires obtained by selectively growing conductive materials, the plurality of conductive nanowires 120 used in this exemplary embodiment can be manufactured by a drawing method. Therefore, in the case of the plurality of conductive nanowires 120 used in this exemplary embodiment, unlike the average diameter of general nanowires, the average diameters of one end and the other end of the conductive nanowire 120 can have a relatively small difference.

[0039] The average distance (i.e., the value in the Z direction) from one end of the plurality of conductive nanowires 120 to the other end can be greater than or equal to 100 μm. The length (i.e., the dimension in the Z direction) of each of the plurality of conductive nanowires 120 can be determined by the thickness of the diced wafer described below, and if necessary, the length (i.e., the dimension in the Z direction) of each of the plurality of conductive nanowires 120 can be greater than or equal to 1000 μm. For example, the length (i.e., the dimension in the Z direction) of each of the plurality of conductive nanowires 120 can be represented by a value obtained in such a way as to measure the dimensions in the Z direction of at least three or more conductive nanowires 120 shown in the image respectively by the method described above, and then arithmetically averaging these dimensions, wherein the image is obtained by capturing the XZ cross section of the capacitor assembly 1 from the center in the Y direction using an optical microscope or a scanning electron microscope (SEM).

[0040] Multiple conductive nanowires 120 can be grouped together to form multiple conductive nanowire bundles 100, and the multiple conductive nanowire bundles 100 can be arranged in a repeating pattern. For example, as Figure 4 and Figure 7 As shown, multiple conductive nanowire bundles 100 and 100"' can each have a roughly circular cross-section. Additionally, as... Figure 5 and Figure 6 As shown, multiple conductive nanowire bundles 100' and 100” can each have a generally hexagonal cross-section. Furthermore, as... Figures 4 to 7 As shown, multiple conductive nanowire bundles 100, 100', 100” and 100”' can form a pattern of bundles with repeating circular or hexagonal cross-sections.

[0041] In any of the conductive nanowire bundles 100, 100', 100”, and 100”’, one of the conductive nanowires 120 and another of the conductive nanowires 120 may have different average diameters, different materials, or different cross-sectional shapes. For example, as Figure 6 As shown, the conductive nanowire bundle 100" may include conductive nanowires 120a, 120b, and 120c that are made of different conductive materials. In this case, the conductive nanowires 120a, 120b, and 120c in the bundle may have the same shape. For another example, such as Figure 7 As shown, the conductive nanowire bundle 100”' may include conductive nanowires 1210 and 1220 with different average diameters, wherein the conductive nanowire 1210 with a larger average diameter may be disposed at the center of the conductive nanowire bundle 100”', and the conductive nanowire 1220 with a smaller average diameter may be disposed in the periphery of the conductive nanowire bundle 100”'.

[0042] A first conductive connecting layer 121 may be disposed at one end of a plurality of conductive nanowires 120 to connect the plurality of conductive nanowires 120 to each other, and a second conductive connecting layer 122 may be disposed at the other end of a plurality of conductive nanowires 120 to connect the plurality of conductive nanowires 120 to each other. The conductive connecting layer 121 or 122 may have a plate-like shape by extending in the XY plane from the upper or lower end of the plurality of conductive nanowires 120 to cover either end of the plurality of conductive nanowires 120. The conductive connecting layers 121 and 122 can connect the plurality of conductive nanowires 120 in parallel with each other.

[0043] The conductive connecting layer 121 or 122 may comprise a conductive material. As an example not limiting this disclosure, the conductive connecting layer 121 or 122 may comprise a metal, including at least one of nickel (Ni), cobalt (Co), titanium (Ti), tungsten (W), palladium (Pd), copper (Cu), and alloys thereof. Optionally, the conductive connecting layer 121 or 122 may comprise a conductive ceramic material, such as titanium nitride (TiN) or tungsten nitride (WN). The conductive connecting layer 121 or 122 and the conductive nanowire 120 may be formed using the same material, for example, both the conductive connecting layer 121 or 122 and the conductive nanowire 120 may be formed using nickel (Ni).

[0044] The conductive layer 121 or 122 can be formed by, for example, thin film processes (such as vapor deposition), plating processes, stacking processes of stacked conductive films, etc., and is not limited thereto.

[0045] The conductive body 130 may surround the plurality of conductive nanowires 120. The conductive body 130 may form the overall appearance of the capacitor assembly 1 according to this exemplary embodiment and serve as the second electrode portion of the capacitor assembly 1. That is, the dielectric film 110 described below may be disposed between each of the plurality of conductive nanowires 120 and the conductive body 130, and charges of different polarities may be applied to each of the plurality of conductive nanowires 120 and the conductive body 130, thereby forming a capacitor in the dielectric film 110.

[0046] The conductive body 130 can fill the space between a plurality of conductive nanowires 120 arranged at intervals from each other, and each of the plurality of conductive nanowires 120 can have a side surface covered by the dielectric film 110 described below. Additionally, the conductive body 130 can be formed on the upper surface of a first conductive layer 121 that connects one end of the plurality of conductive nanowires 120 to each other. The conductive body 130 may not be disposed on a second conductive layer 122 that connects the other ends of the plurality of conductive nanowires 120 to each other, and the scope of this exemplary embodiment is not limited thereto.

[0047] The conductive body 130 may be formed using a conductive material. As an example that does not limit this disclosure, the conductive body 130 may include a metal, including at least one of nickel (Ni), cobalt (Co), titanium (Ti), tungsten (W), palladium (Pd), copper (Cu), and alloys thereof. Optionally, the conductive body 130 may comprise a conductive ceramic material, such as titanium nitride (TiN) or tungsten nitride (WN).

[0048] The conductive body 130 can be formed by, for example, thin film processes (such as vapor deposition), plating processes, etc., and is not limited thereto. As an example that does not limit this disclosure, the conductive body 130 can be formed by atomic layer deposition (ALD).

[0049] The dielectric film 110 may cover the outer periphery of each of the plurality of conductive nanowires 120 and may be disposed between each of the plurality of conductive nanowires 120 and the conductive body 130. That is, the dielectric film 110 may serve as a separator to prevent electrical short circuits between each of the plurality of conductive nanowires 120 and the conductive body 130. As described above, the two ends of the conductive nanowires 120 may respectively contact and connect to the connecting conductive layers 121 and 122. Therefore, the dielectric film 110 may not be disposed between each end of the conductive nanowires 120 and the connecting conductive layers 121 or 122. Furthermore, the dielectric film 110 may be disposed between the connecting conductive layers 121 or 122 and the conductive body 130. In addition, unlike the case of the second connecting conductive layer 122, the entire surface of the first connecting conductive layer 121 may be covered by the dielectric film 110. That is, the surface of the second connecting conductive layer 122 may not be covered by the dielectric film 110.

[0050] The dielectric film 110 may comprise, for example, a high-k material having a relative permittivity of 3 or greater. As an example not limiting this disclosure, the dielectric film 110 may comprise at least one oxide selected from the group consisting of oxides of tantalum (Ta), titanium (Ti), lanthanum (La), zirconium (Zr), barium (Ba), silicon (Si), and hafnium (Hf). As an example not limiting this disclosure, the dielectric film 110 may be a multilayer film. In this case, the dielectric film 110 may be a bilayer film in which an oxide film comprising the aforementioned oxides and a nitride film comprising nitrides (such as silicon nitride (SiN)) are sequentially disposed.

[0051] The dielectric film 110 can be formed by, for example, vapor deposition (such as atomic layer deposition (ALD) or chemical vapor deposition (CVD)), and is not limited thereto.

[0052] The protective layer 150 may cover the conductive body 130 and the second connecting conductive layer 122. The protective layer 150 may be used to protect the capacitor assembly 1 from external impacts or conductive foreign objects.

[0053] The protective layer 150 may include, for example, thermoplastic resins (such as polystyrene, vinyl acetate, polyester, polyethylene, polypropylene, polyamide, rubber, or acrylic resins), thermosetting resins (such as phenol, epoxy resins, polyurethane, melamine, or alkyd resins), photosensitive resins, parylene, and silica (SiO2). x ) or silicon nitride (SiN) x ).

[0054] The protective layer 150 can be formed, for example, by coating with a liquid insulating resin, stacking insulating films, or using vapor deposition. When the protective layer 150 is formed by using an insulating film, the protective layer 150 can be a dry film (DF) including a photosensitive insulating resin, an Ajinomoto build-up film (ABF) excluding a photosensitive insulating resin, or a polyimide film.

[0055] The first terminal 141 can be connected to the first conductive layer 121, and a portion of the first terminal 141 can be exposed outward from the protective layer 150 to serve as a positive or negative electrode. The second terminal 142 can be connected to the conductive body 130, and a portion of the second terminal 142 can be exposed outward from the protective layer 150 to serve as a positive or negative electrode with a polarity different from that of the first terminal 141.

[0056] Terminals 141 or 142 may be formed using a conductive material including at least one of copper (Cu), silver (Ag), nickel (Ni), and tin (Sn). Terminals 141 or 142 may be formed by at least one of paste printing, plating, or thin film processes (such as vapor deposition), and this disclosure is not limited thereto. Multilayer terminals 141 or 142 may be formed, and this disclosure is not limited thereto.

[0057] Figure 8 This is a partial cross-sectional view schematically illustrating a capacitor assembly according to another exemplary embodiment of the present disclosure.

[0058] Reference Figures 1 to 7 and Figure 8 Compared to the capacitor assembly according to an exemplary embodiment of the present disclosure, the capacitor assembly according to another exemplary embodiment of the present disclosure may further include a barrier metal film 125 and a barrier dielectric film 111. Therefore, in describing the capacitor assembly according to this exemplary embodiment, only the barrier metal film 125 and the barrier dielectric film 111, which are components different from those in the exemplary embodiments of the present disclosure, will be described.

[0059] A barrier metal film 125 may surround the outer periphery (i.e., the outer peripheral surface) of the dielectric film 110 (surrounding each side surface of the plurality of conductive nanowires 120). Additionally, a barrier dielectric film 111 may surround the outer periphery (outer peripheral surface) of the barrier metal film 125 (surrounding the outer periphery (outer peripheral surface)) of the dielectric film 110. That is, the barrier metal film 125 and the barrier dielectric film 111 may be sequentially disposed between the dielectric film 110 and the conductive body 130. The barrier metal film 125 and the barrier dielectric film 111 may prevent charge or ions from transferring from the dielectric film 110 to the conductive body 130.

[0060] Hereinafter, a method for manufacturing a capacitor assembly according to exemplary embodiments of the present disclosure is described. The capacitor assembly 1 of the present disclosure may be manufactured in the following sequence.

[0061] Reference Figure 12 and Figure 13 It may be necessary to first prepare a nanowire bundle comprising multiple nanowires 120 covered with glass 200.

[0062] To prepare nanowire bundles, multiple conductive nanowires can be coated with glass to draw out the nanowires. Then, an adhesive can be used to bring the multiple drawn nanowires together in parallel to prepare a nanowire bundle substrate.

[0063] Here, nanowire bundle substrates can be integrated with each other until the number of nanowires reaches one billion or more.

[0064] Therefore, the nanowire substrate can be heat-treated to harden the adhesive, thereby manufacturing nanowires.

[0065] Typically, nanowires may include conductive nanowires (i.e., cores) containing different components and a covering portion surrounding the conductive nanowires.

[0066] Furthermore, in nanowires, the conductive nanowires and the capping portion can be separated from each other using a unit for melting the capping portion. Here, a component with a melting point higher than that of the capping portion can be used as the material for the conductive nanowires. This technique can be used to manufacture nanowires in which a metallic material such as nickel (Ni) is enclosed in glass.

[0067] Therefore, as long as the raw materials for the conductive metal nanowires and the glass covering are continuously supplied, nanowires can be produced continuously and rapidly.

[0068] Nanowires can be produced continuously, so theoretically they have an infinite aspect ratio. For mass production, a template with a three-dimensional patterned structure can be fabricated in which bundles of nanowires formed by winding and stacking are arranged and fixed.

[0069] In this exemplary embodiment, a wafer with a three-dimensional structure can be fabricated, and the wafer may include multiple metal conductive nanowires, wherein the multiple metal conductive nanowires are bundled together to form a nanowire bundle, and the nanowire bundle is vertically cut (along the longitudinal axis of the nanowires) into a thin plate shape and erected vertically. Here, glass 200 is used as a binder material.

[0070] In this way, three-dimensional structures including nanowire bundles can be fixed by heat treatment, cut to any size, and processed into wafer shapes. This method can process large-area nanowire bundles simultaneously, thus increasing productivity, and can also be easily applied to conventional manufacturing (FAB) processes.

[0071] Here, in the FAB process for manufacturing three-dimensional structures in the shape of wafers, components of the basic structure can be easily replaced with necessary components or another structure can be added to the basic structure.

[0072] The surface of the wafer prepared in this way can then be smoothed by polishing and wet etching before performing subsequent processes.

[0073] Next, as Figure 14 As shown, conductive materials can be applied to the upper and lower ends of the wafer to form a first conductive layer 121 that physically connects the upper ends of a plurality of conductive nanowires 120 formed on the upper surface of the wafer to each other, and a second conductive layer 122 that physically connects the lower ends of a plurality of conductive nanowires 120 formed on the lower surface of the wafer.

[0074] In an exemplary embodiment, a plurality of conductive nanowires 120 may be used as a first electrode portion.

[0075] Next, as Figure 15 As shown, in order to perform advanced microdevice (AMD) processing in a wafer, a channel 171 connecting the inside and outside of the wafer can be formed by attaching a mask manufactured in the necessary shape to a first connection conductive layer 121, and then removing the surface of the unmasked portion of the first connection conductive layer 121.

[0076] Here, the uniformity of the unit size and detail pattern of the wafer can be controlled by using the shape of the mask.

[0077] In addition, such as Figure 16 and Figure 17 As shown, a metal wet etching / oxide wet etching process can be performed on the wafer through channel 171 to remove the glass 200 used as a binder from the wafer and leave only the conductive nanowires 120, thereby forming a space 172 in the wafer.

[0078] Next, as Figure 18 and Figure 19 As shown, a dielectric can be deposited in space 172 in a process such as atomic layer deposition (ALD) to form a dielectric film 110 on the outer periphery of each conductive nanowire 120 and on the upper surface of the first interconnecting conductive layer 121.

[0079] In some cases, multilayer patterns with different compositions surrounding conductive nanowires can be formed by controlling ALD or repeated etching / deposition.

[0080] In addition, this deposition technique using ALD allows for precise control of the pattern thickness, thus enabling the creation of virtually any type of three-dimensional pattern.

[0081] For example, a barrier metal film can be further formed to cover the periphery of the dielectric film, and then the process of forming the barrier dielectric film can be further performed by depositing a dielectric again to cover the periphery of the barrier metal film.

[0082] Next, as Figure 20 and Figure 21 As shown, conductive material can be additionally deposited in the space 172 pre-prepared by removing glass 200 and on the upper surface of dielectric film 110 to form a conductive body 130 surrounding dielectric film 110.

[0083] Here, ALD can be used as a method for depositing conductive materials, and this disclosure is not limited thereto.

[0084] In addition, the conductive body 130 can be kept insulated from the plurality of conductive nanowires 120 by the dielectric film 110.

[0085] Next, as Figure 22 As shown, in order to form on the upper part of the wafer Figure 2The first terminal 141 shown can be machined with a groove 173 to expose the first conductive layer 121, and then the first terminal 141 can be formed in the groove 173 to connect to the first conductive layer 121. Here, the first terminal 141 can be configured to be spaced apart from the conductive body 130, which serves as the second electrode portion.

[0086] Next, a conductive body 130 can be formed on its upper surface 131. Figure 2 The second terminal 142 is shown.

[0087] Next, a protective layer 150 can be formed to cover the surfaces of the conductive body 130 and the second connecting conductive layer 122, exposing portions of the first terminal 141 and the second terminal 142 to the outside, thereby manufacturing... Figure 2 Capacitor assembly 1.

[0088] In capacitor assemblies with three-dimensional structures fabricated using existing electrochemical methods, electrode posts can be fabricated by gradually creating grooves throughout the space through etching, or by gradually generating electrode posts using growth methods in zero space.

[0089] As mentioned above, existing manufacturing methods may be advantageous in the width direction of the capacitor assembly but disadvantageous in the depth or length direction of the capacitor assembly in terms of simultaneously processing several holes or simultaneously generating several electrode posts.

[0090] Capacitor components with three-dimensional structures can be classified into three types based on their materials and manufacturing methods. Specifically, capacitor components can be classified into trench type manufactured using silicon (Si) etching, stack type manufactured using oxygen (O) etching, and silicon nanowire (Si-NW) type manufactured using Si growth.

[0091] In addition, existing capacitor assemblies with three-dimensional structures have limitations due to the processing of matrix materials with the same composition.

[0092] In other words, when processing a continuum formed from the same material into a desired pattern, there are many constraints in order to process only the desired part to form the pattern without affecting the surrounding parts of the pattern.

[0093] On the other hand, when the desired pattern is obtained by applying different materials around the base material, rather than by using a continuum formed from the same material, it may be relatively less difficult to change the components included in each pattern to the materials actually needed.

[0094] This disclosure allows the fabrication of wafers with vertical patterns (formed in desired shapes) using nanowire bundles (including multiple conductive nanowires coated with glass), and the easy fabrication of capacitor assemblies with three-dimensional structures on the wafers in a FAB process.

[0095] In addition, existing capacitor assemblies with three-dimensional structures have the following problems.

[0096] The first problem is that the dielectric constant of the dielectric used in three-dimensional capacitor assemblies can be relatively lower than that of the dielectric used in multilayer ceramic capacitors (MLCCs).

[0097] Compared to barium titanate (BT) based dielectrics used in multilayer capacitors, oxide-nitride-oxide (ONO) based dielectrics for capacitor assemblies with three-dimensional structures can have a dielectric constant that is 330 times lower.

[0098] Even when the dielectric constant is corrected for by breakdown voltage at the same thickness, capacitor assemblies with a three-dimensional structure may be about 6.2 times lower.

[0099] The advantages of ONO-based dielectric films lie in their superior thickness distribution, temperature characteristics, and long-term reliability compared to BT-based dielectrics. Therefore, capacitor assemblies with three-dimensional structures manufactured using electrochemical methods may be very useful in specialized products.

[0100] However, in order to use capacitor assemblies with three-dimensional structures in a wider range of products, it is necessary to overcome the problem caused by the lower dielectric constant of multilayer capacitors.

[0101] The second problem is that because the internal electrodes or dielectric films have a high aspect ratio (or longitudinal-to-transverse ratio, i.e., length / thickness), their products may have reduced productivity and increased costs.

[0102] To achieve higher capacitance in a three-dimensional capacitor assembly than a multilayer capacitor of the same volume, the effective area needs to be increased by increasing the aspect ratio of the internal electrodes and dielectric film. Here, a limited aspect ratio can be a significant challenge in manufacturing high-capacitance capacitors.

[0103] In contrast, the capacitor assembly according to this disclosure may have the following advantages.

[0104] First, its cost can be reduced depending on the manufacturing method. Of all the processes, the capacitor assembly according to this disclosure can achieve a three-dimensional structure that ensures a high aspect ratio at a lower cost.

[0105] By avoiding high aspect ratio contact (HARC) etching or growth processes, the capacitor assembly disclosed herein can have a lower production cost compared to prior art capacitor assemblies.

[0106] The capacitor assembly disclosed herein can simultaneously eliminate defect factors (such as pattern lifting, pattern collapse, or pattern bias that occur during growth) to consistently maintain its high yield.

[0107] Furthermore, according to this disclosure, a high degree of freedom is available in designing capacitor assemblies.

[0108] The capacitor assembly disclosed herein can be manufactured into products of various sizes using a single substrate material. Here, the wafer used as an intermediate for manufacturing the capacitor assembly may include the same repeating structure.

[0109] Therefore, capacitor assemblies with the same structure but different sizes can be obtained simply by changing the dicing interval during wafer formation to adjust the length of the wafer in the height direction, or by adjusting the dicing size of individual wafer assemblies differently after wafer formation.

[0110] In other words, the size of the chip assembly can be determined during its manufacturing process, so various chip assemblies of different sizes can be manufactured simultaneously.

[0111] Furthermore, when capacitor assemblies have the same structure, the capacitance of the capacitor assembly is linearly proportional to its volume. Therefore, capacitor assemblies with various capacitances can be manufactured using a single substrate material, thus allowing for a high degree of design freedom.

[0112] In addition, according to this exemplary embodiment, metal can be applied to the surface of the wafer to form a first conductive layer and a second conductive layer, thereby electrically connecting the conductive nanowires of the nanowires to each other.

[0113] Here, a surface aperture process can be performed on the wafer to form the shape of the designed mask, and the three-dimensional shape of the capacitor can be determined based on the shape of the designed mask.

[0114] Furthermore, in this exemplary embodiment, even when the thickness and spacing of the nanowires have been changed, the material deposited on the nanowires by the atomic layer deposition (ALD) process can still have a relatively uniform thickness.

[0115] Furthermore, this uniformity can be further improved by adjusting individual opening points of the mask, while maintaining the overall shape of the capacitor assembly.

[0116] In addition, in the FAB process of wafers, components included in its basic structure can be replaced with another necessary component, or the basic structure can be easily reprocessed to adapt to a specific structure, and the wafer can also be cut to the required size by controlling the mask.

[0117] For example, such as Figure 9A and Figure 9BAs shown, each diameter of wafers W11 and W12 can be controlled, thereby adjusting the dimensions of capacitor assemblies manufactured using these wafers in the X or Y direction. Additionally, as... Figure 10A and 10B As shown, the thickness of each of wafers W21 and W22 can be controlled, thereby adjusting the height of the capacitor assembly manufactured using these wafers in the Z direction. Furthermore, as... Figure 11A and 11B As shown, even wafers W31 and W32 of the same size can be cut into internal regions of different sizes.

[0118] Furthermore, in the capacitor assembly according to this disclosure, the conductive body serving as the second electrode portion can be surrounded by a plurality of conductive nanowires serving as the first electrode portion, separated by a dielectric film, according to its manufacturing method. Therefore, the entire exterior of the capacitor assembly can be treated with a conductive material without any additional processing.

[0119] Therefore, capacitor assemblies to be mounted on boards, etc., can be easily designed, and the capacitor assemblies themselves can have strong durability and reliability against moisture and external shocks.

[0120] As described above, according to exemplary embodiments of the present disclosure, wafers comprising conductive nanowire bundles (in which a plurality of conductive nanowires are covered with glass) can be fabricated, thereby enabling the easy fabrication of smaller, high-capacitance capacitor assemblies with a three-dimensional structure.

[0121] In the FAB process of the wafer according to this exemplary embodiment, a component included in its basic structure can be replaced with another desired component, or the basic structure can be easily reprocessed to adapt to a specific structure, and the wafer can also be cut to the desired size by controlling the mask. Therefore, the design freedom of the capacitor assembly of this disclosure can be increased.

[0122] While exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A capacitor assembly, comprising: Multiple conductive nanowires are arranged to be spaced apart from each other; A first conductive layer and a second conductive layer are respectively disposed on one end and the other end of the plurality of conductive nanowires and connected to the plurality of conductive nanowires; A conductive substrate surrounding the plurality of conductive nanowires; A dielectric film is disposed between the conductive body and each of the plurality of conductive nanowires and the first and second connecting conductive layers; The first terminal is connected to the first conductive layer. as well as The second terminal is connected to the conductive body. The first conductive layer has an opening, and a portion of the conductive body disposed between adjacent conductive nanowires in the plurality of conductive nanowires is exposed from the opening and connected to the second terminal.

2. The capacitor assembly as claimed in claim 1, wherein, Both the plurality of conductive nanowires and the conductive substrate comprise metal.

3. The capacitor assembly as claimed in claim 2, wherein, The plurality of conductive nanowires each include at least one of nickel, cobalt, titanium, tungsten, palladium, and copper.

4. The capacitor assembly as claimed in claim 2, wherein, The conductive substrate includes at least one of nickel, cobalt, titanium, tungsten, palladium, and copper.

5. The capacitor assembly as claimed in claim 4, wherein, The plurality of conductive nanowires each include at least one of nickel, cobalt, titanium, tungsten, palladium, and copper.

6. The capacitor assembly of claim 5, wherein, The plurality of conductive nanowires all include nickel.

7. The capacitor assembly of claim 6, wherein, The conductive component comprises nickel.

8. The capacitor assembly as claimed in claim 2, wherein, The multiple conductive nanowires all comprise the same material.

9. The capacitor assembly of claim 8, wherein, The plurality of conductive nanowires all include nickel.

10. The capacitor assembly of claim 2, wherein, At least one of the plurality of conductive nanowires includes a material different from that of at least one of the plurality of conductive nanowires.

11. The capacitor assembly of claim 1, further comprising: A barrier metal film is disposed between the dielectric film and the conductive body based on the side surface of each of the plurality of conductive nanowires; as well as A barrier dielectric film is disposed between the barrier metal film and the conductive body based on the side surface of each of the plurality of conductive nanowires.

12. The capacitor assembly of claim 1, wherein, The average diameter of the plurality of conductive nanowires is less than or equal to 10 μm.

13. The capacitor assembly of claim 12, wherein, The ratio of the difference between the average diameter of one end of the plurality of conductive nanowires and the average diameter of the other end of the plurality of conductive nanowires to the average diameter of the plurality of conductive nanowires is less than or equal to 10%.

14. The capacitor assembly of claim 1, wherein, The average distance from one end of the plurality of conductive nanowires to the other end of the plurality of conductive nanowires is greater than or equal to 100 μm.

15. The capacitor assembly of claim 1, wherein, The dielectric film comprises at least one oxide selected from the group consisting of oxides of tantalum, oxides of titanium, oxides of lanthanum, oxides of zirconium, oxides of barium, oxides of silicon, and oxides of hafnium.

16. The capacitor assembly of claim 15, wherein, The dielectric film is a multilayer film, which includes an oxide film containing oxides and a nitride film disposed on the oxide film and containing silicon nitride.

17. A capacitor assembly, comprising: The first electrode portion includes a plurality of conductive nanowires, which extend in a first direction and are spaced apart from each other in a second direction perpendicular to the first direction. A first conductive layer and a second conductive layer are respectively disposed on the upper and lower ends of the plurality of conductive nanowires to connect the plurality of conductive nanowires to each other. A dielectric film surrounds the side surface of each of the plurality of conductive nanowires; The second electrode portion fills the space between the plurality of conductive nanowires that are spaced apart from each other between the first and second conductive layers, and surrounds the side surface of the dielectric film. The first terminal is connected to the first conductive layer. as well as The second terminal is connected to the second electrode section. The first conductive layer has an opening, and a portion of the second electrode portion disposed between adjacent conductive nanowires in the plurality of conductive nanowires is exposed from the opening and connected to the second terminal.

18. The capacitor assembly of claim 17, wherein, Based on the cross-section of the capacitor assembly in a direction parallel to the first direction, the second electrode portion is disposed in the space defined by the plurality of conductive nanowires and each of the first and second connecting conductive layers, and the dielectric film is interposed between the plurality of conductive nanowires and each of the first and second connecting conductive layers and the second electrode portion. Based on the cross-section of the capacitor assembly in a direction parallel to the second direction, the second electrode portion surrounds each of the plurality of conductive nanowires through a dielectric film.

19. The capacitor assembly of claim 17, further comprising: A protective layer covers the second electrode portion and the second conductive connection layer. The first terminal is exposed outward from the protective layer, and The second terminal is exposed outward from the protective layer.

20. The capacitor assembly of claim 17, further comprising: A blocking metal film surrounds the outer periphery of the dielectric film; as well as A barrier dielectric film is disposed between the barrier metal film and the second electrode portion.

21. The capacitor assembly of claim 17, wherein, At least one of the plurality of conductive nanowires has a cylindrical or polygonal column shape.

22. The capacitor assembly of claim 17, wherein, The plurality of conductive nanowires are grouped together to form a plurality of conductive nanowire bundles, and the plurality of conductive nanowire bundles are arranged in a repeating pattern based on the cross-section of the capacitor assembly in a direction parallel to the second direction.

23. The capacitor assembly of claim 22, wherein, In the plurality of conductive nanowire bundles, one of the conductive nanowires has an average diameter that is different from the average diameter of the other conductive nanowire.

24. The capacitor assembly of claim 22, wherein, In the plurality of conductive nanowire bundles, one of the conductive nanowires comprises a material different from that of the other conductive nanowires.

25. A method for manufacturing a capacitor assembly, the method comprising: Multiple conductive nanowire bundles were prepared, each conductive nanowire being covered with glass; A wafer is prepared by vertically cutting the plurality of conductive nanowire bundles; A first conductive layer and a second conductive layer are formed on one surface and another surface of the wafer, respectively, to connect the plurality of conductive nanowires to each other. A space is formed in the wafer by removing the glass from the wafer; A dielectric film is formed on the surface of each of the plurality of conductive nanowires and on the surface of each of the first and second connecting conductive layers by depositing a dielectric in the wafer. as well as The second electrode portion is formed by depositing a conductive material in the wafer. The formation of the space in the wafer includes: Channels are formed by removing a portion of the first conductive layer to expose a portion of the plurality of conductive nanowire bundles; and The glass is removed through the channel.

26. The manufacturing method as described in claim 25, wherein, The conductive nanowires have a higher melting point than the glass, and the glass is removed by melting.

27. The manufacturing method of claim 25, further comprising, between forming the dielectric film and forming the second electrode portion: A barrier metal film is formed around the outer periphery of the dielectric film; and A barrier dielectric film is formed around the outer periphery of the barrier metal film by depositing a barrier dielectric.

28. The manufacturing method as described in claim 25, wherein, The fabrication of the plurality of conductive nanowire bundles includes: Multiple conductive nanowires are drawn out by coating the conductive nanowires with glass. A nanowire bundle substrate is prepared by using an adhesive to converge the pulled-out multiple conductive nanowires in parallel, and The adhesive is hardened by heat treatment of the nanowire substrate.

29. The manufacturing method as described in claim 25, wherein, Forming at least one of the dielectric film and forming the second electrode portion includes performing atomic layer deposition.

30. The manufacturing method of claim 25, further comprising, after forming the second electrode portion: A first terminal is formed in the groove by processing a recess to expose the first conductive layer from one surface of the wafer; A second terminal is formed on the second electrode portion; as well as A protective layer is formed, which covers the second electrode portion and the second conductive connection layer, and exposes the first terminal and the second terminal to the outside.

31. A capacitor assembly, comprising: Multiple conductive nanowires, spaced apart from each other; A dielectric film surrounds the side surface of each of the plurality of conductive nanowires; A blocking metal film surrounds the outer periphery of the dielectric film; A barrier dielectric film surrounds the outer periphery of the barrier metal film; A first conductive layer and a second conductive layer are respectively disposed on one end and the other end of the plurality of conductive nanowires and connected to the plurality of conductive nanowires; A conductive substrate is filled between the plurality of conductive nanowires surrounded by the dielectric film, the barrier metal film, and the barrier dielectric film; The first terminal is connected to the first conductive layer. as well as The second terminal is connected to the conductive body. The first conductive layer has an opening, and a portion of the conductive body disposed between adjacent conductive nanowires in the plurality of conductive nanowires is exposed from the opening and connected to the second terminal.

32. The capacitor assembly of claim 31, wherein, At least one of the plurality of conductive nanowires includes a material different from that of at least one of the plurality of conductive nanowires.

33. The capacitor assembly of claim 31, wherein, The plurality of conductive nanowires include at least one of metal and conductive ceramic materials.

34. The capacitor assembly of claim 33, wherein, The metal includes at least one selected from the group consisting of nickel, cobalt, titanium, tungsten, palladium and copper.

35. The capacitor assembly of claim 33, wherein, The conductive ceramic material includes at least one of titanium nitride and tungsten nitride.

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