Package carrier, method of manufacturing the same, circuit board, package structure, and electronic device

Abstract

This application discloses a packaging substrate, its fabrication method, circuit board, packaging structure, and electronic device. The packaging substrate includes: a first circuit layer comprising a first dielectric layer and metal traces filling a hollow area within the first dielectric layer; a stacked structure layered on the first circuit layer, the stacked structure comprising: a second dielectric layer, a second circuit layer, and a third dielectric layer stacked sequentially, vias penetrating the third dielectric layer, the second circuit layer, and the second dielectric layer, and conductive material filling the vias; a second circuit layer comprising a fourth dielectric layer and metal traces filling a hollow area within the fourth dielectric layer, with the vias penetrating the metal traces of the second circuit layer; the first circuit layer and the second circuit layer in the adjacent stacked structure are electrically connected via conductive material. This provides a packaging substrate with high circuit precision and low cost.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202111258938.X, filed on October 27, 2021, entitled "An Encapsulation Structure", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of semiconductor packaging technology, and more particularly to a packaging substrate, its preparation method, circuit board, packaging structure, and electronic device. Background Technology

[0004] As a crucial component of chip packaging, the packaging substrate faces increasingly stringent requirements due to the continuous evolution of Moore's Law and the resulting higher demands on wafer fabrication processes. Consequently, the processing precision of the inner layer circuitry on the packaging substrate also increases. Currently, commonly used processes for fabricating packaging substrates include subtractive processes, Modified Semi-Additive Process (MSAP) processes, and Semi-Additive Process (SAP) processes. The subtractive process for forming the packaging substrate is as follows: Figure 1 As shown, a dielectric layer 02 and copper foil 03 are laminated on a substrate 01. Then, drilling, electroless copper plating 04, photoresist exposure and development 05, and copper electroplating 06 are performed sequentially. After removing the photoresist 05, flash etching of some copper foil 03, and electroless copper plating 04, the circuit pattern is obtained. However, the copper foil 03 used in the subtractive process is relatively thick, resulting in limited circuit accuracy when etching a thicker copper layer. Furthermore, during photolithography, the photoresist tends to tilt on the sidewalls after development, affecting circuit accuracy. Therefore, the packaging substrate formed by the subtractive process typically has a linewidth / spacing of around 40 μm. The MSAP process for forming the packaging substrate is similar. Figure 1 As shown, the difference from the subtractive process lies in the use of an ultra-thin copper foil of approximately 3μm, which avoids the line accuracy issues caused by thicker copper layers in photolithography, thus improving line accuracy. However, the disadvantages are that ultra-thin copper foil is more expensive, and line accuracy is still affected by photoresist exposure and development factors; typically, the line width / spacing can reach around 20μm. The SAP process for forming the packaging substrate is as follows: Figure 2 As shown, compared to the MSAP process, the ultra-thin copper foil is omitted, and copper 04 is directly chemically plated on the dielectric layer 02. The copper layer is thinner, which further improves the accuracy of the circuit. However, to perform chemical copper 04 directly on the dielectric layer 02 and meet the adhesion requirements, the dielectric layer 02 must use special materials, which is costly. In addition, the accuracy of the circuit is still affected by the exposure and development factors of the photoresist. Typically, the line width / line spacing can reach about 10μm.

[0005] Therefore, providing a packaging substrate with high circuit accuracy and low cost is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] This application provides a packaging substrate, its preparation method, a circuit board, a packaging structure, and an electronic device, which are used to provide a packaging substrate with high circuit accuracy and low cost.

[0007] In a first aspect, this application provides a method for fabricating a circuit substrate, which may include the following steps: providing a carrier board having two opposing surfaces; forming a metal layer on at least one surface of the two surfaces of the carrier board; forming a first dielectric layer on the side of each metal layer away from the carrier board; forming a plurality of cutout regions in the first dielectric layer using a laser ablation process; and then forming metal traces in each cutout region of the first dielectric layer. In the circuit substrate formed by this method, since the metal traces are formed in the cutout regions of the first dielectric layer, the precision of the cutout regions determines the precision of the metal traces in the circuit substrate. Since the cutout regions in the first dielectric layer are formed using a laser ablation process, compared to forming the cutout regions using photolithography, the precision can be avoided by the influence of photoresist exposure and development factors, thus enabling the fabrication of circuit substrates with higher precision. In specific implementations, the line width (width of the metal trace) / line spacing (minimum distance between metal traces) can reach below 10 μm.

[0008] It should be noted that in the circuit board fabrication method provided in this application embodiment, when a metal layer, a first dielectric layer, a cutout area, and metal traces are formed on both surfaces of the substrate, this application does not limit the order in which the film layers are formed on the two surfaces, as long as the order of the film layers formed on each surface is: metal layer, first dielectric layer, cutout area, and metal traces. For example, this application may first form a metal layer, a first dielectric layer, a cutout area, and metal traces sequentially on one surface, and then form a metal layer, a first dielectric layer, a cutout area, and metal traces sequentially on the other surface; of course, the film layers on the two surfaces may also be formed alternately.

[0009] In practice, this application does not limit the material and shape of the carrier plate, which is used to support the film layer formed subsequently.

[0010] This application does not limit the material of the metal layer, and it can be gold, silver, copper, platinum, tin, etc. In specific implementations, the metal layer can be formed on the surface of the carrier plate by methods such as lamination and deposition.

[0011] For example, the metal layer can be a copper foil layer, which can be formed on the surface of the carrier board using a lamination process.

[0012] In practice, the first dielectric layer can be formed on the metal layer using a semi-cured material through a lamination or coating process.

[0013] For example, the material of the first dielectric layer may be a material comprising at least one of bismaleimide triazine resin, polyarylamide fiber, epoxy resin, polyphenylene ether, or glass fiber, without limitation herein.

[0014] This application does not limit the thickness of the first dielectric layer, and it can be designed according to actual needs. Generally speaking, the thinner the first dielectric layer, the higher the precision of the hollowed-out area formed by the subsequent laser ablation process.

[0015] The shape of the hollowed-out area is not limited in this application. The shape of the hollowed-out area in the first dielectric layer can be hole-shaped, line-shaped, or groove-shaped, etc., and the specific design is based on the required metal trace pattern.

[0016] This application does not limit the material of the metal traces. For example, the material of the metal traces can be gold, silver, copper, platinum, tin, etc.

[0017] This application does not limit the method of forming metal traces. For example, since a metal layer is disposed below the first dielectric layer, metal traces can be formed directly in each cutout area of ​​the first dielectric layer by electroplating. In this way, the conventional chemical plating step can be eliminated, and no special materials are required. Therefore, it can be achieved using conventional processes and materials, resulting in lower costs.

[0018] Secondly, this application also provides a circuit board, which may include: a carrier board having two opposing surfaces; a metal layer located on at least one of the two surfaces; a first dielectric layer located on the side of each metal layer away from the carrier board, and the first dielectric layer having a plurality of cutout regions; and metal traces filling the cutout regions of the first dielectric layer. Since the principle by which this circuit board solves the problem is similar to the aforementioned method for fabricating a circuit board, the implementation of this circuit board can refer to the implementation of the aforementioned method for fabricating a circuit board, and repeated details will not be elaborated further.

[0019] In this circuit board, since the metal traces fill the hollow areas in the first dielectric layer, the accuracy of the hollow areas determines the accuracy of the metal traces in the circuit board. The hollow areas in the first dielectric layer can be formed by laser ablation, which avoids the influence of photoresist exposure and development factors on accuracy compared to photolithography. Therefore, the circuit accuracy of this circuit board can be higher.

[0020] Furthermore, since the circuit board provided in this application has high circuit precision, it can be used to prepare a high-precision packaging substrate.

[0021] Thirdly, this application also provides a method for preparing a packaging substrate, which may include the following steps:

[0022] Step S201: Provide two circuit substrates as described in the second aspect of this application, each circuit substrate including one metal layer and one first dielectric layer; of the two circuit substrates, one circuit substrate is a first circuit substrate and the other circuit substrate is a second circuit substrate. In specific implementation, the materials of the same-named film layers in the first circuit substrate and the second circuit substrate can be the same or different. For example, the material of the first dielectric layer in the first circuit substrate and the material properties of the first dielectric layer in the second circuit substrate can be the same or different, which is not limited here. However, in actual production, multiple circuit substrates are generally formed simultaneously on a large carrier board, and then cut to form multiple independent circuit substrates, so that the materials of the same-named film layers in different circuit substrates are the same.

[0023] Step S202: A second dielectric layer is laminated between the first circuit substrate and the second circuit substrate, and both the carrier plate of the first circuit substrate and the carrier plate of the second circuit substrate are located on the side away from the second dielectric layer, that is, the metal trace side of the first circuit substrate is disposed opposite to the metal trace side of the second circuit substrate.

[0024] In specific implementation, the material of the second dielectric layer may be a material containing at least one of bismaleimide triazine resin, polyarylamide fiber, epoxy resin, polyphenylene ether or glass fiber, and is not limited herein.

[0025] For example, in order to improve the consistency of materials between adjacent dielectric layers, the material of the second dielectric layer may be the same as the material of the first dielectric layer in the first circuit substrate and the material of the first dielectric layer in the second circuit substrate.

[0026] Step S203: Remove the carrier board and metal layer from the second circuit board.

[0027] Step S204: A third dielectric layer is formed on the side of the first dielectric layer of the second circuit substrate away from the second dielectric layer.

[0028] In practice, the third dielectric layer can be formed on the metal layer using a semi-cured material through a lamination or coating process.

[0029] For example, the material of the third dielectric layer may be a material comprising at least one of bismaleimide triazine resin, polyarylamide fiber, epoxy resin, polyphenylene ether, or glass fiber, without limitation herein.

[0030] This application does not limit the thickness of the third dielectric layer, and it can be designed according to actual needs. Generally speaking, the thinner the third dielectric layer, the higher the precision of the hollowed-out area formed by the subsequent laser ablation process.

[0031] Step S205: Form metal traces penetrating the third dielectric layer, the second circuit substrate, and vias in the second dielectric layer using a laser ablation process.

[0032] In this application, since vias need to penetrate the third dielectric layer, the metal traces in the second circuit board, and the second dielectric layer, the thinner the film layers that the vias need to penetrate, the better the accuracy. Therefore, the thicknesses of the third dielectric layer, the second dielectric layer, and the first dielectric layer can be set according to the actual performance requirements of the product, and made as thin as possible.

[0033] Step S206: Form conductive material in the via to electrically connect the metal traces in the first circuit board to the metal traces in the second circuit board.

[0034] This application does not limit the conductive material in the via. For example, the conductive material can be gold, silver, copper, platinum, tin, etc.

[0035] This application does not limit the method of forming conductive material in vias; any method can be used to form conductive material in vias. For example, conductive material can be formed in vias directly by electroplating.

[0036] Step S207: Remove the carrier board and metal layer from the first circuit substrate to form a packaging carrier board.

[0037] In specific implementation, a packaging carrier board can also be prepared by combining a circuit substrate with metal traces on one side with a circuit substrate with metal traces on both sides, as provided in the above embodiments. The preparation method of the packaging carrier board may include the following steps: Step S301: Provide three circuit substrates, one of which is a first circuit substrate, and the other two are second circuit substrates. The first circuit substrate has metal traces on both sides, and the second circuit substrate has metal traces on one side. In specific implementation, the first circuit substrate has two sides. For either side of the first circuit substrate, the following steps are performed: Step S302: Press a second dielectric layer between the first circuit substrate and the second circuit substrate, and the carriers of the first and second circuit substrates are both located on the side away from the second dielectric layer, that is, the metal trace side of the first circuit substrate is opposite to the metal trace side of the second circuit substrate. Step S303: Remove the carrier and metal layer from the second circuit substrate. Step S304: Form a third dielectric layer on the side of the first dielectric layer of the second circuit substrate away from the second dielectric layer. Step S305: Form vias penetrating the third dielectric layer, the metal traces in the second circuit substrate, and the second dielectric layer using a laser ablation process. Step S306: Form conductive material in the vias to electrically connect the metal traces in the first circuit substrate and the metal traces in the second circuit substrate. Finally, after steps S302 to S306 have been performed on both sides of the first circuit substrate, step S307 is performed to remove the carrier board and metal layer from the first circuit substrate, thereby forming two packaging carrier boards.

[0038] The fabrication method provided in this application allows for high precision in each metal trace layer compared to those formed using photolithography, as each metal trace layer is formed on the circuit substrate provided in this application. Furthermore, since the metal traces are embedded in the first dielectric layer, the third dielectric layer located between adjacent metal trace layers can have a thinner dielectric material between the two metal trace layers compared to directly filling the space between them. Additionally, this application utilizes the third dielectric layer instead of photoresist to form vias connecting different metal trace layers via laser ablation, improving the precision of the vias in the packaging substrate and thus enhancing the overall circuit precision of the packaging substrate. Finally, the bottom of the vias in this application directly contacts the metal traces, eliminating the need for conventional chemical plating and allowing electroplating of conductive materials within the vias without the need for special materials. Therefore, conventional processes and materials can be used, resulting in lower costs.

[0039] The above embodiments of this application are only illustrated by taking the formation of two circuit layers in the packaging substrate as an example. Of course, multiple circuit layers can also be formed in the packaging substrate. The method of continuing to stack circuit layers in the packaging substrate can be found in steps S202 to S206. The following is an illustrative example of continuing to stack one circuit layer in the packaging substrate.

[0040] Further, the fabrication method may include: providing a third circuit substrate, one side of which has metal traces, forming a first stacked structure consisting of a second dielectric layer, a first dielectric layer, metal traces, a third dielectric layer, and a conductive material located above a first circuit substrate; laminating a second dielectric layer between the first stacked structure and the third circuit substrate, with the carrier plate of the third circuit substrate located away from the first stacked structure; removing the carrier plate and metal layer from the third circuit substrate; forming a third dielectric layer on the first dielectric layer of the third circuit substrate; forming vias penetrating the newly formed third dielectric layer, the metal traces in the third circuit substrate, and the newly formed second dielectric layer using a laser ablation process; and forming a conductive material in the vias to electrically connect the metal traces in the second circuit substrate to the metal traces in the third circuit substrate.

[0041] Similarly, circuit layers can be further formed in the packaging substrate, which will not be elaborated here.

[0042] Optionally, when forming the last layer of wiring in the stacked package substrate, when forming the metal traces penetrating the third dielectric layer, the second circuit substrate, and the vias in the second dielectric layer, a first via penetrating the third dielectric layer can be formed first by laser ablation; then a second via penetrating the metal traces penetrating the second dielectric layer and the second circuit substrate can be formed by laser ablation, and the orthographic projection of the first via on the first circuit substrate covers the orthographic projection of the second via on the first circuit substrate.

[0043] Furthermore, in this application, after forming the conductive material in the via, the process may further include removing the third dielectric layer and the conductive material above the metal traces in the second circuit substrate. The resulting package carrier board comprises only the second dielectric layer and the second circuit layer in its stacked structure, which further reduces the thickness of the package carrier board.

[0044] Fourthly, this application also provides a packaging structure, in which the packaging substrate may include: a first circuit layer and a stacked structure stacked on the first circuit layer. The first circuit layer may include a first dielectric layer and metal traces filling a cutout area of ​​the first dielectric layer. The stacked structure may include a second dielectric layer, a second circuit layer, and a third dielectric layer stacked sequentially, vias penetrating the third dielectric layer, the second circuit layer, and the second dielectric layer, and conductive material filling the vias; in this stacked structure, the second circuit layer is located between the second and third dielectric layers, and the second dielectric layer is located closer to the first circuit layer; the second circuit layer may include a fourth dielectric layer (i.e., the first dielectric layer in the second circuit substrate used in the fabrication process) and metal traces filling a cutout area of ​​the fourth dielectric layer; the first circuit layer and the second circuit layer in the adjacent stacked structure can be electrically connected through the conductive material in the vias.

[0045] The packaging substrate provided in this application achieves high precision for each metal trace layer because each metal trace layer is formed using the circuit substrate provided in this application. This is compared to circuit layers formed using photolithography. Furthermore, since the metal traces are embedded in the first dielectric layer, the third dielectric layer located between adjacent metal trace layers can have a thinner dielectric material between the two metal trace layers compared to directly filling the space between them. Additionally, this application utilizes the third dielectric layer instead of photoresist to form vias connecting different metal trace layers using laser ablation, improving the precision of the vias in the packaging substrate and thus enhancing the overall circuit precision of the packaging substrate. Finally, the bottom of the vias in this application directly contacts the metal traces, eliminating the need for conventional chemical plating and allowing electroplating of conductive materials within the vias without the need for special materials. Therefore, it can be achieved using conventional processes and materials, resulting in lower costs.

[0046] Optionally, in the packaging substrate of this application, a multi-layer stacked structure may be stacked on the first circuit layer. Each layer stack may include a second dielectric layer, a second circuit layer, and a third dielectric layer stacked sequentially, vias penetrating the third dielectric layer, the second circuit layer, and the second dielectric layer, and conductive material filling the vias; the second circuit layers in any two adjacent layer stacks are electrically connected through the conductive material in the two adjacent layer stacks.

[0047] Optionally, in the package carrier, in the stacked structure furthest from the first circuit layer, the vias in the stacked structure include a first via penetrating the third dielectric layer, and a second via penetrating the metal trace in the second circuit layer and the second dielectric layer; the orthographic projection of the first via on the first circuit layer covers the orthographic projection of the second via on the first circuit layer. This increases the area of ​​the conductive material on the outermost side of the package carrier, thereby increasing the conductive contact area between the package carrier and other electrical components.

[0048] In this application, solder mask layers may also be included on both sides of the encapsulation substrate, and no limitation is made here.

[0049] Optionally, in this application, to improve material consistency, at least two of the first, second, third, and fourth dielectric layers are made of the same material. Of course, in specific implementations, different dielectric layers may also be made of different materials, which is not limited here.

[0050] Optionally, in this application, the metal traces in different circuit layers are made of the same material. This allows different circuit layers to be formed using the same process, thereby reducing costs.

[0051] Of course, in practice, the materials of the metal traces in different circuit layers can also be different.

[0052] Optionally, in this application, the conductive material in the via can be the same as the material of the metal trace in the circuit layer.

[0053] Fifthly, this application also provides a packaging structure, including a packaging substrate and a chip molded onto one side of the packaging substrate, wherein the packaging substrate is a packaging substrate as described in the fourth aspect or various embodiments of the fourth aspect. Since the principle by which this packaging structure solves the problem is similar to that of the aforementioned packaging substrate, the implementation of this packaging structure can refer to the implementation of the aforementioned packaging substrate, and repeated details will not be elaborated further.

[0054] In one feasible implementation, the package structure can be formed by the following steps: During the fabrication of the package carrier, after forming a target number of circuit layers on a first circuit substrate, and before removing the carrier and metal layers from the first circuit substrate, a chip is bonded on the side away from the first circuit substrate. The chip is encapsulated using a molding compound. The carrier and metal layers are then removed from the first circuit substrate.

[0055] Furthermore, a solder resist layer can also be formed on the side of the packaging substrate away from the chip, etc., which is not limited here.

[0056] Furthermore, solder balls can be implanted on the side of the packaging substrate away from the chip to facilitate subsequent soldering of the packaging structure to the circuit board.

[0057] Accordingly, this application also provides another packaging structure, including a packaging substrate and a chip molded onto one side of the packaging substrate. The packaging substrate may include at least one layered structure, each layer comprising a second dielectric layer, a circuit layer, and a third dielectric layer, wherein the circuit layer includes a first dielectric layer and metal traces filling a cutout area in the first dielectric layer. The layered structure has vias penetrating the second dielectric layer, the circuit layer, and the third dielectric layer, the vias being filled with conductive material.

[0058] In one feasible implementation, the packaging structure can be formed through the following steps: encapsulating the chip using a molding compound; laminating a second dielectric layer between the molding compound and the circuit board; removing the carrier board and metal layers from the circuit board, forming a third dielectric layer on the side of the first dielectric layer away from the second dielectric layer; forming vias penetrating the third dielectric layer, metal traces in the circuit board, and the second dielectric layer using a laser ablation process, and forming conductive material in the vias, thereby forming a multilayer structure; then, laminating the second dielectric layer between the multilayer structure and the circuit board; removing the carrier board and metal layers from the circuit board, forming a third dielectric layer on the side of the first dielectric layer away from the second dielectric layer; forming vias penetrating the third dielectric layer, metal traces in the circuit board, and the second dielectric layer using a laser ablation process, and forming conductive material in the vias, thereby forming a second multilayer structure.

[0059] In practical implementation, when the packaging carrier board of the packaging structure includes a multi-layer stacked structure, the following steps can be repeated: laminating a second dielectric layer between the stacked structure and the circuit board; removing the carrier board and metal layers from the circuit board; forming a third dielectric layer on the side of the first dielectric layer away from the second dielectric layer; forming vias penetrating the third dielectric layer, the metal traces in the circuit board, and the second dielectric layer using a laser ablation process; and forming conductive material in the vias. This process continues until the target number of layers is formed, which will not be elaborated further here.

[0060] This application does not limit the conductive material in the via. For example, the conductive material can be gold, silver, copper, platinum, tin, etc.

[0061] This application does not limit the method of forming conductive material in vias; any method can be used to form conductive material in vias. For example, conductive material can be formed in vias directly by electroplating.

[0062] Sixthly, this application also provides an electronic device, including: a housing, a circuit board located within the housing, and a packaging structure as described in various embodiments of the fifth aspect; the packaging structure is located on the circuit board and is electrically connected to the circuit board. For example, the circuit board is a PCB. Since the principle by which this electronic device solves the problem is similar to that of the aforementioned packaging structure, the implementation of this electronic device can refer to the implementation of the aforementioned packaging structure, and repeated details will not be elaborated further.

[0063] The technical effects that can be achieved in the fifth and sixth aspects can be described with reference to the technical effects that can be achieved by any possible design in the fourth aspect above, and will not be repeated here. Attached Figure Description

[0064] Figure 1 This is a schematic diagram of the fabrication process of a packaging substrate in related technologies;

[0065] Figure 2 This is a schematic diagram of the fabrication process of another packaging substrate in related technologies;

[0066] Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0067] Figure 4 A flowchart illustrating a method for fabricating a circuit board according to an embodiment of this application;

[0068] Figures 5a to 5c A schematic diagram illustrating the fabrication process of a circuit board according to an embodiment of this application;

[0069] Figure 6 A top view of the structure of a first dielectric layer provided in an embodiment of this application;

[0070] Figure 7 This is a schematic cross-sectional view of a circuit board provided in an embodiment of this application;

[0071] Figure 8 A cross-sectional structural schematic diagram of another circuit board provided in an embodiment of this application;

[0072] Figure 9 A flowchart illustrating a method for preparing a packaging carrier plate according to an embodiment of this application;

[0073] Figures 10a to 10e A schematic diagram illustrating the fabrication process of a packaging carrier plate provided in an embodiment of this application;

[0074] Figure 11 A cross-sectional structural diagram of a packaging carrier provided in an embodiment of this application;

[0075] Figure 12This is a schematic diagram of a structure for directly laminating two layers of metal traces, provided in an embodiment of this application.

[0076] Figure 13 A flowchart illustrating the process of forming circuit layers in the method for preparing the packaging substrate provided in this application embodiment;

[0077] Figures 14a to 14e This is a schematic diagram of the fabrication process of continuing to form circuit layers in the packaging substrate, provided in an embodiment of this application.

[0078] Figure 15 A cross-sectional structural diagram of another packaging carrier provided in an embodiment of this application;

[0079] Figure 16 A cross-sectional view of the vias in the packaging substrate provided in this application embodiment;

[0080] Figure 17 A cross-sectional structural diagram of another packaging carrier provided in an embodiment of this application;

[0081] Figure 18 This is a three-dimensional structural diagram of a packaging carrier provided in an embodiment of this application;

[0082] Figure 19 A cross-sectional structural diagram of another packaging carrier provided in an embodiment of this application;

[0083] Figure 20 A cross-sectional structural diagram of another packaging carrier provided in an embodiment of this application;

[0084] Figure 21 This is a cross-sectional view of a packaging structure provided in an embodiment of this application;

[0085] Figure 22a and Figure 22b This is a schematic diagram illustrating the fabrication process of a packaging structure provided in an embodiment of this application.

[0086] Figure 23 A cross-sectional view of another packaging structure provided in this application embodiment;

[0087] Figure 24 A cross-sectional view of another packaging structure provided in this application embodiment;

[0088] Figures 25a to 25c This is a schematic diagram illustrating the fabrication process of a packaging structure provided in an embodiment of this application.

[0089] Figure 26 This is a cross-sectional schematic diagram of another packaging structure provided in the embodiments of this application.

[0090] Explanation of reference numerals in the attached figures:

[0091] 1. Housing; 2. Circuit board;

[0092] 3. Package structure; 10. Package carrier board;

[0093] 20 chips; 101 carrier board;

[0094] 102 Metal layer; 103 First dielectric layer;

[0095] 104 Metal trace; 105 Second dielectric layer;

[0096] 106 Third dielectric layer; 107 Conductive material;

[0097] 108 Fourth dielectric layer; 1030 Cutout area;

[0098] 100 Circuit board; 100a First circuit board;

[0099] 100b Second circuit board; 100c Third circuit board;

[0100] V via; V1 First via;

[0101] V2 Second via; Ln Stacked structure;

[0102] 210 Molding material; 001 Solder ball. Detailed Implementation

[0103] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0104] The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” and “this” are intended to also include expressions such as “one or more,” unless the context clearly indicates otherwise.

[0105] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. The terms expressing position and direction described in this application are all illustrative based on the accompanying drawings, but changes can be made as needed, and all such changes are included within the scope of protection of this application. The accompanying drawings of this application are only used to illustrate relative positional relationships and do not represent actual scale. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0106] In the description of this application, it should be noted that, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0107] To facilitate understanding of the packaging substrate provided in this application embodiment, its application scenarios are first described. The packaging substrate proposed in this application embodiment is used to carry chips and can be applied to various electronic devices. For example, it can be applied to power supply circuits, microprocessors (Micro Controller Units, MCUs), central processing units (CPUs), graphics processing units (GPUs), baseband chips, or system-on-chip (SoC) chips, etc. It should be noted that the packaging substrate proposed in this application embodiment is intended for application in these and any other suitable types of electronic devices, including but not limited to. For example, Figure 3 As shown, the electronic device includes a housing 1 and a circuit board 2 disposed within the housing 1. The circuit board 2 has a packaging structure 3, which includes a packaging substrate 10 and a chip 20 encapsulated on the front side of the packaging substrate 10. The packaging substrate 10 is a crucial component of the chip 20 packaging. With the continuous evolution of Moore's Law, the process requirements for wafers are becoming increasingly stringent, and correspondingly, the processing precision of the inner layer circuitry of the packaging substrate 10 is also becoming increasingly precise. Based on this, this application provides a circuit board with high circuit precision and low cost, a packaging substrate fabricated based on the circuit board, a packaging structure, and an electronic device. The following will describe this application in further detail with reference to the accompanying drawings.

[0108] See Figure 4 , Figure 4 A flowchart illustrating a method for fabricating a circuit board according to an embodiment of this application is provided. The method for fabricating the circuit board may include the following steps:

[0109] Step S101: Provide a carrier plate having two surfaces arranged opposite each other.

[0110] In practice, this application does not limit the material and shape of the carrier plate, which is used to support the film layer formed subsequently.

[0111] Step S102, as follows Figure 5a As shown, a metal layer 102 is formed on at least one of the two surfaces of the carrier plate 101.

[0112] in, Figure 5a The following is an example of forming a metal layer 102 on one surface of a carrier plate 101.

[0113] This application does not limit the material of the metal layer, which can be gold, silver, copper, platinum, tin, etc.

[0114] In practice, the metal layer can be formed on the surface of the carrier plate through methods such as lamination and deposition.

[0115] For example, the metal layer can be a copper foil layer, which can be formed on the surface of the carrier board using a lamination process.

[0116] Step S103, as follows Figure 5b As shown, a first dielectric layer 103 is formed on the side of the metal layer 102 away from the carrier plate 101.

[0117] In practice, the first dielectric layer 103 can be formed on the metal layer using a semi-cured material through a pressing process or a coating process.

[0118] For example, the material of the first dielectric layer 103 may be a material comprising at least one of bismaleimide triazine resin, polyarylamide fiber, epoxy resin, polyphenylene ether or glass fiber, without limitation herein.

[0119] This application does not limit the thickness of the first dielectric layer 103, and it can be designed according to actual needs. Generally speaking, the thinner the first dielectric layer 103, the higher the precision of the hollow area formed by the subsequent laser ablation process.

[0120] Step S104, as follows Figure 5c As shown, multiple hollow areas 1030 are formed in the first dielectric layer 103 using a laser ablation process.

[0121] This application does not limit the shape of the hollowed-out area, such as Figure 6 As shown, Figure 6 This is a top view of a first dielectric layer 103 provided in an embodiment of this application. The shape of the hollowed-out area 1030 in the first dielectric layer 103 can be hole-shaped, line-shaped, or groove-shaped, etc., and is specifically designed according to the required metal trace pattern.

[0122] Step S105, as follows Figure 7 As shown, metal traces 104 are formed in each cutout area of ​​the first dielectric layer 103.

[0123] In the circuit substrate formed by the fabrication method provided in this application, since the metal traces are formed in the hollowed-out areas of the first dielectric layer 103, the precision of the hollowed-out areas determines the precision of the metal traces in the circuit substrate. The hollowed-out areas in the first dielectric layer are formed using a laser ablation process. Compared to forming the hollowed-out areas using photolithography, this avoids the precision being affected by photoresist exposure and development factors, thus enabling the fabrication of circuit substrates with higher precision. In specific implementations, the line width (width of the metal trace) / line spacing (minimum distance between metal traces) can reach below 10 μm.

[0124] This application does not limit the material of the metal traces. For example, the material of the metal traces can be gold, silver, copper, platinum, tin, etc.

[0125] This application does not limit the method of forming metal traces. For example, since a metal layer is disposed below the first dielectric layer, metal traces can be formed directly in each cutout area of ​​the first dielectric layer by electroplating. In this way, the conventional chemical plating step can be eliminated, and no special materials are required. Therefore, it can be achieved using conventional processes and materials, resulting in lower costs.

[0126] It should be noted that in the method for fabricating the circuit board provided in this application embodiment, when a metal layer, a first dielectric layer, a cutout region, and metal traces are formed on both surfaces of the carrier board 101, this application does not limit the order in which the film layers are formed on the two surfaces, as long as the order of the film layers formed on each surface is: metal layer, first dielectric layer, cutout region, and metal traces. For example, this application may first form a metal layer, first dielectric layer, cutout region, and metal traces sequentially on one surface, and then form a metal layer, first dielectric layer, cutout region, and metal traces sequentially on the other surface; of course, the film layers on the two surfaces may also be formed alternately.

[0127] In this application, the first dielectric layer 103 and the metal traces 104 formed in the cutout areas of the first dielectric layer 103 are referred to as circuit layers. In this application, when the metal layer 102 and the circuit layer are sequentially formed only on one surface of the carrier board 101, the resulting circuit board is as follows: Figure 7 As shown, the circuit board 100 includes a carrier board 101, a metal layer 102 on one surface of the carrier board 101, a first dielectric layer 103 on the side of the metal layer 102 away from the carrier board 101, and the first dielectric layer 103 has a plurality of hollow areas; each hollow area is filled with metal traces 104.

[0128] In this application, when a metal layer and a circuit layer are sequentially formed on both surfaces of a carrier board, the resulting circuit board is as follows: Figure 8 As shown, the circuit board 100 includes a carrier board 101, metal layers 102 on two surfaces of the carrier board 101, a first dielectric layer 103 on the side of each metal layer 102 away from the carrier board, and each first dielectric layer 103 has multiple hollow areas; each hollow area is filled with metal traces 104.

[0129] In this circuit board, since the metal traces 104 fill the hollow area 1030 in the first dielectric layer 103, the accuracy of the hollow area 1030 determines the accuracy of the metal traces 104 in the circuit board. The hollow area 1030 in the first dielectric layer 103 can be formed by laser ablation. Compared with photolithography, the accuracy can be avoided by the exposure and development factors of photoresist, so the circuit accuracy of this circuit board can be higher.

[0130] Furthermore, since the circuit board provided in this application has high circuit precision, it can be used to prepare a high-precision packaging substrate.

[0131] For example, to adopt such Figure 7 Taking the circuit board substrate fabrication and packaging substrate as an example, see [reference needed]. Figure 9 , Figure 9 A flowchart illustrating a method for fabricating a packaging substrate according to an embodiment of this application is provided. The method for fabricating the packaging substrate may include the following steps:

[0132] Step S201, provide two such as Figure 7 The circuit boards shown are, in which one circuit board is the first circuit board and the other circuit board is the second circuit board.

[0133] In practical implementation, the materials of the same-named film layers in the first and second circuit substrates can be the same or different. For example, the material of the first dielectric layer in the first circuit substrate and the material of the first dielectric layer in the second circuit substrate can be the same or different, and this is not limited here. However, in actual production, multiple circuit substrates are usually formed simultaneously on a large carrier board, and then cut to form multiple independent circuit substrates. In this way, the materials of the same-named film layers in different circuit substrates are the same.

[0134] Step S202, as follows Figure 10a As shown, a second dielectric layer 105 is laminated between a first circuit substrate 100a and a second circuit substrate 100b, and the carrier plate 101 of the first circuit substrate 100a and the carrier plate 101 of the second circuit substrate 100b are both located on the side away from the second dielectric layer 105, that is, the metal trace 104 side of the first circuit substrate 100a is disposed opposite to the metal trace 104 side of the second circuit substrate 100b.

[0135] In specific implementation, the material of the second dielectric layer 105 may be a material containing at least one of bismaleimide triazine resin, polyarylamide fiber, epoxy resin, polyphenylene ether or glass fiber, and is not limited herein.

[0136] For example, in order to improve the consistency of materials between adjacent dielectric layers, the material of the second dielectric layer 105 may be the same as the material of the first dielectric layer 103 in the first circuit substrate 100a and the material of the first dielectric layer 103 in the second circuit substrate 100b.

[0137] Step S203, as follows Figure 10b As shown, the carrier 101 and metal layer 102 in the second circuit board 100b are removed.

[0138] Step S204, as Figure 10c As shown, a third dielectric layer 106 is formed on the side of the first dielectric layer 103 of the second circuit substrate 100b away from the second dielectric layer 105.

[0139] In practice, the third dielectric layer 106 can be formed on the metal layer using a semi-cured material through a pressing process or a coating process.

[0140] For example, the material of the third dielectric layer 106 may be a material comprising at least one of bismaleimide triazine resin, polyarylamide fiber, epoxy resin, polyphenylene ether or glass fiber, without limitation herein.

[0141] This application does not limit the thickness of the third dielectric layer 106, and it can be designed according to actual needs. Generally speaking, the thinner the third dielectric layer 106, the higher the precision of the hollow area formed by the subsequent laser ablation process.

[0142] Step S205, as follows Figure 10d As shown, a via V is formed by laser ablation process, which penetrates the third dielectric layer 106, the metal trace 104 in the second circuit substrate 100b, and the second dielectric layer 105.

[0143] In this application, since the via V needs to penetrate the third dielectric layer 106, the metal trace 104 in the second circuit board 100b, and the second dielectric layer 105, the thinner the film layers that the via V needs to penetrate, the better the accuracy. Therefore, the thicknesses of the third dielectric layer 106, the second dielectric layer 105, and the first dielectric layer 103 can be set according to the actual product performance requirements, making them as thin as possible.

[0144] Step S206, as follows Figure 10e As shown, conductive material 107 is formed in via V to electrically connect the metal trace 104 in the first circuit board 100a with the metal trace 104 in the second circuit board 100b.

[0145] This application does not limit the conductive material 107 in the via V. For example, the conductive material 107 can be gold, silver, copper, platinum, tin, etc.

[0146] This application does not limit the method of forming the conductive material 107 in the via V; it can be any method that enables the formation of the conductive material 107 in the via V. For example, the conductive material 107 can be formed directly in the via V by electroplating.

[0147] Step S207: Remove the carrier 101 and metal layer 102 from the first circuit board 100a to form a... Figure 11 The encapsulation carrier board 10 shown.

[0148] In practical implementation, the following methods can also be adopted: Figure 7 The circuit board shown is combined as follows Figure 8 The circuit board shown is used to prepare a packaging carrier. The preparation method of the packaging carrier may include the following steps:

[0149] Step S301, provide two such as Figure 7 The circuit boards shown are respectively used as second circuit boards, providing a such Figure 8 The circuit board shown is the first circuit board.

[0150] In practical implementation, the materials of the same-named film layers in the first and second circuit substrates can be the same or different. For example, the material of the first dielectric layer in the first circuit substrate and the material of the first dielectric layer in the second circuit substrate can be the same or different, and this is not limited here. However, in actual production, multiple circuit substrates are usually formed simultaneously on a large carrier board, and then cut to form multiple independent circuit substrates. In this way, the materials of the same-named film layers in different circuit substrates are the same.

[0151] In specific implementation, the first circuit board has two sides, and the following steps are performed on either side of the first circuit board:

[0152] Step S302, as follows Figure 10a As shown, a second dielectric layer 105 is laminated between a first circuit substrate 100a and a second circuit substrate 100b, and the carrier plate 101 of the first circuit substrate 100a and the carrier plate 101 of the second circuit substrate 100b are both located on the side away from the second dielectric layer 105, that is, the metal trace 104 side of the first circuit substrate 100a is disposed opposite to the metal trace 104 side of the second circuit substrate 100b.

[0153] In specific implementation, the material of the second dielectric layer 105 may be a material containing at least one of bismaleimide triazine resin, polyarylamide fiber, epoxy resin, polyphenylene ether or glass fiber, and is not limited herein.

[0154] For example, in order to improve the consistency of materials between adjacent dielectric layers, the material of the second dielectric layer 105 may be the same as the material of the first dielectric layer 103 in the first circuit substrate 100a and the material of the first dielectric layer 103 in the second circuit substrate 100b.

[0155] Step S303, as follows Figure 10b As shown, the carrier 101 and metal layer 102 in the second circuit board 100b are removed.

[0156] Step S304, as Figure 10c As shown, a third dielectric layer 106 is formed on the side of the first dielectric layer 103 of the second circuit substrate 100b away from the second dielectric layer 105.

[0157] In practice, the third dielectric layer 106 can be formed on the metal layer using a semi-cured material through a pressing process or a coating process.

[0158] For example, the material of the third dielectric layer 106 may be a material comprising at least one of bismaleimide triazine resin, polyarylamide fiber, epoxy resin, polyphenylene ether or glass fiber, without limitation herein.

[0159] This application does not limit the thickness of the third dielectric layer 106, and it can be designed according to actual needs. Generally speaking, the thinner the third dielectric layer 106, the higher the precision of the hollow area formed by the subsequent laser ablation process.

[0160] Step S305, as follows Figure 10d As shown, a via V is formed by laser ablation process, which penetrates the third dielectric layer 106, the metal trace 104 in the second circuit substrate 100b, and the second dielectric layer 105.

[0161] In this application, since the via V needs to penetrate the third dielectric layer 106, the metal trace 104 in the second circuit board 100b, and the second dielectric layer 105, the thinner the film layers that the via V needs to penetrate, the better the accuracy. Therefore, the thicknesses of the third dielectric layer 106, the second dielectric layer 105, and the first dielectric layer 103 can be set according to the actual product performance requirements, making them as thin as possible.

[0162] Step S306, as follows Figure 10e As shown, conductive material 107 is formed in via V to electrically connect the metal trace 104 in the first circuit board 100a with the metal trace 104 in the second circuit board 100b.

[0163] This application does not limit the conductive material 107 in the via V. For example, the conductive material 107 can be gold, silver, copper, platinum, tin, etc.

[0164] This application does not limit the method of forming the conductive material 107 in the via V; it can be any method that enables the formation of the conductive material 107 in the via V. For example, the conductive material 107 can be formed directly in the via V by electroplating.

[0165] Finally, after steps S302 to S306 have been completed on both sides of the first circuit board, the following steps are performed:

[0166] Step S307: Remove the carrier 101 and metal layer 102 from the first circuit board 100a to form two... Figure 11 The packaging substrate shown.

[0167] See Figure 11 , Figure 11An exemplary schematic diagram of a packaging substrate prepared using the preparation method provided in this application is shown. The packaging substrate 10 may include a first circuit layer and a stacked structure L1 layered on the first circuit layer. The first circuit layer may include a first dielectric layer 103 and metal traces 104 filling the hollow areas of the first dielectric layer 103. The stacked structure L1 may include a second dielectric layer 105, a second circuit layer, and a third dielectric layer 106 stacked sequentially, vias penetrating the third dielectric layer 106, the second circuit layer, and the second dielectric layer 105, and conductive material 107 filling the vias; in this stacked structure L1, the second circuit layer is located between the second dielectric layer 105 and the third dielectric layer 106, and the second dielectric layer 106 is located closer to the first circuit layer; the second circuit layer may include a fourth dielectric layer 108 (i.e., the first dielectric layer in the second circuit substrate used in the fabrication process) and metal traces 104 filling the hollow areas of the fourth dielectric layer 108; the first circuit layer and the second circuit layer in the adjacent stacked structure L1 may be electrically connected through the conductive material 107 in the vias.

[0168] The packaging substrate provided in this application has two advantages. First, since each metal trace is formed using the circuit substrate provided in this application, the packaging substrate formed in this application can achieve high precision for each metal trace compared to circuit layers formed using photolithography. Second, since the metal traces are embedded in the first dielectric layer, the third dielectric layer located between adjacent metal trace layers, and the... Figure 12 Compared to filling the space between two metal traces with dielectric material, the dielectric material between the two metal traces can be thinner. That is, in this application, the third dielectric layer only needs to separate the two metal traces. Figure 12 The dielectric material in this application not only needs to fill the gaps between metal traces in the same layer, but also needs to separate the two metal traces. Therefore, the amount of dielectric material required must be sufficient, resulting in a relatively thick dielectric material (h) between the two metal traces. Thus, the packaging substrate of this application can achieve a thinner thickness. Thirdly, in this application, a third dielectric layer is used instead of photoresist, and vias connecting different metal trace layers are formed through laser ablation. This improves the accuracy of the vias in the packaging substrate, thereby enhancing the overall circuit accuracy of the packaging substrate. Fourthly, in this application, the bottom of the vias directly contacts the metal traces, eliminating the need for conventional chemical plating. Furthermore, conductive materials can be electroplated inside the vias without the need for special materials. Therefore, conventional processes and materials can be used, resulting in lower costs.

[0169] The above embodiments of this application are only illustrated by taking the formation of two circuit layers in the packaging substrate as an example. Of course, multiple circuit layers can also be formed in the packaging substrate. The method of continuing to stack circuit layers in the packaging substrate can be found in steps S202 to S206. The following is an illustrative example of continuing to stack one circuit layer in the packaging substrate.

[0170] Furthermore, such as Figure 13 As shown, the preparation method may further include:

[0171] Step S401, as follows Figure 14a As shown, a... Figure 7 The third circuit substrate 100c shown has a first stacked structure L1 consisting of a second dielectric layer 105, a first dielectric layer 103, a metal trace 104, a third dielectric layer 106, and a conductive material 107 located above the first circuit substrate 100a. A second dielectric layer 105 is laminated between the first stacked structure L1 and the third circuit substrate 100c, and the carrier plate 101 of the third circuit substrate 100c is located on the side away from the first stacked structure L1.

[0172] Step S402, as Figure 14b As shown, the carrier 101 and metal layer 102 in the third circuit board 100c are removed.

[0173] Step S403, as Figure 14c As shown, a third dielectric layer 106 is formed on the first dielectric layer 103 of the third circuit substrate 100c.

[0174] Step S404, as follows Figure 14d As shown, a via V is formed by laser ablation process, penetrating the newly formed third dielectric layer 106, the metal trace 104 in the third circuit substrate 100c, and the newly formed second dielectric layer 105.

[0175] Step S405, as follows Figure 14e As shown, conductive material 107 is formed in via V to electrically connect the metal trace 104 in the second circuit board 100b with the metal trace 104 in the third circuit board 100c.

[0176] The specific implementation methods of steps S401 to S405 can be found in steps S202 to S206, and will not be repeated here.

[0177] Similarly, circuit layers can be further formed in the packaging substrate, which will not be elaborated here.

[0178] See Figure 15 , Figure 15An exemplary schematic diagram of another packaging substrate provided in an embodiment of this application is shown. In this packaging substrate 10, a multi-layer stacked structure Ln is stacked on the first circuit layer. Figure 15 The following diagram illustrates a three-layer stacked structure L1 to Ln in the packaging substrate 10. Each layer Ln may include a second dielectric layer 105, a second circuit layer, and a third dielectric layer 106 stacked sequentially, a via V penetrating the third dielectric layer 106, the second circuit layer, and the second dielectric layer 105, and a conductive material 107 filling the via V; the second circuit layers in any two adjacent layers Ln and Ln+1 are electrically connected through the conductive materials in the adjacent layers Ln and Ln+1.

[0179] See Figure 16 In the packaging substrate 10, in the stacked structure L1 furthest from the first circuit layer, the vias V in the stacked structure L1 include a first via V1 penetrating the third dielectric layer 106, and a second via V2 penetrating the metal trace in the second circuit layer and the second dielectric layer 105; the orthographic projection of the first via V1 on the first circuit layer covers the orthographic projection of the second via V2 on the first circuit layer, that is, the first via V1 covers the second via V2, and the area of ​​the first via V1 is greater than or equal to the area of ​​the second via V2. Thus... Figure 17 As shown, after forming conductive material 107 in via V, the area of ​​conductive material 107 in the outermost via of the encapsulation substrate 10 can be increased, thereby increasing the conductive contact area between the encapsulation substrate 10 and other electrical components.

[0180] Thus, during fabrication, when stacking the last layer of traces, and when forming the metal traces penetrating the third dielectric layer, the second circuit substrate, and the vias in the second dielectric layer, as follows: Figure 16 As shown, a first via V1 penetrating the third dielectric layer 106 can be formed first by laser ablation; then a second via V2 penetrating the metal trace 104 in the second dielectric layer 105 and the second circuit substrate can be formed by laser ablation, and the first via V1 is formed in the first circuit substrate ( Figure 16 The orthographic projection of the first dielectric layer 103 and metal trace 104 in the first circuit substrate is only shown, which covers the orthographic projection of the second via V2 in the first circuit substrate.

[0181] Furthermore, in this application, such as Figure 18As shown, in the packaging substrate 10, in each layer of the stacked structure Ln, the via V in the stacked structure Ln includes a first via V1 penetrating the third dielectric layer 106, and a second via V2 penetrating the metal trace in the second circuit layer and the second dielectric layer 105. The orthographic projection of the first via V1 on the first circuit layer covers the orthographic projection of the second via V2 on the first circuit layer. In this way, the area of ​​the upper surface of the conductive material 107 in the via V can be increased. Thus, when the area of ​​the upper surface of the conductive material 107 is increased, even if the position of the via V formed in the stacked structure Ln is slightly incorrect, it can still form good contact with the conductive material 107.

[0182] In the packaging carrier 10 provided in the embodiments of this application, such as Figure 18 As shown, the pattern of the metal trace 104 in the first dielectric layer 103 can be designed according to the actual product and is not limited here. Generally, the patterns of the metal trace 104 in different first dielectric layers 103 are different, and the metal traces 104 located in different first dielectric layers 103 can be electrically connected through the conductive material 107 in the via V.

[0183] Furthermore, in this application, after forming the conductive material 107 in the via V, the process may further include: removing the third dielectric layer 106 and the conductive material 107 located within the via of the third dielectric layer 106, i.e., removing the conductive material 107 located above the metal trace 104 in the second circuit substrate 100b. The formed packaging substrate is as follows: Figure 19 and Figure 20 As shown, the stacked structure Ln of the packaging substrate 10 includes only the second dielectric layer 105 and the second circuit layer, which can further reduce the thickness of the packaging substrate. In specific implementations, the third dielectric layer may be omitted from part of the stacked structure Ln, or the third dielectric layer may be omitted from all stacked structures; this is not limited here.

[0184] In this application, solder mask layers may also be included on both sides of the encapsulation substrate, and no limitation is made here.

[0185] Optionally, in this application, to improve material consistency, at least two of the first, second, third, and fourth dielectric layers are made of the same material. Of course, in specific implementations, different dielectric layers may also be made of different materials, which is not limited here.

[0186] Optionally, in this application, the metal traces in different circuit layers are made of the same material. This allows different circuit layers to be formed using the same process, thereby reducing costs.

[0187] Of course, in practice, the materials of the metal traces in different circuit layers can also be different.

[0188] Optionally, in this application, the conductive material in the via can be the same as the material of the metal trace in the circuit layer.

[0189] Correspondingly, such as Figure 21 As shown, this application embodiment also provides a packaging structure 3, including any of the above-described packaging substrates 10, and a chip 20 molded onto one side of the packaging substrate 10. Since the principle of this packaging structure 3 in solving the problem is similar to that of the aforementioned packaging substrate 10, the implementation of this packaging structure 3 can refer to the implementation of the aforementioned packaging substrate 10, and the repeated parts will not be described again.

[0190] In one feasible implementation, this encapsulation structure can be formed through the following steps:

[0191] Step S501, as follows Figure 22a As shown, when preparing the packaging carrier 10, after forming a target number of circuit layers on the first circuit substrate 100a, and before removing the carrier 101 and metal layer 102 from the first circuit substrate 100a, the chip 20 is bonded on the side away from the first circuit substrate 100a.

[0192] Step S502, as follows Figure 22b As shown, chip 20 is encapsulated using molding compound 210.

[0193] Step S503: Remove the carrier 101 and metal layer 102 from the first circuit board 100a, thereby forming as shown in the figure. Figure 21 The packaging structure shown is 3.

[0194] Furthermore, a solder resist layer may also be formed on the side of the packaging substrate 10 away from the chip 20, etc., which is not limited here.

[0195] Furthermore, such as Figure 23 As shown, solder balls 001 can also be implanted on the side of the packaging substrate 10 away from the chip 20 to facilitate subsequent soldering of the packaging structure 3 to the circuit board.

[0196] Correspondingly, such as Figure 24 As shown, this application embodiment also provides another packaging structure 3, including a packaging substrate 10 and a chip 20 molded onto one side of the packaging substrate 10. The packaging substrate 10 may include at least one layer of stacked structure Ln. Figure 24The following diagram illustrates a two-layer stacked structure L1 and L2 in the packaging substrate 10. Each layer Ln includes a second dielectric layer 105, a circuit layer, and a third dielectric layer 106. The circuit layer includes a first dielectric layer 103 and metal traces 104 filling the cutout areas of the first dielectric layer 103. The layered structure Ln has vias V that penetrate the second dielectric layer 105, the metal traces 104 of the circuit layer, and the third dielectric layer 106. The vias V are filled with conductive material 107.

[0197] In one feasible implementation, this encapsulation structure can be formed through the following steps:

[0198] Step S601, as follows Figure 25a As shown, chip 20 is encapsulated using molding compound 210.

[0199] Step S602, as follows Figure 25b As shown, a second dielectric layer 105 is laminated between the molding compound 210 and the circuit board 100.

[0200] Step S603, as follows Figure 25c As shown, the carrier 101 and metal layer 102 in the circuit board 100 are removed, and a third dielectric layer 106 is formed on the side of the first dielectric layer 103 away from the second dielectric layer 105. A via is formed through the third dielectric layer 106, the metal trace 104 in the circuit board 100 and the second dielectric layer 105 by laser ablation process. A conductive material 107 is formed in the via, thereby forming a stacked structure L1.

[0201] Step S604: A second dielectric layer 105 is laminated between the stacked structure L1 and the circuit board 100; the carrier 101 and metal layer 102 in the circuit board 100 are removed, and a third dielectric layer 106 is formed on the side of the first dielectric layer 103 away from the second dielectric layer 105; a via V is formed through the third dielectric layer 106, the metal trace 104 in the circuit board 100, and the second dielectric layer 105 by laser ablation process; a conductive material 107 is formed in the via V, thereby forming the second stacked structure L2, and thus forming the structure as shown in the figure. Figure 24 The encapsulation structure 3 shown has two stacked structures L1 and L2 forming a packaging carrier 10.

[0202] In practical implementation, when the packaging carrier board of the packaging structure includes a multi-layer stacked structure, step S604 can be repeated until the target number of stacked layers is formed, which will not be elaborated here.

[0203] This application does not limit the conductive material in the via. For example, the conductive material can be gold, silver, copper, platinum, tin, etc.

[0204] This application does not limit the method of forming conductive material in vias; any method can be used to form conductive material in vias. For example, conductive material can be formed in vias directly by electroplating.

[0205] Furthermore, such as Figure 26 As shown, solder balls 001 can also be implanted on the side of the packaging substrate 10 away from the chip 20 to facilitate subsequent soldering of the packaging structure 3 to the circuit board.

[0206] Accordingly, this application also provides an electronic device, such as Figure 3 As shown, it includes: a housing 1, a circuit board 2 located within the housing 1, and a packaging structure 3; the packaging structure 3 is located on the circuit board 2, and the packaging module 3 is electrically connected to the circuit board 2. For example, the circuit board can be a PCB. Since the principle by which this electronic device solves the problem is similar to that of the aforementioned packaging structure 3, the implementation of this electronic device can refer to the implementation of the aforementioned packaging structure 3, and repeated details will not be elaborated further.

[0207] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of protection of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A packaging carrier board (10), characterized in that, include: The first circuit layer includes a first dielectric layer (103) and metal traces (104) filling the hollow area of ​​the first dielectric layer (103). A stacked structure (Ln) is stacked on the first circuit layer, the stacked structure (Ln) comprising: a second dielectric layer (105), a second circuit layer and a third dielectric layer (106) stacked sequentially, a via (V) penetrating the third dielectric layer (106), the second circuit layer and the second dielectric layer (105), and a conductive material (107) filling the via (V); wherein: The second dielectric layer (105) is located on the side close to the first circuit layer, and the second circuit layer is located between the second dielectric layer (105) and the third dielectric layer (106); The second circuit layer includes a fourth dielectric layer (108) and metal traces (104) filling the hollow area of ​​the fourth dielectric layer (108), and the vias penetrate the metal traces (104) of the second circuit layer. The first circuit layer and the second circuit layer in the adjacent stacked structure (Ln) are electrically connected through the conductive material (107); In the stack structure (Ln) furthest from the first line layer, the via (V) in the stack structure (Ln) includes: a first via (V1) penetrating the third dielectric layer (106), and a second via (V2) penetrating the metal trace (104) and the second dielectric layer (105) in the second line layer; the orthographic projection of the first via (V1) on the first line layer covers the orthographic projection of the second via (V2) on the first line layer.

2. The packaging carrier (10) as described in claim 1, characterized in that, The first line layer has multiple layers of the aforementioned stacked structure (Ln); The second circuit layer in any two adjacent stacked structures (Ln) is electrically connected through the conductive material (107) in the two adjacent stacked structures (Ln).

3. The packaging carrier (10) as described in claim 1 or 2, characterized in that, At least two of the first dielectric layer (103), the second dielectric layer (105), the third dielectric layer (106), and the fourth dielectric layer (108) are made of the same material.

4. The packaging carrier (10) as described in any one of claims 1-3, characterized in that, The metal traces (104) in the first circuit layer are made of the same material as the metal traces (104) in the second circuit layer.

5. The packaging carrier (10) as described in any one of claims 1-4, characterized in that, The conductive material (107) is the same as the material of the metal trace (104).

6. A packaging structure (3), characterized in that, It includes a packaging substrate (10) as described in any one of claims 1-5, and a chip (20) encapsulated on one side of the packaging substrate.

7. An electronic device, characterized in that, It includes a housing (1), a circuit board (2) located within the housing (1), and a packaging structure (3) as described in claim 6 located on the circuit board (2).

8. A method for preparing a packaging carrier plate (10), characterized in that, include: Two circuit boards (100a and 100b) are provided, each circuit board (100a and 100b) comprising: a carrier board (101) having two opposing surfaces; a metal layer (102) on one of the two surfaces; a first dielectric layer (103) on the side of the metal layer (102) away from the carrier board (101), and the first dielectric layer (103) having a plurality of cutout regions (1030); and metal traces (104) filling each of the cutout regions (1030) of the first dielectric layer (103); one of the two circuit boards is a first circuit board (100a) and the other circuit board is a second circuit board (100b). A second dielectric layer (105) is laminated between the first circuit substrate (100a) and the second circuit substrate (100b), and the carrier plate (101) of the first circuit substrate (100a) and the carrier plate (101) of the second circuit substrate (100b) are both located on the side away from the second dielectric layer (105). Remove the carrier board (101) and metal layer (102) from the second circuit substrate (100b). A third dielectric layer (106) is formed on the side of the first dielectric layer (103) of the second circuit substrate (100b) away from the second dielectric layer (105). A via (V) is formed by laser ablation process, which penetrates the third dielectric layer (106), the metal trace (104) in the second circuit substrate (100b), and the second dielectric layer (105). Conductive material (107) is formed in the via (V) to electrically connect the metal traces (104) in the first circuit board (100a) with the metal traces (104) in the second circuit board (100b); Remove the carrier board (101) and metal layer (102) from the first circuit substrate (100a). A via (V) is formed by laser ablation process, penetrating the third dielectric layer (106), the metal trace (104) in the second circuit substrate (100b), and the second dielectric layer (105), including: A first via (V1) is formed through the third dielectric layer (106) by laser ablation process. A second via (V2) is formed by a laser ablation process, which penetrates the metal trace (104) in the second dielectric layer (105) and the second circuit substrate (100b). The orthographic projection of the first via (V1) on the first circuit substrate (100a) covers the orthographic projection of the second via (V2) on the first circuit substrate (100a).

9. The preparation method according to claim 8, characterized in that, A conductive material (107) is formed in the via (V), comprising: Conductive material (107) is formed in the via (V) by electroplating.

10. The preparation method according to claim 8 or 9, characterized in that, After forming the conductive material (107) in the via (V), the process further includes: Remove the third dielectric layer (106) and the conductive material (107) located in the vias of the third dielectric layer (106).

11. A method for preparing a packaging carrier plate (10), characterized in that, include: Three circuit boards (100a and 100b) are provided, each circuit board (100a and 100b) comprising: a carrier board (101) having two opposing surfaces; a metal layer (102) on at least one of the two surfaces; a first dielectric layer (103) on the side of the metal layer (102) away from the carrier board (101), and the first dielectric layer (103) having a plurality of cutout regions (1030); and metal traces (104) filling each of the cutout regions (1030) of the first dielectric layer (103); wherein one of the three circuit boards is a first circuit board (100a) and the other two circuit boards are second circuit boards (100b), the first circuit board (100a) comprising two metal layers (102) and two first dielectric layers (103), and each of the second circuit boards comprising one metal layer (102) and one first dielectric layer (103). The first circuit board (100a) has two sides, and regarding either side of the first circuit board (100a): A second circuit substrate (100b) is superimposed on the first circuit substrate (100a), and a second dielectric layer (105) is laminated between the first circuit substrate (100a) and the second circuit substrate (100b), and the carrier plate (101) of the first circuit substrate (100a) and the carrier plate (101) of the second circuit substrate (100b) are both located on the side away from the second dielectric layer (105); Remove the carrier board (101) and metal layer (102) from the second circuit substrate (100b). A third dielectric layer (106) is formed on the side of the first dielectric layer (103) of the second circuit substrate (100b) away from the second dielectric layer (105). A via (V) is formed by laser ablation process, which penetrates the third dielectric layer (106), the metal trace (104) in the second circuit substrate (100b), and the second dielectric layer (105). Conductive material (107) is formed in the via (V) to electrically connect the metal trace (104) in the first circuit board (100a) with the metal trace (104) in the second circuit board (100b); After the conductive material (107) is formed on both sides of the first circuit substrate (100a), the carrier plate (101) and the metal layer (102) in the first circuit substrate (100a) are removed. A via (V) is formed by laser ablation process, penetrating the third dielectric layer (106), the metal trace (104) in the second circuit substrate (100b), and the second dielectric layer (105), including: A first via (V1) is formed through the third dielectric layer (106) by laser ablation process. A second via (V2) is formed by a laser ablation process, which penetrates the metal trace (104) in the second dielectric layer (105) and the second circuit substrate (100b). The orthographic projection of the first via (V1) on the first circuit substrate (100a) covers the orthographic projection of the second via (V2) on the first circuit substrate (100a).

12. The preparation method according to claim 11, characterized in that, A conductive material (107) is formed in the via (V), comprising: Conductive material (107) is formed in the via (V) by electroplating.

13. The preparation method according to claim 11 or 12, characterized in that, After forming the conductive material (107) in the via (V), the process further includes: Remove the third dielectric layer (106) and the conductive material (107) located in the vias of the third dielectric layer (106).

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