FPGA logic parallel loading circuit fault diagnosis system and method

Abstract

The application provides a FPGA logic parallel loading circuit fault diagnosis system and method, which comprises: a logic parallel loading circuit formed by interconnection of a FPGA chip and a PROM chip; a plurality of signal points between the FPGA chip and the PROM chip are taken as specific test points; the system further comprises a microprocessor, which accesses a host interface designed in the FPGA chip through an external host interface, samples signals on the specific test points through a discrete quantity interface, reads JTAG interface information of the FPGA module through a JTAG interface, executes a fault diagnosis program, intelligently analyzes test results in combination with external tests between the specific test points, and accurately locates fault points of the logic parallel loading circuit. The application realizes intelligent detection and analysis of the FPGA logic parallel loading circuit, and greatly improves detection efficiency and positioning accuracy of FPGA logic loading abnormality related faults.

Description

Technical Field

[0001] This invention relates to the field of embedded system design technology for FPGAs, and specifically to a fault diagnosis system and method for FPGA logic parallel loading circuits. Background Technology

[0002] FPGA-based embedded system design technology is widely used in various high-tech application fields. By loading different logic, the functional circuit with FPGA as the core can realize different functions. Currently, FPGA logic loading is mostly implemented by parallel loading circuit design. The logic is stored in PROM and loaded into FPGA by PROM after power-on.

[0003] Embedded products used in next-generation avionics systems are characterized by high module density and complex operating environments. During module production, debugging, and field use, various problems such as chip, soldering, solder joints, and power supply often occur, causing FPGAs to fail to load logic properly, which in turn leads to product malfunction. In parallel loading circuits, both FPGA and PROM devices are BGA packaged devices with numerous signals, and the lack of external test points makes it difficult to test them, resulting in extremely complex and difficult logic loading fault location. Summary of the Invention

[0004] In view of this, the present application provides a fault diagnosis method for FPGA logic parallel loading circuit, which realizes intelligent detection and analysis of FPGA logic parallel loading circuit faults caused by abnormalities in chips, soldering, solder joints, power supply, etc., which greatly improves the detection efficiency and location accuracy of FPGA logic loading abnormality related faults.

[0005] This application provides the following technical solution: a fault diagnosis system for FPGA logic parallel loading circuits, comprising:

[0006] A logic parallel loading circuit formed by interconnecting an FPGA chip and a PROM chip; multiple signal points between the FPGA chip and the PROM chip are used as specific test points;

[0007] It also includes a microprocessor, which accesses the host interface designed inside the FPGA chip through an external host interface, samples the signals at the specific test points through a discrete interface, and reads the JTAG interface information of the FPGA module through a JTAG interface to execute a fault diagnosis program. At the same time, it combines impedance detection and signal waveform detection between specific test points to perform intelligent analysis of the test results and accurately locate the fault point of the logic parallel loading circuit.

[0008] According to one embodiment of this application, the FPGA chip is internally designed with a PROM access control unit, and the microprocessor performs access control operations on the PROM access control unit through the host interface to perform read / write access control on the PROM chip.

[0009] According to one embodiment of this application, the PROM access control unit includes a host interface and a PROM control interface. The PROM access control unit receives PROM read / write commands issued by the host through the host interface, parses them, and then executes the PROM read / write commands on the PROM chip through the PROM control interface.

[0010] According to one embodiment of this application, the plurality of signal points include the solder joints of pull-up / pull-down resistor signal terminals and power signal points between the FPGA chip and the PROM chip.

[0011] This application also provides a fault diagnosis method based on the above-mentioned FPGA logic parallel loading circuit fault diagnosis system, including:

[0012] Multiple signal points between the FPGA chip and the PROM chip are used as specific test points;

[0013] A microprocessor is used to control access to the PROM access control unit designed inside the FPGA chip, sample the signals at the specific test points, and read the JTAG interface information of the FPGA module to execute a fault diagnosis program. Combined with the signal waveform detection and impedance detection methods at the specific test points, the test results are intelligently analyzed, and finally the FPGA loading failure fault is located to the specific failure signal and the specific FPGA or PROM failure pin.

[0014] According to one embodiment of this application, the detection types in the fault diagnosis program include:

[0015] DONE (load complete) signal detection, PROGRAM_B signal detection, INIT_B signal detection, M0, M1, M2 mode selection signal detection, CLK clock signal detection, W (write) signal detection, R (read) signal detection, CS (chip select) signal detection, data signal detection, and address signal detection.

[0016] According to one embodiment of this application, a power supply test is performed before the fault diagnosis program begins. The power supply test involves the microprocessor testing the voltages of the parallel loading logic circuit, including: FPGA core voltage VCC_INT, FPGA configuration circuit voltage VCC_CFG, FPGA auxiliary voltage VCC_AUX, FPGA interface voltage VCCO, PROM power supply voltages VCC_1.8V and VCC_3.3V. If any of these voltage values ​​is incorrect, the diagnosis result is an abnormal power supply to the relevant voltage. If the start-up time between the voltages does not meet the power-on sequence requirements, the diagnosis is an abnormal power-on sequence, and the test results are output via a serial port.

[0017] According to one embodiment of this application, the signal waveform detection and impedance detection method includes: defining the solder joint of the pull-up / pull-down resistor signal terminal between the FPGA chip and the PROM chip as a specific test point, measuring the static resistance value of the solder joint of the pull-up / pull-down resistor signal terminal using a multimeter, and measuring the signal waveform at the solder joint of the pull-up / pull-down resistor signal terminal using an oscilloscope.

[0018] This invention addresses the problem of logic loading failure and difficulty in fault location in FPGA logic parallel loading circuits during production and use due to abnormalities in chips, soldering, solder joints, and power supply. It innovatively proposes a fault diagnosis method for FPGA logic parallel loading circuits, achieving intelligent detection and analysis of related faults, significantly improving the detection efficiency and location accuracy of FPGA logic loading anomalies. The specific technical effects are as follows:

[0019] (1) This invention provides an effective means of fault detection: for the interconnection circuit of dual BGA devices composed of FPGA and PROM, an effective means of fault detection is provided;

[0020] (2) This invention provides a test method for interconnect signals without test points: for the direct connection signals between FPGA and PROM, it provides an intelligent detection method based on host interface access;

[0021] (3) Intelligent analysis and fault location: Design a PROM access control unit, and the microprocessor performs diagnostic test operations. Combined with relevant external test results, intelligent analysis and location of relevant fault points in the FPGA logic parallel loading circuit. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a circuit diagram for fault diagnosis of the FPGA logic parallel loading circuit according to an embodiment of the present invention. Detailed Implementation

[0024] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0025] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments, providing a clear and complete description of the technical solutions of the present invention. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0026] like Figure 1 As shown, this invention provides a fault diagnosis system for FPGA logic parallel loading circuits. The FPGA logic parallel loading circuit fault diagnosis method is based on a microprocessor executing a fault diagnosis program. It controls access to the host interface designed internally by the FPGA through external host access interfaces and discrete quantity interfaces, samples power supply and related control signals, and reads the FPGA's JTAG interface information. The FPGA internally designs a PROM access control unit, which the microprocessor can operate through the host interface to achieve read / write access control of the PROM. The microprocessor executes diagnostic test operations, combines relevant external tests, and performs intelligent analysis based on the test results to accurately locate fault points related to chips, soldering, solder joints, power supply, etc., in the FPGA logic parallel loading circuit. This greatly improves the detection efficiency and location accuracy of FPGA logic loading anomaly-related faults.

[0027] This invention provides an intelligent detection method based on host interface access for the interconnect circuit of dual BGA devices composed of FPGA and PROM and the direct connection signal between FPGA and PROM. It designs a PROM access control unit, and the microprocessor performs diagnostic test operations. Combined with relevant external test results, it intelligently analyzes and locates relevant fault points in the FPGA logic parallel loading circuit.

[0028] This embodiment uses a microprocessor to execute a fault diagnosis program, and the fault diagnosis circuit design is as follows: Figure 1As shown, the interconnection between the FPGA and the PROM represents the basic connection relationship of a parallel logic loading circuit. The FPGA internally incorporates a PROM access control unit. The microprocessor controls access to the host interface designed within the FPGA via an external host interface, thereby implementing read / write access control of the PROM based on the PROM access control unit. The microprocessor samples power supply and related control signals through a discrete interface. Finally, the microprocessor reads the FPGA's JTAG interface information through the JTAG interface.

[0029] The PROM access control unit includes a host interface and a PROM control interface, and is capable of executing PROM read and write operations issued by the host. During the read and write process, the PROM access control unit first parses the read / write commands from the host interface, then sends the read / write commands to the PROM interface, and executes the command to end the operation at a specific time point; for read operations, it needs to latch the data on the bus at a specific time point and pass it to the host interface. The PROM access control unit and other main functional logic in the FPGA share the host interface resources and run in parallel with other functional logic.

[0030] The microprocessor performs diagnostic tests, combines them with relevant external tests, and performs intelligent analysis based on the test results to accurately locate faults in the FPGA logic parallel loading circuit.

[0031] The diagnostic method will be explained below with reference to relevant signals and specific operations.

[0032] (1) Power supply detection

[0033] The microprocessor tests the following voltages via the I / O interface: FPGA core voltage VCC_INT, FPGA configuration circuit voltage VCC_CFG, FPGA auxiliary voltage VCC_AUX, FPGA interface voltage VCCO, and PROM power supply voltages VCC_1.8V or VCC_3.3V. If any voltage value is incorrect, the diagnosis is an abnormal power supply to that voltage. If the startup time between any of the voltages does not meet the power-on sequence requirements, the diagnosis is a power-on sequence abnormality. The test results are output via serial port.

[0034] (2) DONE loading complete signal detection

[0035] Define point A as the solder joint of the "DONE Load Complete Signal" pin of the FPGA. After the module is powered on, the microprocessor reads the "DONE Load Complete Signal" status flag DONE_JTAG through the JTAG interface; the microprocessor reads the "DONE Load Complete Signal" status flag DONG_MCU through the IO interface; determine the faults related to the DONE Load Complete Signal according to the following diagnostic table, and output the test results through the serial port.

[0036] Table 1: DONE Loading Complete Signal Detection Table

[0037]

[0038] (3) PROGRAM_B signal detection

[0039] Define point B as the solder joint for the pull-up resistor of the "PROGRAM_B signal", point C as the solder joint for the "PROGRAM_B signal" pin on the FPGA, and point D as the solder joint for the "PROGRAM_B signal" pin on the PROM. Measure the static resistance value R_PROGRAM_B at point B using a multimeter. After the module powers on, the microprocessor reads the "PROGRAM_B signal" status flag PROGRAM_B_MCU through the I / O interface. Determine any faults related to the PROGRAM_B signal according to the diagnostic table below, and output the test results via serial port.

[0040] Table 2 PROGRAM_B Signal Detection Table

[0041]

[0042]

[0043] (4) INIT_B signal detection

[0044] Define point E as the solder joint for the pull-up resistor of the "INIT_B signal", point F as the solder joint for the "INIT_B signal" pin of the FPGA, and point G as the solder joint for the "INIT_B signal" pin of the PROM. Measure the static resistance value R_INIT_B at point E using a multimeter. After the module powers on, the microprocessor reads the "INIT_B signal" status flag INIT_B_MCU through the I / O interface. Determine any faults related to the INIT_B signal according to the following diagnostic table, and output the test results via serial port.

[0045] Table 3 INIT_B Signal Detection Table

[0046]

[0047] (5) Detection of M0, M1, and M2 mode selection signals

[0048] Define point H as the pull-up resistor signal terminal solder joint for the mode selection signal "M0", define point I as the pull-up resistor signal terminal solder joint for the mode selection signal "M1", define point G as the pull-up resistor signal terminal solder joint for the mode selection signal "M2", define point K as the solder joint for the "M0" pin of the FPGA, define point L as the solder joint for the "M1" pin of the FPGA, and define point M as the solder joint for the "M2" pin of the FPGA. At point H, measure the static resistance value R_M0 using a multimeter; at point I, measure the static resistance value R_M1 using a multimeter; and at point J, measure the static resistance value R_M2 using a multimeter. After the module is powered on, the microprocessor sets the status flags M0_MCU, M1_MCU, and M2_MCU for each signal via the I / O interface. The microprocessor also reads the status flags M0_JTAG, M1_JTAG, and M2_JTAG for each signal via the I / O interface. Use the diagnostic table below to determine the faults related to signals M0, M1, and M2, and output the test results via serial port.

[0049] Table 4 M0 Signal Detection Table

[0050]

[0051] Table 5M1 Signal Detection Table

[0052]

[0053]

[0054] Table 6 M2 Signal Detection Table

[0055]

[0056] (6) CLK clock signal detection

[0057] Define point N as the solder joint on the FPGA side where the crystal oscillator output terminal for the "CLK clock signal" is connected to the resistor; point O is the solder joint on the FPGA's "CLK clock signal" pin; and point P is the solder joint on the PROM's "CLK clock signal" pin. Measure the static resistance value R_CLK at point N using a multimeter. After the module powers on, measure the CLK clock signal waveform at point N using an oscilloscope. The microprocessor sets the values ​​of M0, M1, and M2 via the I / O interface to enable the FPGA to switch between Master active mode and Slave passive mode after power-on. When the FPGA is in Master active mode, the resistor at point N is removed, and the FPGA outputs the CLK clock signal to the PROM. When the FPGA is in Slave passive mode, the resistor at point N is retained, and the FPGA and PROM receive the CLK clock signal provided by the crystal oscillator. Determine the faults related to the INIT_B signal according to the following diagnostic table, and output the test results via serial port.

[0058] Table 7 CLK Clock Signal Detection Table

[0059]

[0060] (7) W-Write signal detection

[0061] Define point Q as the pull-up resistor signal solder joint for the "W write signal", point R as the "W write signal" pin solder joint on the FPGA, and point S as the "W write signal" pin solder joint on the PROM. Measure the static resistance value R_W at point Q using a multimeter. After the module is powered on, measure the waveform of the W write signal at point Q using an oscilloscope. The microprocessor controls the PROM access control unit to perform a write operation on the PROM through the host interface, and the "W write signal" status flag is W_PORT. Determine any faults related to the W write signal according to the following diagnostic table, and output the test results via serial port.

[0062] Table 8 W Write Signal Detection Table

[0063]

[0064] (8) R reading signal detection

[0065] Define point T as the solder joint for the pull-down resistor signal of the "R read signal", point U as the solder joint for the "R read signal" pin of the FPGA, and point V as the solder joint for the "R read signal" pin of the PROM. Measure the static resistance value R_R at point T using a multimeter. After the module is powered on, measure the waveform of the W write signal at point T using an oscilloscope. The microprocessor controls the PROM access control unit to perform write operations on the PROM through the host interface, and the "R read signal" status flag R_PORT is displayed. Determine any faults related to the R read signal according to the following diagnostic table, and output the test results via serial port.

[0066] Table 9R Read Signal Detection Table

[0067]

[0068] (9) CS chip select signal detection

[0069] Define point W as the solder joint for the pull-down resistor of the "CS chip select signal", point X as the solder joint for the "W write signal" pin of the FPGA, and point Y as the solder joint for the "CS chip select signal" pin of the PROM. Measure the static resistance value R_CS at point W using a multimeter. After the module is powered on, measure the waveform of the CS chip select signal at point W using an oscilloscope. The microprocessor controls the PROM access control unit to perform read / write operations on the PROM through the host interface. The "CS chip select signal" status flag is CS_PORT. Determine any faults related to the CS chip select signal according to the following diagnostic table, and output the test results via serial port.

[0070] Table 10 CS Chip Select Signal Detection Table

[0071]

[0072] (10) Data signal detection

[0073] Define point Z as the solder joint of the pull-down resistor for the "data signal". After the module is powered on, measure the waveform of the data signal at point Z using an oscilloscope. The microprocessor operates the PROM access control unit through the host interface, writing the values ​​0x0, 0x1, 0x2, 0x4, 0x8, ..., 0x80000, 0x100000, 0x200000, and 0x400000 sequentially into the specified address units of the PROM and reading the values ​​at those addresses. It then checks whether the values ​​match the expected values, and repeats this process of writing and reading these data to complete a traversal test of the high-level '1' of all data lines. The values ​​0xFFFFFF, 0xFFFFFE, 0xFFFFFD, 0xFFFFFB, 0Xfffff7…, 0Xf7FFFF, 0xEFFFFF, 0xDFFFFF, and 0xBFFFFF are sequentially written to the specified address units in the PROM, and the values ​​at those addresses are read out. The results are then compared to the expected values. This process of writing and reading these data is repeated to complete a traversal test of all data lines at a high level of '0'. Faults related to the CS chip select signal are diagnosed according to the following diagnostic table, and the test results are output via the serial port.

[0074] Table 11 Data Signal Detection Table

[0075]

[0076] (11) Address signal detection

[0077] The microprocessor operates the PROM access control unit through the host interface. For a contiguous address space in the PROM (covering the address lines to be tested), the current address value is assigned to the current address. First, a high-level "1" traversal is performed, followed by a low-level "0" traversal. The stored values ​​are read from the corresponding addresses sequentially and compared with the current address value to determine if the address bus read / write is correct. Then, the traversal order is reversed: first a "0" traversal, then a "1" traversal, and again the stored values ​​are read from the corresponding addresses sequentially and compared with the current address value to determine if the address bus read / write is correct. Faults related to the CS chip select signal are diagnosed according to the following diagnostic table, and the test results are output via serial port.

[0078] Table 12 Address Signal Detection Table

[0079]

[0080]

[0081] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A fault diagnosis system for FPGA logic parallel loading circuits, characterized in that, include: A logic parallel loading circuit formed by interconnecting an FPGA chip and a PROM chip; Multiple signal points between the FPGA chip and the PROM chip are used as specific test points; It also includes a microprocessor, which accesses the host interface designed inside the FPGA chip through the external host interface, samples the signals at the specific test points through the discrete interface, and reads the JTAG interface information of the FPGA module through the JTAG interface to execute the fault diagnosis program. At the same time, it combines impedance detection and signal waveform detection between specific test points to perform intelligent analysis of the test results and accurately locate the fault point of the logic parallel loading circuit. The FPGA chip is internally designed with a PROM access control unit. The microprocessor performs access control operations on the PROM access control unit through the host interface to perform read / write access control on the PROM chip. The PROM access control unit includes a host interface and a PROM control interface. The PROM access control unit receives PROM read / write commands issued by the host through the host interface, parses them, and then executes the PROM read / write commands on the PROM chip through the PROM control interface. The fault diagnosis method of the system includes: Multiple signal points between the FPGA chip and the PROM chip are used as specific test points; A microprocessor is used to control access to the PROM access control unit designed inside the FPGA chip, sample the signals at the specific test points, and read the JTAG interface information of the FPGA module to execute a fault diagnosis program. Combined with the signal waveform detection and impedance detection methods at the specific test points, the test results are intelligently analyzed, and finally the FPGA loading failure fault is located to the specific failure signal and the specific FPGA or PROM failure pin.

2. The FPGA logic parallel loading circuit fault diagnosis system according to claim 1, characterized in that, The multiple signal points include the solder joints of the pull-up / pull-down resistor signal terminals and the power signal points between the FPGA chip and the PROM chip.

3. The FPGA logic parallel loading circuit fault diagnosis system according to claim 1, characterized in that, The detection types in the fault diagnosis program include: DONE (load complete) signal detection, PROGRAM_B signal detection, INIT_B signal detection, M0, M1, M2 mode selection signal detection, CLK clock signal detection, W (write) signal detection, R (read) signal detection, CS (chip select) signal detection, data signal detection, and address signal detection.

4. The FPGA logic parallel loading circuit fault diagnosis system according to claim 1, characterized in that, Before the fault diagnosis program begins, a power supply test is performed. This test involves the microprocessor testing the voltages of the parallel loading logic circuit, including: FPGA core voltage VCC_INT, FPGA configuration circuit voltage VCC_CFG, FPGA auxiliary voltage VCC_AUX, FPGA interface voltage VCCO, and PROM power supply voltages VCC_1.8V and VCC_3.3V. If any of these voltage values ​​is incorrect, the diagnosis is an abnormal power supply to the relevant voltage. If the startup time between the voltages does not meet the power-on sequence requirements, the diagnosis is an abnormal power-on sequence. The test results are output via the serial port.

5. The FPGA logic parallel loading circuit fault diagnosis system according to claim 1, characterized in that, The signal waveform detection and impedance detection method includes: defining the solder joint of the pull-up / pull-down resistor signal terminal between the FPGA chip and the PROM chip as a specific test point; using a multimeter to measure the static resistance value of the solder joint of the pull-up / pull-down resistor signal terminal; and using an oscilloscope to measure the signal waveform at the solder joint of the pull-up / pull-down resistor signal terminal.

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