Display substrate and driving method thereof, and display device

Abstract

The present invention provides a display substrate and a driving method thereof, and a display device, which relate to the field of display technology, and are for solving the problem that a high-resolution liquid crystal display panel cannot achieve a high refresh rate. The display substrate includes: a display area and a peripheral area surrounding the display area; the display substrate also includes: a plurality of sub-pixels, the plurality of sub-pixels are located in the display area, and the plurality of sub-pixels are divided into a plurality of rows of sub-pixel rows; a plurality of shift register units, the plurality of shift register units are located in the peripheral area, the shift register units correspond to at least one row of sub-pixel rows, and the shift register units are respectively coupled to each sub-pixel in the corresponding sub-pixel row; the plurality of shift register units are divided into a plurality of shift register unit groups, the plurality of shift register unit groups are arranged in sequence, and each shift register unit group includes X shift register units, and the X shift register units simultaneously output gate drive signals to the sub-pixels coupled thereto, and X is an integer greater than or equal to 2.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a driving method thereof, and a display device. Background Art

[0002] With the continuous development of display technology, the application fields of liquid crystal display panels are becoming more and more extensive, and the corresponding requirements for the display quality and various display parameters of liquid crystal display panels are becoming higher and higher. High resolution and high refresh rate are one of the development trends of liquid crystal display panels. However, the current high-resolution liquid crystal display panels cannot achieve high refresh rates well. Summary of the invention

[0003] The object of the present invention is to provide a display substrate and a driving method thereof, and a display device, so as to solve the problem that a high-resolution liquid crystal display panel cannot achieve a high refresh rate.

[0004] In order to achieve the above object, the present invention provides the following technical solutions:

[0005] A first aspect of the present invention provides a display substrate, comprising: a display area and a peripheral area surrounding the display area; the display substrate further comprises:

[0006] A plurality of sub-pixels, the plurality of sub-pixels are located in the display area, and the plurality of sub-pixels are divided into a plurality of rows of sub-pixel rows;

[0007] A plurality of shift register units, the plurality of shift register units are located in the peripheral area, the shift register units correspond to at least one row of sub-pixels, and the shift register units are respectively coupled to each sub-pixel in the corresponding sub-pixel row;

[0008] The multiple shift register units are divided into multiple shift register unit groups, which are arranged in sequence, each shift register unit group includes X shift register units, and the X shift register units simultaneously output gate drive signals to the sub-pixels coupled thereto, where X is an integer greater than or equal to 2.

[0009] Optionally, the time periods of the gate driving signals output by adjacent shift register unit groups partially overlap in terms of the effective levels.

[0010] Optionally, the shift register unit group includes three shift register units, and the three shift register units are correspondingly coupled to three rows of sub-pixel rows; or, the shift register unit group includes four shift register units, and the four shift register units are correspondingly coupled to four rows of sub-pixel rows.

[0011] Optionally, the display substrate further includes: a first frame start signal line, a second frame start signal line and M clock signal lines, where M is a positive integer;

[0012] The first frame start signal line is coupled to the first shift register unit, the third shift register unit and the fifth shift register unit respectively;

[0013] The second frame start signal line is coupled to the second shift register unit, the fourth shift register unit and the sixth shift register unit respectively;

[0014] The display substrate includes N shift register units, where N is an integer greater than M;

[0015] The nth shift register unit is used to carry the n+M / 2th shift register unit, and the n+M / 2+2th shift register unit is used to reset the nth shift register unit.

[0016] Optionally, the display substrate displays multiple frames of display data;

[0017] Each frame of display data includes display data of odd-numbered sub-pixel rows; or,

[0018] Each frame of display data includes display data of even-numbered sub-pixel rows; or,

[0019] Multiple frames of display data are divided into multiple groups of frame display data, each group of frame display data includes X adjacent frames of display data, the i-th frame display data in the X frames of display data includes the display data of the sub-pixel row coupled to the i-th shift register unit in each group of shift register units, and i is less than or equal to M.

[0020] Optionally, the sub-pixel includes a pixel electrode; the pixel electrode includes a first electrode pattern, a second electrode pattern and a plurality of third electrode patterns;

[0021] The first electrode pattern and the second electrode pattern both extend along a first direction; the plurality of third electrode patterns are arranged along the first direction, and an angle between an extending direction of the third electrode pattern and the first direction is less than 90 degrees;

[0022] The first electrode pattern is located on a first side of the plurality of third electrode patterns, and the second electrode pattern is located on a second side of the plurality of third electrode patterns; the first side and the second side are opposite to each other along the extending direction; the first electrode pattern and the second electrode pattern are staggered along the first direction;

[0023] The multiple third electrode patterns are divided into three groups of third electrode patterns, one end of each third electrode pattern in the first group of third electrode patterns is respectively coupled to the first electrode pattern; one end of each third electrode pattern in the second group of third electrode patterns is respectively coupled to the second electrode pattern; the first end of each third electrode pattern in the third group of third electrode patterns is respectively coupled to the first electrode pattern, and the second end of each third electrode pattern in the third group of third electrode patterns is respectively coupled to the second electrode pattern.

[0024] Optionally, at least part of the third electrode patterns in adjacent sub-pixels in each row of sub-pixels are symmetrically arranged, at least part of the first electrode patterns in adjacent sub-pixels in each row of sub-pixels are symmetrically arranged, and at least part of the second electrode patterns in adjacent sub-pixels in each row of sub-pixels are symmetrically arranged; the axis of symmetry is located between the first electrode patterns in adjacent sub-pixels.

[0025] Optionally, an angle between extension directions of the symmetrically arranged third electrode patterns in each row of sub-pixels is between 158 degrees and 174 degrees.

[0026] Optionally, the number of third electrode patterns included in the third group of third electrode patterns is greater than or equal to 2.

[0027] Optionally, a ratio between the number of third electrode patterns included in the first group of third electrode patterns and the number of third electrode patterns included in the second group of third electrode patterns is 9:8, 10:9 or 11:10.

[0028] Optionally, the width of the first electrode pattern in a direction perpendicular to the first direction, the width of the second electrode pattern in a direction perpendicular to the first direction, and the width of the third electrode pattern in a direction perpendicular to the extension direction thereof are all the same.

[0029] Optionally, the plurality of sub-pixels are divided into a plurality of columns of sub-pixels, and the sub-pixels included in each column of sub-pixels have the same color; the display substrate further includes: a plurality of data lines;

[0030] Part of the data lines are respectively coupled to part of the sub-pixels in two adjacent columns of sub-pixels, and the part of the sub-pixels are divided into a plurality of first sub-pixel groups and a plurality of second sub-pixel groups, the plurality of first sub-pixel groups are located on a first side of the data line, the plurality of second sub-pixel groups are located on a second side of the data line, and the first side and the second side are opposite; the first sub-pixels and the second sub-pixels are located in different sub-pixel rows; along the extension direction of the data line, the first sub-pixel groups and the second sub-pixel groups are alternately arranged;

[0031] The number of first sub-pixels included in the plurality of first sub-pixel groups is equal to k1*X, where k1 is an integer greater than or equal to 1;

[0032] The number of second sub-pixels included in the plurality of second sub-pixel groups is equal to k2*X, where k2 is an integer greater than or equal to 1.

[0033] Optionally, the first sub-pixel and the second sub-pixel have opposite polarities.

[0034] Optionally, the display substrate further includes a plurality of common electrode lines; the sub-pixels further include a common electrode, and the plurality of sub-pixels in the same row include

[0035] The plurality of common electrodes are respectively coupled to a corresponding common electrode line;

[0036] The pixel electrode also includes a target electrode pattern, which is coupled to the first electrode pattern, and the orthographic projection of the target electrode pattern on the substrate at least partially overlaps with the orthographic projection of a common electrode line coupled to the common electrode in the sub-pixel to which it belongs on the substrate; in the extension direction along the data line, the width of the target electrode pattern is greater than the width of the third electrode pattern.

[0037] Optionally, the display substrate includes multiple groups of connection components, each group of connection components includes a first conductive connection part and two second conductive connection parts; one of the second conductive connection parts is respectively coupled to the first end of the first conductive connection part and the corresponding common electrode, and the other second conductive connection part is respectively coupled to the second end of the first conductive connection part and the common electrode adjacent to the corresponding common electrode along the first direction; the second conductive connection part is arranged in the same layer and material as the pixel electrode, and the second conductive connection part is at least partially surrounded by the pixel electrode.

[0038] Based on the technical solution of the above display substrate, a second aspect of the present invention provides a method for driving a display substrate, which is used to drive the above display substrate. The driving method includes:

[0039] A plurality of shift register units in the display substrate sequentially output gate driving signals, and X shift register units in each shift register unit group simultaneously output gate driving signals to the sub-pixels coupled thereto, where X is an integer greater than or equal to 2.

[0040] Based on the technical solution of the above-mentioned display substrate, a third aspect of the present invention provides a display device, comprising the above-mentioned display substrate.

[0041] In the technical solution provided by the present invention, the refresh rate of the display substrate is improved by sacrificing a certain vertical resolution without reducing the charging time. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0043] Figure 1 A first timing diagram of a clock signal connected to a gate driving circuit provided in an embodiment of the present invention;

[0044] Figure 2 A second timing diagram of a clock signal connected to a gate driving circuit provided in an embodiment of the present invention;

[0045] Figure 3 and Figure 4 To adopt Figure 2 Schematic diagram of two adjacent frames of data signals during timing drive;

[0046] Figure 5 To adopt Figure 1 Timing and Figure 2 Schematic diagram of the display screen when timing driven;

[0047] Figure 6 A third timing diagram of a clock signal connected to a gate driving circuit provided in an embodiment of the present invention;

[0048] Figures 7 to 9 To adopt Figure 6 Schematic diagram of three adjacent frames of data signals during timing drive;

[0049] Fig.10 A fourth timing diagram of a clock signal connected to a gate driving circuit provided in an embodiment of the present invention;

[0050] Figures 11 to 14 To adopt Fig.10 Schematic diagram of four adjacent frames of data signals during sequential driving;

[0051] Fig.15 A schematic diagram of a cascade of shift register units provided in an embodiment of the present invention;

[0052] Fig.16 A control timing diagram of a gate drive circuit and a data line provided by an embodiment of the present invention;

[0053] Fig.17 A schematic diagram of a first pixel structure of a display substrate provided by an embodiment of the present invention;

[0054] Fig.18 A first schematic diagram of pixel polarity Dot flipping provided by an embodiment of the present invention;

[0055] Fig.19 A schematic diagram of pixel polarity column flipping provided by an embodiment of the present invention;

[0056] Fig. 20 A schematic diagram of a second pixel structure of a display substrate provided by an embodiment of the present invention;

[0057] Fig.21 A schematic diagram of a third pixel structure of a display substrate provided in an embodiment of the present invention;

[0058] Fig. 22 A second schematic diagram of pixel polarity Dot flipping provided by an embodiment of the present invention;

[0059] Figure 23 to Figure 27 A schematic diagram of a plurality of first sub-pixel groups and a plurality of second sub-pixel groups coupled to data lines provided by an embodiment of the present invention;

[0060] Fig.28 A first schematic diagram of a minimum repeating unit of a pixel electrode provided by an embodiment of the present invention;

[0061] Fig.29 A second schematic diagram of a minimum repeating unit of a pixel electrode provided by an embodiment of the present invention;

[0062] Fig.30 A schematic diagram of the layout of sub-pixels provided in an embodiment of the present invention;

[0063] Fig.31 for Fig.30 The cross-sectional view along the A1A2 direction;

[0064] Fig.32 for Fig.30 Schematic diagram of the layout of the first part of the membrane layer;

[0065] Fig.33 for Fig.30 Schematic diagram of the layout of the second part of the membrane layer. DETAILED DESCRIPTION

[0066] In order to further illustrate the display substrate and its driving method and the display device provided by the embodiments of the present invention, a detailed description is given below in conjunction with the accompanying drawings.

[0067] See also Figure 2 , Figure 6 and Fig.10 , an embodiment of the present invention provides a display substrate, comprising: a display area and a peripheral area surrounding the display area; the display substrate further comprises:

[0068] A plurality of sub-pixels, the plurality of sub-pixels are located in the display area, and the plurality of sub-pixels are divided into a plurality of rows of sub-pixel rows;

[0069] A plurality of shift register units, the plurality of shift register units are located in the peripheral area, the shift register units correspond to at least one row of sub-pixels, and the shift register units are respectively coupled to each sub-pixel in the corresponding sub-pixel row;

[0070] The multiple shift register units are divided into multiple shift register unit groups, which are arranged in sequence, each shift register unit group includes X shift register units, and the X shift register units simultaneously output gate drive signals to the sub-pixels coupled thereto, where X is an integer greater than or equal to 2.

[0071] Exemplarily, the display substrate is applied to 8K (Super Ultra HD) liquid crystal display screens, or can also be applied to products with other resolutions such as 16K or 4K.

[0072] Exemplarily, the plurality of shift register units correspond one-to-one to a plurality of sub-pixel rows; or, each shift register unit corresponds to at least two sub-pixel rows.

[0073] Exemplarily, the sub-pixel includes a control transistor, and the shift register unit is respectively coupled to the gate of the transistor included in each sub-pixel in the corresponding sub-pixel row.

[0074] Exemplarily, the multiple groups of shift register unit groups are arranged in sequence, and the sub-pixel rows corresponding to the multiple groups of shift register unit groups are arranged in sequence.

[0075] Exemplarily, the plurality of shift register unit groups sequentially output gate driving signals, and each shift register unit group includes X shift register units that simultaneously output gate driving signals to sub-pixels coupled thereto.

[0076] Exemplarily, the display substrate further comprises a plurality of data lines, and among the plurality of sub-pixels coupled to each data line, the sub-pixels located in different rows and coupled to the same group of shift register units have the same data signal written therein in the same period.

[0077] For example, for TV products, the PPI (Pixels per inch) of 8K display products is above 100, such as 136 for a 65-inch 8K display product. Therefore, it is possible to consider sacrificing some resolution indicators to increase the refresh rate to meet the display requirements of some high-speed motion pictures or game pictures. It is worth noting that these high-speed motion pictures or game pictures have high requirements for refresh rate, but not very urgent requirements for resolution.

[0078] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiment of the present invention, the refresh rate of the display substrate is improved by sacrificing a certain vertical resolution (ie, the direction in which the data lines extend) without reducing the charging time.

[0079] When the display substrate provided by the embodiment of the present invention is applied to display products, taking 8K display products as an example, reducing the vertical resolution by N times can increase the refresh rate by 1 / N times. For example: 8K4K 60Hz can achieve 8K2K 120Hz or 8K1.3K 180Hz or 8K1K 240Hz through this patent solution; for example, 8K4K 120Hz can achieve 8K2K 240Hz or 8K1.3K 360Hz or 8K1K 480Hz through this patent solution. The display substrate provided by the embodiment of the present invention can also be used for future 16K or existing lower 4K resolution products. For example, 16K8K 60Hz becomes 16K4K 120Hz; for example, 4K2K120Hz becomes 4K1K 240Hz, etc.

[0080] In some embodiments, the gate driving signals output by adjacent shift register unit groups are configured such that the time periods in which the effective levels are located partially overlap.

[0081] Exemplarily, in the same time period, effective levels of gate driving signals output by adjacent shift register unit groups overlap.

[0082] The above-mentioned setting method makes it possible for when the current shift register unit group outputs a gate drive signal, the adjacent next shift register unit group will also output a gate drive signal, so that while charging the sub-pixel row coupled to the current shift register unit group, it can also pre-charge the sub-pixel row coupled to the adjacent next shift register unit group.

[0083] In some embodiments, the shift register unit group includes two shift register units, and the two shift register units are coupled to two rows of sub-pixels in a one-to-one correspondence.

[0084] like Figure 1As shown in the figure, it is a schematic diagram of the gate drive signal control waveform and the line-by-line scanning of the gate line of a conventional 8K4K 60HZ display product. In the figure, T4 is 1H time, specifically 3.7us. Each clock signal (such as CLK1-CLK8) represents the control waveform of a row of gate lines. The high level of the clock signal indicates that the transistor included in the gate line control sub-pixel is turned on, and the data signal can be written to the sub-pixel. The corresponding T1 time is 6H, that is, 22.2us. The low level of the clock signal indicates that the transistor included in the gate line control sub-pixel is turned off, and the data signal is stopped from being written to the sub-pixel. The corresponding T2 time is also 6H. The waveforms of CLK1~CLK8 represent the control waveforms of the gate lines corresponding to eight rows of sub-pixels. The actual 8K product adopts a 12CLK cycle design, and the control waveform of the gate line is cycled as a cycle. On the time axis, the phases of the control waveforms of adjacent gate lines are exactly staggered by 1H time, and the rising edges of the waveforms are staggered by 1H time. The sub-pixels are turned on in sequence in each row, that is, they are turned on and charged row by row. 8K4K has a total of 4320 rows in the vertical direction (i.e. the direction in which the data lines extend), so 4320 rows of pixels are turned on in turn for charging, and the time required for one frame is 16.7ms.

[0085] like Figure 2 As shown, the waveforms of the gate lines corresponding to two adjacent rows of sub-pixels are the same, that is, the two adjacent rows of sub-pixels are turned on at the same time. To ensure that the charging time T4 is not less than that of a 60Hz product, at least T4 = 2H = 3.7us is ensured. In this way, the charging time to complete a frame of the picture is actually only half of that of a 60Hz, that is, 8.3ms, so the picture refresh rate is increased to 120Hz. Figure 3 and Figure 4 It shows the situation of 4320 lines of data displayed in two consecutive frames, that is, every two adjacent lines of sub-pixels display the same data, and the data of the previous and next frames are complementary, that is, the previous frame displays odd-numbered lines of data, and the next frame displays even-numbered lines of data. It is worth noting that the high level T1 time and low level T2 time of the clock signal are the same, both are 6H, that is, 22.2us, and the rising edge time difference T3 of CLK1&CLK2 and CLK3&CLK4 is 2H, that is, 3.7us. Figure 5 The figure shows the difference in the displayed image before and after sacrificing resolution to increase refresh rate. It should be noted that under the double frequency condition, the charging time of two rows of sub-pixels is guaranteed to be 3.7us.

[0086] In some embodiments, the shift register unit group includes three shift register units, and the three shift register units are coupled to three rows of sub-pixel rows in a one-to-one correspondence.

[0087] like Figure 6As shown, three adjacent rows of sub-pixels are turned on at the same time. To ensure the charging time, T4 is 3H = 3.7us. The charging time to complete a frame is only 1 / 3 of 60Hz, that is, 5.5ms, so the picture refresh rate is increased to 180Hz. It should be noted that in the case of triple frequency, the charging time of three rows of sub-pixels is guaranteed to be 3.7us.

[0088] In some embodiments, the shift register unit group includes four shift register units, and the four shift register units are coupled to four rows of sub-pixels in a one-to-one correspondence.

[0089] like Fig.10 As shown, four adjacent rows of sub-pixels are turned on at the same time. To ensure the charging time, T4 is 4H = 3.7us, and the charging time to complete a frame is only 4.2ms, so the refresh rate of the picture is 240Hz. It should be noted that in the case of quadruple frequency, the charging time of four rows of sub-pixels is guaranteed to be 3.7us.

[0090] like Fig.15 and Fig.16 As shown, in some embodiments, the display panel includes 12 clock signal lines, namely CLK1-CLK12, and the number of clock signal lines is set according to actual needs and is not limited here. The display substrate also includes: a first frame start signal line STV1, a second frame start signal line STV2 and M clock signal lines, M is a positive integer, and M is an even number;

[0091] The first frame start signal line is coupled to the first shift register unit, the third shift register unit and the fifth shift register unit respectively;

[0092] The second frame start signal line is coupled to the second shift register unit, the fourth shift register unit and the sixth shift register unit respectively;

[0093] The display substrate includes N shift register units, where N is an integer greater than M;

[0094] The nth shift register unit is used to carry the n+M / 2th shift register unit, and the n+M / 2+2th shift register unit is used to reset the nth shift register unit, n≤N.

[0095] Need to explain, Fig.15 and Fig.16 CLK1 to CLK12 are clock signals provided by 12 clock signal lines. Fig.15 Gate1 to Gate12 are gate drive signals outputted by 12 shift register units. Fig.16STV0 is a reset signal for resetting all shift register units. Data1 to Data12 are data signals. TP is a trigger pulse signal for triggering the writing of data signals.

[0096] Exemplarily, the gate driving circuit of the display substrate adopts a 3STV+12CLK design. The display substrate includes a first frame start signal line, a second frame start signal line and a third frame start signal line. The third frame start signal line is used to reset all shift register units in the display substrate.

[0097] Exemplarily, the first frame start signal line and the second frame start signal line are two independent signal lines; or, the first frame start signal line and the second frame start signal line are connected together.

[0098] Exemplarily, there is no cascade relationship between the first shift register unit and the second to sixth shift register units. The first shift register unit carries to the seventh shift register unit, the second shift register unit carries to the eighth shift register unit, and so on. The first shift register unit is reset by the ninth shift register unit, the second shift register unit is reset by the tenth shift register unit, and so on.

[0099] Exemplarily, the display substrate further includes virtual shift register units. A portion of the virtual shift register units is close to the upper side of the display area, that is, the side of the chip away from the display substrate. The number of these virtual shift register units can be 1 to 2. Another portion of the virtual shift register units is close to the lower side of the display area, that is, the side of the chip close to the display substrate. The number of these virtual shift register units can be 8 to 16. These virtual shift register units can carry and reset the normal shift register units.

[0100] In some embodiments, the display substrate displays multiple frames of display data;

[0101] Each frame of display data includes display data of odd-numbered sub-pixel rows; or,

[0102] Each frame of display data includes display data of even-numbered sub-pixel rows; or,

[0103] Multiple frames of display data are divided into multiple groups of frame display data, each group of frame display data includes X adjacent frames of display data, the i-th frame display data in the X frames of display data includes the display data of the sub-pixel row coupled to the i-th shift register unit in each group of shift register units, and i is less than or equal to M.

[0104] For example, when the double frequency scheme is adopted, the display substrate can be set to display multiple frames of display data, and each frame of display data only includes display data of odd-numbered sub-pixel rows, that is, the display data of even-numbered sub-pixel rows is lost. In this way, only the odd-numbered rows of data of the original image data are retained in two adjacent frames, and then each row of data of the 8K2K product is displayed as two rows on the screen, which becomes 8K4K.

[0105] For example, when the double frequency scheme is adopted, the display substrate can be set to display multiple frames of display data, and each frame of display data only includes display data of even-numbered sub-pixel rows, that is, the display data of odd-numbered sub-pixel rows is lost. In this way, only the even-numbered rows of data of the original image data are retained in two adjacent frames, and the row data of 8K2K data is displayed every two rows, and the screen displays 8K4K.

[0106] For example, when a double frequency scheme is adopted, multiple frames of display data may be divided into multiple groups of frame display data, each group of frame display data includes two adjacent frames of display data. Figure 3 As shown, the first frame of display data in the two frames of display data includes display data of the sub-pixel row coupled to the first shift register unit (ie, an odd number of shift register units) in each group of shift register units. Figure 4 As shown, the second frame of display data in the two frames of display data includes display data of the sub-pixel row coupled to the second shift register unit (ie, an even number of shift register units) in each group of shift register units.

[0107] For example, when a triple frequency scheme is adopted, multiple frames of display data may be divided into multiple groups of frame display data, each group of frame display data includes three adjacent frames of display data. Figure 7 As shown, the first frame of display data in the three frames of display data includes display data of the sub-pixel row coupled to the first shift register unit in each group of shift register units. Figure 8 As shown, the second frame of display data in the three frames of display data includes display data of the sub-pixel row coupled to the second shift register unit in each group of shift register units. Fig. 9 As shown, the third frame of display data among the three frames of display data includes display data of the sub-pixel row coupled to the third shift register unit in each group of shift register units.

[0108] In more detail, taking the first shift register unit group, the second shift register unit group and the third shift register unit group as examples, each shift register unit group includes three shift register units.

[0109] The first shift register unit in the first shift register unit group is coupled to the first row of sub-pixels. The second shift register unit in the first shift register unit group is coupled to the second row of sub-pixels. The third shift register unit in the first shift register unit group is coupled to the third row of sub-pixels.

[0110] The first shift register unit in the second shift register unit group is coupled to the fourth row of sub-pixels. The second shift register unit in the second shift register unit group is coupled to the fifth row of sub-pixels. The third shift register unit in the second shift register unit group is coupled to the sixth row of sub-pixels.

[0111] The first shift register unit in the third shift register unit group is coupled to the seventh row of sub-pixels. The second shift register unit in the third shift register unit group is coupled to the eighth row of sub-pixels. The third shift register unit in the third shift register unit group is coupled to the ninth row of sub-pixels.

[0112] like Figure 7 As shown, the first frame of display data in the three frames of display data includes the display data of the sub-pixel row coupled to the first shift register unit in each group of shift register units. That is, the first frame of display data includes the display data of the first row of sub-pixels, the display data of the fourth row of sub-pixels, and the display data of the seventh row of sub-pixels.

[0113] like Figure 8 As shown, the second frame of display data in the three frames of display data includes the display data of the sub-pixel row coupled to the second shift register unit in each group of shift register units. That is, the second frame of display data includes the display data of the second row of sub-pixels, the display data of the fifth row of sub-pixels, and the display data of the eighth row of sub-pixels.

[0114] like Fig. 9 As shown, the third frame of display data in the three frames of display data includes the display data of the sub-pixel row coupled to the third shift register unit in each group of shift register units. That is, the third frame of display data includes the display data of the third row of sub-pixels, the display data of the sixth row of sub-pixels, and the display data of the ninth row of sub-pixels.

[0115] For example, when a quadruple frequency scheme is adopted, multiple frames of display data may be divided into multiple groups of frame display data, each group of frame display data including four adjacent frames of display data. Fig.11 As shown, the first frame of display data in the four frames of display data includes display data of the sub-pixel row coupled to the first shift register unit in each group of shift register units. Fig.12 As shown, the second frame of display data in the four frames of display data includes display data of the sub-pixel row coupled to the second shift register unit in each group of shift register units. Fig.13As shown, the third frame of display data in the four frames of display data includes display data of the sub-pixel row coupled to the third shift register unit in each group of shift register units. Fig.14 As shown, the fourth frame of display data among the four frames of display data includes display data of the sub-pixel row coupled to the third shift register unit in each group of shift register units.

[0116] like Fig.28 , Fig.29 and Fig.32 As shown, in some embodiments, the sub-pixel includes a pixel electrode; the pixel electrode includes a first electrode pattern 10, a second electrode pattern 20 and a plurality of third electrode patterns 30;

[0117] The first electrode pattern 10 and the second electrode pattern 20 both extend along a first direction; the plurality of third electrode patterns 30 are arranged along the first direction, and an angle between an extending direction of the third electrode pattern 30 and the first direction is less than 90 degrees;

[0118] The first electrode pattern 10 is located on a first side of the plurality of third electrode patterns 30, and the second electrode pattern 20 is located on a second side of the plurality of third electrode patterns 30; the first side and the second side are opposite to each other along the extending direction; the first electrode pattern 10 and the second electrode pattern 20 are staggered along the first direction;

[0119] The multiple third electrode patterns 30 are divided into three groups of third electrode patterns, one end of each third electrode pattern 30 in the first group of third electrode patterns 31 is respectively coupled to the first electrode pattern 10; one end of each third electrode pattern 30 in the second group of third electrode patterns 32 is respectively coupled to the second electrode pattern 20; the first end of each third electrode pattern 30 in the third group of third electrode patterns 33 is respectively coupled to the first electrode pattern 10, and the second end of each third electrode pattern 30 in the third group of third electrode patterns 33 is respectively coupled to the second electrode pattern 20.

[0120] like Figure 31 to Figure 33 As shown, exemplarily, the sub-pixel includes a control transistor TFT, a pixel electrode and a common electrode 61; the gate of the control transistor TFT is coupled to the corresponding gate line 40, the first electrode of the control transistor TFT is coupled to the corresponding data line 50, and the second electrode of the control transistor TFT is coupled to the pixel electrode. Fig.31 Also illustrated are a substrate 63, a common electrode line 60, a gate insulating layer GI, a first conductive connection portion 62, a second conductive connection portion 64, and a passivation layer PVX. Fig.32 The middle grid line 40 includes a hexagonal pattern, and the orthographic projection of the hexagonal pattern on the substrate overlaps with the orthographic projection of the spacer in the display substrate on the substrate. Fig.32Also shown is a spacer retaining wall PS0, which is used to prevent the spacer from sliding toward the surrounding area.

[0121] Exemplarily, the common electrode 61 and the common electrode line 60 can be prepared on the same layer as the gate line 40 using different masks, the common electrode 61 and the common electrode line 60 are overlapped to form an electrical connection, the first conductive connection part 62 can be set on the same layer as the source and drain metal layer, and the second conductive connection part 64 can be set on the same layer as the pixel electrode.

[0122] Exemplarily, the first electrode pattern 10, the second electrode pattern 20 and the third electrode pattern 30 are all formed into an integrated structure.

[0123] Exemplarily, the data line includes at least a portion extending along the first direction.

[0124] Exemplarily, the first electrode pattern 10 and the second electrode pattern 20 are staggered along the first direction, and the first electrode pattern 10 and the second electrode pattern 20 are staggered along the extending direction of the third electrode pattern 30 .

[0125] Exemplarily, the first electrode pattern 10 is located on a first side of the first group of third electrode patterns 30 , and the second electrode pattern 20 is located on a second side of the second group of third electrode patterns 30 .

[0126] In the above-mentioned display substrate, the pixel electrode adopts a "horse"-shaped pixel design, which reduces the light-shielding property of the pixel electrode, thereby better improving the transmittance of the display substrate and meeting the requirements of high resolution and high refresh rate.

[0127] like Figure 28 to Figure 32 As shown, in some embodiments, at least a portion of the third electrode patterns 30 in adjacent sub-pixels in each row of sub-pixels are symmetrically arranged, at least a portion of the first electrode patterns 10 in adjacent sub-pixels in each row of sub-pixels are symmetrically arranged, and at least a portion of the second electrode patterns 20 in adjacent sub-pixels in each row of sub-pixels are symmetrically arranged; the axis of symmetry is located between the first electrode patterns 10 in adjacent sub-pixels.

[0128] Exemplarily, the third groups of third electrode patterns 30 in adjacent sub-pixels in each row of sub-pixels are symmetrically arranged.

[0129] like Fig.28As shown, a minimum repeating unit of a "horse" type pixel is illustrated. The minimum repeating unit mainly considers the consistency of the optical performance of each monochrome in all directions after the color filter is combined, so as to ensure that there is no deviation in the color observed in all directions. Each minimum repeating unit contains 4 "horse" type pixel units. Each "horse" type pixel unit includes three sub-pixels, such as: R, G, and B. In the minimum repeating unit, the three sub-pixels R, G, and B all include a two-domain structure. Exemplarily, the angle between the third electrode pattern 30 of one pixel electrode in the two-domain structure and the horizontal direction is 7°, and the angle between the third electrode pattern 30 of the other pixel electrode and the horizontal direction is 173°. The angles between the pixel electrodes in the two-domain structure and the horizontal direction are complementary.

[0130] Exemplarily, in the minimum repeating unit, the pixel electrode is symmetrical about the upper and lower center lines and the left and right center lines. If there are structures such as vias and TFTs (thin film transistors), some areas are not completely symmetrical.

[0131] like Fig.29 FIG. 1 shows another minimum repeating unit of a “horse” type pixel. In this minimum repeating unit, the three sub-pixels R, G, and B also include a two-domain structure.

[0132] The above-mentioned symmetrical arrangement can effectively improve the color shift phenomenon, which is beneficial to improving the display uniformity of the display substrate and improving the display quality of the display substrate.

[0133] like Fig.28 As shown, in some embodiments, the angle (such as b1 and b2) between the extension directions of the symmetrically arranged third electrode patterns 30 in each row of sub-pixels is set to be between 158 degrees and 174 degrees, including end points.

[0134] The above configuration can fully consider the initial orientation requirements of the liquid crystal, better match the initial orientation direction of the liquid crystal, and improve the display quality of the display substrate.

[0135] like Fig.32 As shown, in some embodiments, the number of third electrode patterns 30 included in the third group of third electrode patterns 30 is greater than or equal to 2.

[0136] The above arrangement enables the first electrode pattern 10 and the second electrode pattern 20 to be coupled through at least two third electrode patterns 30 in each sub-pixel, thereby ensuring the reliability of the connection between the first electrode pattern 10 and the second electrode pattern 20, and the reliability of the electrical connection between the first group of third electrode patterns 31 and the second group of third electrode patterns 32. The disconnection between the first electrode pattern 10 and the second electrode pattern 20 caused by particles is reduced.

[0137] In some embodiments, a ratio between the number of third electrode patterns 30 included in the first group of third electrode patterns 31 and the number of third electrode patterns 30 included in the second group of third electrode patterns 32 is set to 9:8, 10:9 or 11:10.

[0138] The above configuration is beneficial to improving the reliability of the electrical connection between the first electrode pattern 10, the second electrode pattern 20 and the third electrode pattern 30 in the sub-pixel.

[0139] In some embodiments, the width of the first electrode pattern 10 in a direction perpendicular to the first direction, the width of the second electrode pattern 20 in a direction perpendicular to the first direction, and the width of the third electrode pattern 30 in a direction perpendicular to the extension direction thereof are all set to be the same.

[0140] Exemplarily, the minimum width of the first electrode pattern 10 in a direction perpendicular to the first direction, the minimum width of the second electrode pattern 20 in a direction perpendicular to the first direction, and the minimum width of the third electrode pattern 30 in a direction perpendicular to the extension direction thereof are all the same.

[0141] Exemplarily, the minimum width of the first electrode pattern 10 in the direction perpendicular to the first direction is greater than or equal to 2.4 micrometers.

[0142] Exemplarily, a foot 70 is provided at the connection between the first electrode pattern 10 and the third electrode pattern 30, and at the connection between the second electrode pattern 20 and the third electrode pattern 30, so as to improve the yield of the electrical connection between the first electrode pattern 10 and the third electrode pattern 30, and between the second electrode pattern 20 and the third electrode pattern 30.

[0143] It is worth noting that near the via hole setting area and the control transistor setting area of ​​the sub-pixel, the lengths of the first electrode pattern 10, the second electrode pattern 20 and / or the third electrode pattern 30 can be shortened to meet actual layout requirements.

[0144] The above arrangement is beneficial to improving the overall uniformity of the pixel electrode and the display quality of the display substrate.

[0145] In some embodiments, the plurality of sub-pixels are divided into a plurality of columns of sub-pixels, and the sub-pixels included in each column of sub-pixels have the same color; the display substrate further includes: a plurality of data lines;

[0146] Part of the data lines are respectively coupled to part of the sub-pixels in two adjacent columns of sub-pixels, and the part of the sub-pixels are divided into a plurality of first sub-pixel groups and a plurality of second sub-pixel groups, the plurality of first sub-pixel groups are located on a first side of the data line, the plurality of second sub-pixel groups are located on a second side of the data line, and the first side and the second side are opposite; the first sub-pixels and the second sub-pixels are located in different sub-pixel rows; along the extension direction of the data line, the first sub-pixel groups and the second sub-pixel groups are alternately arranged;

[0147] The number of first sub-pixels included in the plurality of first sub-pixel groups is equal to k1*X, where k1 is an integer greater than or equal to 1;

[0148] The number of second sub-pixels included in the plurality of second sub-pixel groups is equal to k2*X, where k2 is an integer greater than or equal to 1.

[0149] In some embodiments, the polarities of the first sub-pixel and the second sub-pixel are opposite. This arrangement is beneficial to prolonging the service life of the liquid crystal display product.

[0150] For example, Fig.17 As shown, the display substrate adopts a 1G1D structure, that is, a row of sub-pixels is connected to the same gate line, and a column of sub-pixels is connected to the same data line. This 1G1D structure has the following characteristics:

[0151] (1) D1 to D12 are data lines, Gate1 to Gate 8 are gate lines, and all sub-pixels connected to the data lines are located to the right of the data lines.

[0152] (2) After matching the color filter, all sub-pixels connected to a data line are of the same color, which can support simultaneous control of opening of two rows of gate lines. Sub-pixels of the same color coupled to the data line are charged with the same data voltage and data mischarging will not occur.

[0153] (3) Considering the high power consumption of high-resolution products, the polarity changes of sub-pixels on each data line should be minimized to reduce power consumption. Therefore, each data line adopts Colum flipping, that is, the polarity on the line is flipped once a frame.

[0154] (4) Outside the display area, there is a virtual sub-pixel design, with a row of virtual sub-pixels on the upper and lower sides of the display area, and a column of sub-pixels on the left and right sides of the display area.

[0155] The display substrate adopts a 1G1D structure, and each data line is coupled to a sub-pixel of the same color, so that M adjacent rows of sub-pixels can be turned on simultaneously.

[0156] However, the display substrate of the above structure has the following problems: because the sub-pixels in the same column have the same polarity, the polarity of the entire display screen is reversed. Fig.19 As shown, there will be a visual feeling of vertical lines.

[0157] like Fig.18 As shown, the display polarity with the best real visual effect is Dot flip. However, if the sub-pixels coupled to the same data line are arranged in rows on the left and right, when M rows of sub-pixels are controlled to turn on at the same time, the same data signal will be written to sub-pixels of different colors at the same time, resulting in abnormal display.

[0158] like Fig. 20 As shown, for example, X=2, k1=k2=1, so that the sub-pixels in the display substrate form a Z-2 pixel structure. Under this pixel structure, when two rows of sub-pixels are controlled to be turned on at the same time (i.e., double frequency is achieved), the same data signal can be written to the sub-pixels of the same color at the same time, and there will be no display abnormality.

[0159] like Fig.21 As shown, k1*X=k2*X=12, so that the sub-pixels in the display substrate form a Z-12 pixel structure. Under this pixel structure, when two, three or four rows of sub-pixels are controlled to be turned on at the same time (i.e., double frequency, triple frequency or quadruple frequency is achieved), the same data signal can be written to the sub-pixels of the same color at the same time, and there will be no display abnormality.

[0160] The above Z-12 pixel structure has the following characteristics:

[0161] (1) Among the sub-pixels coupled to the same data line, 12 rows of sub-pixels located on the left side of the data line and 12 rows of sub-pixels located on the right side of the data line are alternately arranged along the extending direction of the data line.

[0162] (2) The sub-pixels coupled to the same data line have different colors after matching the color filter. Generally, two colors are connected on one data line, and there are three color combinations: RB, GR, and BG.

[0163] (3) For polarity reversal, each data line can use 12dot reversal, such as Fig. 22 As shown, it is similar to Fig.18 Dot flips.

[0164] like Figure 23 to Figure 27 As shown, by way of example, k1*X=12 or 24 or 36 and k2*X=12 or 24 or 36 can be set. Double frequency, triple frequency and quadruple frequency can be achieved simultaneously.

[0165] like Figure 30 to Figure 33As shown, in some embodiments, the display substrate further includes a plurality of common electrode lines 60; the sub-pixels further include a common electrode 61, and the plurality of common electrodes 61 included in the plurality of sub-pixels in the same row are respectively coupled to a corresponding common electrode line 60;

[0166] The pixel electrode also includes a target electrode pattern 34, which is coupled to the first electrode pattern 10, and the orthographic projection of the target electrode pattern 34 on the substrate at least partially overlaps with the orthographic projection of the common electrode line 60 coupled to the common electrode 61 in the sub-pixel to which it belongs on the substrate; in the extension direction along the data line 50, the width d1 of the target electrode pattern 34 is greater than the width d2 of the third electrode pattern 30.

[0167] Exemplarily, the plurality of common electrodes 61 included in the display substrate are divided into a plurality of rows of common electrodes 61 , and the plurality of rows of common electrodes 61 correspond one-to-one to the plurality of common electrode lines 60 .

[0168] Exemplarily, the target electrode pattern 34 and the first electrode pattern 10 are formed into an integral structure.

[0169] Exemplarily, the minimum width of the portion where the target electrode pattern 34 overlaps the common electrode line 60 is greater than the minimum width of the third electrode pattern 30 .

[0170] Exemplarily, the target electrode pattern 34 overlaps with the common electrode line 60 to form a storage capacitor.

[0171] like Figure 30 to Figure 33 As shown, in some embodiments, the display substrate includes multiple groups of connection components, each group of connection components includes a first conductive connection part 62 and two second conductive connection parts 64; one of the second conductive connection parts 64 is respectively coupled to the first end of the first conductive connection part 62 and the corresponding common electrode 61, and the other second conductive connection part 64 is respectively coupled to the second end of the first conductive connection part 62 and the common electrode 61 adjacent to the corresponding common electrode 61 along the first direction; the second conductive connection part 64 is arranged in the same layer and material as the pixel electrode, and the second conductive connection part 64 is at least partially surrounded by the pixel electrode, for example, half-surrounded.

[0172] Exemplarily, one of the second conductive connection parts 64 is coupled to the first end of the first conductive connection part 62 and the corresponding common electrode 61 through a via hole. Another second conductive connection part 64 is coupled to the second end of the first conductive connection part 62 and the common electrode 61 adjacent to the corresponding common electrode 61 along the first direction through a via hole.

[0173] Exemplarily, the orthographic projection of the first conductive connection portion 62 on the substrate partially overlaps with the orthographic projection of the gate line 40 on the substrate. In the extending direction perpendicular to the gate line 40, the width of the portion where the gate line 40 overlaps with the first conductive connection portion 62 is smaller than the width of the other portions of the gate line 40. This is conducive to reducing the parasitic capacitance formed between the first conductive connection portion 62 and the gate line 40.

[0174] The pixel electrode is at least partially hollowed out on one side of the second conductive connection portion 64 , which can further improve the transmittance of the pixel electrode.

[0175] An embodiment of the present invention further provides a method for driving a display substrate, which is used to drive the display substrate provided by the above embodiment. The driving method includes:

[0176] A plurality of shift register units in the display substrate sequentially output gate driving signals, and X shift register units in each shift register unit group simultaneously output gate driving signals to the sub-pixels coupled thereto, where X is an integer greater than or equal to 2.

[0177] The driving method provided in the embodiment of the present invention is used to drive the display substrate provided in the above embodiment, thereby improving the refresh rate of the display substrate by sacrificing a certain vertical resolution (ie, the direction in which the data lines extend) without reducing the charging time.

[0178] An embodiment of the present invention further provides a display device, comprising the display substrate provided by the above embodiment.

[0179] In the display substrate provided by the above embodiment, the refresh rate of the display substrate is improved by sacrificing the resolution in a certain vertical direction (ie, the direction in which the data lines extend) without reducing the charging time.

[0180] The display device provided by the embodiment of the present invention also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0181] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane, etc.

[0182] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0183] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the present invention belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0184] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0185] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0186] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A display substrate, characterized in that: include: A display area and a peripheral area surrounding the display area; The display substrate further comprises: A plurality of sub-pixels, the plurality of sub-pixels are located in the display area, and the plurality of sub-pixels are divided into a plurality of rows of sub-pixel rows; A plurality of shift register units, the plurality of shift register units are located in the peripheral area, the shift register units correspond to at least one row of sub-pixels, and the shift register units are respectively coupled to each sub-pixel in the corresponding sub-pixel row; The plurality of shift register units are divided into a plurality of shift register unit groups, the plurality of shift register unit groups are arranged in sequence, each shift register unit group includes X shift register units, the X shift register units simultaneously output gate drive signals to the sub-pixels coupled thereto, where X is an integer greater than or equal to 2; The sub-pixel includes a pixel electrode; the pixel electrode includes a first electrode pattern, a second electrode pattern and a plurality of third electrode patterns; The first electrode pattern and the second electrode pattern both extend along a first direction; the plurality of third electrode patterns are arranged along the first direction, and an angle between an extending direction of the third electrode pattern and the first direction is less than 90 degrees; The first electrode pattern is located on a first side of the plurality of third electrode patterns, and the second electrode pattern is located on a second side of the plurality of third electrode patterns; the first side and the second side are opposite to each other along the extending direction; the first electrode pattern and the second electrode pattern are staggered along the first direction; The multiple third electrode patterns are divided into three groups of third electrode patterns, one end of each third electrode pattern in the first group of third electrode patterns is respectively coupled to the first electrode pattern; one end of each third electrode pattern in the second group of third electrode patterns is respectively coupled to the second electrode pattern; the first end of each third electrode pattern in the third group of third electrode patterns is respectively coupled to the first electrode pattern, and the second end of each third electrode pattern in the third group of third electrode patterns is respectively coupled to the second electrode pattern.

2. The display substrate according to claim 1, characterized in that: The gate driving signals output by adjacent shift register unit groups have their effective level periods partially overlapped.

3. The display substrate according to claim 2, characterized in that: The shift register unit group includes three shift register units, and the three shift register units are correspondingly coupled to three rows of sub-pixel rows; or, the shift register unit group includes four shift register units, and the four shift register units are correspondingly coupled to four rows of sub-pixel rows.

4. The display substrate according to claim 1, characterized in that: The display substrate further includes: a first frame start signal line, a second frame start signal line and M clock signal lines, where M is a positive integer; The first frame start signal line is coupled to the first shift register unit, the third shift register unit and the fifth shift register unit respectively; The second frame start signal line is coupled to the second shift register unit, the fourth shift register unit and the sixth shift register unit respectively; The display substrate includes N shift register units, where N is an integer greater than M; The nth shift register unit is used to carry the n+M / 2th shift register unit, and the n+M / 2+2th shift register unit is used to reset the nth shift register unit.

5. The display substrate according to claim 1, characterized in that: The display substrate displays multiple frames of display data; Each frame of display data includes display data of odd-numbered sub-pixel rows; or, Each frame of display data includes display data of even-numbered sub-pixel rows; or, Multiple frames of display data are divided into multiple groups of frame display data, each group of frame display data includes X adjacent frames of display data, the i-th frame display data in the X frames of display data includes the display data of the sub-pixel row coupled to the i-th shift register unit in each group of shift register units, and i is less than or equal to M.

6. The display substrate according to claim 1, characterized in that: At least part of the third electrode patterns in adjacent sub-pixels in each row of sub-pixels are symmetrically arranged, at least part of the first electrode patterns in adjacent sub-pixels in each row of sub-pixels are symmetrically arranged, and at least part of the second electrode patterns in adjacent sub-pixels in each row of sub-pixels are symmetrically arranged; the axis of symmetry is located between the first electrode patterns in adjacent sub-pixels.

7. The display substrate according to claim 6, characterized in that: The angle between the extension directions of the symmetrically arranged third electrode patterns in each row of sub-pixels is between 158 degrees and 174 degrees.

8. The display substrate according to claim 1, characterized in that: The number of the third electrode patterns included in the third group of third electrode patterns is greater than or equal to 2.

9. The display substrate according to claim 1, characterized in that: A ratio between the number of third electrode patterns included in the first group of third electrode patterns and the number of third electrode patterns included in the second group of third electrode patterns is 9:8, 10:9 or 11:

10.

10. The display substrate according to claim 1, characterized in that: The width of the first electrode pattern in a direction perpendicular to the first direction, the width of the second electrode pattern in a direction perpendicular to the first direction, and the width of the third electrode pattern in a direction perpendicular to the extension direction thereof are all the same.

11. The display substrate according to claim 1, characterized in that: The plurality of sub-pixels are divided into a plurality of columns of sub-pixels, and the sub-pixels in each column of sub-pixels have the same color; the display substrate further comprises: a plurality of data lines; Part of the data lines are respectively coupled to part of the sub-pixels in two adjacent columns of sub-pixels, and the part of the sub-pixels are divided into a plurality of first sub-pixel groups and a plurality of second sub-pixel groups, the plurality of first sub-pixel groups are located on a first side of the data line, the plurality of second sub-pixel groups are located on a second side of the data line, and the first side and the second side are opposite; the first sub-pixels and the second sub-pixels are located in different sub-pixel rows; along the extension direction of the data line, the first sub-pixel groups and the second sub-pixel groups are alternately arranged; The number of first sub-pixels included in the plurality of first sub-pixel groups is equal to k1*X, where k1 is an integer greater than or equal to 1; The number of second sub-pixels included in the plurality of second sub-pixel groups is equal to k2*X, where k2 is an integer greater than or equal to 1.

12. The display substrate according to claim 11, characterized in that: The first sub-pixel and the second sub-pixel have opposite polarities.

13. The display substrate according to claim 1, characterized in that: The display substrate further includes a plurality of common electrode lines; the sub-pixels further include common electrodes, and the plurality of common electrodes included in the plurality of sub-pixels in the same row are respectively coupled to a corresponding common electrode line; The pixel electrode further comprises a target electrode pattern, the target electrode pattern is coupled to the first electrode pattern, and an orthographic projection of the target electrode pattern on the base of the display substrate at least partially overlaps with an orthographic projection of a common electrode line coupled to a common electrode in a sub-pixel to which the target electrode pattern belongs on the base; In the extending direction along the data line, the width of the target electrode pattern is greater than the width of the third electrode pattern.

14. The display substrate according to claim 13, characterized in that: The display substrate includes multiple groups of connection components, each group of connection components includes a first conductive connection part and two second conductive connection parts; one of the second conductive connection parts is coupled to the first end of the first conductive connection part and the corresponding common electrode, and the other second conductive connection part is coupled to the second end of the first conductive connection part and the common electrode adjacent to the corresponding common electrode along the first direction; the second conductive connection part is arranged in the same layer and material as the pixel electrode, and the second conductive connection part is at least partially surrounded by the pixel electrode.

15. A method for driving a display substrate, characterized in that: Used to drive the display substrate according to any one of claims 1 to 14, the driving method comprising: A plurality of shift register units in the display substrate sequentially output gate driving signals, and X shift register units in each shift register unit group simultaneously output gate driving signals to the sub-pixels coupled thereto, where X is an integer greater than or equal to 2.

16. A display device, characterized in that: The invention comprises the display substrate according to any one of claims 1 to 14.

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