Display device

Abstract

The display device includes a substrate (101), a light-emitting element (230), a first transistor (210A), and a second transistor (250). The first transistor includes a first gate electrode (204_1) provided on the substrate, a first insulating film (206) provided on the first gate electrode, a first oxide semiconductor layer (208_1) provided on the first insulating film and having a region overlapping with the first gate electrode, a second insulating film (212) provided on the first oxide semiconductor layer, and a first conductive layer (218) provided on the second insulating film. The second transistor includes a first insulating film provided on the substrate, a second oxide semiconductor layer (208_2) provided on the first insulating film, a second insulating film provided on the first oxide semiconductor layer and the second oxide semiconductor layer and having a film thickness smaller than that of the first insulating film, and a second gate electrode (214) provided on the second insulating film and having a region overlapping with the second oxide semiconductor layer.

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device. In particular, it relates to the configuration of pixels of a display device. Background Art

[0002] Organic electroluminescence (hereinafter referred to as organic EL) display devices are being actively researched due to advantages such as a wide viewing angle, high-speed response, and the ability to be used as a thin-panel display. An organic EL display device has a light-emitting element provided in each pixel, and displays an image by individually controlling light emission. The light-emitting element has a structure in which a layer including an organic EL material (hereinafter also referred to as a "light-emitting layer") is sandwiched between a pair of electrodes, one of which is an anode and the other is a cathode. When electrons are injected into the light-emitting layer from the cathode and holes are injected from the anode, the electrons and holes recombine. The remaining energy released thereby is used to excite the light-emitting molecules in the light-emitting layer, and then light is emitted through de-excitation.

[0003] In recent years, oxide semiconductors (Oxide Semiconductor; OS) have attracted attention as semiconductor layers constituting organic EL display devices. Transistors using an oxide semiconductor layer are expected to be applied to low-power display devices because of their low off-state leakage current and the ability to perform low-frequency driving. In particular, by applying transistors using an oxide semiconductor layer to a self-emitting organic EL display device, a large effect of reducing power consumption can be obtained.

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2013-254950 Summary of the Invention

[0007] Problems to be Solved by the Invention

[0008] Transistors using an oxide semiconductor layer have problems in terms of low reliability such as a temporal change in the threshold voltage. In the case of forming a transistor using an oxide semiconductor layer by a bottom-gate structure or a double-gate structure, it is difficult to ensure sufficient reliability.

[0009] In view of the above problems, one object of an embodiment of the present invention is to improve the reliability of a display device.

[0010] Means for Solving the Problems

[0011] A display device according to an embodiment of the present invention includes: a substrate; a light-emitting element; a first transistor that controls the current value flowing into the light-emitting element from a driving power line; and a second transistor that writes a voltage corresponding to the light-emitting luminance of the light-emitting element to a first gate electrode of the first transistor. The first transistor includes: a first gate electrode provided on the substrate; a first insulating film provided on the first gate electrode; a first oxide semiconductor layer provided on the first insulating film and having a region overlapping with the first gate electrode; a second insulating film provided on the first oxide semiconductor layer; and a first conductive layer provided on the second insulating film. The second transistor includes: a first insulating film provided on the substrate; a second oxide semiconductor layer provided on the first insulating film; a second insulating film provided on the first oxide semiconductor layer and the second oxide semiconductor layer and having a film thickness smaller than that of the first insulating film; and a second gate electrode provided on the second insulating film and having a region overlapping with the second oxide semiconductor layer. Among them, the first conductive layer is electrically connected to the light-emitting element.

[0012] A display device according to an embodiment of the present invention includes: a substrate; a light-emitting element; a first transistor that controls the current value flowing into the light-emitting element from a driving power line; and a second transistor that writes a voltage corresponding to the light-emitting luminance of the light-emitting element to a first gate electrode of the first transistor. The first transistor includes: a first gate electrode provided on the substrate; a first insulating film provided on the first gate electrode; and a first oxide semiconductor layer provided on the first insulating film and having a region overlapping with the first gate electrode. The second transistor includes: a first insulating film provided on the substrate; a second oxide semiconductor layer provided on the first insulating film; a second insulating film provided on the first oxide semiconductor layer and the second oxide semiconductor layer and having a film thickness smaller than that of the first insulating film; and a second gate electrode provided on the second insulating film and having a region overlapping with the second oxide semiconductor layer. The first oxide semiconductor layer has a first channel region, a low-concentration impurity region provided with the first channel region interposed therebetween, and a first high-concentration impurity region provided adjacent to the low-concentration impurity region. The second oxide semiconductor layer has a second channel region and a second high-concentration impurity region provided with the second channel region interposed therebetween. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a top view illustrating the configuration of a display device according to an embodiment of the present invention.

[0014] Figure 2 is an equivalent circuit diagram of a pixel included in a display device according to an embodiment of the present invention.

[0015] Figure 3 is a diagram illustrating a cross-sectional structure of a pixel of a display device according to an embodiment of the present invention.

[0016] ​​​​Figure 4 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present invention.

[0017] Figure 5 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present invention.

[0018] Figure 6 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present invention.

[0019] Figure 7 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present invention.

[0020] Figure 8 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present invention.

[0021] Figure 9 is a diagram showing a cross-sectional structure of a pixel of a display device according to an embodiment of the present invention.

[0022] Figure 10 is an equivalent circuit diagram of a pixel included in a display device according to an embodiment of the invention.

[0023] Figure 11 is a diagram showing a cross-sectional structure of a pixel of a display device according to an embodiment of the present invention.

[0024] Figure 12 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present invention.

[0025] Figure 13 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present invention.

[0026] Figure 14 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present invention.

[0027] Figure 15 is a diagram showing a cross-sectional structure of a pixel of a display device according to an embodiment of the present invention.

[0028] Figure 16 is an equivalent circuit diagram of a pixel included in a display device according to an embodiment of the present invention.

[0029] Figure 17 is Figure 16 a timing diagram of the pixel circuit shown in

[0030] Figure 18 is an equivalent circuit diagram of a pixel included in a display device according to an embodiment of the present invention.​​​​​​​​​​​​​​

[0031] Figure 19 is Figure 18 the timing diagram of the pixel circuit shown.

[0032] Figure 20 is the diagram showing the cross-sectional structure of the transistor of the embodiment.

[0033] Figure 21 is the diagram showing the Id-Vg characteristics of the double-gate bottom-gate-driven transistor.

[0034] Figure 22 is the diagram showing the Id-Vg characteristics of the double-gate top-gate-driven transistor.

[0035] Figure 23 is the diagram showing the Id-Vg characteristics of the top-gate type.

[0036] Figure 24 is the diagram showing the results of the constant current stress test of the double-gate top-gate-driven transistor.

[0037] Figure 25 is the diagram showing the results of the constant current stress test of the double-gate bottom-gate-driven transistor. DETAILED DESCRIPTION

[0038] Hereinafter, each embodiment of the present invention will be described with reference to the drawings and the like. It should be noted that the present invention can be implemented in various ways without departing from its gist, and is not limited to the content described in the following exemplary embodiments. In addition, regarding the drawings, in order to make the description clearer, there are cases where the width, thickness, shape, etc. of each part are schematically shown compared with the actual mode, and these schematic diagrams are examples and do not limit the interpretation of the present invention. Furthermore, in this specification and each drawing, sometimes the same reference numerals are assigned to elements that are the same as or similar to the elements already described in the drawings appearing previously, and repeated explanations are omitted.

[0039] In the present invention, when a certain film is processed to form a plurality of films, there are cases where the plurality of films have different functions and effects. However, the plurality of films are derived from the films formed as the same layer in the same process and have the same layer structure and the same material. Therefore, it is defined that the plurality of films are in the same layer.

[0040] ​​​​​​​It should be noted that in this specification, expressions such as "upper" and "lower" when describing the drawings represent the relative positional relationship between the structure of interest and other structures. In this specification, when viewed from the side, the direction from the first substrate described later towards the pixel electrode is defined as "upper", and the opposite direction is defined as "lower". In this specification and the claims, when expressing the manner of disposing other structures above a certain structure, in the case of simply noted as "upper", unless otherwise specified, it includes both the case of disposing other structures directly above it in contact with the certain structure and the case of disposing other structures above the certain structure with another structure in between.

[0041] (First Embodiment)

[0042] Refer to Figures 1 to 9 Describe the display device 100 according to an embodiment of the present invention.

[0043] Describe a top view of the configuration of the display device according to an embodiment of the present invention. As Figure 1 shown, the display device 100 includes a display area 102 and a peripheral area 109 provided on a substrate 101.

[0044] The display area 102 has a plurality of pixels 103 arranged in a matrix. Each of the plurality of pixels 103 has a plurality of transistors and light-emitting elements.

[0045] The peripheral area 109 is provided so as to surround the display area 102. It should be noted that the peripheral area 109 refers to the area of the substrate 101 from the display area 102 to the end of the substrate 101. In other words, the peripheral area 109 refers to the area other than the area of the substrate 101 where the display area 102 is provided (i.e., the area outside the display area 102). The peripheral area 109 has gate drive circuits 104_1, 104_2, a terminal portion 107 including a plurality of terminals 106, and a driver IC 105. The gate drive circuits 104_1, 104_2 are provided so as to sandwich the display area 102. The driver IC 105 is connected to the plurality of terminals 106, and the plurality of terminals 106 are connected to a flexible printed circuit 108. In Figure 1 it, an example is shown in which an anode drive circuit is assembled in the driver IC 105, but it is not limited to this manner, and the source drive circuit may be provided independently of the driver IC 105 on the substrate 101. In addition, an example is shown in which the driver IC 105 is arranged on the substrate 101 in the manner of an IC chip, but it is not limited to this manner, and it may also be arranged on the flexible printed circuit 108.

[0046] The driver IC 105 is connected to the gate drive circuits 104_1, 104_2 and a plurality of image signal lines VL. The gate drive circuit 104_1 or the gate drive circuit 104_2 is connected to the pixel 103 via the write control scan line Sg. Among the plurality of write control scan lines Sg, for example, the write control scan lines Sg of odd rows are connected to the gate drive circuit 104_1, and the write control scan lines Sg of even rows are connected to the gate drive circuit 104_2. The image signal line VL is connected to the pixel 103. A control signal SG for selecting each pixel 103 is given to the display area 102 from the driver IC 105 via the gate drive circuits 104_1, 104_2 and the write control scan line Sg. In addition, an image signal Vsig is given to the display area 102 from the driver IC 105 via the image signal line VL. The transistor included in the pixel 103 can be driven by these signals, and image display corresponding to the image signal Vsig is performed on the display area 102. It should be noted that the high-potential power supply SLa and the low-potential power supply electrode SLb connected to the pixel 103 are respectively connected to different terminals 106.

[0047] As the substrate 101, a glass substrate or a flexible plastic substrate is used. When a flexible plastic substrate is used as the substrate 101, the area between the display area 102 and the terminal portion 107 can be bent. Thereby, narrow bezelization of the display device 100 can be achieved.

[0048] <Equivalent circuit diagram>

[0049] Figure 2 It is an equivalent circuit diagram of the pixel 103 included in the display device 100 according to an embodiment of the present invention. The display device 100 includes a high-potential power supply SLa, a low-potential power supply electrode SLb, a write control scan line Sg, and an image signal line VL. The high-potential power supply SLa is supplied with a high-potential power supply Pvdd, and the low-potential power supply electrode SLb is supplied with a low-potential power supply Pvss. The write control scan line Sg is connected to the gate drive circuits 104_1, 104_2, and the image signal line VL is connected to the driver IC 105.

[0050] Each pixel 103 has at least a driving transistor DRT, a writing transistor SST, and a light-emitting element OLED. A high-potential power supply Pvdd is applied to the anode (also referred to as a pixel electrode) of the light-emitting element OLED via the driving transistor DRT, and a low-potential power supply Pvss is applied to the cathode (also referred to as a common electrode). The driving transistor DRT is connected in series with the light-emitting element OLED between the high-potential power supply SLa and the low-potential power supply electrode SLb. The driving transistor DRT functions as a current control element that controls the current value flowing into the light-emitting element OLED corresponding to the gate-source voltage. The writing transistor SST functions as a switching element that selects conduction or non-conduction between two nodes and writes a voltage corresponding to the emission luminance of the light-emitting element OLED. A holding capacitor Cs may be provided between the gate and source of the driving transistor DRT. The holding capacitor Cs holds the gate-source voltage of the driving transistor DRT for a certain period.

[0051] The writing transistor SST has a first terminal, a second terminal, and a control terminal. The driving transistor DRT has a first terminal, a second terminal, a first control terminal, and a second control terminal. In the present embodiment, the first terminal is described as a source electrode, the second terminal is described as a drain electrode, the first control terminal is described as a first gate electrode, and the second control terminal is described as a second gate electrode.

[0052] In the writing transistor SST, the first gate electrode and the second gate electrode are connected to the writing control scan line Sg, the source electrode is connected to the video signal line VL, and the drain electrode is connected to the first gate electrode of the driving transistor DRT. In the driving transistor DRT, the drain electrode is connected to the high-potential power supply SLa, the source electrode is connected to the second gate electrode and one electrode (here, the anode) of the light-emitting element OLED. The other electrode (here, the cathode) of the light-emitting element OLED is connected to the low-potential power supply electrode SLb. The driving transistor DRT outputs a driving current with an electric current amount corresponding to the video signal Vsig to the light-emitting element OLED.

[0053] As the semiconductor layer of the transistor constituting the display device 100, for example, amorphous silicon, low-temperature polycrystalline silicon, or an oxide semiconductor is used. Here, a transistor using an oxide semiconductor layer can achieve a low-power consumption display device 100 because it has a low cut-off leakage current and can perform low-frequency driving. In addition, compared with a transistor having a low-temperature polycrystalline silicon layer, a transistor using an oxide semiconductor layer has good saturation characteristics without observing a kink effect. In the present embodiment, the case where an oxide semiconductor layer is used as the semiconductor layer of the transistor constituting the display device 100 is described.

[0054] Transistors using an oxide semiconductor layer have problems such as low reliability, such as time-dependent variation of the threshold voltage. For example, in the case where a write transistor and a drive transistor are formed by a double-gate structure in order to increase the on-current of a transistor using an oxide semiconductor layer, the voltage applied to the oxide semiconductor layer easily acts on the drive transistor, causing a large amount of current to flow into the drive transistor. As a result, the oxide semiconductor layer undergoes thermal degradation, and the reliability of the drive transistor decreases.

[0055] In the case where a transistor using an oxide semiconductor layer is formed by a top-gate structure, by forming the thickness of the gate insulating film to be 100 nm or more and 200 nm or less, the on-current can be increased and the subthreshold swing value (hereinafter referred to as the S value) can be decreased. Therefore, in the case where a top-gate structure transistor is used as a write transistor, good switching characteristics can be obtained due to the small S value. On the other hand, in the case where a top-gate structure transistor is used as a drive transistor, since it is current-driven, there is a problem that the current variation becomes large due to the small S value. In particular, in a low gray-scale region where fine current control is required, the gray-scale control cannot be finely controlled because the current variation of the drive transistor becomes large. As a result, in the display region 102, there is a problem that display unevenness is likely to occur.

[0056] In addition, in the case where a transistor using an oxide semiconductor layer is formed by a bottom-gate structure, by increasing the thickness of the gate insulating film, the voltage applied to the oxide semiconductor layer is less likely to be generated, so the amount of current flowing into the transistor can be reduced. Therefore, in the case where a bottom-gate structure transistor with a thick gate insulating film is used as a drive transistor, the thermal degradation of the oxide semiconductor layer can be suppressed, and the reliability of the transistor can be improved. On the other hand, in the case where a bottom-gate structure transistor with a thick gate insulating film is used as a write transistor, the on-current Ion of the write transistor tends to decrease due to the thick gate insulating film.

[0057] Therefore, in the case where a transistor using an oxide semiconductor layer is applied to a display device, it is preferable to provide transistors with different characteristics and structures according to the required functions. For example, for a write transistor, it is preferable to provide a transistor with good switching characteristics and a high on-current, while for a drive transistor, it is preferable to provide a transistor with switching characteristics lower than those of the write transistor, capable of suppressing thermal degradation, and having high reliability.

[0058] Therefore, in the display device 100 according to an embodiment of the present invention, the writing transistor SST having a switching function and the transistors constituting the gate drive circuits 104_1 and 104_2 are top-gate driven or dual-gate driven, and the drive transistor having a current control function is bottom-gate driven. It should be noted that in this specification and the like, the so-called top-gate drive means controlling on / off through a gate electrode disposed above the oxide semiconductor layer. As a transistor for top-gate drive, it may be a top-gate structure composed of a gate electrode disposed above the oxide semiconductor layer, or a dual-gate structure composed of gate electrodes above and below the oxide semiconductor layer. In addition, in this specification and the like, the so-called bottom-gate drive means controlling on / off through a gate electrode disposed below the oxide semiconductor layer. As a transistor for bottom-gate drive, it may be a bottom-gate structure composed of a gate electrode disposed below the oxide semiconductor layer, or a dual-gate structure composed of gate electrodes above and below the oxide semiconductor layer. In addition, in this specification, the so-called dual-gate drive means a drive for controlling on / off by inputting the same control signal to the gate electrodes disposed above and below the oxide semiconductor layer.

[0059] <Pixel cross-sectional structure>

[0060] Figure 3 This is a diagram illustrating the cross-sectional structure of the pixel 103 of the display device 100 according to an embodiment of the present invention. As Figure 3 shown, a transistor 210 and a transistor 220 are provided on a substrate 101 with a base film 202 interposed therebetween. The transistor 210 is connected to the light-emitting element 230. Here, the transistor 210 corresponds to the drive transistor DRT, the transistor 220 corresponds to the writing transistor SST, and the light-emitting element 230 corresponds to the light-emitting element OLED.

[0061] The transistor 210 that functions as the driving transistor DRT has a double-gate structure. The transistor 210 has at least a conductive layer 204_1, an insulating film 206 provided on the conductive layer 204_1, an oxide semiconductor layer 208_1 provided on the insulating film 206, an insulating film 212 provided on the oxide semiconductor layer 208_1, and a conductive layer 214_1 provided on the insulating film 212. Here, the first control terminal for controlling the switching of the transistor 210 is the conductive layer 204_1. Therefore, the transistor 210 is bottom-gate driven. In addition, the conductive layer 204_1 also functions as a light-shielding layer that suppresses light irradiation on the back surface of the oxide semiconductor layer 208. The second control terminal is the conductive layer 214_1. Here, the oxide semiconductor layer 208_1 has a channel region 208a and high-concentration impurity regions 208b, 208c. The high-concentration impurity regions 208b, 208c are provided with the channel region 208a interposed therebetween. Here, the channel region 208a overlaps with the conductive layer 204_1. The insulating film 206 functions as the gate insulating film of the transistor 210. An insulating film 216 is provided on the oxide semiconductor layer 208_1. The insulating film 216 functions as an interlayer insulating film. Source electrodes or drain electrodes 218_1, 218_2 are provided on the insulating film 216. The source electrode or drain electrode 218_1 is connected to the high-concentration impurity region 208b through a contact hole provided on the insulating films 212, 216. The source electrode or drain electrode 218_2 is connected to the high-concentration impurity region 208c and the conductive layer 214_1. The conductive layer 214_1 is connected to the pixel electrode 226 of the light-emitting element OLED through the source electrode or drain electrode 218_2. Although not shown, the conductive layer 204_1 is electrically connected to either of the source electrodes or drain electrodes 218_3, 218_4. In addition to the connection of the conductive layer 214_1 shown in Figure 3 , for example, it may also be connected to a fixed potential. As an example of the fixed potential, it is a high-potential power supply Pvdd that is the driving power supply of the light-emitting element OLED, or a low-potential power supply Pvss, etc.

[0062] The transistor 220 that functions as a write transistor SST has a dual-gate structure. The transistor 220 has at least a conductive layer 204_2, an insulating film 206 on the conductive layer 204_2, an oxide semiconductor layer 208_2 disposed on the insulating film 206, an insulating film 212 disposed on the oxide semiconductor layer 208_2, and a conductive layer 214_2 disposed on the insulating film 212. Here, the first control terminal that controls the switch of the transistor 220 is the conductive layer 204_2 and the conductive layer 214_2. Therefore, the transistor 220 is dual-gate driven. In addition, the conductive layer 204_1 also functions as a light shielding layer for suppressing light from being irradiated to the back side of the oxide semiconductor layer 208. The insulating film 206 and the insulating film 212 function as gate insulating films. The oxide semiconductor layer 208_2 has a channel region 208f and high-concentration impurity regions 208g and 208h. The high-concentration impurity regions 208g and 208h are disposed with the channel region 208f sandwiched therebetween. Here, the channel region 208f overlaps with the conductive layer 214_2. An insulating film 216 is provided on the conductive layer 214_2. Source or drain electrodes 218_3 and 218_4 are provided on the insulating film 216. The source or drain electrodes 218_3 and 218_4 are connected to the high-concentration impurity regions 208g and 208h via contact holes provided in the insulating films 212 and 216.

[0063] In this embodiment, in the display device 100, a dual-gate driven transistor having a dual-gate structure is provided as a write transistor SST on the same substrate, and a bottom-gate driven transistor having a dual-gate structure is provided as a drive transistor DRT. At this time, with respect to the insulating films 206 and 212 sandwiching the oxide semiconductor layers 208_1 and 208_2 from top to bottom, in the write transistor SST, both the insulating film 212 and the insulating film 206 function as gate insulating films, and in the drive transistor DRT, the insulating film 206 functions as a gate insulating film. The film thickness of the insulating film 212 is smaller than the film thickness of the insulating film 206. Therefore, the thickness of the gate insulating film can be different in the write transistor SST and the drive transistor DRT. The write transistor SST is configured as a dual-gate drive, and in terms of the threshold voltage, the applied voltage based on the conductive layer 214_2 provided across the thin insulating film 212 is dominant.

[0064] The gate insulating film of the writing transistor SST is formed thinner than that of the driving transistor DRT. Therefore, an electric field is easily applied to the oxide semiconductor layer 208_2, and the on-current can be increased. Further, in the writing transistor SST, impurity elements are added to the oxide semiconductor layer 208_2 using the conductive layer 214_2 as a mask, so that the channel length L can be made short. In one embodiment of the present invention, the channel length L of the writing transistor SST and the driving transistor DRT can be set to, for example, 1.5 μm or more and 4.0 μm or less. As a result, since the S value of the writing transistor SST can be decreased, the switching characteristics of the writing transistor SST are improved. On the other hand, since the gate insulating film of the driving transistor DRT is formed thicker than that of the writing transistor SST, an electric field is less likely to be applied to the oxide semiconductor layer 208_1, and the on-current of the driving transistor DRT can be decreased. Further, since the S value of the driving transistor DRT can be increased, the current change can be made small in the low gray-scale region controlled by a minute current, and gray-scale control can be performed finely. As a result, in the display region 102, occurrence of display unevenness can be suppressed. Further, since a large amount of current can be suppressed from continuously flowing into the driving transistor DRT, a reduction in reliability due to thermal degradation can be suppressed.

[0065] In the driving transistor DRT, the conductive layer 214_1 and the high-concentration impurity region 208c are connected via the source electrode or the drain electrode 218_2. The conductive layer 214_1 is connected to the pixel electrode 226 of the light-emitting element OLED via the source electrode or the drain electrode 218_2. As a result, the source-side signal of the driving transistor DRT can be stabilized. Therefore, in the display region 102, occurrence of display unevenness can be suppressed.

[0066] Note that by applying the transistor 220 having the same configuration as that of the writing transistor SST to the transistors constituting the gate drive circuits 104_1 and 104_2, the gate drive circuits 104_1 and 104_2 can be driven at high speed.

[0067] A planarization film 222 is provided on the source electrodes or drain electrodes 218_1 to 218_4. As the planarization film 222, an organic resin material such as polyimide, polyamide, acrylic resin, or epoxy resin can be used. These materials can form a film by a solution coating method and have an advantage of a high planarization effect. Note that the planarization film 222 is not provided in the peripheral region 109.

[0068] The transistor 210 is connected to the light-emitting element 230. The light-emitting element 230 has a pixel electrode 226, an organic layer 232, and a common electrode 234. In one embodiment of the present invention, the display device 100 can be either a top-emission type or a bottom-emission type. In the present embodiment, the case where the display device 100 has a top-emission structure will be described. In the case of the top-emission structure, the pixel electrode 226 serves as an anode, and the common electrode 234 serves as a cathode.

[0069] The pixel electrode 226 is provided on the planarization film 222. The pixel electrode 226 is provided for each pixel 103. The pixel electrode 226 is connected to the source electrode or the drain electrode 218_2 of the transistor 210 through a contact hole provided on the planarization film 222. A metal film with a high reflectivity is used as the pixel electrode 226. Alternatively, a stacked structure of a transparent conductive layer with a high work function, such as an indium oxide-based transparent conductive layer (e.g., ITO) or a zinc oxide-based transparent conductive layer (e.g., IZO, ZnO), and a metal film is used as the pixel electrode 226.

[0070] An insulating layer 228 is provided so as to cover the end portion of the pixel electrode 226. The insulating layer 228 is also referred to as a partition or a dam. As the insulating layer 228, a photosensitive acrylic resin is used in the same manner as the planarization film 222. The insulating layer 228 is opened in such a manner as to expose the pixel electrode 226, and preferably, the end portion of the opening has a gentle tapered shape. If the end portion of the opening has a steep shape, poor coverage of the subsequently formed organic layer 232 will occur.

[0071] A plurality of organic materials constituting the organic layer 232 are stacked on the pixel electrode 226 and the insulating layer 228. The organic layer 232 is sequentially stacked with a hole transport layer, a light-emitting layer, an electron transport layer, etc. starting from the pixel electrode 226 side. These layers can also be formed by evaporation or coating on the basis of solvent dispersion. In addition, the hole transport layer, the electron transport layer, etc. can be selectively formed for each sub-pixel or formed over the entire surface of the display area 102.

[0072] The common electrode 234 is provided on the organic layer 232. In the present embodiment, since it is a top-emission structure, the common electrode 234 must have light transmissivity. When MgAg is used as the common electrode 234, it is formed of a thin film with a degree of light transmission from the organic layer 232. The common electrode 234 is connected to the wiring layer at the cathode contact portion provided in the peripheral area 109 and is electrically connected to the terminal 106.

[0073] A sealing film 240 is provided on the common electrode 234. The sealing film 240 is provided to suppress moisture invading from the outside from invading the organic layer 232. In the present embodiment, as the sealing film 240, an example formed of a three-layer structure of an inorganic insulating layer 236, an organic insulating layer 238, and an inorganic insulating layer 242 is shown. As the inorganic insulating layers 236 and 233, silicon nitride with high gas barrier properties is preferably used, and as the organic insulating layer 238, an organic resin material with high flexibility is preferably used. It should be noted that a silicon oxide film or an amorphous silicon film can also be provided between the silicon nitride and the organic resin material. Thereby, the adhesion between the silicon nitride and the organic resin material can be improved. A top coat can also be provided on the inorganic insulating layer 242 to achieve planarization at the same time.

[0074] A touch sensor 110 is provided on the sealing film 240. The touch sensor 110 can also be directly formed on the sealing film 240. Alternatively, a cover glass on which the touch sensor 110 is formed can also be provided on the sealing film 240.

[0075] <Manufacturing method of display device>

[0076] Next, with reference to Figures 4 to 8 The manufacturing method of the display device 100 according to an embodiment of the present invention will be described.

[0077] Figure 4 It is a diagram for explaining the process of forming the base film 202 to the insulating film 206 on the substrate 101. As the substrate 101, a glass substrate, a quartz substrate, a flexible substrate (polyimide, polyethylene terephthalate, polyethylene naphthalate, triacetyl cellulose, cyclic olefin copolymer, cycloolefin polymer, other flexible resin substrates) can be used.

[0078] The base film 202 is formed on the substrate 101. As the base film 202, a single-layer silicon oxide or silicon nitride can be used, or silicon oxide and silicon nitride can be combined and laminated. The conductive layers 204_1 and 204_2 are formed on the base film 202. The conductive layers 204_1 and 204_2 are formed by forming a conductive film on the base film 202 and processing it by photolithography. As the conductive layers 204_1 and 204_2, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), zinc (Zn), molybdenum (Mo), copper (Cu), indium (In), tin (Sn), hafnium (Hf), tantalum (Ta), tungsten (W), platinum (Pt), bismuth (Bi), etc. can be used. In addition, alloys of these metals can also be used.

[0079] Next, an insulating film 206 is formed on the conductive layers 204_1 and 204_2. As the insulating film 206, a single-layer silicon oxide or silicon nitride can be used, or a combination of silicon oxide and silicon nitride can be laminated and used. In addition, it is preferable that the film thickness of the insulating film 206 is larger than the film thickness of the insulating film 212 described later. Preferably, the film thickness of the insulating film 206 is formed to be, for example, 250 nm or more and 500 nm or less.

[0080] Figure 5 FIG. is a diagram for explaining the process of forming the oxide semiconductor layers 208_1 and 208_2 to the conductive layers 214_1 and 214_2 on the insulating film 206. First, the oxide semiconductor layers 208_1 and 208_2 are formed on the insulating film 206. The oxide semiconductor layers 208_1 and 208_2 are formed by sputtering an oxide semiconductor film and then processed by photolithography. Preferably, the oxide semiconductor film is formed to have a film thickness of, for example, 30 nm or more and 100 nm or less by sputtering. As the oxide semiconductor layers 208_1 and 208_2, for example, group 13 elements such as indium and gallium can be included. Different multiple group 13 elements can also be contained, or a compound of indium and gallium (IGO) can be used. The oxide semiconductor layers 208_1 and 208_2 can further include group 12 elements, for example, a compound of indium, gallium, and zinc (IGZO) can be cited. The oxide semiconductor layers 208_1 and 208_2 can include other elements, and can also include tin as a group 14 element, titanium as a group 4 element, zirconium, etc.

[0081] Specifically, as the oxide semiconductor layers 208_1 and 208_2, materials such as InOx, ZnOx, SnOx, In-Ga-O, In-Zn-O, In-Al-O, In-Sn-O, In-Hf-O, In-Zr-O, In-W-O, In-Y-O, In-Ga-Zn-O, In-Al-Zn-O, In-Sn-Zn-O, In-Hf-Zn-O, In-Ga-Sn-O, In-Al-Sn-O, In-Hf-Sn-O, In-Ga-Al-Zn-O, In-Ga-Hf-Zn-O, In-Sn-Ga-Zn-O can be used. The crystallinity of the oxide semiconductor layers 208_1 and 208_2 is not limited either, and it can be single crystal, polycrystal, microcrystal, or amorphous.

[0082] When forming an oxide semiconductor film, the power supply applied to the oxide semiconductor target can be either a direct current (DC) or an alternating current (AC), which can be determined according to the shape, composition, etc. of the oxide semiconductor target. As the oxide semiconductor target, for example, if it is InGaZnO, In:Ga:Zn:O = 1:1:1:4 (In2O3:Ga2O3:ZnO = 1:1:2) etc. can be used. In addition, the composition ratio can be determined according to purposes such as the characteristics of the transistor.

[0083] As the sputtering gas for forming the oxide semiconductor film, oxygen, a mixed gas of oxygen and a noble gas, or a noble gas can be used. As the sputtering gas for forming the oxide semiconductor film, it is preferably carried out in an atmosphere of a mixed gas of oxygen and a noble gas, and more preferably the oxygen flow ratio relative to the noble gas is 5% or more. By setting the oxygen flow ratio to 5% or more, it becomes easier to add oxygen to the oxide semiconductor film, so it is preferred.

[0084] Next, an insulating film 212 is formed on the oxide semiconductor layers 208_1 and 208_2. As the insulating film 212, a single-layer silicon oxide or silicon nitride can be used, or a combination of silicon oxide and silicon nitride can be laminated and used. It is preferred that the film thickness of the insulating film 212 is smaller than the film thickness of the insulating film 206. It is preferred that the film thickness of the insulating film 212 is formed to be, for example, 100 nm or more and 200 nm or less.

[0085] It is also possible to perform a heat treatment at least once after the formation of the oxide semiconductor film, after the formation of the oxide semiconductor layers 208_1 and 208_2, or after the formation of the insulating film 212. The oxide semiconductor layers 208_1 and 208_2 may shrink in volume (contract) through the heat treatment, so it is preferred to perform the heat treatment before processing using photolithography. By performing a heat treatment at least once after the formation of the oxide semiconductor film, after the formation of the oxide semiconductor layers 208_1 and 208_2, or after the formation of the insulating film 212, it is possible to improve the film quality such as reducing the hydrogen concentration and increasing the density of the oxide semiconductor layers 208_1 and 208_2.

[0086] The heat treatment performed on the oxide semiconductor film or the oxide semiconductor layers 208_1 and 208_2 can be carried out at atmospheric pressure or low pressure (vacuum) in the presence of nitrogen, dry air, or the atmosphere. The heating temperature is 250°C to 500°C, preferably 350°C to 450°C. In addition, the heating time is, for example, 15 minutes or more and 1 hour or less. Through the heat treatment, oxygen is introduced or dislocated to the oxygen-deficient sites of the oxide semiconductor layers 208_1 and 208_2, thereby obtaining oxide semiconductor layers 208_1 and 208_2 with few crystal defects and high crystallinity. In addition, the hydrogen concentration of the oxide semiconductor layers 208_1 and 208_2 can be reduced through the heat treatment.

[0087] Next, conductive layers 214_1 and 214_2 are formed on the insulating film 212. The conductive layers 214_1 and 214_2 are formed by forming a conductive film on the insulating film 212 and processing it using photolithography. As the conductive layers 214_1 and 214_2, for example, the same materials as those of the conductive layers 204_1 and 204_2 can be used. The conductive layer 214_1 is formed in a region overlapping with the conductive layer 204_1 and the oxide semiconductor layer 208_1, and the conductive layer 214_2 is formed in a region overlapping with the conductive layer 204_2 and the oxide semiconductor layer 208_2.

[0088] Figure 6 It is a diagram for explaining the process of adding impurity elements to the oxide semiconductor layers 208_1 and 208_2 by ion implantation. Using the conductive layers 214_1 and 214_2 as masks, impurity elements are added to the oxide semiconductor layers 208_1 and 208_2 by ion implantation. Here, as the impurity elements, hydrogen, argon, phosphorus, boron, etc. are used. The purpose of adding impurity elements to the oxide semiconductor layer is not to control the conductivity type of the transistor, so the type of impurity element is not particularly limited. The concentration (dose) of the impurity element is set to 1×10 14 atoms / cm 2 ~5×10 15 atoms / cm 2 , and added to the oxide semiconductor layers 208_1 and 208_2. Thereby, in the oxide semiconductor layer 208_1, high-concentration impurity regions 208b and 208c are formed in regions not overlapping with the conductive layer 214_1, and a channel region 208a is formed in a region overlapping with the conductive layer 214_1. In the oxide semiconductor layer 208_2, high-concentration impurity regions 208g and 208h are formed in regions not overlapping with the conductive layer 214_2, and a channel region 208f is formed in a region overlapping with the conductive layer 214_2. The high-concentration impurity regions 208b, 208c, 208g, and 208h include impurity elements at a concentration of about 5×10 13 atoms / cm 3 ~2.5×10 15 atoms / cm 3 . The concentration of the impurity elements contained in the oxide semiconductor layers 208_1 and 208_2 can be measured, for example, by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry).

[0089] By adding impurity elements to the oxide semiconductor layers 208_1 and 208_2, defects are generated in the crystals of the oxide semiconductor layers 208_1 and 208_2, so that the resistance of this region is reduced. The resistance of the oxide semiconductor layers 208_1 and 208_2 can be reduced corresponding to the concentration of the added impurity elements. Since the channel regions 208a and 208f have few crystal defects and low hydrogen concentration, they maintain a high-resistance state. In this way, the resistance of the high-concentration impurity regions 208b, 208c, 208g, and 208h can be made lower than the resistance of the channel regions 208a and 208f.

[0090] Figure 7 FIG. is a diagram for explaining the process of forming the source electrode or drain electrode 218_1 to 218_4 from the insulating film 216 on the oxide semiconductor layers 208_1 and 208_2. First, an insulating film 216 is formed on the oxide semiconductor layers 208_1 and 208_2. As the insulating film 216, a single-layer silicon oxide or silicon nitride can be used, or a combination of silicon oxide and silicon nitride can be laminated. In addition, it is preferable that the film thickness of the insulating film 216 is larger than the film thickness of the insulating film 212. It is preferable that the film thickness of the insulating film 216 is formed to be, for example, 250 nm or more and 500 nm or less.

[0091] Next, contact holes reaching the oxide semiconductor layers 208_1, 208_2, and the conductive layer 214_1 are formed on the insulating film 212 and the insulating film 216. Next, source electrodes or drain electrodes 218_1 to 218_4 are formed on the insulating film 216. The source electrodes or drain electrodes 218_1 to 218_4 are formed by forming a conductive film on the insulating film 216 and processing the conductive film using photolithography. Thus, the source electrode or drain electrode 218_1 is connected to the high-concentration impurity region 208b, and the source electrode or drain electrode 218_2 is connected to the high-concentration impurity region 208c and the conductive layer 214_1. The source electrode or drain electrode 218_3 is connected to the high-concentration impurity region 208g, and the source electrode or drain electrode 218_4 is connected to the high-concentration impurity region 208h. As the source electrodes or drain electrodes 218_1 to 218_4, the same materials as those of the conductive layers 204_1 and 204_2 can be used. Although not shown, at this process, contact holes reaching the conductive layer 204_1 can also be formed on the insulating films 206, 212, and 216. Thus, the conductive layer 204_1 can be connected to the source electrode or drain electrode 218_3. The transistors 210 and 220 can be formed by the processes so far.

[0092] Figure 8This is a diagram illustrating the process of forming the planarization film 222 and the pixel electrode 226. The planarization film 222 is formed on the source or drain electrodes 218_1 to 218_4. As the planarization film 222, an organic resin material such as polyimide, acrylic resin, or epoxy resin can be used. These materials can form a film by a solution coating method and have a high planarization effect.

[0093] The light-emitting element 230 is formed by forming the pixel electrode 226, the organic layer 232, and the common electrode 234. First, a contact hole reaching the source electrode or drain electrode 218_2 is formed in the planarization film 222. Next, the pixel electrode 226 is formed on the planarization film 222. The pixel electrode 226 is formed by forming a conductive film on the planarization film 222 and processing the conductive film using photolithography. An insulating layer 228 is formed with an opening that exposes the pixel electrode 226. Next, a plurality of organic materials constituting the organic layer 232 are formed on the pixel electrode 226 and the insulating layer 228. Next, the common electrode 234 is formed on the organic layer 232.

[0094] Then, the encapsulation film 240 is formed by forming the inorganic insulating layer 236, the organic insulating layer 238, and the inorganic insulating layer 242 on the common electrode 234. First, the inorganic insulating layer 236 is formed on the common electrode 234. Next, the organic insulating layer 238 is formed on the inorganic insulating layer 236. Next, the inorganic insulating layer 242 is formed on the organic insulating layer 238. At this time, it is preferable that the end portion of the inorganic insulating layer 236 is in contact with the end portion of the inorganic insulating layer 242 to encapsulate the organic insulating layer 238. Thereby, it is possible to suppress the deterioration of the light-emitting element 230 due to the intrusion of moisture from the outside of the encapsulation film 240.

[0095] Through the above processes, it is possible to manufacture Figure 3 the display device 100 having the configuration of the pixel 103 shown.

[0096] According to the manufacturing method of the display device 100 according to an embodiment of the present invention, even for a small area within one pixel, it is possible to more simply form two types of transistors having different characteristics and structures without increasing the processing.

[0097] (Modification 1)

[0098] Next, with reference to Figure 9 description will be made of the pixel 103A having a configuration different from that of the pixel 103 shown. Figure 3 shown.

[0099] Figure 9 This is a diagram illustrating the cross-sectional structure of the pixel 103A of the display device 100 according to an embodiment of the present invention. As Figure 9As shown, a transistor 210 and a transistor 250 are provided on a substrate 101 with a base film 202 interposed therebetween. Here, the transistor 210 corresponds to the driving transistor DRT shown in Figure 3 and the transistor 250 corresponds to the writing transistor SST shown in Figure 3 . It should be noted that the structure of the transistor 210 is the same as that of the transistor 210 shown in Figure 3 , so the description thereof is omitted.

[0100] The transistor 250 functioning as the writing transistor SST has a top-gate structure. The transistor 250 has at least an oxide semiconductor layer 208_3 provided on an insulating film 206, an insulating film 212 provided on the oxide semiconductor layer 208_3, and a conductive layer 214_3 provided on the insulating film 212. Here, the control terminal for controlling the switching of the transistor 250 is the conductive layer 214_3. The insulating film 212 functions as a gate insulating film. The oxide semiconductor layer 208 has a channel region 208i and high-concentration impurity regions 208j, 208k. An insulating film 212 is provided on the conductive layer 214_3. Source electrodes or drain electrodes 218_5, 218_6 are provided on the insulating film 212. The source electrodes or drain electrodes 218_5, 218_6 are connected to the high-concentration impurity regions 208j, 208k through contact holes provided in the insulating films 212, 216.

[0101] Since the gate insulating film of the writing transistor SST is formed thinner than that of the driving transistor DRT, an electric field is more easily applied to the oxide semiconductor layer 208_3, and the on-current can be increased. In addition, since the channel length L can be shortened, the switching characteristics are improved. On the other hand, since the gate insulating film of the driving transistor DRT is formed thicker than that of the writing transistor SST, an electric field is less easily applied to the oxide semiconductor layer 208_1, and the on-current can be decreased. In particular, in the low-gray-scale region controlled by a small current, since the current change of the driving transistor DRT can be made small, gray-scale control can be performed finely. Thus, in the display region 102, display unevenness can be suppressed. In addition, since a large amount of current flowing continuously into the driving transistor DRT can be suppressed, a reduction in reliability associated with thermal degradation can be suppressed.

[0102] (Second Embodiment)

[0103] In this embodiment, the structure of a pixel 103B that is different from the pixel 103 described in the first embodiment will be described with reference to Figure 10 and Figure 11 . It should be noted that for the structure of the pixel 103B, parts having the same parts or the same functions as those of the pixel 103 are denoted by the same reference numerals, and repeated descriptions are omitted.

[0104] <Equivalent circuit diagram>

[0105] Figure 10 This is the equivalent circuit diagram of the pixel 103B included in the display device 100 according to an embodiment of the present invention. In Figure 10 the shown equivalent circuit diagram, the difference from Figure 2 the shown equivalent circuit diagram lies in the configuration of the driving transistor DRT. In Figure 10 it, the driving transistor DRT is bottom-gate driven, and the writing transistor SST is top-gate driven.

[0106] <Cross-sectional structure of pixel>

[0107] Figure 11 This is a diagram for explaining the cross-sectional structure of the pixel 103B of the display device 100 according to an embodiment of the present invention. As Figure 11 shown, a transistor 210A and a transistor 250 are provided on a substrate 101 with a base film 202 interposed therebetween. Here, the transistor 250 corresponds to Figure 10 the shown writing transistor SST, and the transistor 210A corresponds to Figure 10 the shown driving transistor DRT. It should be noted that the structure of the transistor 250 is the same as that of the transistor 250 shown in Figure 9 so a detailed description thereof is omitted.

[0108] The transistor 210A that functions as a driving transistor DRT has a bottom gate structure. The transistor 210A has at least a conductive layer 204_1, an insulating film 206 provided on the conductive layer 204_1, and an oxide semiconductor layer 208_1 provided on the insulating film 206. Here, the oxide semiconductor layer 208_1 has a channel region 208a, high-concentration impurity regions 208b, 208c, and low-concentration impurity regions 208d, 208e. The low-concentration impurity regions 208d, 208e are provided with the channel region 208a interposed therebetween. The high-concentration impurity regions 208b, 208c are provided adjacent to the low-concentration impurity regions 208d, 208e. Here, the channel region 208a and the low-concentration impurity regions 208d, 208e overlap with the conductive layer 204_1. The insulating film 206 functions as a gate insulating film of the transistor 210. An insulating film 212 is provided on the oxide semiconductor layer 208_1, and an insulating film 216 is further provided on the insulating film 212. Preferably, the film thickness of the insulating film 206 is larger than the film thickness of the insulating film 212. The film thickness of the insulating film 206 is 250 nm or more and 500 nm or less. The film thickness of the insulating film 212 is 100 nm or more and 200 nm or less. Source electrodes or drain electrodes 218_1, 218_2 are provided on the insulating film 216. The source electrodes or drain electrodes 218_1, 218_2 are connected to the high-concentration impurity regions 208b, 208c via contact holes provided on the insulating films 212, 216. Although not shown, the conductive layer 204_1 is electrically connected to one of the source electrodes or drain electrodes 218_3, 218_4.

[0109] Figure 11 In the transistor 210A shown, low-concentration impurity regions 208d, 208e are provided between the channel region 208a and the high-concentration impurity regions 208b, 208c in the oxide semiconductor layer 208_1. Thereby, since the electric field applied near the end of the channel region 208a becomes smaller, the source / drain resistance can be improved. By overlapping the low-concentration impurity regions 208d, 208e with the conductive layer 204_1, the source / drain resistance can be further improved.

[0110] As Figure 11As shown, in the display device 100, on the same substrate, a transistor with a top-gate structure is provided as the writing transistor SST, and a transistor with a bottom-gate structure is provided as the driving transistor DRT. At this time, regarding the insulating films 206 and 212 that sandwich the oxide semiconductor layers 208_1 and 208_2 up and down, in the writing transistor SST, the insulating film 212 functions as a gate insulating film, and in the driving transistor DRT, the insulating film 206 functions as a gate insulating film. At this time, the film thickness of the insulating film 212 is smaller than the film thickness of the insulating film 206. Therefore, in the writing transistor SST and the driving transistor DRT, the thickness of the gate insulating film can be made different. That is to say, a thin gate insulating film can be applied to the top-gate-driven SST, and a thick gate insulating film can be applied to the bottom-gate-driven driving transistor DRT.

[0111] The gate insulating film of the writing transistor SST is formed thinner than the gate insulating film of the driving transistor DRT. Therefore, the electric field becomes easy to be applied to the oxide semiconductor layer 208_2, and a large conduction current can be obtained. In addition, in the writing transistor SST, since impurity elements are added to the oxide semiconductor layer 208_2 via the conductive layer 214_2, the channel length L can be made short. Thereby, the S value of the writing transistor SST can be made small. On the other hand, the gate insulating film of the driving transistor DRT is formed thicker than the gate insulating film of the writing transistor SST. Therefore, the electric field becomes difficult to be applied to the oxide semiconductor layer 208_1, and a small conduction current can be obtained. In particular, in the low gray-scale region controlled by a small current, since the current change of the driving transistor DRT can be made small, gray-scale control can be performed finely. Thereby, in the display region 102, the occurrence of display unevenness can be suppressed. In addition, since a large amount of current flowing continuously into the driving transistor DRT can be suppressed, the reduction in reliability associated with thermal degradation can be suppressed. In addition, as described in the first embodiment, when dual-gate driving is performed in the writing transistor SST, the BT stress of the gate becomes larger compared with the case of performing single-side gate driving. Therefore, although there is an advantage that the on-off characteristics of the transistor become sharp, there is a case where the reliability is somewhat sacrificed. Therefore, in the case where the driving ability is sufficient in top-gate driving and backlight shielding is not required, by omitting the bottom gate, the reliability can be improved.

[0112] <Manufacturing method of the display device>

[0113] Next, refer to Figures 12 to 15 The manufacturing method of the display device 100 according to an embodiment of the present invention will be described. It should be noted that for the process of forming the base film 202 on the substrate 101 to the process of forming the insulating film 212, refer to Figure 4 and Figure 5 for the description.

[0114] Figure 12 2 is a diagram illustrating a process of forming a conductive layer 214_2 and a resist mask 215 on an insulating film 212. First, a conductive layer 214_2 is formed on the insulating film 212. The conductive layer 214_4 is formed by forming a conductive film on the insulating film 212 and processing it using a photolithography method. The conductive layer 214_2 is formed in a region overlapping with the oxide semiconductor layer 208_2. Next, a resist mask 215 is formed in a portion of the region overlapping with the oxide semiconductor layer 208_1 provided on the insulating film 212. Here, the resist mask 215 is formed in a manner such that the end portion becomes a tapered shape. The resist mask 215 may be formed such that the film thickness decreases as it approaches the end portion, and is not limited to a tapered shape.

[0115] Figure 13 2 is a diagram for explaining a process of adding an impurity element to the oxide semiconductor layers 208_1 and 208_2 by ion implantation. Using the conductive layer 214_2 and the resist mask 215 as a mask, an impurity element is added to the oxide semiconductor layers 208_1 and 208_2 by ion implantation. The impurity element is added to the oxide semiconductor layers 208_1 and 208_2 to a concentration of 1×10 14 Atom / cm 2 ~5×10 15 Atom / cm 2 Thus, in the oxide semiconductor layer 208_2, high-concentration impurity regions 208g and 208h are formed in regions not overlapping with the conductive layer 214_2, and a channel region 208f is formed in a region overlapping with the conductive layer 214_2. 13 Atom / cm 3 ~2.5×10 15 Atom / cm 3 The concentration of about 1000 impurity elements is included. At the same time, in the oxide semiconductor layer 208_1, high-concentration impurity regions 208b and 208c are formed in the region not overlapped by the resist mask 215. In addition, in the region overlapped by the resist mask 215, impurity elements are added through the resist mask 215 in the region overlapping with the cone shape, thereby forming low-concentration impurity regions 208d and 208e. In addition, the region of the resist mask 215 that overlaps with the portion other than the cone shape forms the channel region 208a. In the high-concentration impurity regions 208b and 208c, 5×10 13 Atom / cm 3 ~2.5×10 15 Atom / cm 3 In addition, in the low-concentration impurity regions 208d and 208e, since the impurity elements are added via the resist mask 215, the concentration of 2.5×10 12 Atom / cm3 ~5×10 13 atoms / cm 3 The concentration of about... includes impurity elements.

[0116] By adding impurity elements to the oxide semiconductor layers 208_1 and 208_2, defects are generated in the crystals of the oxide semiconductor layers 208_1 and 208_2, so that the resistance of this region decreases. The resistance of the oxide semiconductor layers 208_1 and 208_2 can be reduced corresponding to the concentration of the added impurity elements. Therefore, the resistance of the high-concentration impurity regions 208b, 208c, 208g, and 208h can be lower than that of the low-concentration impurity regions 208d and 208e. In addition, by using the resist mask 215 having a conical shape and the conductive layer 214_2 as masks, a structure having low-concentration impurity regions 208d and 208e can be formed on the oxide semiconductor layer 208_1 and a structure without low-concentration impurity regions can be formed on the oxide semiconductor layer 208_2 through a single impurity element addition process. On the other hand, the channel regions 208a and 208f have a high resistance because they have few crystal defects and a low hydrogen concentration. In this way, different oxide semiconductor layers 208_1 and 208_2 can be formed through the same process. It should be noted that the resist mask 215 is removed after adding the impurity elements.

[0117] Figure 14 It is a diagram for explaining the process from forming the insulating film 216 to forming the pixel electrode 226. For the process from forming the insulating film 216 to forming the pixel electrode 226, refer to Figure 8 the description in... In addition, for the process from forming the insulating layer 228 to forming the inorganic insulating layer 242, the manufacturing method described in the first embodiment can be applied.

[0118] Through the above process, a display device 100 having the configuration of the pixel 103B shown in Figure 11 can be manufactured.

[0119] According to the manufacturing method of the display device 100 according to an embodiment of the present invention, even in a small area within one pixel, two types of transistors having different characteristics and structures can be simply formed without increasing the processing. In particular, the oxide semiconductor layer 208_1 including the high-concentration impurity regions 208b and 208c and the low-concentration impurity regions 208d and 208e and the oxide semiconductor layer 208_2 including the high-concentration impurity regions 208g and 208h can be formed simultaneously.

[0120] (Modification Example 2)

[0121] Figure 15This is a cross-sectional structure diagram of pixel 103C of display device 100 according to an embodiment of the present invention. As Figure 15 shown, transistor 210B and transistor 250 are provided on substrate 101 with base film 202 therebetween. Here, transistor 250 corresponds to Figure 10 the write transistor SST shown, and transistor 210B corresponds to Figure 10 the drive transistor DRT shown.

[0122] Regarding transistor 210B, in the structure of transistor 210A, conductive layer 214_1 and high-concentration impurity region 208b are connected via source electrode or drain electrode 218_2. When forming transistor 210B, after forming conductive layers 214_1 and 214_2, impurity elements of about 5×10 12 atoms / cm 2 ~1×10 14 atoms / cm 2 are added using conductive layers 214_1 and 214_2 as masks. Then, after forming a resist mask to cover conductive layer 214_1 and low-concentration impurity regions 208d and 208e, impurity elements are added to the extent of 1×10 14 atoms / cm 2 ~5×10 13 atoms / cm 2 . Thus, channel region 208a, high-concentration impurity regions 208b and 208c, and low-concentration impurity regions 208d and 208e can also be formed in oxide semiconductor layer 208_1 of drive transistor DRT.

[0123] (Embodiment 3)

[0124] In this embodiment, with reference to Figure 16 and Figure 17 the circuit configuration and operation method of the pixel included in display device 100 are described.

[0125] <Equivalent Circuit Diagram>

[0126] Figure 16 This is an equivalent circuit diagram of pixel 103E included in display device 100 according to an embodiment of the present invention. Display device 100 includes a high-potential power supply SLa, a low-potential power supply electrode SLb, a light emission control scan line Sga, a write control scan line Sgb, a reset control scan line Sgc, and an image signal line VL. The high-potential power supply SLa is supplied with a high-potential power Pvdd, and the low-potential power supply electrode SLb is supplied with a low-potential power Pvss. The light emission control scan line Sga, the write control scan line Sgb, and the reset control scan line Sgc are connected to gate drive circuits 104_1 and 104_2. In addition, the image signal line VL is connected to driver IC 105.

[0127] Pixel 103E includes a write transistor SST, a drive transistor DRT, a holding capacitor Cs, and an additional capacitor Cad. The holding capacitor Cs and the additional capacitor Cad are capacitors. The additional capacitor Cad is an element provided for adjusting the light emission current amount, and there are cases where it is not required depending on the situation. The parasitic capacitance Cel is the capacitance of the light emitting element itself (the parasitic capacitance of the light emitting element OLED). The light emitting element OLED also functions as a capacitor.

[0128] Each pixel 103E includes an output transistor BCT. In the present embodiment, four adjacent pixels 103E in the row direction X and the column direction Y share one output transistor BCT. In addition, a plurality of reset transistors RST are provided in the gate drive circuits 104_1 and 104_2. The reset transistors RST and the reset control scan line Sgr are connected one-to-one.

[0129] The drive transistor DRT has the structure of the transistor 210 shown in the first embodiment, and the write transistor SST, the output transistor BCT, and the reset transistor RST have the structure of the transistor 220 shown in the first embodiment. Alternatively, the drive transistor DRT may have the structure of the transistor 210A or the transistor 210B shown in the second embodiment, and the write transistor SST, the output transistor BCT, and the reset transistor RST may have the structure of the transistor 220 or the transistor 250 shown in the second embodiment. In the display device 100 of the present embodiment, all the drive transistors and the transistors respectively constituting each switch are formed in the same process.

[0130] The write transistor SST, the drive transistor DRT, the output transistor BCT, and the reset transistor RST each have a first terminal, a second terminal, and a control terminal. In the present embodiment, the first terminal is set as the source electrode, the second terminal is set as the drain electrode, and the control terminal is set as the gate electrode.

[0131] In the pixel circuit of the pixel, the drive transistor DRT is connected in series with the light emitting element OLED between the high potential power supply SLa and the low potential power supply electrode SLb.

[0132] In the output transistor BCT, the drain electrode is connected to the high potential power supply SLa, the source electrode is connected to the drain electrode of the drive transistor DRT, and the gate electrode is connected to the light emission control scan line Sga. Thus, the output transistor BCT is controlled to be turned on (conducting state) and turned off (non-conducting state) by the control signal BG(1~m / 2) from the light emission control scan line Sga. The output transistor BCT controls the light emission time of the light emitting element OLED in response to the control signal BG.

[0133] In the driving transistor DRT, the drain electrode is connected to the source electrode of the output transistor BCT and the reset control scan line Sgr, and the source electrode is connected to one electrode (here, the anode) of the light-emitting element OLED. The other electrode (here, the cathode) of the light-emitting element OLED is connected to the low-potential power supply electrode SLb. The driving transistor DRT outputs a driving current having an amount corresponding to the video signal Vsig to the light-emitting element OLED.

[0134] In the writing transistor SST, the source electrode is connected to the video signal lines VL(1 to n), the drain electrode is connected to the gate electrode of the driving transistor DRT, and the gate electrode is connected to the writing control scan lines Sgb(1 to m) that function as gate wirings for signal writing control. The writing transistor SST is controlled to be turned on and off by the control signals SG(1 to m) supplied from the writing control scan lines Sgb. Further, the writing transistor SST controls the connection and disconnection between the pixel circuit and the video signal lines VL(1 to n) in response to the control signals SG(1 to m), and takes in the video signal Vsig from the corresponding video signal lines VL(1 to n) into the pixel circuit.

[0135] The reset transistor RST is provided in the gate driving circuits 104_1 and 104_2 every two rows. The reset transistor RST is connected between the drain electrode of the driving transistor DRT and the reset power supply. In the reset transistor RST, the source electrode is connected to the reset power supply line SLc to which the reset power supply is connected, the drain electrode is connected to the reset control scan line Sgr, and the gate electrode is connected to the reset control scan line Sgc that functions as a gate wiring for reset control. As described above, the reset power supply line SLc is connected to the reset power supply and is fixed to the reset potential Vrst that is a constant potential.

[0136] The reset transistor RST switches the connection between the reset power supply line SLc and the reset control scan line Sgr to a conductive state (conductive) or a non-conductive state (cutoff) in response to the control signal RG(1 to m / 2) applied via the reset control scan line Sgc. By switching the reset transistor RST to the conductive state, the potential of the source electrode of the driving transistor DRT is initialized.

[0137] The gate drive circuits 104_1 and 104_2 include a shift register, an output buffer, etc. (not shown), sequentially transfer the horizontal scan start pulse supplied from the outside to the next stage, and supply three control signals, namely, control signal BG(1 to m / 2), control signal SG(1 to m), and control signal RG(1 to m / 2) to the pixels 103E of each row via the output buffer. It should be noted that although the control signal RG is not directly supplied to the pixel 103E, a prescribed voltage is supplied from the reset power supply line SLc fixed at the reset potential Vrst at a prescribed timing corresponding to the control signal RG. Thus, the light emission control scan line Sga, the write control scan line Sgb, and the reset control scan line Sgc are respectively driven by the control signals BG, SG, and RG.

[0138] <Timing diagram>

[0139] Figure 17 is for driving Figure 16 The timing diagrams of the gate drive circuits 104_1 and 104_2 for driving the pixels shown. In Figure 17 it, the control signal RGk, the control signal BGk, and the control signal SGk of the k-th row and the control signal RGk+1, the control signal BGk+1, and the control signal SGk+1 of the (k + 1)-th row are shown. Each section represented by G1 to G4 is a horizontal period, although omitted later, it continues to the last row. The periods represented by T0 to in Figure 16 will be described in detail below.

[0140] <T0. Previous frame light emission>

[0141] During the period until the start of processing in a certain frame period, the pixel continues the light emission state of the previous frame.

[0142] <T1. DRT source initialization operation>

[0143] During this period, first, the control signal BG becomes the L level, the control signal RG becomes the H level, the control signal SG becomes the L level, the output transistor BCT is cut off, the reset transistor RST is turned on, and the write transistor SST is cut off. Here, the holding capacitor Cs holds "the voltage corresponding to the video signal written in the previous frame". If the video signal Vsig is greater than the reset potential Vrst, the source side also approaches the reset potential Vrst through the driving transistor DRT. In addition, since the reset potential Vrst becomes a potential substantially the same as the low potential power supply Pvss, the current supply to the light emitting element OLED stops. Thus, the source side potential of the driving transistor DRT becomes the lowest state in the pixel system.

[0144] <T2. DRT gate initialization>

[0145] During this period, the control signal BG becomes the L level, the control signal RG becomes the H level, the control signal SG becomes the H level, the image signal line VL becomes the initialization potential Vini, the output transistor BCT is turned off, the reset transistor RST is turned on, and the write transistor SST is turned on. In each pixel 103E of each row, via the write transistor SST, the gate of the drive transistor DRT is fixed at the initialization potential Vini. The initialization potential Vini is set to a potential larger than the threshold value of the drive transistor DRT with respect to the reset potential Vrst. That is to say, through this operation, the drive transistor DRT becomes the conducting state. It should be noted that since the output transistor BCT is in the off state, no current flows into the drive transistor DRT yet. It should be noted that in the T1.DRT source initialization operation, even if the image signal Vsig is not in a state larger than the reset potential Vrst, the source of the drive transistor DRT can be initialized during this period.

[0146] <T3. Offset cancellation operation>

[0147] During this period, the control signal BG becomes the H level, the control signal RG becomes the L level, the control signal SG becomes the H level, the image signal line VL becomes the initialization potential Vini, the output transistor BCT is turned on, the reset transistor RST is turned off, and the write transistor SST is turned on. Since the drive transistor DRT has become the conducting state through the previous operation, current is supplied to the drive transistor DRT from the high-potential power supply Pvdd via the output transistor BCT. At this stage, since the voltage between the anode and the cathode of the light-emitting element OLED does not exceed the light-emitting start voltage, no current flows. Therefore, the source of the drive transistor DRT is charged by the current supplied from the high-potential power supply Pvdd, and its potential rises. At this time, the gate potential of the drive transistor DRT becomes Vini. Therefore, when the source of the drive transistor DRT becomes (Vini - Vth), the drive transistor DRT is turned off and the rise of the potential stops. Vth is the threshold voltage of the drive transistor DRT. Since there are deviations according to the pixel 103E, the potential of the source of the drive transistor DRT when the potential rise stops is different according to the pixel. That is to say, through this operation, a voltage equivalent to the threshold voltage of the drive transistor DRT is obtained in each pixel 103E. At this time, a voltage of {(Vini - Vth) - Pvss} is applied between the anode and the cathode of the light-emitting element OLED, but since this voltage still does not exceed the light-emitting start voltage, no current flows into the light-emitting element OLED.

[0148] It should be noted that according to Figure 17 the timing diagram, the operations of 1. to 3. are implemented in parallel for two rows, but it is not limited to this. It can also be implemented one by one row by row, or three or more rows can be implemented in parallel.

[0149] <T4. Migration Rate Elimination and Image Signal Writing Operation>

[0150] The control signal BG becomes high level, the control signal RG becomes low level, the control signal SG becomes high level, the image signal line VL becomes the image signal Vsig, the output transistor BCT is turned on, the reset transistor RST is turned off, and the write transistor SST is turned on. In each pixel 103E of this row, the image signal Vsig is input to the gate of the driving transistor DRT, and the gate potential of the driving transistor DRT changes from the initialization potential Vini to the image signal Vsig. On the other hand, the source potential of the driving transistor DRT remains (Vini - Vth). As a result, the gate-source voltage of the driving transistor DRT becomes {Vsig - (Vini - Vth)}, thereby reflecting the threshold deviation between the pixels 103E.

[0151] Since the image signal line VL sharing the image signal Vsig is shared by multiple rows of pixels 103E belonging to the same column, the image signal writing operation is sequentially performed row by row.

[0152] <T5. Light Emission Operation>

[0153] The control signal BG becomes high level, the control signal RG becomes low level, the control signal SG becomes low level, the output transistor BCT is turned on, the reset transistor RST is turned off, and the write transistor SST is turned off. Current is supplied from the high-potential power supply Pvdd to the driving transistor DRT via the output transistor BCT. The driving transistor DRT causes current corresponding to the gate-source voltage set until the previous stage to flow into the light-emitting element OLED, and the light-emitting element OLED emits light with a brightness corresponding to the current. At this time, the anode-cathode voltage of the light-emitting element OLED becomes a voltage corresponding to the current. Therefore, the potential on the anode side rises, and the gate-source voltage of the driving transistor DRT is held by the holding capacitor Cs. Therefore, along with the rise of the potential on the anode side, the gate potential of the driving transistor DRT also rises through the coupling of the holding capacitor Cs. In fact, since the gate of the driving transistor DRT has not only the holding capacitor Cs but also an additional capacitor Cad and other parasitic capacitors, the rise of the gate potential of the driving transistor DRT is slightly smaller than the rise of the potential on the anode side. However, since this value is known, the potential of the image signal Vsig can be determined so that the desired current value is obtained at the gate-source voltage of the final driving transistor DRT.

[0154] Thus, a series of operations of the pixel is completed. When this operation is completed from the first row to the last row, a display of one frame period is formed. Thereafter, this operation is repeated to display an image.

[0155] Any one of the bottom-gate-driven transistors 210, 210A, and 210B described in the first embodiment and the second embodiment is applied to the driving transistor DRT. In addition, any one of the top-gate-driven transistors 220 and 250 described in the first embodiment and the second embodiment is applied to the reset transistor RST, the initialization transistor IST, etc., in addition to the writing transistor SST. Thus, since the S value of the driving transistor DRT is large, in a low gray-scale region where fine current control is required, the current change of the driving transistor DRT can be made small, and gray-scale control can be performed finely. As a result, display unevenness can be suppressed in the display area 102.

[0156] (Fourth Embodiment)

[0157] In this embodiment, with reference to Figure 18 and Figure 19 the circuit configuration and operation method of the pixel 103F included in the display device 100 are described.

[0158] <Circuit Diagram>

[0159] Figure 18 is an equivalent circuit diagram of the pixel circuit of the pixel 103F. The light emission control scan line Sga, the write control scan line Sgb, the reset control scan line Sgc, and the initialization control scan line Sgd are respectively connected to the gate drive circuits 104_1 and 104_2 provided outside the display area 102. In each pixel 103F, an output transistor BCT, an initialization transistor IST, a write transistor SST, and a driving transistor DRT are provided. Some transistors may be shared among adjacent multiple pixels 103F. The reset transistor RST is provided, for example, one for each row outside the display area. A holding capacitor Cs may be provided between the gate and source of the driving transistor DRT. The parasitic capacitance Cel is the parasitic capacitance between the anode and cathode of the light-emitting element OLED. A high-potential power supply Pvdd is applied to the anode of the light-emitting element OLED via the output transistor BCT and the driving transistor DRT, and a low-potential power supply Pvss is applied to the cathode. The output transistor BCT, the initialization transistor IST, and the write transistor SST function as switching elements for selecting conduction and non-conduction between two nodes, and the driving transistor DRT functions as a current control element for controlling the current value flowing into the OLED corresponding to the voltage between its gate and source. In this embodiment, the transistor 210 is applied as the driving transistor DRT, and the transistor 220 is applied as the output transistor BCT, the initialization transistor IST, and the write transistor SST.

[0160] <Timing Diagram>

[0161] Figure 19 is for driving Figure 18Timing diagram of the gate drive circuits 104_1 and 104_2 of the pixels shown. Each interval represented by G1 to G3 is one horizontal period and continues until the last line. The following describes the periods represented by T0 to T6 in Figure 19

[0162] <T0. Previous frame emission>

[0163] During the period until the start of processing in a certain frame, the pixels continue to emit light in the previous frame state.

[0164] <T1. Source initialization operation of the driving transistor DRT>

[0165] During this period, first, the control signal BG becomes the L level, the control signal RG becomes the H level, the control signal IG becomes the L level, the control signal SG becomes the L level, the output transistor BCT is cut off, the reset transistor RST is turned on, the initialization transistor IST is cut off, and the write transistor SST is cut off. Here, the holding capacitor Cs holds "the voltage corresponding to the video signal written in the previous frame". If the video signal Vsig is greater than the reset potential Vrst, the source side also approaches the reset potential Vrst through the driving transistor DRT. In addition, since the reset potential Vrst becomes a potential substantially the same as the low potential power supply Pvss, the current supply to the light emitting element OLED stops. As a result, the source side potential of the driving transistor DRT becomes the lowest state in the pixel system.

[0166] <T2. Gate initialization of the driving transistor DRT>

[0167] The control signal IG becomes the H level, and the initialization transistor IST is turned on. In each pixel of this row, the gate of the driving transistor DRT is fixed to the initialization potential Vini via the initialization transistor IST. The initialization potential Vini is set to a potential greater than the threshold value of the driving transistor DRT with respect to the reset potential Vrst. That is, by this operation, the driving transistor DRT becomes in a conducting state. It should be noted that since the output transistor BCT is cut off, no current flows into the driving transistor DRT yet.

[0168] <T3. Offset cancellation operation>

[0169] ​The control signal BG becomes the H level, the control signal RG becomes the L level, the control signal IG becomes the H level, the output transistor BCT turns on, the reset transistor RST turns off, and the initialization transistor IST turns on. Since the driving transistor DRT is in the on state through the previous operation, current is supplied from Pvdd to the driving transistor DRT via the output transistor BCT. At this stage, since the voltage between the anode and cathode of the light-emitting element OLED does not exceed the light-emitting start voltage, no current flows in. Therefore, the source of the driving transistor DRT is charged by the current supplied from the high-potential power supply Pvdd, and its potential rises. At this time, the gate potential of the driving transistor DRT becomes the initialization potential Vini. Therefore, when the source of the driving transistor DRT becomes (Vini - Vth), the driving transistor DRT turns off and the rise of the potential stops. Vth is the threshold voltage of the driving transistor DRT, and since there are deviations according to the pixel 103F, the potential of the source of the DRT when the potential rise stops is different for each pixel. That is, through this operation, a voltage equivalent to the threshold voltage of the driving transistor DRT is obtained in each pixel. At this time, a voltage of {(Vini - Vth) - Pvss} is applied between the anode and cathode of the light-emitting element OLED, but since this voltage still does not exceed the light-emitting start voltage, no current flows into the light-emitting element OLED.

[0170] It should be noted that according to Figure 19 the timing diagram, the operations of T1. to T3. are implemented in parallel in 2 rows, but it is not limited to this. It can be implemented sequentially row by row, or 3 or more rows can be implemented in parallel.

[0171] <T4.T5. Image signal writing operation>

[0172] The control signal BG becomes the H level, the control signal RG becomes the L level, the control signal IG becomes the L level, the control signal SG becomes the H level, the output transistor BCT turns on, the reset transistor RST turns off, the initialization transistor IST turns off, and the writing transistor SST turns on. In each pixel of this row, the image signal Vsig is input to the gate of the driving transistor DRT, and the gate potential of the driving transistor DRT changes from Vini to Vsig. On the other hand, the source potential of the driving transistor DRT is still (Vini - Vth). As a result, the gate-source voltage of the driving transistor DRT becomes {Vsig - (Vini - Vth)}, reflecting the threshold deviation between pixels.

[0173] Since the image signal line VL sharing Vsig is shared by multiple rows of pixels belonging to the same column, the writing operation of the image signal VSig is implemented sequentially row by row.

[0174] <T6. Light-emitting operation>

[0175] The control signal BG changes to the H level, the control signal RG changes to the L level, the control signal IG changes to the L level, the control signal SG changes to the L level, the output transistor BCT turns on, the reset transistor RST turns off, the initialization transistor IST turns off, and the write transistor SST turns off. Current is supplied from the high potential power supply Pvdd to the drive transistor DRT via the output transistor BCT. The drive transistor DRT allows current corresponding to the gate-source voltage set until the previous stage to flow into the light-emitting element OLED, and the light-emitting element OLED emits light with a brightness corresponding to the current. The anode-cathode voltage of the light-emitting element OLED at this time becomes a voltage corresponding to the current, so the potential of the anode side rises. However, since the gate-source voltage of the drive transistor DRT is held by the holding capacitor Cs, the gate potential of the drive transistor DRT also rises by the coupling of the holding capacitor Cs as the potential of the anode side rises. In practice, since the gate of the drive transistor DRT has not only the holding capacitor Cs but also an additional capacitor Cad and other parasitic capacitors Cel, the rise of the gate potential of the drive transistor DRT is slightly smaller than the rise of the potential of the anode side. However, since this value is known, the potential of the image signal Vsig can be determined so that the desired current value is obtained at the gate-source voltage of the final drive transistor DRT.

[0176] Thus, a series of operations of the pixel 103F is completed. When this operation is completed from the first row to the last row, a display of one frame period is achieved. Thereafter, this operation is repeated to perform image display.

[0177] Any one of the bottom-gate-driven transistors 210, 210A, 210B described in the first embodiment and the second embodiment is applied to the drive transistor DRT. In addition, any one of the top-gate-driven transistors 220, 250 described in the first embodiment and the second embodiment is applied to the reset transistor RST and the initialization transistor IST, etc., in addition to the write transistor SST. Thus, since the S value of the drive transistor DRT is large, in the low gray-scale region where control with a minute current is required, the current change of the drive transistor DRT can be made small, and gray-scale control can be performed finely. Thereby, in the display area 102, display unevenness can be suppressed.

[0178] Example

[0179] In this example, a dual-gate bottom-gate-driven transistor, a dual-gate top-gate-driven transistor, and a top-gate transistor are formed on the same substrate, and the results of evaluating the characteristics of each transistor are described.

[0180] Refer to Figure 20Describe the manufacturing methods of the double-gate bottom-gate-driven transistor 310, the double-gate top-gate-driven transistor 320, and the top-gate transistor 350 fabricated in this embodiment.

[0181] First, on the substrate 301, a base film 302 is formed of silicon oxide or silicon nitride in a single layer or using a stack thereof. Next, on the base film 302, conductive layers 304_1, 304_2 are formed using aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), zinc (Zn), molybdenum (Mo), copper (Cu), indium (In), tin (Sn), hafnium (Hf), tantalum (Ta), tungsten (W), platinum (Pt), bismuth (Bi). Next, on the conductive layers 304_1, 304_2, an insulating film 306 is formed of silicon oxide or silicon nitride in a single layer or using a stack thereof. Preferably, the film thickness of the insulating film 306 is formed to be, for example, 250 nm or more and 500 nm or less. Next, oxide semiconductor layers 308_1 to 308_3 are formed on the insulating film 306. Preferably, the oxide semiconductor film is formed to have a film thickness of 30 nm or more and 100 nm or less, for example, by sputtering. Next, on the oxide semiconductor layers 308_1 to 308_3, an insulating film 312 is formed of silicon oxide or silicon nitride in a single layer or using a stack thereof. Preferably, the film thickness of the insulating film 312 is formed to be, for example, 100 nm or more and 200 nm or less. Next, conductive layers 314_1 to 314_3 are formed. Next, using the conductive layers 314_1 to 314_3 as a mask, ions of impurity elements are implanted at 1×10 14 atoms / cm 2 to 5×10 15 atoms / cm 2 As the impurity elements, hydrogen, argon, phosphorus, boron, etc. can be used. Thus, a channel region 308a, high-concentration impurity regions 308b, 308c are formed in the oxide semiconductor layer 308_1. A channel region 308f and high-concentration impurity regions 308g, 308h are formed in the oxide semiconductor layer 308_2. A channel region 308i and high-concentration impurity regions 308j, 208k are formed in the oxide semiconductor layer 308_3. Next, on the conductive layers 314_1 to 314_3, an insulating film 316 is formed of silicon oxide or silicon nitride in a single layer or using a stack thereof. Preferably, the film thickness of the insulating film 316 is formed to be, for example, 250 nm or more and 500 nm or less. Contact holes reaching the oxide semiconductor layers 308_1 to 308_3 and the conductive layer 314_1 are formed on the insulating film 316. Finally, source electrodes or drain electrodes 318_1 to 318_6 are formed on the insulating film 316.

[0182] Through the above processes, transistors 310, 320, and 350 with different film thicknesses of the gate insulating film are simultaneously formed on the substrate 101. In transistor 310, the conductive layer 304_1 functions as a gate electrode. In transistor 320, the conductive layer 314_2 functions as a gate electrode. In transistor 350, the conductive layer 314_3 functions as a gate electrode. Here, in any of transistors 310, 320, and 350, the channel width is 3 μm and the channel length is 4 μm. The channel width and channel length correspond to the width and length of the region where the conductive layer functioning as a gate overlaps with the oxide semiconductor layer. Note that 28 of each of transistors 310, 320, and 350 are formed on the same substrate.

[0183] Next, the Id-Vg characteristics of transistors 310, 320, and 350 are measured. In the measurement of the Id-Vg characteristics, as the gate voltage (Vg) applied to the gate electrode of each transistor, it is applied from -5 V to +10 V in 0.1 V steps. In addition, the source voltage (Vs) applied to the source electrode is set to 0 V, and the drain voltage (Vd) applied to the drain electrode is set to 0.1 V and 10 V. In addition, in transistor 320, the back gate voltage applied to the conductive layer 304_2 is set to 0 V.

[0184] Figure 21 It is a graph of the Id-Vg characteristics of the double-gate bottom-gate-driven transistor 310. Figure 22 It is a graph of the Id-Vg characteristics of the double-gate top-gate-driven transistor 320. Figure 23 It is a graph of the Id-Vg characteristics of the top-gate transistor 350. Note that in Figures 21 to 22 , the vertical axis is the drain current Id [A], and the horizontal axis is the gate voltage Vg [V]. In Figure 21 , the solid line 401 is a graph of the Id-Vg characteristics with Vd = 0.1 V, and the solid line 402 is a graph of the Id-Vg characteristics with Vd = 10 V. In Figure 22 , the solid line 403 is a graph of the Id-Vg characteristics with Vd = 0.1 V, and the solid line 404 is a graph of the Id-Vg characteristics with Vd = 10 V. In Figure 23 , the solid line 405 is a graph of the Id-Vg characteristics with Vd = 0.1 V, and the solid line 406 is a graph of the Id-Vg characteristics with Vd = 10 V.

[0185] Tables 1 to 3 are respectively the mobilities μFE(Lin) [m 2 / V / s] in the linear region and the mobilities μFE(Sat) [m 2Table summarizing the [V / s], threshold voltage Vth [V], and subthreshold swing value S.S [V / decade] (S value). The maximum (Max), average (ave.), minimum (min), and standard deviation (3σ) of μFE(Sat), threshold voltage Vth, and subthreshold swing value S.S (S value) are calculated respectively.

[0186] [Table 1]

[0187]

[0188] [Table 2]

[0189]

[0190] [Table 3]

[0191]

[0192] As shown in Tables 1 to 3, the S values of transistors 320 and 350 are smaller than those of transistor 310. This is considered to be because the film thickness of the insulating film 312 that functions as the gate insulating film of transistors 320 and 350 is thinner than that of the insulating film 306 that functions as the gate insulating film of transistor 310.

[0193] On the other hand, it is shown that the mobility μFE(Lin) in the linear region and the mobility μFE(Sat) in the saturation region of transistors 320 and 350 are larger than those of transistor 310. This is considered to be because the film thickness of the insulating film 312 that functions as the gate insulating film of transistors 320 and 350 is thinner than that of the insulating film 306 that functions as the gate insulating film of transistor 310.

[0194] Next, the results of the current stress test for transistors 310 and 350 are described.

[0195] As the conditions for the constant current stress test, the test temperature is 35°C, the stress current is 160 nA, and the drain voltage and gate voltage are adjusted and the current is continuously applied for 12 hours.

[0196] Figure 24 are the results of the constant current stress test for transistor 350, Figure 25 are the results of the constant current stress test for transistor 310. It should be noted that in Figure 24 and Figure 25 , the vertical axis is the degradation rate of the on-current (Ion) of the transistor, and the horizontal axis is the stress time.

[0197] As Figure 24As shown, the degradation rate of transistor 350 after 10 hours is 1.9%, as Figure 25 shown, the degradation rate of transistor 310 after 10 hours is 1.0%. As Figure 24 and Figure 25 shown, it can be seen that both transistors 310 and 350 have high reliability. In particular, in transistor 310, the degradation rate of the on-current after 10 hours is very small. Based on the above results, it shows that the transistors of one embodiment of the present invention have high reliability.

[0198] Based on the display device described as an embodiment and an example of the present invention, those skilled in the art can appropriately add, delete, or design-change components, or add, omit, or change conditions in the process. As long as the gist of the present invention is possessed, the obtained structures are all included in the scope of the present invention. In addition, the above embodiments can be combined with each other within the range where no technical contradiction occurs.

[0199] In addition, regarding the effects that are clear from the description of this specification or are easily predictable by those skilled in the art, other effects different from the effects brought by the above embodiments should of course be regarded as the effects brought by the present invention.

[0200] Those skilled in the art should know that within the scope of the present invention, the change examples and correction examples corresponding to various change examples and correction examples also belong to the scope of the present invention. For example, as long as the gist of the present invention is possessed, the structures obtained by those skilled in the art by appropriately adding, deleting, or designing changes to the above-mentioned embodiments, or adding, omitting, or changing conditions in the process are all included in the scope of the present invention.

[0201] Description of Reference Numerals

[0202] 100: Display device, 101: Substrate, 102: Display area, 103: Pixel, 103A - 103C, 103E, 103F: Pixels, 104_1, 104_2: Gate driver circuits, 105: Driver IC, 106: Terminal, 107: Terminal portion, 108: Flexible printed circuit, 109: Peripheral area, 110: Touch sensor, 202: Base film, 204_1, 204_2: Conductive layers, 206: Insulating film, 208_1, 208_2: Oxide semiconductor layers, 208a: Channel region, 208b: High-concentration impurity region, 208c: High-concentration impurity region, 208d: Low-concentration impurity region, 208e: Low-concentration impurity region, 208f: Channel region, 208g: High-concentration impurity region, 208h: High-concentration impurity region, 208i: Channel region, 208j: High-concentration impurity region, 208k: High-concentration impurity region, 210, 210A: Transistors, 212: Insulating film, 213: Conductive layer, 214: Conductive layer, 215: Resist mask, 216: Insulating film, 218: Drain electrode, 220, 220A: Transistors, 222: Planarization film, 226: Pixel electrode, 228: Insulating layer, 230: Light-emitting element, 232: Organic layer, 233: Inorganic insulating layer, 234: Common electrode, 236: Inorganic insulating layer, 238: Organic insulating layer, 240: Encapsulation film, 242: Inorganic insulating layer, 250: Transistor, 301: Substrate, 302: Base film, 304: Conductive layer, 306: Insulating film, 308: Oxide semiconductor layer, 310: Transistor, 312: Insulating film, 314: Conductive layer, 316: Insulating film, 318: Drain electrode, 320: Transistor, 350: Transistor, BCT: Output transistor, BG: Control signal, Cad: Additional capacitance, Cel: Parasitic capacitance, DRT: Driving transistor, IST: Initialization transistor, OLED: Light-emitting element, Pvdd: High-potential power supply, Pvss: Low-potential power supply, RG: Control signal, RST: Reset transistor, Sg: Write control scan line, SG: Control signal, Sga: Light emission control scan line, Sgb: Write control scan line, Sgc: Reset control scan line, Sgd: Initialization control scan line, Sgr: Reset control scan line, SLa: High-potential power supply, SLb: Low-potential power supply electrode, SLc: Reset power supply line, SST: Write transistor, Vini: Initialization potential, VL: Image signal line, Vrst: Reset potential, Vsig: Image signal

Claims

1. A display device, comprising: a substrate; a light-emitting element; a first transistor that controls a current value flowing into the light-emitting element from a driving power supply line; a second transistor that writes a voltage corresponding to the light-emitting luminance of the light-emitting element to a first gate electrode of the first transistor; and a third transistor electrically connected to the driving power supply line, wherein the first transistor includes: the first gate electrode provided on the substrate; a first insulating film provided on the first gate electrode; a first oxide semiconductor layer provided on the first insulating film and having a region overlapping with the first gate electrode; a second insulating film provided on the first oxide semiconductor layer; and a first conductive layer provided on the second insulating film, wherein the second transistor includes: the first insulating film provided on the substrate; a second oxide semiconductor layer provided on the first insulating film; the second insulating film provided on the first oxide semiconductor layer and the second oxide semiconductor layer and having a film thickness smaller than that of the first insulating film; and a second gate electrode provided on the second insulating film and having a region overlapping with the second oxide semiconductor layer, wherein the third transistor includes: the first insulating film provided on the substrate; a third oxide semiconductor layer provided on the first insulating film; the second insulating film provided on the third oxide semiconductor layer; and a third gate electrode provided on the second insulating film and having a region overlapping with the third oxide semiconductor layer, wherein the first conductive layer is electrically connected to the light-emitting element.

2. The display device according to claim 1, wherein, The film thickness of the first insulating film is 250 nm or more and 500 nm or less, and the film thickness of the second insulating film is 100 nm or more and 200 nm or less.

3. The display device according to claim 1, wherein, The second transistor further has a second conductive layer provided on the second insulating film, and the first gate electrode is electrically connected to the second conductive layer.

4. The display device according to claim 1, wherein, A third conductive layer overlapping with the second oxide semiconductor layer and the second gate electrode is further provided between the substrate and the first insulating film.

5. A display device, comprising: a substrate; a light-emitting element; a first transistor that controls a current value flowing into the light-emitting element from a driving power supply line; and a second transistor that writes a voltage corresponding to the light-emitting luminance of the light-emitting element to a first gate electrode of the first transistor, wherein the first transistor includes: a first gate electrode provided on the substrate; a first insulating film provided on the first gate electrode; a first oxide semiconductor layer provided on the first insulating film and having a region overlapping with the first gate electrode, wherein the second transistor includes: the first insulating film provided on the substrate; a second oxide semiconductor layer provided on the first insulating film; a second insulating film provided on the first oxide semiconductor layer and the second oxide semiconductor layer and having a film thickness smaller than that of the first insulating film; and a second gate electrode provided on the second insulating film and having a region overlapping with the second oxide semiconductor layer, The first oxide semiconductor layer has a first channel region, a low-concentration impurity region provided sandwiching the first channel region, and a first high-concentration impurity region provided adjacent to the low-concentration impurity region. The second oxide semiconductor layer has a second channel region and a second high-concentration impurity region provided sandwiching the second channel region.

6. The display device according to claim 5, wherein, The low-concentration impurity region overlaps with the first gate electrode.

7. The display device according to claim 5, wherein, The film thickness of the first insulating film is 250 nm or more and 500 nm or less. The film thickness of the second insulating film is 100 nm or more and 200 nm or less.

8. The display device according to claim 5, wherein, The impurity element contained in the first high-concentration impurity region and the impurity element contained in the second high-concentration impurity region are the same element.

9. The display device according to claim 5, wherein The concentrations of the impurity elements contained in the first high-concentration impurity region and the second high-concentration impurity region are 1×10 15 atoms / cm 3 or more. The concentration of the impurity element contained in the low-concentration impurity region is 2.5×10 12 atoms / cm 3 or more and less than 5×10 13 atoms / cm 3 .

10. The display device according to claim 5, wherein, The second transistor further has a first conductive layer provided on the second insulating film. The first gate electrode is electrically connected to the first conductive layer.

11. The display device according to claim 5, further comprising: a third insulating film provided on the first gate electrode; and a second conductive layer provided on the third insulating film, wherein the second conductive layer is electrically connected to the light-emitting element.

12. The display device according to claim 5, wherein, Between the substrate and the first insulating film, there is further a third conductive layer overlapping with the second oxide semiconductor layer and the second gate electrode.

13. The display device according to claim 5, further comprising a third transistor electrically connected to the driving power line. The third transistor includes: a fourth conductive layer provided on the substrate; the first insulating film provided on the fourth conductive layer; a third oxide semiconductor layer provided on the first insulating film and having a region overlapping with the fourth conductive layer; and the second insulating film provided on the third oxide semiconductor layer; and a third gate electrode provided on the second insulating film and having a region overlapping with the third oxide semiconductor layer.

Images