Cloud computing accelerated DPU system

Abstract

The present disclosure provides a cloud computing acceleration DPU system, relating to the technical field of cloud computing. The system comprises a RISC-V subsystem and an FPGA subsystem, wherein the RISC-V subsystem comprises a network management component and a control component, and the FPGA subsystem comprises a management module, a first-level network module, a second-level network module and a third-level network module; the RISC-V subsystem is used to accelerate various processing of data according to a self-defined vector calculation acceleration instruction set extension, a data redundancy check instruction set extension and a encryption and decryption acceleration instruction set extension; the management module is used to receive a management command from the RISC-V subsystem, and perform parameter configuration and management on the first-level network module, the second-level network module and / or the third-level network module according to the management command; the first-level network module is used for data forwarding; the second-level network module is used to accelerate the forwarding of data packets; and the third-level network module is used for processing and forwarding of multi-protocol data. The present disclosure reduces the use cost and customization cost of the DPU.

Description

Technical Field

[0001] This disclosure relates to the field of cloud computing technology, and in particular to a cloud computing acceleration DPU system. Background Technology

[0002] A Data Processing Unit (DPU) is a dedicated processor used to accelerate networking, storage, virtualization, and other functions of cloud computing servers. The DPU works by acting as an offloading engine for the CPU (central processing unit), taking over the networking, storage, and virtualization functions previously handled by the CPU. This frees up CPU computing power for upper-layer applications, improving the efficiency of the entire computing system and reducing its overall cost. The DPU is also considered the "third main chip" in cloud data centers, following the CPU and GPU (Graphics Processing Unit), and will drive a transformation in the entire cloud computing architecture.

[0003] Existing DPUs often use computing cores based on ARM or MIPS instruction set architectures to provide good programmability. However, DPUs based on these instruction set architectures have the following problems: 1) ARM has high licensing fees, including upfront licensing fees, royalties, and technical consulting service fees, often reaching millions to tens of millions of US dollars; 2) MIPS is affected by commercial factors, and its development continuity is unstable, resulting in a fragile ecosystem; 3) Both ARM and MIPS are difficult to extend with custom instructions, leading to high customization costs.

[0004] Therefore, how to reduce the cost of using and customizing DPUs has become an urgent technical problem to be solved.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] This disclosure provides a cloud computing acceleration DPU system that overcomes, to some extent, the problem of high usage and customization costs of DPUs in related technologies.

[0007] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0008] According to one aspect of this disclosure, a cloud computing acceleration DPU system is provided, comprising: a RISC-V subsystem and an FPGA subsystem, wherein the RISC-V subsystem and the FPGA subsystem are communicatively connected, the RISC-V subsystem including a network management component and a control component, the network management component being communicatively connected to the control component; the network management component being configured to configure parameters and flow tables of the control component according to a vector computing acceleration instruction set extension, wherein the vector computing acceleration instruction set extension is used to accelerate the execution of AI algorithms; the control component being configured to send a first management command to the FPGA subsystem to control the FPGA subsystem to accelerate the forwarding of data packets; the FPGA subsystem being configured to receive the first management command sent by the control component and configure parameters based on the first management command; the FPGA subsystem being further configured to receive target data packets from an external network, accelerate the forwarding of the target data packets, and forward the target data packets to a target application.

[0009] In one embodiment of this disclosure, the FPGA subsystem includes a management module, a first-level network module, and a second-level network module, which are communicatively connected. The management module is configured to receive a first management command from the control component and configure and manage the parameters of the second-level network module according to the first management command to control the second-level network module to accelerate the forwarding of data packets. The first-level network module is configured to receive target data packets from an external network and send the target data packets to the second-level network module. The second-level network module is configured to accelerate the forwarding of the target data packets and forward the target data packets to a target application.

[0010] In one embodiment of this disclosure, the FPGA subsystem further includes a third-level network module, which is communicatively connected to the second-level network module. The network management component is further configured to generate a second management command based on the vector computation acceleration instruction set extension and send the second management command to the management module. The management module is configured to receive the second management command and configure the parameters of the RDMA component of the third-level network module according to the second management command. The second-level network module is further configured to accelerate the forwarding of the target data packet and forward the target data packet to the third-level network module. The third-level network module is configured to receive the target data packet sent by the second-level network module, and the RDMA component sends the target data packet to the target application through the RDMA interface.

[0011] In one embodiment of this disclosure, the third-level network module further includes TCP and UDP components to support the processing and forwarding of TCP, UDP, and RDMA protocol data.

[0012] In one embodiment of this disclosure, the management module is further configured to receive management commands from the RISC-V subsystem via the CXL Switch protocol interface, and to configure and manage the parameters of the first-level network module, the second-level network module, and / or the third-level network module based on the management commands.

[0013] In one embodiment of this disclosure, the vector computation acceleration instruction set extension includes at least one of the following: MATADD instruction, MATMUL instruction, MATSTORE instruction, MATLOAD instruction, MATSIG instruction, MATSOFT instruction, and MATRELU instruction.

[0014] In one embodiment of this disclosure, the RISC-V subsystem further includes a data storage acceleration component, and the FPGA subsystem further includes a third-level network module, which is communicatively connected to the second-level network module. The data storage acceleration component is configured to receive stored data from the target application, accelerate data verification of the stored data based on a data redundancy check instruction set extension, accelerate encryption and decryption of the stored data based on an encryption / decryption acceleration instruction set extension, and send the stored data to the third-level network module. The data redundancy check instruction set extension is used to accelerate data redundancy check of the stored data, and the encryption / decryption acceleration instruction set extension is used to accelerate encryption and decryption tasks of the stored data. The third-level network module is configured to forward the stored data to the second-level network module. The second-level network module is further configured to forward the stored data to the first-level network module. The first-level network module is further configured to forward the stored data to the external network.

[0015] In one embodiment of this disclosure, the data redundancy check instruction set extension includes CRC instructions.

[0016] In one embodiment of this disclosure, the encryption / decryption acceleration instruction set extension includes at least one of the following: GGADD instruction, GFMUL instruction, GFINV instruction, and GFSQR instruction.

[0017] In one embodiment of this disclosure, the RISC-V subsystem further includes a hardware driver component; the hardware driver component includes multiple RISC-V processor cores; the RISC-V processor cores are used to store preset instruction set extensions, the preset instruction set extensions including vector computation acceleration instruction set extensions, data redundancy check instruction set extensions, and encryption / decryption acceleration instruction set extensions.

[0018] In one embodiment of this disclosure, the network management component is also used for traffic offloading scheduling and traffic classification and identification.

[0019] The cloud computing acceleration DPU system provided in this disclosure includes a RISC-V subsystem and an FPGA subsystem. The RISC-V subsystem includes a network management component and a control component. The FPGA subsystem includes a management module, a first-level network module, and a second-level network module. The network management component configures the parameters and flow tables of the control component according to the vector computing acceleration instruction set extension. The control component sends a first management command to the management module. The management module receives the first management command from the control module and configures and manages the parameters of the second-level network module according to the first management command to control the second-level network module to accelerate the forwarding of data packets. The second-level network module accelerates the forwarding of target data packets and forwards the target data packets to the target application. This disclosure uses a custom vector computing acceleration instruction set extension to accelerate DPU tasks, improving the performance of RISC-V in DPU application scenarios and reducing the cost of using and customizing DPUs.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0022] Figure 1 This diagram illustrates a cloud computing acceleration DPU system architecture according to an embodiment of the present disclosure. Figure 2 This diagram illustrates a cloud computing acceleration DPU system according to an embodiment of the present disclosure; Figure 3 This diagram illustrates another cloud computing acceleration DPU system according to an embodiment of the present disclosure; Figure 4 This diagram illustrates the format of a vector computation acceleration instruction set extension according to an embodiment of the present disclosure. Figure 5 This diagram illustrates another cloud computing acceleration DPU system according to an embodiment of the present disclosure; Figure 6 This diagram illustrates another cloud computing acceleration DPU system according to an embodiment of the present disclosure; Figure 7 This diagram illustrates the format of an extended data redundancy check instruction set according to an embodiment of the present disclosure. Figure 8 This diagram illustrates a format of an encryption / decryption acceleration instruction set extension according to an embodiment of the present disclosure. Detailed Implementation

[0023] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0024] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0025] As mentioned in the background section, existing DPUs often use computing cores based on ARM or MIPS instruction set architectures to provide good programmability. However, DPUs based on these instruction set architectures have the following problems: 1) ARM has high licensing fees, including upfront licensing fees, royalties, and technical consulting service fees, often reaching millions to tens of millions of US dollars; 2) MIPS is affected by commercial factors, and its development continuity is unstable, resulting in a fragile ecosystem; 3) Both ARM and MIPS are difficult to extend with custom instructions, leading to high customization costs.

[0026] RISC-V is an open-source instruction set architecture with advantages such as complete openness, no licensing fees, and stable development. It can also be implemented modularly and customized, and has the potential to replace ARM and MIPS, reducing the cost of DPUs. However, there is currently a lack of RISC-V-based DPU architecture designs, and a lack of RISC-V instruction set extensions specifically for the DPU field.

[0027] Based on this, the present disclosure provides a cloud computing acceleration DPU system, which uses a combination of a customized RISC-V subsystem and an FPGA (Field Programmable Gate Array) subsystem to accelerate cloud computing networks and storage. The RISC-V subsystem has flexible programmability and is mainly responsible for carrying out the control tasks and some computing tasks of the DPU, while the FPGA subsystem has high-speed processing and forwarding performance and good customizability, and is mainly responsible for carrying out network data transmission acceleration tasks.

[0028] This disclosure provides custom DPU-related instruction set extensions for RISC-V, including vector computation acceleration instruction set extensions, data redundancy check instruction set extensions, and encryption / decryption acceleration instruction set extensions, to improve DPU performance.

[0029] The system disclosed herein has the advantages of being based on the open instruction set architecture RISC-V and being customizable. Furthermore, it employs a custom DPU-related instruction set to accelerate DPU tasks, thereby improving the performance of RISC-V in DPU application scenarios.

[0030] Figure 1 A schematic diagram of an exemplary system architecture that can be applied to the image processing method or image processing apparatus of the present disclosure embodiments is shown.

[0031] like Figure 1 As shown, the system architecture may include a RISC-V subsystem and an FPGA subsystem.

[0032] The communication connection between the RISC-V subsystem and the FPGA subsystem can be established via a CXL Switch interface. The system can also establish connections with server hosts, external SSDs, and GPUs via the CXL Switch interface.

[0033] The RISC-V subsystem is used to carry out the control tasks and some computing tasks of the DPU.

[0034] The RISC-V subsystem consists of software and hardware components; The software portion of the RISC-V subsystem includes control components, network management components, data storage acceleration components, and hardware driver components. Control components are used for data forwarding logic control; Network management components are used to support automatic configuration of RDMA parameters, traffic offloading and scheduling, and traffic classification and identification. The hardware driver components are the drivers for the FPGA subsystem and the CXL switch; The hardware portion of the RISC-V subsystem is a custom SoC based on the RISC-V instruction set architecture, which includes multiple RISC-V processor cores, L2 / L3 cache modules, and DDR memory modules.

[0035] The RISC-V processor core stores a preset instruction set extension, which can include vector computation acceleration instruction set extensions, data redundancy check instruction set extensions, and encryption / decryption acceleration instruction set extensions. The preset instruction set extensions are used to improve the performance of the DPU.

[0036] The FPGA subsystem includes a first-level network module, a second-level network module, a third-level network module, and a management module.

[0037] The first-level network module is used to support the forwarding of Ethernet protocol data; The second-level network module acts as a data acceleration pipeline, speeding up packet forwarding and forwarding packets to the third-level network module or delivering them to the server application. The second-level network module is controllable by the control component. The third-level network module contains TCP / UDP and RDMA components to support TCP / UDP and RDMA protocol data processing and forwarding. The third-level network module can process IP or RDMA protocol format packets from the second-level network module and deliver them to the server application.

[0038] The management module can interface with the RISC-V subsystem, accept management commands from the RISC-V subsystem through the CXL protocol interface, and configure and manage the first-level network module, the second-level network module, and the third-level network module.

[0039] A network is a medium used to provide a communication link between the RISC-V subsystem and the FPGA subsystem; it can be a wired network or a wireless network.

[0040] Optionally, the aforementioned wireless or wired networks use standard communication technologies and / or protocols. The network is typically the Internet, but can also be any network, including but not limited to Local Area Networks (LANs), Metropolitan Area Networks (MANs), Wide Area Networks (WANs), mobile, wired or wireless networks, private networks, or any combination of virtual private networks. In some embodiments, technologies and / or formats including Hyper Text Markup Language (HTML), Extensible Markup Language (XML), etc., are used to represent data exchanged over the network. Furthermore, conventional encryption technologies such as Secure Socket Layer (SSL), Transport Layer Security (TLS), Virtual Private Networks (VPNs), and Internet Protocol Security (IPsec) can be used to encrypt all or some links. In other embodiments, custom and / or dedicated data communication technologies can be used to replace or supplement the aforementioned data communication technologies.

[0041] A server host can be a server that provides various services, such as a backend management server that supports the devices operated by users through terminal devices. The backend management server can analyze and process received requests and other data, and then feed the processing results back to the terminal device.

[0042] Optionally, the server host can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. The terminal can be a smartphone, tablet, laptop, desktop computer, smart speaker, smartwatch, etc., but is not limited to these. The terminal and server can be directly or indirectly connected via wired or wireless communication, which is not limited herein.

[0043] The following detailed description of this exemplary implementation method is provided in conjunction with the accompanying drawings and embodiments.

[0044] First, this disclosure provides a cloud computing acceleration DPU system.

[0045] Figure 2 This diagram illustrates a cloud computing acceleration DPU system according to an embodiment of the present disclosure, such as... Figure 2 As shown, the cloud computing acceleration DPU system provided in this embodiment includes: The RISC-V subsystem 210 and the FPGA subsystem 220 are connected in communication. The RISC-V subsystem 210 includes a network management component 211 and a control component 212, and the network management component 211 and the control component 212 are connected in communication. The network management component 211 is used to configure the parameters and flow tables of the control component 212 according to the vector computing acceleration instruction set extension, wherein the vector computing acceleration instruction set extension is used to accelerate the execution of AI algorithms. Control component 212 is used to send a first management command to FPGA subsystem 220 to control FPGA subsystem 220 to accelerate the forwarding of data packets; FPGA subsystem 220 is used to receive the first management command sent by the control component and to configure parameters based on the first management command; The FPGA subsystem 220 is also used to receive target data packets from an external network, accelerate the forwarding of the target data packets, and forward the target data packets to the target application.

[0046] In one embodiment of this disclosure, the FPGA subsystem includes a management module, a first-level network module, and a second-level network module, which are communicatively connected. The management module is used to receive a first management command from the control component and configure and manage the parameters of the second-level network module according to the first management command to control the second-level network module to accelerate the forwarding of data packets. The first-level network module is used to receive target data packets from an external network and send the target data packets to the second-level network module. The second-level network module is used to accelerate the forwarding of the target data packets and forward the target data packets to the target application.

[0047] In one embodiment of this disclosure, see Figure 3 The diagram shown is of another cloud computing acceleration DPU system. Figure 3This example demonstrates an implementation of OVS (Open vSwitch) acceleration. In this example, the OVS on the server host is offloaded to the DPU. The network management component of the RISC-V subsystem configures the parameters and flow tables of the control component based on the vector computation acceleration instruction set extension. The network management component uses a custom vector computation acceleration instruction set extension for acceleration. The control component of the RISC-V subsystem controls the second-level network module to accelerate packet forwarding through the management module of the FPGA subsystem. When the first-level network module receives a target packet from the external network, the second-level network module receives the target packet forwarded by the first-level network module, accelerates the forwarding of the target packet through the data acceleration channel of the second-level network module, and sends the target packet to the delivery service application. The data acceleration channel of the second-level network module is responsible for the OVS data plane forwarding function. The delivery service application is a program on the VM (Virtual Machine) in the Host OS (Host Operating System), and the vNIC (Virtualized Network Interface Controller) is used to transmit data packets.

[0048] In one embodiment of this disclosure, the vector computation acceleration instruction set extension may include at least one of the following: MATADD instruction, MATMUL instruction, MATSTORE instruction, MATLOAD instruction, MATSIG instruction, MATSOFT instruction, and MATRELU instruction.

[0049] It should be noted that the vector computation acceleration instruction set extension is used to accelerate AI-based computing. The primary purpose of this extension is to accelerate AI network management algorithms deployed on the DPU. See also... Figure 4 The diagram shows a format illustration of a vector computation acceleration instruction set extension. The specific format of the vector computation acceleration instruction set extension is as follows: Figure 4As shown, the vector computation acceleration instruction set extension can contain seven instructions: MATADD, MATMUL, MATSTORE, MATLOAD, MATSIG, MATSOFT, and MATRELU. The opcodes for MATADD, MATMUL, MATSTORE, MATLOAD, MATSIG, MATSOFT, and MATRELU are all "0001011". The MATADD instruction is used for matrix addition, with its func3 code being "010"; the MATMUL instruction is used for matrix multiplication, with its func3 code being "011"; the MATSTORE instruction is used to store a matrix address in memory, with its func3 code being "000" and its func7 code being "0000001". It also defines a matrix size register (msr) for configuring the matrix size; the MATLOAD instruction is used to load a matrix address from memory, with its func3 code being "000" and its func7 code being "0000010"; the MATSIG instruction is used to quickly calculate the sigmoid function, with its func3 code being "000" and its func7 code being "0000011"; and the MATSOFT instruction is used to quickly calculate the softmax function, with its func3 code being "000". The func7 code of the MATSOFT instruction is "0000100"; the MATRELU instruction is used to quickly calculate the ReLU function, the func3 code of the MATRELU instruction is "000", and the func7 code of the MATRELU instruction is "0000101".

[0050] In one embodiment of this disclosure, the FPGA subsystem further includes a third-level network module, which is communicatively connected to the second-level network module; a network management component, which is further configured to generate a second management command based on vector computation acceleration instruction set extension, and send the second management command to the management module; a management module, which is configured to receive the second management command and configure the parameters of the RDMA component of the third-level network module according to the second management command; a second-level network module, which is further configured to accelerate the forwarding of target data packets and forward the target data packets to the third-level network module; and a third-level network module, which is configured to receive the target data packets sent by the second-level network module, and the RDMA component sends the target data packets to the target application through the RDMA interface.

[0051] In one embodiment of this disclosure, see Figure 5The diagram shown is of another cloud computing acceleration DPU system. Figure 5 As an implementation example of RDMA (Remote Direct Memory Access) acceleration, the network management component of the RISC-V subsystem can be extended according to the vector computing acceleration instruction set, and the RDMA parameters of the second-level network module can be configured through the management module. The control component of the RISC-V subsystem can control the second-level network module through the management module. When the first-level network module receives a target data packet from an external network, the second-level network module receives the target data packet forwarded by the first-level network module, accelerates the forwarding of the target data packet through the data acceleration channel of the second-level network module, and sends the target data packet to the third-level network module. The RDMA component of the third-level network module can send the target data packet to the target application through the RDMA interface.

[0052] In one embodiment of this disclosure, the third-level network module further includes TCP and UDP components to support the processing and forwarding of TCP (Transmission Control Protocol), UDP (User Datagram Protocol), and RDMA protocol data.

[0053] In one embodiment of this disclosure, the management module is further configured to receive management commands from the RISC-V subsystem via the CXL Switch protocol interface, and to configure and manage the parameters of the first-level network module, the second-level network module, and / or the third-level network module based on the management commands.

[0054] In one embodiment of this disclosure, the RISC-V subsystem further includes a data storage acceleration component, and the FPGA subsystem further includes a third-level network module, which is communicatively connected to the second-level network module. The data storage acceleration component is used to receive stored data from the target application, accelerate data verification of the stored data based on a data redundancy check instruction set extension, accelerate encryption and decryption of the stored data based on an encryption / decryption acceleration instruction set extension, and send the stored data to the third-level network module. The data redundancy check instruction set extension is used to accelerate data redundancy check of the stored data, and the encryption / decryption acceleration instruction set extension is used to accelerate encryption and decryption tasks of the stored data. The third-level network module is used to forward the stored data to the second-level network module. The second-level network module is also used to forward the stored data to the first-level network module. The first-level network module is also used to forward the stored data to an external network.

[0055] In one embodiment of this disclosure, see Figure 6 The diagram shown is of another cloud computing acceleration DPU system. Figure 6 As an example of accelerating storage data, the target application can perform storage read and other operations through the NVMe interface. After the storage task is offloaded to the system disclosed herein, the RISC-V subsystem can perform data verification and encryption / decryption operations on the stored data. The data storage acceleration component of the RISC-V subsystem can accelerate data verification of the stored data by utilizing the data redundancy verification instruction set extension, and can accelerate the encryption / decryption of the stored data by utilizing the encryption / decryption acceleration instruction set extension, and send the stored data to the third-level network module. The third-level network module forwards the stored data to the second-level network module, and then the second-level network module forwards the stored data to the first-level network module. Finally, the first-level network module sends the stored data to the external network.

[0056] In one embodiment of this disclosure, the data redundancy check instruction set extension includes CRC (Cyclic Redundancy Check) instructions.

[0057] It should be noted that the Data Redundancy Check instruction set extension is used to accelerate data redundancy check in storage. The Data Redundancy Check instruction set extension can include a single CRC instruction; see [link to relevant documentation]. Figure 7 The diagram shows a format illustration of a data redundancy check instruction set extension. The specific format of the data redundancy check instruction set extension is as follows: Figure 7 As shown, the CRC instruction's opcode is "0001011", func3 is "000", and func7 is "0000101". Furthermore, a custom checksum register cr is introduced to store the address of the checksum.

[0058] In one embodiment of this disclosure, the encryption / decryption acceleration instruction set extension includes at least one of the following: GGADD instruction, GFMUL instruction, GFINV instruction, and GFSQR instruction.

[0059] It should be noted that the encryption / decryption acceleration instruction set extension is used to accelerate storage encryption / decryption tasks. The main purpose of this extension is to accelerate encryption algorithms that require Galois field operations, adding support for Galois field operations. See also... Figure 8 The diagram shows a format illustration of an encryption / decryption acceleration instruction set extension. The specific format of the encryption / decryption acceleration instruction set extension is as follows: Figure 8As shown, the encryption / decryption acceleration instruction set extension can contain four instructions: GFADD, GFMUL, GFINV, and GFSQR. The opcodes of GFADD, GFMUL, GFINV, and GFSQR are all "0001011", and their func3 codes are all "000". Specifically, the GFADD instruction accelerates addition calculations in the Galois field, and its func7 code is "0000111"; the GFMUL instruction accelerates multiplication calculations in the Galois field, and its func7 code is "0001000"; the GFINV instruction accelerates inversion operations in the Galois field, and its func7 code is "0001001"; and the GFSQR instruction accelerates squaring operations in the Galois field, and its func7 code is "0001010".

[0060] In one embodiment of this disclosure, the RISC-V subsystem further includes a hardware driver component; the hardware driver component includes multiple RISC-V processor cores; the RISC-V processor cores are used to store preset instruction set extensions, the preset instruction set extensions including vector computation acceleration instruction set extensions, data redundancy check instruction set extensions, and encryption / decryption acceleration instruction set extensions.

[0061] In one embodiment of this disclosure, the network management component is also used for traffic offloading scheduling and traffic classification and identification.

[0062] In the various embodiments of this disclosure, the functional units can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0063] The above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit it. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A cloud computing acceleration DPU system, characterized in that, include: The RISC-V subsystem and the FPGA subsystem are communicatively connected. The RISC-V subsystem includes a network management component and a control component, and the network management component is communicatively connected to the control component. The network management component is used to configure the parameters and flow tables of the control component according to the vector computing acceleration instruction set extension, wherein the vector computing acceleration instruction set extension is used to accelerate the execution of AI algorithms; The control component is used to send a first management command to the FPGA subsystem to control the FPGA subsystem to accelerate the forwarding of data packets; The FPGA subsystem is used to receive the first management command sent by the control component and to configure parameters based on the first management command; The FPGA subsystem is also used to receive target data packets from an external network, accelerate the forwarding of the target data packets, and forward the target data packets to the target application.

2. The cloud computing acceleration DPU system according to claim 1, characterized in that, The FPGA subsystem includes a management module, a first-level network module, and a second-level network module, which are connected in communication with each other. The management module is used to receive a first management command from the control component, and to configure and manage the parameters of the second-level network module according to the first management command, so as to control the second-level network module to accelerate the forwarding of data packets; The first-level network module is used to receive target data packets from an external network and send the target data packets to the second-level network module; The second-level network module is used to accelerate the forwarding of the target data packet and forward the target data packet to the target application.

3. The cloud computing acceleration DPU system according to claim 2, characterized in that, The FPGA subsystem also includes a third-level network module, which is communicatively connected to the second-level network module. The network management component is further configured to generate a second management command based on the vector computing acceleration instruction set extension, and send the second management command to the management module; The management module is used to receive the second management command and configure the parameters of the RDMA component of the third-level network module according to the second management command; The second-level network module is also used to accelerate the forwarding of the target data packet and forward the target data packet to the third-level network module; The third-level network module is used to receive the target data packet sent by the second-level network module, and the RDMA component sends the target data packet to the target application through the RDMA interface.

4. The cloud computing acceleration DPU system according to claim 3, characterized in that, The third-level network module also includes TCP and UDP components to support the processing and forwarding of TCP, UDP, and RDMA protocol data.

5. The cloud computing acceleration DPU system according to claim 3, characterized in that, The management module is also used to receive management commands from the RISC-V subsystem through the CXL Switch protocol interface, and to configure and manage the parameters of the first-level network module, the second-level network module and / or the third-level network module based on the management commands.

6. The cloud computing acceleration DPU system according to any one of claims 1 to 5, characterized in that, The vector computation acceleration instruction set extension includes at least one of the following: MATADD instruction, MATMUL instruction, MATSTORE instruction, MATLOAD instruction, MATSIG instruction, MATSOFT instruction, and MATRELU instruction.

7. The cloud computing acceleration DPU system according to claim 2, characterized in that, The RISC-V subsystem also includes a data storage acceleration component, and the FPGA subsystem also includes a third-level network module, which is communicatively connected to the second-level network module. The data storage acceleration component is used to receive stored data from the target application, accelerate data verification of the stored data based on the data redundancy check instruction set extension, accelerate encryption and decryption of the stored data based on the encryption and decryption acceleration instruction set extension, and send the stored data to the third-level network module. The data redundancy check instruction set extension is used to accelerate data redundancy check of the stored data, and the encryption and decryption acceleration instruction set extension is used to accelerate the encryption and decryption tasks of the stored data. The third-level network module is used to forward the stored data to the second-level network module; The second-level network module is also used to forward the stored data to the first-level network module; The first-level network module is also used to forward the stored data to the external network.

8. The cloud computing acceleration DPU system according to claim 7, characterized in that, The data redundancy check instruction set extension includes CRC instructions.

9. The cloud computing acceleration DPU system according to claim 7, characterized in that, The encryption / decryption acceleration instruction set extension includes at least one of the following: GGADD instruction, GFMUL instruction, GFINV instruction, and GFSQR instruction.

10. The cloud computing acceleration DPU system according to claim 1, characterized in that, The RISC-V subsystem also includes hardware driver components; The hardware driver component includes multiple RISC-V processor cores; The RISC-V processor core is used to store preset instruction set extensions, which include vector computation acceleration instruction set extensions, data redundancy check instruction set extensions, and encryption / decryption acceleration instruction set extensions.

11. The cloud computing acceleration DPU system according to claim 1, characterized in that, The network management component is also used for traffic offloading scheduling and traffic classification and identification.

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