A method for parallelizing blockable floating-point addition operations

Abstract

The application discloses a kind of blockable floating point number parallelization addition operation method, comprising the following steps: based on IEEE754's floating point number representation, design a kind of low-precision storage mode that can be blocked, the mantissa part of floating point number can be blocked by custom floating block bit number, using the characteristics that FPGA can be processed in parallel, in the process of summing mantissa, the floating block in each list of addend storage pool is operated simultaneously, so as to improve the efficiency of calculation.The application is simple to realize, can effectively reduce the computational complexity under the condition that the calculation error is basically unchanged, reduce the time delay generated by calculation, greatly improve the efficiency of calculation, and can adjust the block bit number, according to specific application demand, performance and accuracy are weighed.

Description

Technical Field

[0001] The present invention relates to the field of computers, and relates to the design of floating-point addition operators. More specifically, it relates to a method for parallel floating-point addition operation that can be segmented. Background Art

[0002] During the development of computer systems, various low-precision storage methods have been proposed. So far, the commonly used computer data representation methods are mainly two types: fixed-point numbers (Fixed Point Number) and floating-point numbers (Floating Point Number).

[0003] The IEEE floating-point arithmetic standard (IEEE Standard for Floating-point Arithmetic, IEEE-754) defines two types of floating-point arithmetic standards for single-precision format and double-precision format, which are the most widely used currently. In addition, IEEE also defines four types of floating-point numbers: half-precision floating-point numbers, extended double-precision floating-point numbers, quadruple-precision floating-point numbers, and floating-point numbers with longer bit lengths. Taking the IEEE single-precision floating-point data format standard as an example, its data storage unit is divided into three parts. The highest bit s is a 1-bit sign bit, representing the positive or negative of the data. The exponent bit e is 8 bits, recording the power exponent value with base 2, and usually needs to subtract the offset value. The remaining 23 bits represent the mantissa bits, storing the fractional part of the data.

[0004] The representation method of floating-point numbers is similar to scientific notation. According to the IEEE single-precision floating-point data format standard, the value of a normalized floating-point number is (-1) s ×1.f×2 e-127 (0 < e < 255). When s takes 0, it represents a positive value, and when it takes 1, it represents a negative value. 1.f represents the mantissa. According to the IEEE standard, the mantissa is also represented in the original code. When normalizing, the mantissa needs to be shifted until the first bit is 1. Therefore, to improve the precision, the highest bit 1 is default omitted and restored only when performing operations. Floating-point numbers also define three types of special values: ±0, ±∞, and NAN. For 0, the single-precision representation is (-1) s ×0 (e = 0, f = 0); the representation of positive infinity is (-1) 0 ×∞ (e = 255, f = 0); the representation of negative infinity is (-1) 1 ×∞ (e = 255, f = 0; for Not a number (NAN), the representation is e = 255, f ≠ 0.

[0005] Traditional floating-point addition generally consists of five steps: exponent comparison, alignment, addition, normalization, and rounding. Suppose there are two sets of floating-point numbers X1 = (s1, e1, f1) and X2 = (s2, e2, f2). The steps for calculating X1 and X2 are described as follows: (1) Exponent comparison. If the decimal points of the floating-point numbers involved in the operation are not in the same position, first compare the magnitudes of the exponents to obtain the difference in exponents d = e1 - e2. If e1 < e2, then swap the mantissa parts of the two numbers. Set the larger number as the alignment benchmark. (2) Alignment. Align the smaller value to the larger value, that is, move the smaller value d bits to the right to align the decimal points of the two numbers. (3) Mantissa summation. Calculate the two mantissas after alignment according to the rules of fixed-point addition and subtraction operations. (4) Normalization. If there are leading zeros in the mantissa result, the shifter shifts the mantissa to the left and the exponent decreases accordingly. If the adder overflows, the mantissa is shifted one bit to the right and the exponent is incremented by one. (5) Rounding. Discard the excess mantissa, and the least significant bit is rounded according to one of the four rounding methods in the standard. If an overflow occurs during the rounding process, the mantissa is shifted one bit to the right and the exponent is incremented by one.

[0006] When performing addition calculations using the IEEE floating-point arithmetic standard, due to its relatively fixed representation error and inability to be segmented, only traditional linear addition operations can be used, resulting in a high computational complexity and thus a large delay in the calculation process. However, as applications become more data-intensive, the development speed of data calculation far lags behind the growth rate of demand. At the same time, the impacts of calculation on bandwidth, energy, and latency are gradually emerging. These trends are particularly evident in today's data-intensive servers and energy-constrained mobile systems. Summary of the Invention

[0007] Object of the Invention: To solve the above problems, based on the IEEE 754 floating-point storage format, the present invention proposes a method for parallelized floating-point addition operation that can be segmented. During the mantissa summation process, the number of bits of the floating block can be customized to segment the mantissa. After segmentation, through the parallelized operation of the addition pool, the computational complexity is reduced, the delay generated by the calculation is reduced, and the calculation efficiency can be significantly improved.

[0008] To achieve the above object, the technical solution adopted by the present invention is:

[0009] A block-based parallel floating-point addition method is proposed. The operator design follows these steps: A block-based low-precision storage method is designed, including the design of floating blocks. Since this method can be implemented on an FPGA, the parallel processing capability of the FPGA is utilized. During the mantissa summation process, the number of bits in the floating block is customized to divide the mantissa into blocks. After block division, addition calculations are performed in parallel through an addition pool. By performing addition operations on the addition pool in parallel at the same time, computational complexity and latency are reduced, thereby improving the efficiency of addition calculations.

[0010] The present invention provides a block-based, parallelized floating-point addition operation method, comprising the following steps:

[0011] Step 1: Divide the mantissa after exponent comparison and alignment into blocks to obtain m floating blocks with the same number of digits. The number of floating blocks m is:

[0012]

[0013] in, This indicates rounding up, m0 represents the number of bits in the mantissa of IEEE 754, F represents the number of bits in each floating block, and d represents the difference between the two sets of floating-point exponents being added.

[0014] Step 2, construct the addend storage pool

[0015] Construct an addend storage pool, including a carry pool and m floating block storage pools;

[0016] The first one is the carry pool, denoted as A0, which is used to store the carry result of the entire addition operation;

[0017] m floating block storage pools are denoted as A1, A2…A… m Each addend has m floating blocks, denoted as a1, a2, ..., a m Add the last digits of each block to the floating block storage pool in descending order of their most significant digits.

[0018] If the last floating block a m If the number of digits is less than F, add 0s after the significant digits to make the floating block a m The number of bits reaches F bits;

[0019] Step 3: Simultaneously perform a fixed-point addition operation on the two floating blocks in each floating block storage pool, delete the two floating blocks in the floating block storage pool, add the addition result to the floating block storage pool, and retain the carry result in the previous floating block storage pool.

[0020] Repeat the above addition operation until only one floating block remains in each floating block storage pool. At this point, the fixed-point addition operation is complete.

[0021] Further, the exponent comparison described in step 1 includes the following:

[0022] If the decimal points of two sets of floating-point numbers X1 = (s1, e1, f1) and X2 = (s2, e2, f2) participating in the operation are not in the same position, first compare the magnitudes of the exponents, where s corresponds to the sign bit of the floating-point number; e corresponds to the exponent part of the floating-point number, and the exponent is represented in integer form, and this integer is called the exponent; f corresponds to the mantissa part of the floating-point number;

[0023] If e1 < e2, then swap the mantissa parts of the two sets of floating-point numbers; and set the larger number as the alignment reference.

[0024] Further, the alignment described in step 1 includes the following:

[0025] Align the smaller value to the larger value, that is, move the smaller value d bits to the right so that the decimal points of the two numbers are aligned. Moving d bits to the right means padding d zeros in front.

[0026] Further, a method for parallelized addition operation of divisible floating-point numbers according to the present invention further includes the following steps:

[0027] Step 4, normalization

[0028] If there are leading zeros in the mantissa result, the shifter shifts the mantissa to the left and the exponent decreases accordingly; if there is a carry after summation, the mantissa is shifted one bit to the right and the exponent is incremented by one;

[0029] Step 5, rounding

[0030] Discard the redundant mantissa, and round the least significant bit according to one of the four rounding methods in the standard; if an overflow occurs during the rounding process, the mantissa is shifted one bit to the right and the exponent is incremented by one;

[0031] The method for judging the overflow is as follows: when calculating a finite number, if the positive value of the obtained result exceeds the representation range of the floating-point number, an overflow occurs.

[0032] Advantageous effects: A method for parallelized addition operation of divisible floating-point numbers provided by the present invention has the following advantages:

[0033] (1) This invention fully considers the computational complexity of linear addition and the resulting computational latency. For mantissa addition, this invention adopts a block-based parallel floating-point addition method. In the FPGA hardware environment, by customizing the floating block bit width parameter, the mantissa of the floating-point number is divided into blocks. Multiple sequential logics with the same function can be implemented in the FPGA to achieve parallel execution. Therefore, by utilizing the parallel processing of the FPGA to perform parallel operations on the block-based addition pool, the computational complexity can be reduced, the computational latency can be reduced, and the computational efficiency can be greatly improved.

[0034] (2) Compared with the fixed-bit IEEE 754 floating-point storage method, this invention allows for customization of the number of bits in the floating block, significantly improving the flexibility of calculation accuracy. It enables the customization of the number of bits in the floating block according to calculation needs, thus adjusting the computational flexibility. Attached Figure Description

[0035] Figure 1 This is a flowchart illustrating the implementation of the computation method of this invention;

[0036] Figure 2 This is a structural diagram of the addition storage pool constructed in an embodiment of the present invention;

[0037] Figure 3 This is a diagram of the digestion process in the additive storage pool;

[0038] Figure 4 This is a bar chart showing the variation of simulation error variance with the number of iterations for different numbers of blocks used in the embodiments of the present invention and the IEEE 754 addition algorithm;

[0039] Figure 5 This is a comparison chart of the computational complexity of the method of this invention and the IEEE 754 addition algorithm. Detailed Implementation

[0040] The invention will now be further described with reference to the accompanying drawings.

[0041] A block-based parallel floating-point addition method is proposed, which divides the mantissa of the floating-point number into blocks by customizing the bit width parameter of the addition pool. Utilizing the parallel processing capabilities of an FPGA, parallel operations are performed on the block-based addition pool, reducing computational complexity, minimizing computational latency, and significantly improving computational efficiency.

[0042] like Figure 1 As shown, the present invention provides a blockable parallel addition method for floating-point numbers, wherein the floating-point numbers are represented in the form (s, e, f) according to the IEEE 754 single-precision floating-point data format standard, and the two sets of floating-point numbers to be added are X1 = (s1, e1, f1) and X2 = (s2, e2, f2); the method includes the following steps:

[0043] Step 1, exponent comparison;

[0044] If the decimal points of the two sets of floating-point numbers involved in the operation are not in the same position, first compare the magnitudes of the exponents to obtain the difference d = e1 - e2 of the exponents;

[0045] If e1 < e2, then swap the mantissa parts of the two sets of floating-point numbers. Set the larger number as the alignment benchmark.

[0046] Among them, in this example, the two sets of floating-point numbers are respectively: X1 = (0, 10000100, 11101001001100110011001), and X2 = (0, 10000101, 11101101100000000000000), corresponding to the decimal numbers 61.15 and 123.375 respectively, and the difference of exponents between the two numbers is d = 1.

[0047] Step 2, alignment

[0048] Align the smaller value with the larger value, that is, move the smaller value d bits to the right to make the decimal point positions of the two numbers aligned. When moving d bits to the right, add d zeros in front of the mantissa;

[0049] Among them, d is the difference of exponents of the two sets of floating-point numbers. After alignment in this example, the mantissas are: the first addend X1: 111101001001100110011001, the second addend X2: 11101101100000000000000.

[0050] Step 3, block division

[0051] Divide the mantissa after alignment in the floating-point number defined by IEEE754 into several floating blocks with the same number of digits. Give the custom parameter F to represent the number of digits of the floating block, then the number of floating blocks is:

[0052]

[0053] Among them, represents rounding up, m0 represents the number of digits of the mantissa included in IEEE754, and F represents the number of digits of each floating block. In this example, the number of digits of each floating block is taken as F = 4, and m = 6 is calculated.

[0054] Step 4, construct the addend storage pool

[0055] Construct the addend storage pool, including a carry pool and m floating block storage pools;

[0056] Among them, the first one is the carry pool, denoted as A0, which is used to store the carry result of the entire addition operation.

[0057] m floating block storage pools are denoted as A1, A2…A… m Each addend has m floating blocks, denoted as a1, a2, ..., a m The remaining bits of each block are added to the floating block storage pool in descending order of their digits. Since the number of floating blocks is the integer part of the calculation result, the last floating block, i.e., 'a', is... m The number of digits may not reach F digits, so it is necessary to pad it with 0s after the significant digits to make it reach F digits.

[0058] In this example, the floating blocks a1 to a6 of the first addend are:

[1111] ,

[0100] ,

[1001] ,

[1001] ,

[1001] ,

[1001] , and the floating blocks a1′ to a6′ of the second addend are padded with 0s as:

[1110] ,

[1101] ,

[1000] ,

[0000] ,

[0000] ,

[0000] .

[0059] Step 5: Simultaneously digest all addend pool lists. The digestion process is as follows:

[0060] Simultaneously, a fixed-point addition operation is performed on the two floating blocks in each floating block storage pool, the two floating blocks in the floating block storage pool are deleted, the addition result is added to the floating block storage pool, and the carry result is retained in the previous floating block storage pool, that is, a floating block with the value [0,0,0,1] is added to the previous floating block storage pool; the carry result of the first floating block storage pool A1 is retained in the carry pool A0.

[0061] Repeat the above addition operation until only one floating block remains in each floating block storage pool. At this point, the fixed-point addition operation is complete.

[0062] Therefore, each floating block storage pool performs an F-bit binary addition operation, reducing computational complexity.

[0063] like Figure 3 As shown in (b), two floating blocks in floating block storage pool A3 are added at a fixed point. The two floating blocks in floating block storage pool A3 are deleted. The result of the addition is added to floating block storage pool A3. The carry result [0,0,0,1] is saved to the previous floating block storage pool A4.

[0064] The digestion results of the addition pool in this example are: A0 =

[0001] , A1 =

[1110] , A2 =

[0010] , A3 =

[0001] , A4 =

[1001] , A5 =

[1001] , A6 =

[1001] .

[0065] Step 6, Normalization

[0066] To increase the number of significant digits and improve computational precision, the mantissa after summation must be normalized. If the mantissa contains leading zeros, the shifter shifts the mantissa to the left, and the exponent decreases accordingly. If there is a carry after summation, the mantissa is shifted one bit to the right, and the exponent is incremented by one.

[0067] Since the adder contains a carry, the calculation result obtained in this example is: s = 0, e = 10000110, f = 0111000100001100110011001. At this time, the number of bits of the mantissa is not the same as the number of bits of the mantissa m0 = 23 under the IEEE 754 single-precision floating-point data format standard. Therefore, the next step is to round the mantissa.

[0068] Step 7, Rounding

[0069] To improve accuracy, the number of bits lost during right shift of the mantissa must be considered. Excess mantissa bits are discarded, and the least significant bit is rounded using one of the four rounding methods specified in the standard. If overflow occurs during rounding, the mantissa is shifted one bit to the right, and the exponent is incremented by one.

[0070] The final calculation result obtained in this example is: s = 0, e = 10000110, f = 01110001000011001100110.

[0071] The overflow determination method is as follows: when calculating finite numbers, if the positive value of the result exceeds the representation range of floating-point numbers, such as the exponent exceeding the range that the exponent field can represent, then overflow has occurred. This example does not exhibit overflow.

[0072] Figure 2 This is a schematic diagram illustrating a specific example of a block-based parallelized floating-point addition method proposed in this invention. Figure 2 This is an addition storage pool constructed according to the example, where the first is the carry pool, denoted as A0, and the remaining m lists store floating blocks, denoted as A1, A2…A m . Figure 3 As shown in (a), the floating blocks of the two addends are placed into the addend storage pool. Figure 3 (c) and (d) in the example are the digestion process of the addition pool, and the digestion results of the addition pool are: A0 =

[0001] , A1 =

[1110] , A2 =

[0010] , A3 =

[0001] , A4 =

[1001] , A5 =

[1001] , A6 =

[1001] .

[0073] Figure 4This is a bar chart showing the variation of simulation error variance between the proposed parallel floating-point addition operator and the IEEE 754 addition algorithm under different numbers of blocks, as a function of iteration number. In the chart, IEEE 754 uses a single-precision floating-point data format with an 8-bit exponent and a 23-bit mantissa. The proposed parallel floating-point addition operator divides the mantissa of the IEEE 754 single-precision floating-point data format into blocks: 12 bits per block for 2 blocks, 6 bits per block for 4 blocks, 4 bits per block for 6 blocks, and 3 bits per block for 8 blocks. For calculating the error variance on the ordinate, the result obtained by the addition operator of this invention is first subtracted from the high-precision calculation result on the computer to obtain the error value. Then, the average of the errors after multiple iterations is taken to obtain the expected error, which is approximately zero. Finally, the error variance is calculated using the variance formula. As shown in the figure, the iteration error variance increases exponentially with the number of iterations. The error variance of the addition operator in this invention is roughly the same as that of IEEE 754, although the error variance of the addition operator in this invention is slightly higher. Furthermore, in the floating-point parallelized addition operator proposed in this invention, the error variance of the calculation result increases slightly with the increase of the number of blocks, but this increase is negligible.

[0074] Figure 5 This chart compares the computational complexity of the parallelized floating-point addition operator proposed in this invention with the IEEE 754 addition algorithm. The parallelized floating-point addition operator proposed in this invention divides the mantissa of the IEEE 754 single-precision floating-point data format into blocks: 1 block, 23 bits per block; 2 blocks, 12 bits per block; 3 blocks, 8 bits per block; 4 blocks, 6 bits per block; 5 blocks, 5 bits per block; 6 blocks, 4 bits per block; 7 blocks, 4 bits per block; and 8 blocks, 3 bits per block. The computational latency for each different number of blocks is obtained by averaging the latency after nearly a thousand calculations. It can be seen that as the number of blocks increases linearly, the parallelization degree of the addition operator of this invention increases, the computational complexity decreases, and therefore the computational latency decreases approximately exponentially. However, due to the computational overhead caused by partitioning, the computation latency will increase slightly on top of the above, ultimately resulting in... Figure 5 The results presented.

[0075] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for parallelizing a floating-point number blockable addition operation, characterized by, It includes the following steps: Step 1: Divide the mantissa after exponent comparison and alignment into blocks to obtain m floating blocks with the same number of digits. The number m of floating blocks is: wherein, represents upward rounding, m0 represents the number of bits of the mantissa included in IEEE 754, F represents the number of bits of each floating block, and d is the difference between the exponents of the two groups of floating-point numbers to be added. Step 2: Construct an adder storage pool Construct an adder storage pool, which includes a carry pool and m floating block storage pools; Among them, the first one is the carry pool, denoted as A0, which is used to store the carry result of the entire addition operation; m floating block storage pools are denoted as A1, A2…A… m Each addend has m floating blocks, denoted as a1, a2, ..., a m Add the last digits of each block to the floating block storage pool in descending order of their most significant digits. If the number of bits of the last floating block a m does not reach F bits, 0 is added after the significant digit to make the number of bits of the floating block a m reach F bits; Step 3: Perform a fixed-point addition operation on two floating blocks in each floating block storage pool simultaneously, delete these two floating blocks in the floating block storage pool, add the addition result to the floating block storage pool, and retain the carry result in the previous floating block storage pool; Repeat the above addition operation until there is only one floating block left in each floating block storage pool. At this point, the fixed-point addition operation is completed.

2. The method of claim 1, wherein, The exponent comparison includes the following content: If the decimal points of the two sets of floating-point numbers X1 = (s1, e1, f1) and X2 = (s2, e2, f2) participating in the operation are not in the same position, first compare the magnitudes of the exponents, where s corresponds to the sign bit of the floating-point number; e corresponds to the exponent part of the floating-point number, and the exponent is represented in integer form, and this integer is called the exponent; f corresponds to the mantissa part of the floating-point number; If e1 < e2, then exchange the mantissa parts of the two sets of floating-point numbers; and set the larger number as the alignment benchmark.

3. The method of claim 2, wherein, The alignment includes the following content: Align the smaller value to the larger value, that is, move the smaller value d bits to the right so that the decimal point positions of the two numbers are aligned. Moving d bits to the right means padding d zeros in front.

4. The method of claim 1, wherein, It also includes the following steps: Step 4: Normalize If there are leading zeros in the mantissa result, then the shifter shifts the mantissa to the left and the exponent decreases accordingly; if there is a carry after summation, then the mantissa is shifted one bit to the right and the exponent is incremented by one; Step 5: Rounding Discard the redundant mantissa, and round the least significant bit according to one of the four rounding methods in the standard; if an overflow occurs during the rounding process, then the mantissa is shifted one bit to the right and the exponent is incremented by one; The method for judging the overflow is: when calculating a finite number, if the positive value of the obtained result exceeds the representation range of the floating-point number, then an overflow occurs.

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