A shift register, display panel and display device

Abstract

The application discloses a shift register, a display panel and a display device. The shift register comprises a plurality of cascaded shift register circuits. A first control module of the shift register circuit controls the potential of a first node according to a first clock signal, a second clock signal and the potential of the first node. A second control module controls the potential of a second node according to a third clock signal, a first level signal and the potential of the first node. An output module controls the time of outputting the first level signal according to the potential of the first node, and controls the time of outputting a second level signal according to the potential of the second node. In a data writing stage, the third clock signal comprises a plurality of effective pulses, and the second level signal output by the signal output end of each shift register circuit is sequentially shifted. In a holding stage, each shift register circuit outputs the first level signal. At least in a first holding frame, the third clock signal is an ineffective fixed level. The above technical scheme can reduce power consumption.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, and in particular, to a shift register, a display panel and a display device. BACKGROUND

[0002] With the development of display technology, while pursuing higher resolution of display devices, the power consumption of display devices is also increased. In order to reduce the power consumption of display devices, some products are in standby mode, even executing driving frequency based on 0.1Hz or less.

[0003] In the prior art, the shift register circuit is still in normal working state in the low frequency holding stage of the display panel, so that the power consumption generated by the shift register circuit is the same as that in the high frequency display mode, resulting in that the display panel still has large power consumption, thereby not fully playing the advantage of low power consumption in low frequency display mode. SUMMARY

[0004] The present application provides a shift register, a display panel and a display device to reduce the power consumption of the display device in low frequency display mode.

[0005] In a first aspect, an embodiment of the present application provides a shift register, comprising: a plurality of cascaded shift register circuits; the shift register circuit comprises a first clock terminal, a second clock terminal, a third clock terminal, a first level terminal, a second level terminal, a signal input terminal, a signal output terminal, a first control module, a second control module and an output module;

[0006] In the same shift register circuit, the first control module and the output module are electrically connected to a first node; the first control module is also electrically connected to the first clock terminal, the second clock terminal and the signal input terminal; the first control module is used to control the potential of the first node according to the first clock signal of the first clock terminal, the second clock signal of the second clock terminal and the input signal of the signal input terminal; the second control module is electrically connected to a second node with the output module; the second control module is also electrically connected to the third clock terminal, the first level terminal and the first node; the second control module is used to control the potential of the second node according to the third clock signal of the third clock terminal, the first level signal of the first level terminal and the potential of the first node; the output module is also electrically connected to the first level terminal, the second level terminal and the signal output terminal respectively; the output module is used to control the time for the signal output terminal to output the first level signal under the control of the potential of the first node, and is used to control the time for the signal output terminal to output the second level signal of the second level terminal under the control of the potential of the second node;

[0007] The shift register has each driving period including a data writing stage and a holding stage; the holding stage includes at least one first holding frame; in the data writing stage, the third clock signal includes a plurality of effective pulses, and the second level signals output by the shift register circuits at different stages are sequentially shifted; in the holding stage, the first level signals are output by the shift register circuits at different stages; and at least in the first holding frame, the third clock signal is an invalid fixed level.

[0008] In a second aspect, the embodiment of the present application further provides a display panel including the shift register.

[0009] In a third aspect, the embodiment of the present application further provides a display device including the display panel.

[0010] The technical scheme of the present application has each driving period of the shift register including a data writing stage and a holding stage, so that the second level signals output by the shift register circuits at different stages are sequentially shifted in the data writing stage, and the first level signals are output by the shift register circuits at different stages in the holding stage; and since the potential of the first node can control the output time of the first level signal, and the potential of the second node controls the output time of the second level signal, in the data writing stage, the third clock signal includes a plurality of effective pulses, so that the second control modules of the shift register circuits at different stages accurately charge and discharge the second node and the associated nodes according to the third clock signal, the first level signal and the potential of the first node, to control the potential of the second node, and ensure that the shift register circuits at different stages can accurately output the second level signal; and in the holding frame, the shift register circuits at different stages do not output the second level signal, at this time, the third clock signal can be set to an invalid fixed level at least in the first holding frame of the holding stage, so that the third clock signal will not repeatedly charge and discharge the nodes in the second control modules, to avoid the waste of power consumption caused by repeated charging and discharging, thereby facilitating to reduce the power consumption of the shift register, and when the shift register is applied to the display panel, the power consumption of the display panel in the low-frequency display mode can be significantly reduced.

[0011] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some specific embodiments of the present application, and for those skilled in the art, based on the basic concept of the device structure, driving method and manufacturing method disclosed and suggested by various embodiments of the present application, other structures and drawings can be expanded and extended, which should be within the scope of the claims of the present application.

[0013] Figure 1 A structural schematic diagram of a shift register provided by an embodiment of the present application;

[0014] Figure 2 A structural schematic diagram of a shift register circuit provided by an embodiment of the present application;

[0015] Figure 3 A driving timing diagram of a shift register circuit provided by an embodiment of the present application;

[0016] Figure 4 A structural schematic diagram of a pixel circuit provided by an embodiment of the present application;

[0017] Figure 5 A structural schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0018] Figure 6 A structural schematic diagram of another shift register circuit provided by an embodiment of the present application;

[0019] Figure 7 A structural schematic diagram of still another shift register circuit provided by an embodiment of the present application;

[0020] Figure 8 A structural schematic diagram of still another shift register circuit provided by an embodiment of the present application;

[0021] Figure 9 A driving timing diagram of another shift register circuit provided by an embodiment of the present application;

[0022] Figure 10 A driving timing diagram of still another shift register circuit provided by an embodiment of the present application;

[0023] Figure 11 A driving timing diagram of still another shift register circuit provided by an embodiment of the present application;

[0024] Figure 12 A driving timing diagram of still another shift register circuit provided by an embodiment of the present application;

[0025] Figure 13A driving timing diagram of the shift register circuit provided by the embodiment of the present application;

[0026] Figure 14 A driving timing diagram of the shift register circuit provided by the embodiment of the present application;

[0027] Figure 15 A driving timing diagram of the shift register circuit provided by the embodiment of the present application;

[0028] Figure 16 A driving timing diagram of the shift register circuit provided by the embodiment of the present application;

[0029] Figure 17 A driving timing diagram of the shift register circuit provided by the embodiment of the present application;

[0030] Figure 18 A structural schematic diagram of another shift register circuit provided by the embodiment of the present application;

[0031] Figure 19 A structural schematic diagram of a display panel provided by the embodiment of the present application;

[0032] Figure 20 A structural schematic diagram of a display device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described clearly and completely by embodiments with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the basic concepts disclosed and suggested by the embodiments in the present application, all other embodiments obtained by those skilled in the art belong to the scope of protection of the present application.

[0034] As described in the background, because active devices or passive devices such as transistors and capacitors are provided in the shift register circuit, the clock signal provided to the shift register circuit repeatedly charges and discharges each device in the shift register circuit during the operation of the shift register circuit. Especially during the low-frequency holding stage of the display panel, during the period when the signal output terminal of the shift register circuit outputs a fixed level for a long time, the clock signal continuously repeatedly charges and discharges each device in the shift register circuit, which will cause power consumption waste, and is not conducive to low power consumption of the shift register including the shift register circuit.

[0035] Based on the above technical problems, the embodiment of the present application provides a shift register, which is characterized in that comprising: a plurality of cascaded shift register circuits; the shift register circuit comprises a first clock end, a second clock end, a third clock end, a first level end, a second level end, a signal input end, a signal output end, a first control module, a second control module and an output module.

[0036] In the same shift register circuit, the first control module and the output module are electrically connected to the first node; the first control module is further electrically connected to the first clock end, the second clock end and the signal input end; the first control module is used for controlling the potential of the first node according to the first clock signal of the first clock end, the second clock signal of the second clock end and the input signal of the signal input end; the second control module and the output module are electrically connected to the second node; the second control module is further electrically connected to the third clock end, the first level end and the first node; the second control module is used for controlling the potential of the second node according to the third clock signal of the third clock end, the first level signal of the first level end and the potential of the first node; the output module is further electrically connected to the first level end, the second level end and the signal output end respectively; the output module is used for controlling the time of outputting the first level signal of the signal output end under the control of the potential of the first node, and is used for controlling the time of outputting the second level signal of the second level end of the signal output end under the control of the potential of the second node.

[0037] In the same shift register circuit, the first control module and the output module are electrically connected to the first node; the first control module is further electrically connected to the first clock end, the second clock end and the signal input end; the first control module is used for controlling the potential of the first node according to the first clock signal of the first clock end, the second clock signal of the second clock end and the input signal of the signal input end; the second control module and the output module are electrically connected to the second node; the second control module is further electrically connected to the third clock end, the first level end and the first node; the second control module is used for controlling the potential of the second node according to the third clock signal of the third clock end, the first level signal of the first level end and the potential of the first node; the output module is further electrically connected to the first level end, the second level end and the signal output end respectively; the output module is used for controlling the time of outputting the first level signal of the signal output end under the control of the potential of the first node, and is used for controlling the time of outputting the second level signal of the second level end of the signal output end under the control of the potential of the second node.

[0038] According to the technical scheme, each driving period of the shift register includes a data writing stage and a holding stage, so that the second level signals output by the shift register circuits at each stage are sequentially shifted in the data writing stage, and the shift register circuits at each stage all maintain the output of the first level signals in the holding stage. Since the potential of the first node controls the output time of the first level signals, and the potential of the second node controls the output time of the second level signals, in the data writing stage, by making the third clock signal include a plurality of effective pulses, the second control modules of the shift register circuits at each stage accurately charge and discharge the second node and the associated nodes according to the third clock signal, the first level signals and the potential of the first node, so as to control the potential of the second node and ensure that the shift register circuits at each stage can accurately output the second level signals. In the holding stage, the shift register circuits at each stage do not output the second level signals, and at least in the first holding stage of the holding stage, the third clock signal is set to an invalid fixed level, so that the third clock signal does not repeatedly charge and discharge the nodes in the second control modules, so as to avoid the waste of power consumption caused by repeated charging and discharging, thereby reducing the power consumption of the shift register. When the shift register is applied to a display panel, the power consumption of the display panel in a low-frequency display mode can be significantly reduced.

[0039] The above is the core idea of the present application. The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0040] Figure 1 A structural schematic diagram of a shift register provided by an embodiment of the present application is shown in Figure 2 A structural schematic diagram of a shift register provided by an embodiment of the present application is shown in Figure 1 and Figure 2 The shift register 100 includes a plurality of shift register circuits 10 arranged in cascade; the shift register circuit 10 includes a first clock end CK1, a second clock end XCK, a third clock end CK2, a first level end VGL, a second level end VGH, a signal input end IN, a signal output end OUT, a first control module 11, a second control module 12 and an output module 13.

[0041] In the same shift register circuit 10, the first control module 11 and the output module 13 are electrically connected to the first node N1; the first control module 11 is also electrically connected to the first clock terminal CK1, the second clock terminal XCK and the signal input terminal IN; the first control module 11 is used to control the potential of the first node N1 according to the first clock signal ck1 of the first clock terminal CK1, the second clock signal xck of the second clock terminal XCK and the input signal Vin of the signal input terminal IN. The second control module 12 and the output module 13 are electrically connected to the second node N2; the second control module 12 is also electrically connected to the third clock terminal CK2, the first level terminal VGL and the first node N1; the second control module 12 is used to control the potential of the second node N2 according to the third clock signal ck2 of the third clock terminal CK2, the first level signal Vgl of the first level terminal VGL and the potential of the first node N1. The output module 13 is also electrically connected to the first level terminal VGL, the second level terminal VGH and the signal output terminal OUT respectively; the output module 13 is used to control the time of the signal output terminal OUT outputting the first level signal Vgl under the control of the potential of the first node N1, and is used to control the time of the signal output terminal OUT outputting the second level signal Vgh of the second level terminal VGH under the control of the potential of the second node N2.

[0042] It can be understood that the electrical connection mentioned in the embodiment can be direct connection, for example, the first control module 11 is electrically connected to the first clock terminal CK1, which can be that the first control module 11 is directly connected to the first clock terminal CK1; or the electrical connection can be that other elements are connected in the middle, for example, the first control module 11 is electrically connected to the first clock terminal CK1, which can be that the first control module 11 is connected to the first clock terminal CK1 through resistors, capacitors, inductors, switches and the like. The definition of the electrical connection in the embodiment of the application is not specifically limited on the premise that the core invention point of the embodiment of the application can be realized.

[0043] In the embodiment, each driving period of the shift register 100 includes a data writing stage t1 and a holding stage t2; the holding stage t2 includes at least one first holding frame t21; in the data writing stage t1, the third clock signal ck2 includes a plurality of effective pulses, and the second level signal Vgh output by the signal output terminal OUT of each stage shift register circuit 10 is sequentially shifted; in the holding stage t2, each stage shift register circuit 10 outputs the first level signal Vgl; at least in the first holding frame t21, the third clock signal ck2 is an invalid fixed level.

[0044] It can be understood that the electrical connection mentioned in the embodiment can be direct connection, for example, the first control module 11 is electrically connected to the first clock terminal CK1, which can be that the first control module 11 is directly connected to the first clock terminal CK1; or the electrical connection can be that other elements are connected in the middle, for example, the first control module 11 is electrically connected to the first clock terminal CK1, which can be that the first control module 11 is connected to the first clock terminal CK1 through resistors, capacitors, inductors, switches and the like. The definition of the electrical connection in the embodiment of the application is not specifically limited on the premise that the core invention point of the embodiment of the application can be realized. Figure 1, the shift register 100 comprises a plurality of cascaded shift register circuits 10, wherein the signal input end IN of the first stage shift register circuit 10 receives a start pulse signal, so that the start pulse signal can control the signal output by the first stage shift register circuit 10; the signal input end IN of each stage shift register circuit 10 except the first stage shift register circuit 10 is electrically connected with the signal output end OUT of the previous stage shift register circuit 10, so that the signal output by the signal output end OUT of the previous stage shift register circuit 10 can control the signal output by the signal output end OUT of the next stage shift register circuit 10. For reference Figure 2 , the enable signal output by the signal output end OUT of each stage shift register circuit 10 can be the first level signal Vgl of the first level end VGL, or the second level signal Vgh of the second level end VGH.

[0045] For reference Figure 3 , the first clock signal ck1 can be a pulse signal in which a high level signal (for example, vgh) and a low level signal (for example, vgl) alternate, and similarly, the second clock signal xck can also be a pulse signal in which a high level signal vgh and a low level signal vgl alternate. Generally, a high level signal vgh and a low level signal vgl continuous therewith constitute a pulse period, the time of the effective pulse of the second clock signal xck does not overlap with the time of the effective pulse of the first clock signal ck1, that is, the enable level of the second clock signal xck and the first clock signal ck1 do not overlap. Thus, when the first clock signal ck1 is a high level signal vgh, the second clock signal xck can be a low level signal vgl, and vice versa, when the first clock signal ck1 is a low level signal vgl, the second clock signal xck can be a high level signal vgh. It can be understood that the high and low of the enable level corresponding to the effective pulse of the first clock signal ck1 and the second clock signal xck can be set as needed, and the embodiments of the present application do not make specific limitation thereon.

[0046] It can also be understood that when the third clock signal ck2 comprises a plurality of effective pulses, the third clock signal ck2 can also be a pulse signal in which a high level signal (for example, vgh) and a low level signal (for example, vgl) alternate, and the effective pulse of the third clock signal ck2 is the enable level corresponding to the third clock signal ck2, wherein the time of the effective pulse of the third clock signal ck2 can overlap with the time of the effective pulse of the first clock signal ck1, that is, the enable level of the third clock signal ck2 and the first clock signal ck1 overlap. Thus, the first clock signal ck1 and the third clock signal ck2 can be simultaneously a high level signal vgh or a low level signal vgl. The high and low of the enable level corresponding to the effective pulse of the first clock signal ck1 and the third clock signal ck2 can be set as needed, and the embodiments of the present application do not make specific limitation thereon.

[0047] The first level signal Vgl of the first level terminal VGL and the second level signal Vgh of the second level terminal VGH can be fixed signals. For example, when the first level signal Vgl of the first level terminal VGL is a low level signal (e.g., vgl), the second level signal Vgh of the second level terminal VGH can be a high level signal (e.g., vgh). Conversely, when the first level signal Vgl of the first level terminal VGL is a high level signal vgh, the second level signal Vgh of the second level terminal VGH can be a low level signal vgl. It can be understood that the first level signal Vgl of the first level terminal VGL and the second level signal Vgh of the second level terminal VGH can be set as needed, and the embodiments of the present application do not make specific limitations thereto.

[0048] It can also be understood that when the shift register circuit is applied to the display panel, the display panel maintains the same display image for a long time at a lower refresh frequency. At this time, the display panel does not need to be refreshed continuously, and the display panel can have a longer display driving period, that is, the shift register circuit 10 can have a longer driving period, so that each driving period of each shift register circuit 10 includes a data writing stage t1 and a holding stage t2. Wherein, one display driving period at a lower refresh frequency can be equivalent to multiple display driving periods at a higher refresh frequency. At this time, the data writing stage t1 of the shift register circuit 10 can be equivalent to one display driving period at a higher refresh frequency, and the time length of one holding stage t2 can be equivalent to at least one display driving period at a higher refresh frequency. In this way, at a lower driving frequency, the display panel will maintain the same display image for a long time, that is, the display panel will not perform image switching for a long time, thereby reducing the power consumption caused by image switching.

[0049] Specifically, Figure 3 The driving timing diagram of the shift register circuit provided by the embodiments of the present application is combined with reference Figure 2 and Figure 3As shown, in the data writing stage t1, the first control module 11 can control the potential of the first node N1 to match the input signal Vin under the control of the active pulse of the first clock signal ck1. Since the time of the active pulse of the first clock signal ck1 and the time of the active pulse of the second clock signal xck do not overlap, when the first clock signal ck1 is at the enable level, the first control module 11 can transmit the input signal Vin to the first node N1 under the control of the first clock signal ck1, and when the first clock signal ck1 is at the non-enable level, the second clock signal xck is at the enable level, at this time, the first control module 11 cannot transmit the input signal Vin to the first node N1 under the control of the first clock signal ck1, but the first control module 11 can control the potential of the first node N1 to match the enable level of the active pulse of the second clock signal xck under the control of the active pulse of the second clock signal xck, so that the potential of the first node N1 continues to stabilize at the enable level, and thus the output module 13 can transmit the first level signal Vgl of the first level end VGL to the signal output end OUT under the control of the potential of the first node N1, that is, the output signal Out is the first level signal Vgl. At the same time, in the data stage t1, the third clock signal ck2 includes a plurality of active pulses, the time of the active pulse of the third clock signal ck2 overlaps with the time of the active pulse of the first clock signal ck1, and the second control module 12 controls the potential of the second node N2 according to the potential of the first node N1 under the control of the third clock signal ck2 and the first level signal Vgl, so that when the potential of the second node N2 is at the enable level, the output module 13 can be controlled to transmit the second level signal Vgh of the second level end VGH to the signal output end OUT, that is, the output signal Out is the second level signal Vgh. In this way, the second level signals Vgh output by the signal output ends OUT of the shift register circuits 10 of each stage in the shift register 100 are sequentially shifted.

[0050] When the shift register circuit 10 enters the holding stage t2, the holding stage t2 can include at least one first holding frame t21. During the whole holding stage t2, the output module 13 of the shift register circuit 10 is controlled by the potential of the first node N1, so that the output signal Out of the signal output end OUT is maintained at the first level signal Vgl for a long time, thereby causing the display panel including the shift register to maintain the same display screen for a long time. At this time, the potential of the second node N2 can be maintained at the non-enabled level, i.e., the second node N2 and its associated nodes do not need to be repeatedly charged and discharged; thus, at least in the first holding frame t21 of the holding stage t2, the third clock signal ck2 can be an invalid fixed level, i.e., the third clock signal ck2 is maintained at the non-enabled level, thereby avoiding repeated charging and discharging of the potential of the node in the second control module 12, saving power consumption, and being conducive to reducing the power consumption of the shift register, and further being conducive to low power consumption of the display panel.

[0051] Optionally, continuing to refer to Figure 3 For the third clock signal ck2, the time of maintaining the invalid fixed level in the first holding frame t21 is at least greater than the interval time between adjacent two valid pulses in the data writing stage t1.

[0052] Specifically, the interval time between adjacent two valid pulses of the third clock signal ck2 in the data writing stage t1 is the time of maintaining the invalid fixed level of the third clock signal ck2 in the data writing stage t1. It can be understood that each time the third clock signal ck2 generates a jump of a valid pulse, the node potential in the second control module 12 is charged or discharged once. When the time of maintaining the invalid fixed level of the third clock signal ck2 in the first holding frame t21 is greater than the interval time between adjacent two valid pulses of the third clock signal ck2 in the data writing stage t1, the third clock signal ck2 can be maintained at the invalid fixed level for a relatively long time, thereby reducing the number of jumps of the third clock signal ck2, reducing the number of repeated charging and discharging of the node potential in the second control module 12, and further reducing the power consumption of the shift register circuit.

[0053] In the first holding frame t21, the longer the time of maintaining the invalid fixed level of the third clock signal ck2, the more conducive to saving power consumption. In an optional embodiment, the whole holding stage t2 is the first holding frame t21, and at this time, the third clock signal ck2 is maintained at the invalid fixed level in the whole holding stage t2, so as to maximize the saving of power consumption.

[0054] In an optional embodiment, when the shift register 100 is applied to a display panel, the signals output by each stage of the shift register circuit 10 in the shift register 100 can control the transistors of the pixel circuits in the display area of ​​the display panel to turn on or off. For example, Figure 4 A schematic diagram of a pixel circuit provided in an embodiment of the present invention is shown below. Figure 4 As shown, the pixel circuit in the display area of ​​the display panel can be a typical 7T1C circuit. In this case, the pixel circuit may include a driving transistor M2, an initialization transistor M6, a threshold compensation transistor M5, a data writing transistor M4, a first light-emitting control transistor M1, a second light-emitting control transistor M3, a reset transistor M7, and a storage capacitor Cst. It can be understood that the seven transistors in the pixel circuit are turned on or off under the control of the corresponding scan signals (Scan1, Scan2, Scan3) and the light-emitting control signal Emit, respectively, to control the on / off state of the transmission paths of the data signal Vdata, the initialization signal, and the reset signal Vref, and to control the timing of providing driving current to the light-emitting element D. Figure 4 The example shows seven P-type transistors, but is not limited to this. See also... Figure 4 The signals output by each shift register circuit 10 in the shift register 100 can be used to control the first light-emitting control transistor M1 and the second light-emitting control transistor M3 to be turned on or off.

[0055] In another alternative embodiment, Figure 5 A schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, as shown below. Figure 5 As shown, with Figure 4 The difference lies in the pixel circuit, which also includes a bias adjustment transistor M8. The bias adjustment transistor M8 can be turned on or off under the control of the scan signal Scan4, and when on, it writes the bias adjustment signal DVH to the gate of the driving transistor M2. Simultaneously, the threshold compensation transistor M5 and the initialization transistor M6 in the pixel circuit are both N-type transistors, while the other transistors are P-type transistors. In this case, the signals output from each stage of the shift register circuit 10 in the shift register 100 can be used to control the on or off state of the initialization transistor M6 and / or the threshold compensation transistor M5, or they can be used to control the on or off state of the first light-emitting control transistor M1 and / or the second light-emitting control transistor M3.

[0056] Among them, in conjunction with reference Figure 2 , Figure 4 and Figure 5If the signals outputted by the shift register circuits 10 in the shift register 100 are used to control the turn-on or turn-off of the initialization transistor M6 and / or the threshold compensation transistor M5, i.e. the signals outputted by the shift register circuits 10 are the scan signals Scan3 and / or Scan2, when the output module 13 transmits the second level signal Vgh of the second level terminal VGH to the signal output terminal OUT, the output signal Out of the shift register circuit 10 can be considered as an enable level capable of controlling the turn-on of the transistor in the pixel circuit of the display panel; and when the output module 13 transmits the second level signal Vgl of the first level terminal VGL to the signal output terminal OUT, the output signal Out of the shift register circuit 10 can be considered as a non-enable level capable of controlling the turn-off of the transistor in the pixel circuit of the display panel.

[0057] If the signals outputted by the shift register circuits 10 in the shift register 100 are used to control the turn-on or turn-off of the first light emitting control transistor M1 and / or the second light emitting control transistor M3, i.e. the signals outputted by the shift register circuits 10 are the light emitting control signals Emit, when the output module 13 transmits the first level signal Vgl of the first level terminal VGL to the signal output terminal OUT, the output signal Out of the shift register circuit 10 can be considered as an enable level capable of controlling the turn-on of the transistor in the pixel circuit of the display panel; and when the output module 13 transmits the second level signal Vgh of the second level terminal VGH to the signal output terminal OUT, the output signal Out of the shift register circuit 10 can be considered as a non-enable level capable of controlling the turn-off of the transistor in the pixel circuit of the display panel.

[0058] It should be noted that the above only exemplarily takes the signals outputted by the shift register circuits 10 in the shift register 100 as an example for controlling the transistors in the pixel circuit, and the devices controlled by the signals outputted by the shift register circuits 10 in the embodiments of the present application are not limited thereto, and the structure of the pixel circuit is also not limited thereto, and can be designed as required, and the embodiments of the present application do not make specific limitation thereon.

[0059] It can be understood that the high and low of the enable level and the non-enable level are related to the type of the transistor controlled thereby, for example, when the transistor is a P-channel transistor, the enable level is a low level signal and the non-enable level is a high level signal; and when the transistor is an N-channel transistor, the enable level is a high level signal and the non-enable level is a low level signal. The high and low of the enable level and the non-enable level can be limited according to actual needs in the embodiments of the present application. For the convenience of description, in the absence of special instructions, the embodiments of the present application are described by taking the active pulse as the enable level, and the enable level as the low level signal and the non-enable level as the high level signal as an example.

[0060] It can also be understood that in the embodiment of the present application, the third clock signal is mainly used for charging or discharging the second control module of the shift register circuit, when the third clock signal is at an invalid fixed level, the second control module will not be charged or discharged, at this time, the second control module can be kept in a non-working state, thereby realizing low power consumption of the shift register circuit. Accordingly, under the premise of realizing low power consumption of the shift register circuit when the third clock signal is kept at an invalid fixed level, the structure of the second control module is not specifically limited in the embodiment of the present application.

[0061] Optionally, Figure 6 Another structure schematic diagram of a shift register circuit provided by the embodiment of the present application is shown in FIG. 2, which is similar to the structure schematic diagram shown in FIG. 1, and the difference between the two is that the second control module 12 in the structure schematic diagram shown in FIG. 2 further includes a fourth node control unit 123. Figure 6 As shown in FIG. 2, the second control module 12 includes a second node control unit 121 and a third node control unit 122. In the same shift register circuit 10: the third node control unit 122 and the second node control unit 121 are electrically connected to the third node N3; the third node control unit 122 is further electrically connected to the first node N1, the third clock terminal CK2 and the first level terminal VGL respectively; the third node control unit 122 is used for controlling the time of transmission of the third clock signal ck2 to the third node N3 under the control of the potential of the first node N1, and controlling the time of transmission of the first level signal Vgl to the third node N3 under the control of the third clock signal ck2. The second node control unit 121 is further electrically connected to the second clock terminal XCK and the second node N2 respectively, and the second node control unit 121 is used for controlling the potential of the second node N2 according to the second clock signal xck and the potential of the third node N3.

[0062] Specifically, the third node control unit 122, under the control of the potential of the first node N1, controls the transmission time of the third clock signal ck2 to the third node N3. When the potential of the first node N1 is at the enable level, it controls the transmission of the third clock signal ck2 to the third node N3. Simultaneously, under the control of the third clock signal ck2, the third node control unit 122 controls the transmission time of the first level signal Vgl to the third node N3. When the third clock signal ck2 is a valid pulse (i.e., an enable level), it controls the transmission of the first level signal Vgl to the third node N3. This controls the potential of the third node N3 so that its potential matches either the third clock signal ck2 or the first level signal Vgl. Correspondingly, the second node control unit 121, under the control of the second clock signal xck and the potential of the third node N3, controls the potential of the second node N2. Since the potential of the first node N1 is enabled, the potential of the second node N2 must be disabled. That is, when the first node N1 is enabled, the second node control unit 121 should not be able to transmit the potential of the third node N3 to the second node N2. At this time, the second clock signal xck should be a disabled level that controls the second node control unit 121 to not transmit the potential of the third node N3 to the second node N2.

[0063] Since the signal output terminal OUT of the output module 13 maintains the output of the first level signal Vgl during the holding phase t2, that is, the potential of the first node N1 is kept at the enabled level, while the potential of the second node N2 is at the disabled level, the third clock signal ck2 is an invalid fixed level, that is, a disabled level, at least during the first holding frame t21 of the holding phase t2. This makes the potential of the third node N3 match the third clock signal ck2 and also keep it at the disabled level. At this time, the potentials of the third node N3 and the second node N2, which are electrically connected at both ends of the second node control unit 121, are both at the disabled level, thereby avoiding charging or discharging the second node control unit 121 and facilitating the low power consumption of the shift register.

[0064] Optional, Figure 7 A schematic diagram of another shift register circuit provided in an embodiment of the present invention is shown below. Figure 7 As shown, the second node control unit 121 includes a first capacitor C1, a first transistor T1, and a second transistor T2. In the same shift register circuit 10: the first plate of the first capacitor C1 and the gate of the first transistor T1 are both coupled to the third node N3; the first terminal of the first transistor T1 is electrically connected to the second clock terminal XCK; the second terminal of the first transistor T1 is electrically connected to the second plate of the first capacitor C1; the gate of the second transistor T2 is electrically connected to the second clock terminal XCK, the first terminal of the second transistor T2 is electrically connected to the second plate of the first capacitor C1, and the second terminal of the second transistor T2 is electrically connected to the second node N2.

[0065] In an optional embodiment, continuing to refer to Figure 7 As shown, the third node control unit 122 can include a third transistor T3 and a fourth transistor T4. The gate of the third transistor T3 is electrically connected with the third clock terminal CK2, the first pole of the third transistor T3 is electrically connected with the first level terminal VGL, and the second pole of the third transistor T3 is electrically connected with the third node N3. The gate of the fourth transistor T4 is electrically connected with the first node N1, the first pole of the fourth transistor T4 is electrically connected with the third clock terminal CK2, and the second pole of the fourth transistor T4 is electrically connected with the third node N3. In this way, the fourth transistor T4 can be turned on or off under the control of the potential of the first node N1, and in the on state, the third clock signal ck2 of the third clock terminal CK2 is transmitted to the third node N3, or the third transistor T3 can be turned on or off under the control of the third clock signal ck2, and in the on state, the first level signal Vgl is transmitted to the third node N3.

[0066] Specifically, continuing to refer to Figure 3 and Figure 7 In the data writing stage t1, the first transistor T1 can be turned on or off under the control of the potential of the third node N3, and the second pole of the first transistor T1 is electrically connected with the second pole plate of the first capacitor C1 at the fourth node N4. In the on state of the first transistor T1, the second clock signal xck is transmitted to the fourth node N4. At this time, the second transistor T2 can be turned on or off under the control of the second clock signal xck, and in the on state, the potential of the fourth node N4 is transmitted to the second node N2, so that the potential of the second node N2 is the enable level, so that the signal output terminal OUT of the shift register circuit 10 outputs the second level signal Vgh. When the third clock signal ck2 includes a plurality of valid pulses, the second level signal Vgh output by the signal output terminal OUT of each stage of the shift register circuit 10 can be sequentially shifted. Due to the action of the first capacitor C1, the potential of the second node N2 can be more stably maintained at the enable level.

[0067] In the holding stage t2, if the third clock signal ck2 is a pulse signal, in the active pulse (i.e. the enable level) stage of the third clock signal ck2, the third transistor T3 is turned on, so that the first level signal Vgl is transmitted to the third node, and then the first capacitor C1 is discharged; in the non-active pulse (i.e. the non-enable level) stage of the third clock signal ck2, the non-enable level of the third clock signal ck2 is transmitted to the third node N3 through the turned-on fourth transistor T4, so that the first capacitor C1 starts to charge. Thus, the pulse signal of the third clock signal ck2 repeatedly charges and discharges the first capacitor C1, resulting in the waste of power consumption. Therefore, at least in the first holding frame t21 of the holding stage t2, the third clock signal ck2 is an invalid fixed level, i.e. the third clock signal ck2 remains in the non-enable level, so that the first level signal Vgl cannot be transmitted to the third node N3 through the third transistor T3. At the same time, the non-enable level of the third clock signal ck2 can be transmitted to the third node N3 in the case that the fourth transistor T4 is turned on under the control of the potential of the first node N1. At this time, the non-enable level of the potential of the third node N3 controls the first transistor T1 to be turned off, so that the second clock signal xck cannot be transmitted to the fourth node N4 through the first transistor T1; when the second clock signal xck is in the enable level to control the second transistor T2 to be turned on, the potential of the fourth node N4 remains consistent with the potential of the second node N2, both of which are in the non-enable level; when the second clock signal xck is in the non-enable level to control the second transistor T2 to be turned off, the potential of the fourth node N4 still maintains in the non-enable level. Thus, the potential of the third node N3 and the potential of the fourth node N4 at both ends of the first capacitor C1 are both in the non-enable level, which avoids the first capacitor C1 from repeatedly charging and discharging, and is beneficial to reduce the power consumption.

[0068] Among them, the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 can be N-channel or P-channel transistors, which can be designed according to the needs, and the embodiments of the present application do not make specific limitations thereto. It is worth noting that the structure of the third node control unit 122 is only exemplary, and is not limited thereto.

[0069] Optionally, continuing to refer to Figure 7As shown, the second control module 12 further comprises a first voltage stabilizing transistor T5; the third node N3 comprises a first sub-node N31 and a second sub-node N32; the gate of the first voltage stabilizing transistor T5 is electrically connected with the first level end VGL, the first pole of the first voltage stabilizing transistor T5 is electrically connected with the first sub-node N31, and the second pole of the first voltage stabilizing transistor T5 is electrically connected with the second sub-node N32; the first voltage stabilizing transistor T5 is in a conductive state under the control of the first level signal Vgl; wherein the third node control unit 122 is electrically connected with the first sub-node N31 of the third node N3, and the second node control unit 121 is electrically connected with the second sub-node N32 of the third node N3.

[0070] Specifically, Figure 7 As shown, the first voltage stabilizing transistor T5 is a P-channel transistor, and the first level signal Vgl controls the first voltage stabilizing transistor T5 to be in a conductive state, so that the potential of the original third node N3 can be shared at the first sub-node N31 and the second sub-node N32, thereby avoiding the common action of the third node control unit 122 and the second node control unit 121, so that the third node N3 changes and affects the working of the shift register circuit 10. In this way, by setting the first voltage stabilizing transistor T5, the device electrically connected to the other node can be protected when the potential of one of the first sub-node N31 and the second sub-node N32 is abnormal.

[0071] In an optional embodiment, continuing to refer to Figure 7 As shown, the first control module 11 comprises a first input transistor T6, a switch transistor T7, a second voltage stabilizing transistor T8 and a second capacitor C2. The gate of the first input transistor T6 is electrically connected with the first clock end CK1, the first pole of the first input transistor T6 is electrically connected with the signal input end IN, and the second pole of the first input transistor T6 is electrically connected with the first node N1. In this way, the first clock signal ck1 of the first clock end CK1 can control the first input transistor T6 to be in a conductive state or a closed state, so as to transmit the input signal Vin of the signal input end IN to the first node N1 when the first input transistor T6 is in a conductive state.

[0072] The first node N1 can comprise a third sub-node N11 and a fourth sub-node N12; the gate of the second voltage stabilizing transistor T8 is electrically connected with the first level end VGL, the first pole of the second voltage stabilizing transistor T8 is electrically connected with the third sub-node N11, and the second pole of the second voltage stabilizing transistor T8 is electrically connected with the fourth sub-node N12; the second voltage stabilizing transistor T8 is in a conductive state under the control of the first level signal Vgl. It can be understood that the function of the second voltage stabilizing transistor T8 is the same as that of the first voltage stabilizing transistor T5, which will not be described here.

[0073] The gate of the switching transistor T7 is electrically connected with the fourth sub-node N12 of the first node N1, the first electrode of the switching transistor T7 is electrically connected with the second clock end XCK, the second electrode of the switching transistor T7 is electrically connected with the first electrode plate of the second capacitor C2, and the second electrode plate of the second capacitor C2 is electrically connected with the fourth sub-node N12 of the first node N1. The switching transistor T7 is used to control the second clock signal xck to be transmitted to the first electrode plate of the second capacitor C2 at least when the potential of the first node N1 is the enable level of the control output module 13 to transmit the first level signal Vgl to the signal output end OUT, and after the second clock signal xck jumps from the high level signal vgh to the low level signal vgl, the coupling effect of the second capacitor C2 can pull down the potential of the first node N1 to the potential corresponding to the second clock signal xck, so that the potential of the first node N1 is stably kept at a lower potential, and then the signal output end OUT stably outputs the first level signal Vgl.

[0074] It should be noted that the structure of the first control module 11 includes but is not limited to Figure 7 As shown, the first control module 11 can be set according to actual needs, Figure 7 which is only an example.

[0075] In other optional embodiments, as Figure 7 different from Figure 8 , the first control module 11 can further include a second input transistor T13, a third voltage stabilizing transistor T14 and a filter transistor T15. The gate of the second input transistor T13 is electrically connected with the first clock end CK1, the first electrode of the second input transistor T13 is electrically connected with the signal input end IN, and the second electrode of the second input transistor T13 is electrically connected with the first electrode of the third voltage stabilizing transistor T14. In this way, the first clock signal ck1 of the first clock end CK1 can control the second input transistor T13 to be turned on or turned off, so as to transmit the input signal Vin of the signal input end IN to the first electrode of the third voltage stabilizing transistor T14 when the second input transistor T13 is in the on state. The second electrode of the third voltage stabilizing transistor T14 is electrically connected with the gate of the switching transistor T7 at the fifth node N5, and the gate of the third voltage stabilizing transistor T14 is electrically connected with the first level end VGL. The third voltage stabilizing transistor T14 is in the on state under the control of the first level signal Vgl. It can be understood that the third voltage stabilizing transistor T14 has the same effect as the first voltage stabilizing transistor T5 and the second voltage stabilizing transistor T8, which will not be described here.

[0076] The second electrode of the switch transistor T7 is electrically connected with the first electrode plate of the second capacitor C2, the gate electrode of the switch transistor T7 is electrically connected with the second electrode plate of the second capacitor C2, the gate electrode of the filter transistor T15 is electrically connected with the drain electrode of the filter transistor T15, the source electrode of the filter transistor T15 is electrically connected with the fourth sub-node N12 of the first node N1, and the drain electrode of the filter transistor T15 is electrically connected with the fifth node N5. It can be understood that the gate electrode of the filter transistor T15 is electrically connected with the drain electrode of the filter transistor T15, and the filter transistor T15 can be equivalent to a diode with unidirectional conduction performance. Specifically, the switch transistor T7 is used to turn on when the potential of the fifth node N5 is the low level vgl, and when the second clock signal xck jumps to the enable level (low level vgl), the potential of the fifth node N5 is pulled down under the coupling action of the second capacitor C2. At this time, the potential difference between the fourth sub-node N12 of the first node N1 and the fifth node N5 is the forward bias voltage for turning on the filter transistor T15, so that the filter transistor T15 is in the on state, and then the high level vgh of the fourth sub-node N12 is written to the fifth node N5, so that the switch transistor T7 is closed, and the coupling action of the second capacitor C2 cannot affect the potential stability of the fourth sub-node N12, thereby ensuring the stable output of the signal output end OUT in the output module 13. In addition, when the output of the signal output end OUT jumps from the second level signal Vgh (high level vgh) to the first level signal Vgl (low level vgl), the input signal Vin (low level vgl) of the signal input end IN is written to the fifth node N5, so that the potential difference between the fourth sub-node N12 and the fifth node N5 is the reverse bias voltage for controlling the filter transistor T15 to be closed, that is, the filter transistor T15 is in the off state. Even if the second clock signal xck (high level vgh) of the second clock end XCK is pulled up under the coupling action of the first capacitor C1, the potential of the fifth node N5 is pulled up, and the potential of the fourth sub-node N12 is continuously stable at a lower potential due to the fact that the filter transistor T15 is always in the off state, thereby improving the stability of the potential of the fourth sub-node N12 of the first node N1.

[0077] Optionally, continuing to refer to Figure 7 Or Figure 7 As shown, the shift register circuit 10 further comprises an interlocking module 14, and the interlocking module 14 is electrically connected with the second level end VGH, the first control module 11 and the second control module 12 in the same shift register circuit 10. The interlocking module 14 is used to control the time of transmitting the second level signal Vgh to the second node N2 under the control of the first control module 11, and control the time of transmitting the second level signal Vgh to the first node N1 under the control of the second control module 12.

[0078] Exemplary, Figure 8 OrFigure 7 The shown interlocking module 14 includes a first interlocking transistor T9 and a second interlocking transistor T10; a gate of the first interlocking transistor T9 is electrically connected with a third sub-node N11 of the first node N1, a first electrode of the first interlocking transistor T9 is electrically connected with the second level end VGH, and a second electrode of the first interlocking transistor T9 is electrically connected with the second node N2; a gate of the second interlocking transistor T10 is electrically connected with a first sub-node N31 of the third node N3, a first electrode of the second interlocking transistor T10 is electrically connected with the second level end VGH, and a second electrode of the second interlocking transistor T10 is electrically connected with a first plate of the second capacitor C2.

[0079] In this way, the first interlocking transistor T9 can be turned on or off under the control of the potential of the first node N1, and when it is turned on, the second level signal Vgh is transmitted to the second node N2; the second interlocking transistor T10 can be turned on or off under the control of the potential of the third node N3, and when it is turned on, the second level signal Vgh is transmitted to the first node N1 through the second capacitor C2, realizing mutual clamping of the first node N1 and the second node N2. It can be understood that after the second level signal Vgh is transmitted to the first node N1 through the second capacitor C2, the potential of the first node N1 is raised to a potential comparable to the second level signal Vgh through the coupling effect of the second capacitor C2, stabilizing the potential of the first node N1.

[0080] Optionally, continuing to refer to Figure 8 or Figure 7 The output module 13 includes a first output transistor T11 and a second output transistor T12; a gate of the first output transistor T11 is electrically connected with the first node N1, a first electrode of the first output transistor T11 is electrically connected with the first level end VGL, and a second electrode of the first output transistor T11 is electrically connected with the signal output end OUT; a gate of the second output transistor T12 is electrically connected with the second node N2, a first electrode of the second output transistor T12 is electrically connected with the second level end VGH, and a second electrode of the second output transistor T2 is electrically connected with the signal output end OUT.

[0081] It can be understood that the output module 13 further includes a third capacitor C3 electrically connected between the second level end VGH and the second node N2, to store the potential of the second node N2 and maintain the stability of the potential of the second node N2.

[0082] The channel type of the first output transistor T11 and the second output transistor T12 can be the same or different, and the embodiments of the present application do not limit this. When the first output transistor T11 is a P-channel transistor, the enable level of the first node N1 for controlling the first output transistor T11 to be turned on is a low-level signal vgl, so that the first-level signal Vgl of the first-level terminal VGL is transmitted to the signal output terminal OUT, and the non-enable level of the first node N1 for controlling the first output transistor T11 to be turned off is a high-level signal vgh. When the first output transistor T11 is an N-channel transistor, the enable level of the first node N1 for controlling the first output transistor T11 to be turned on is a high-level signal vgh, so that the first-level signal Vgl of the first-level terminal VGL is transmitted to the signal output terminal OUT, and the non-enable level of the first node N1 for controlling the first output transistor T11 to be turned off is a low-level signal vgl. Similarly, when the second output transistor T12 is a P-channel transistor, the enable level of the second node N2 for controlling the second output transistor T12 to be turned on is a low-level signal vgl, so that the second-level signal Vgh of the second-level terminal VGH is transmitted to the signal output terminal OUT, and the non-enable level of the second node N2 for controlling the second output transistor T12 to be turned off is a high-level signal vgh. When the second output transistor T12 is an N-channel transistor, the enable level of the second node N2 for controlling the second output transistor T12 to be turned on is a high-level signal vgh, so that the second-level signal Vgh of the second-level terminal VGH is transmitted to the signal output terminal OUT, and the non-enable level of the second node N2 for controlling the second output transistor T12 to be turned off is a low-level signal vgl.

[0083] It should be noted that, Figure 8 and Figure 7 The structure diagram of the structure in which each transistor is a P-channel transistor is only exemplarily shown, but the present application is not limited thereto, and a person skilled in the art can design according to the needs, and the present application does not specifically limit this. For the convenience of description, the technical solutions of the embodiments of the present application are exemplarily described below by taking the structure in which each transistor in the shift register circuit 10 is a P-channel transistor as an example.

[0084] Optionally, continuing to refer to Figure 8 In the holding stage t2, the clock period of the first clock signal ck1 is the same as that in the data writing stage t1, and the width of the active pulse of the first clock signal ck1 in the holding stage t2 is the same as that in the data writing stage t1. And / or, in the holding stage t2, the clock period of the second clock signal xck is the same as that in the data writing stage t1, and the width of the active pulse of the second clock signal xck in the holding stage t2 is the same as that in the data writing stage t1.

[0085] Specifically, the first input transistor T6 in the first control module 11 can be controlled by the active pulse of the first clock signal ck1, so that the potential of the first node N1 matches the input signal Vin, that is, the potential of the first node N1 is directly controlled by the first clock signal ck1. The clock period of the first clock signal ck1 in the data writing stage t1 is T1, and the clock period in the holding stage t2 is T1'. By making T1 and T1' the same, and the width of the active pulse in T1 the same as the width of the active pulse in T1', the first clock signal ck1 has the same jump frequency in the data writing stage t1 and the holding stage t2, thereby making the control of the first node N1 by the first control module 11 consistent in the data writing stage t1 and the holding stage t2, ensuring that the signal output end OUT of the shift register circuit 10 outputs the first level signal Vgl under the potential of the first node N1, and ensuring that the shift register circuit 10 can work normally in the data writing stage t1 and the holding stage t2.

[0086] Similarly, the switch transistor T7 in the first control module 11 can be controlled by the potential of the first node N1, and the second clock signal xck is transmitted to the first plate of the second capacitor C2, so that after the second clock signal xck jumps from the high-level signal vgh to the low-level signal vgl, the potential of the first node N1 is continuously stabilized at a lower potential by the coupling effect of the second capacitor C2, ensuring that the signal output end OUT stably outputs the first level signal Vgl, that is, the potential of the first node N1 and the output signal of the signal output end OUT are also controlled by the jump of the second clock signal xck. The clock period of the second clock signal xck in the data writing stage t1 is T2, and the clock period in the holding stage t2 is T2'. By making T2 and T2' the same, and the width of the active pulse in T2 the same as the width of the active pulse in T2', the second clock signal xck has the same jump frequency in the data writing stage t1 and the holding stage t2, thereby making the control of the first node N1 by the first control module 11 consistent in the data writing stage t1 and the holding stage t2, ensuring that the signal output end OUT of the shift register circuit 10 outputs the first level signal Vgl under the potential of the first node N1, and ensuring that the shift register circuit can work normally in the data writing stage t1 and the holding stage t2.

[0087] Optionally, Figure 3 The driving timing diagram of another shift register circuit provided by the embodiment of the present application is shown in Figure 9 The holding stage t2 also includes at least one second holding frame t22; in the second holding frame t22, the third clock signal ck2 includes at least one active pulse.

[0088] It can be understood that, in the long time of the holding stage t2, if the potential of the third node N3 is kept as an invalid fixed level for a long time, that is, the potential of the gate of the first transistor T1 is kept as a non-enabled level for a long time, so that there is a voltage difference between the gate and the source or the drain of the first transistor T1 for a long time, so that the first transistor T1 is in a bias state for a long time, and the long-term work of the first transistor T1 in the bias state will cause the threshold voltage to drift, resulting in a hysteresis effect, which cannot make the first transistor T1 fully open when the potential of the third node N3 is an enabled level, and affects the transmission of the enabled level of the second pulse signal xck to the second node N2, thereby affecting the stable output of the signal output end OUT of the output module 13.

[0089] Therefore, in the second holding frame t22 of the holding stage t2, the third clock signal ck2 includes at least one valid pulse, so that the third transistor T3 in the third node control unit 122 is turned on under the control of the valid pulse of the third clock signal ck2, and the first level signal Vgl is transmitted to the third node N3, the bias state of the first transistor T1 is adjusted, thereby slowing down the hysteresis effect of the first transistor T1, so that the second node N2 can provide a stable enabled level to control the signal output end of the shift register circuit 10 to stably output the second level signal Vgh.

[0090] It should be noted that, Figure 9 It is only exemplarily shown that the third clock signal ck2 includes two valid pulses in the second holding frame t22, and the number of pulses of the third clock signal ck2 can be set according to actual needs, and the embodiments of the present application do not make specific limitations thereon.

[0091] Optionally, continuing to refer to Figure 9 It is shown that the width of the valid pulse of the third clock signal ck2 in the second holding frame t22 is less than or equal to the width of the valid pulse of the third clock signal ck2 in the data writing stage t1.

[0092] Specifically, taking the active pulse of the third clock signal ck2 as an example, the width of the active pulse of the third clock signal ck2 in the data writing stage t1 is the time t20 during which the third clock signal ck2 is a low-level signal vgl, and the width of the active pulse of the third clock signal ck2 in the second holding frame t22 is the time t20' during which the third clock signal ck2 is a low-level signal vgl. It can be understood that each time the third clock signal ck2 generates a transition of an active pulse, the potential of the third node N3 is charged or discharged, which causes power waste. By setting t20' to be less than or equal to t20, the discharging time of the potential of the third node N3 when the third clock signal ck2 is an active pulse can be reduced, and thus the charging time of the potential of the third node N3 when the third clock signal ck2 returns to an inactive fixed level can be reduced. In this way, the purpose of saving power consumption can be achieved.

[0093] Optionally, continuing to refer to Figure 9 The clock period of the third clock signal ck2 in the second holding frame t22 is greater than the clock period of the third clock signal ck2 in the data writing stage t1.

[0094] Specifically, the clock period of the third clock signal ck2 in the data writing stage t1 is T3, and the clock period of the third clock signal ck2 in the second holding frame t22 is T3'. On the basis that the width of the active pulse of the third clock signal ck2 in the second holding frame t22 is less than or equal to the width of the active pulse of the third clock signal ck2 in the data writing stage t1, T3' is set to be greater than T3, so that the transition frequency of the third clock signal ck2 in the holding stage t2 is less than the transition frequency of the third clock signal ck2 in the data writing stage t1, and thus the inactive fixed level is maintained for a longer time between the active pulses of the third clock signal ck2 in the second holding frame t22. This avoids charging and discharging the potential of the third node N3 multiple times, which causes the power consumption of the shift register circuit 10 to increase, thereby being conducive to low power consumption of the shift register circuit 10.

[0095] It should be noted that the clock period T3' of the third clock signal ck2 in the second holding frame t22 can be set according to actual requirements, as long as it is greater than the clock period T3 of the third clock signal ck2 in the data writing stage t1, Figure 9This is merely an illustrative example. Similarly, when the clock period of the first clock signal ck1 in the data writing phase t1 is the same as its clock period in the holding phase t2, the clock period of the third clock signal ck2 in the second holding frame t22 is also greater than the clock period of the first clock signal ck1; and when the clock period of the second clock signal xck in the data writing phase t1 is the same as its clock period in the holding phase t2, the clock period of the third clock signal ck2 in the second holding frame t22 can also be greater than the clock period of the second clock signal xck. While reducing power consumption, this embodiment of the invention does not limit the length of the clock period of the third clock signal ck2 in the second holding frame t22, provided that the transistor bias adjustment in the second control module 12 is achieved.

[0096] Optional, continue to refer to Figure 9 As shown, the time of the second hold frame t22 is after the time of at least one first hold frame t21.

[0097] Specifically, placing the second holding frame t22 after at least one first holding frame t21 is primarily because when the potential of the third node N3 remains at an invalid fixed level for an extended period, it can cause issues with transistors directly electrically connected to the third node N3 (e.g., Figure 9 The first transistor T1 in the circuit is in a biased state for an extended period, causing its threshold voltage to drift and resulting in a hysteresis effect. This affects the stability of the potential of the second clock signal xck transmitted to the second node N2. Therefore, it is necessary to enter the second hold frame t22 after at least one first hold frame t21 to mitigate the hysteresis effect of the transistor directly connected to the third node N3, ensuring the stability of the potential of the second node N2 while also saving power.

[0098] Optional, Figure 6 A driving timing diagram for another shift register circuit provided in an embodiment of the present invention is shown below. Figure 10 As shown, the time of the second hold frame t22 is between the times of the two adjacent first hold frames t21.

[0099] Specifically, Figure 10 An exemplary illustration shows that the holding phase t2 includes two second holding frames t22, the time of which is between the times of two adjacent first holding frames t21, such that at least one transition occurs between two adjacent long-term invalid fixed levels of the third clock signal ck2, i.e., from an invalid fixed transition to an effective pulse, to charge and discharge the potential of the third node N3 at least once, so as to prevent the potential of the third node N3 from being maintained at the first level signal Vgl for a long time, which would affect the stability of the potential of the second clock signal xck transmitted to the second node N2.

[0100] It can be understood that, Figure 10 It is only exemplarily shown that the holding stage t2 includes two first holding frames t21 and one second holding frame t22, while in the embodiment of the present application, the number of the first holding frame t21 and the second holding frame t22 in the holding stage t2 can be set as required, and the embodiment of the present application does not make specific limitation thereon.

[0101] Optionally, Figure 10 The driving timing diagram of another shift register circuit provided by the embodiment of the present application is shown in FIG. 6, and the driving timing diagram of the shift register circuit is shown in FIG. 7. Figure 11 As shown in FIG. 6, in the data writing stage t1, the clock period of the first clock signal ck1 is the first clock period T1, and in at least part of the first holding frame t21, the clock period of the first clock signal ck1 is the second clock period T1', and the first clock period T1 is less than or equal to the second clock period T1'.

[0102] The second clock period T1' can be any value greater than the first clock period T1, and the embodiment of the present application does not make specific limitation thereon, Figure 11 It is only exemplarily shown that the second clock period T1' is twice the first clock period T1.

[0103] Specifically, the frequency of the first clock signal ck1 in the part of the first holding frame t21 is less than the frequency of the first clock signal ck1 in the data writing stage t1, so that the first clock signal ck1 controls the first control module 11 at a lower frequency in the first holding frame t21, so that the potential of the first node N1 matches the input signal Vin, so as to further save power consumption.

[0104] Exemplarily, referring to FIG. 5 and FIG. 6, Figure 11 and Figure 7 In the data writing stage t1, the first clock signal ck1 can control the first input transistor T6 to be turned on or off, so as to transmit the input signal Vin of the signal input end IN to the first node N1 when the first input transistor T6 is in the on state, and when the potential of the first node N1 is the enable level, the signal output end OUT outputs the first level signal Vgl under the control of the potential of the first node N1. In the first holding frame t21, the signal output end OUT continuously outputs the first level signal Vgl, that is, the potential of the first node N1 continuously remains as the enable level, and the potential of the second node N2 continuously remains as the non-enable level. At this time, when the first clock signal ck1 is the non-enable level, the first control module 11 is controlled by the second clock signal xck, so that the potential of the first node N1 can still remain as the enable level. Therefore, the frequency of the effective pulse of the first clock signal ck1 can be further reduced, and the number of times that the first input transistor T6 is turned on and off under the control of the first clock signal ck1 is reduced, so as to save power consumption.

[0105] Optionally, Figure 11 A driving timing diagram of the shift register circuit is provided for an embodiment of the present application, referring to Figure 12 As shown, the holding stage t2 further includes at least one second holding frame t22, in which the third clock signal ck2 includes at least one active pulse. In the second holding frame t22, the time of the active pulse of the first clock signal ck1 overlaps with the time of the active pulse of the third clock signal ck2.

[0106] In the second holding frame t22, the clock period of the first clock signal ck1 can be the first clock period T1 or the second clock period T1', and the embodiment of the present application does not make specific limitation thereon, Figure 12 Exemplarily, it is shown that the clock period of the first clock signal ck1 in the second holding frame t22 is the same as the clock period in the first holding frame t21, both of which are the second clock period T1', but the present application is not limited thereto. In addition, Figure 11 Exemplarily, it is shown that the third clock signal ck2 includes one active pulse in the second holding frame t22, but the present application is not limited thereto.

[0107] Specifically, referring to Figure 11 and Figure 7 In the second holding frame t22, the time of the active pulse of the first clock signal ck1 overlaps with the time of the active pulse of the third clock signal ck2, that is, when the third clock signal ck2 is the active pulse (i.e., the enable level), the first clock signal ck1 is also the active pulse (i.e., the enable level), at this time, the second clock signal xck is the non-enable level, the first control module 11 transmits the input signal Vin to the first node N1 under the control of the enable level of the first clock signal ck1, the second control module 12 transmits the first level signal Vgl to the third node N3 under the control of the enable level of the third clock signal ck2, and at the same time, the second control module 12 also makes the potential of the second node N2 continue to be the non-enable level under the control of the non-enable level of the second clock signal xck.

[0108] When the first clock signal ck1 transitions to a disabled level, the third clock signal ck2 also transitions to an invalid fixed level (i.e., a disabled level), and the second clock signal xck transitions to an enabled level. Under the control of the enabled level of the first clock signal ck1, the first control module 11 blocks the input signal Vin from continuing to be transmitted to the first node N1, and under the control of the second clock signal xck, keeps the potential of the first node N1 stable at the enabled level, so that the signal output terminal OUT continues to stably output the first level signal Vgl. At the same time, the second control module 12, based on the potential of the first node N1, transmits the third clock signal ck2 at a disabled level to the third node N3, and under the control of the potential of the third node N3, keeps the potential of the second node N2 stable at the disabled level.

[0109] Thus, in the second hold frame t22, the effective pulse time of the first clock signal ck1 overlaps with the effective pulse time of the third clock signal ck2, which allows the transistors in the first control module 11 and the second control module 12 in the shift register circuit 10 to perform a complete driving process under the control of the first clock signal ck1 and the third clock signal, avoiding the hysteresis effect caused by the transistors being in the same bias state for a long time, and improving the output accuracy of the shift register circuit.

[0110] Optional, Figure 12 A driving timing diagram for another shift register circuit provided in an embodiment of the present invention is shown below. Figure 13 As shown, during the data writing phase t1, the clock period of the second clock signal xck is the third clock period T2; during the at least partially held phase t2, the clock period of the second clock signal xck is the fourth clock period T2'; the third clock period T2 is less than or equal to the fourth clock period T2'.

[0111] Wherein, the fourth clock period T2' can be any value greater than the third clock period T2, and the embodiments of the present invention do not impose specific limitations on it. Figure 13 The fourth clock cycle T2' is shown as twice the third clock cycle T2, for example only.

[0112] Specifically, the transition frequency of the second clock signal xck during the partial hold phase t2 is lower than its transition frequency during the data write phase t1, so that the second clock signal xck controls the first control module 11 at a lower frequency during the hold phase t2, thereby enabling the first control module 11 to maintain the stability of the potential of the first node N1 under the control of the second clock signal xck, and at the same time, further achieving the purpose of saving power consumption.

[0113] Optional, Figure 12 A driving timing diagram for another shift register circuit provided in an embodiment of the present invention is shown below. Figure 14As shown, when the holding phase t2 further includes at least one second holding frame t22, in the second holding frame t22, the third clock signal ck2 includes at least one valid pulse. In the second holding frame t22, the timing of the valid pulse of the second clock signal xck does not overlap with the timing of the valid pulse of the third clock signal ck2.

[0114] In the second hold frame t22, the clock period of the second clock signal xck can be either the third clock period T2 or the fourth clock period T2'. This embodiment of the invention does not specifically limit this. Figure 14 An example is shown where the clock period of the second clock signal xck in the second hold frame t22 is the fourth clock period T2', but it is not limited thereto. Furthermore, Figure 11 It is also exemplarily shown that the third clock signal ck2 includes a valid pulse in the second hold frame t22, but is not limited thereto.

[0115] For details, please refer to Figure 11 and Figure 7 In the second hold frame t22, the effective pulse time of the second clock signal xck does not overlap with the effective pulse time of the third clock signal ck2. That is, when the third clock signal ck2 is an effective pulse (i.e., an enabled level), the second clock signal xck is an disabled level. At this time, under the control of the third clock signal ck2, the first control module 11 transmits the first level signal Vgl to the third node N3 to discharge the potential of the third node N3, so as to avoid the potential of the third node N3 remaining unchanged for a long time, which would damage the transistors electrically connected to the node. Figure 14 The first transistor T1 exhibits a hysteresis effect. Simultaneously, the second control module 12, under the control of the second clock signal xck, maintains the potential of the second node N2 at an disabled level.

[0116] When the third clock signal ck2 transitions to an enabled level, the second clock signal xck becomes an active pulse (i.e., an enabled level). At this time, the first control module 11, under the control of the second clock signal xck, maintains the potential of the first node N1 at an enabled level. Simultaneously, under the control of the third clock signal ck2, the second control module 12 charges the potential of the third node N3, making the potential of the third node N3 an enabled level, thus blocking the transmission of the enabled level of the second clock signal xck to the second node N2, keeping the potential of the second node N2 at an enabled level, thereby enabling the signal output terminal OUT to stably output the first level signal Vgl.

[0117] Thus, in the second holding frame t22, the time of the active pulse of the second clock signal xck does not overlap with the time of the active pulse of the third clock signal ck2, so that the transistors in the first control module 11 and the second control module 12 in the shift register circuit 10 can be controlled by the second clock signal xck and the third clock signal to perform a complete driving process, thereby avoiding the hysteresis effect caused by the transistors being in the same bias state for a long time, and improving the output accuracy of the shift register circuit.

[0118] In an alternative embodiment, Figure 7 Another driving timing diagram of the shift register circuit according to an embodiment of the present application is shown in FIG. 4. Figure 15 As shown in FIG. 4, in the first holding frame t21, the clock period of the first clock signal ck1 is the same as the clock period of the second clock signal xck.

[0119] Specifically, in the first holding frame t21, the clock period of the first clock signal ck1 is T1', and the clock period of the second clock signal xck is T2'. When the clock period T1' of the first clock signal ck1 in the first holding frame t21 is the same as the clock period T2' of the second clock signal xck, the clock period T1' of the first clock signal ck1 in the first holding frame t21 is greater than the clock period T1 of the first clock signal ck1 in the data writing stage t1, because the clock period of the second clock signal xck in the first holding frame t21 is greater than the clock period T2 of the second clock signal xck in the data writing stage t1. Thus, in the first holding frame t21, the first clock signal ck1 and the second clock signal xck are reduced by the same degree, which ensures the normal operation of the shift register circuit 10 while saving power consumption.

[0120] In another alternative embodiment, Figure 15 Another driving timing diagram of the shift register circuit according to an embodiment of the present application is shown in FIG. 4. Figure 16 As shown in FIG. 4, in the first holding frame t21, the clock period of the first clock signal ck1 is the same as the clock period of the second clock signal xck.

[0121] Specifically, in the second holding frame t22, the clock period of the first clock signal ck1 is T1', and the clock period of the second clock signal xck is T2'. When the clock period T1' of the first clock signal ck1 and the clock period T2' of the second clock signal xck are the same in the second holding frame t22, since the clock period of the second clock signal xck in the second holding frame t22 is greater than its clock period T2 in the data writing stage t1, the clock period T1' of the first clock signal ck1 in the second holding frame t22 is greater than its clock period T1 in the data writing stage t1. Thus, in the second holding frame t22, the first clock signal ck1 and the second clock signal xck are downclocked to the same extent, saving power while ensuring the normal operation of the shift register circuit 10.

[0122] In yet another alternative embodiment, Figure 16 A driving timing diagram for another shift register circuit provided in an embodiment of the present invention is shown below. Figure 17 As shown, in the first holding frame t21, the clock period of the first clock signal ck1 is the same as the clock period of the second clock signal xck, and in the second holding frame t22, the clock period of the first clock signal ck1 is the same as the clock period of the second clock signal xck. This further enables the first clock signal ck1 and the second clock signal xck to have the same degree of frequency reduction in the holding phase t2, so as to ensure the normal operation of the shift register circuit 10 and save power consumption.

[0123] Based on any of the above embodiments, optionally, Figure 17 This is a schematic diagram of another shift register provided in an embodiment of the present invention, with reference to... Figure 18 As shown, in each stage of the shift register circuit 10, the signal input terminal IN of the (i+1)th stage shift register circuit 10 is electrically connected to the signal output terminal OUT of the i-th stage shift register circuit 10; the signal input terminal IN of the first stage shift register circuit 10 receives the start pulse signal Stv; where i is a positive integer. The first clock signal ck1 received by the i-th stage shift register circuit 10 is multiplexed to the second clock signal xck received by the (i+1)th stage shift register circuit; and / or, the second clock signal xck received by the i-th stage shift register circuit 10 is multiplexed to the first clock signal ck1 received by the (i+1)th stage shift register circuit 10.

[0124] It can be understood that each stage of the shift register circuit 10 includes a first clock terminal CK1, a second clock terminal XCK and a third clock terminal CK2, that is, each stage of the shift register circuit 10 needs three clock signals, so that the entire shift register 100 needs multiple clock signals, which will increase the number of signal terminals in the driving chip for providing clock signals to each shift register circuit 10 in the shift register 10, which is not conducive to the low cost of the driving chip. At the same time, in order to ensure that each clock signal does not affect each other during transmission, clock signal transmission lines with corresponding spacing and width need to be set to transmit different clock signals, which will increase the frame size of the display panel, which is not conducive to the narrow frame of the display panel.

[0125] Exemplary, Figure 18 The structural schematic diagrams of the first stage of the shift register circuit 10 to the fourth stage of the shift register circuit 10 (that is, ASG1, ASG2, ASG3 and ASG4) are shown, wherein the input terminal of the first stage of the shift register circuit 10 is electrically connected with the start pulse signal line STV transmitting the start pulse signal Stv. The signal input terminal IN of each stage of the shift register circuit 10 from the second stage of the shift register circuit 10 to the fourth stage of the shift register circuit 10 is electrically connected with the signal output terminal OUT of the previous stage of the shift register circuit 10. In the first stage of the shift register circuit 10, the first clock terminal CK1 is electrically connected with the first clock signal line L1 transmitting the first clock signal ck1, the second clock terminal XCK is electrically connected with the second clock signal line L2 transmitting the second clock signal xck, and the third clock terminal CK2 is electrically connected with the third clock signal line L3 transmitting the third clock signal ck2.

[0126] Since the time of the active pulse of the first clock signal ck1 and the time of the active pulse of the second clock signal xck do not overlap, in this way, in the two adjacent stages of the shift register circuit 10, the first clock signal ck1 of the previous stage of the shift register circuit 10 is multiplexed as the second clock signal xck of the next stage of the shift register circuit 10, which reduces the number of clock signals provided to each stage of the shift register circuit 10 in the shift register 100. Or, the second clock signal xck of the previous stage of the shift register circuit 10 is multiplexed as the first clock signal ck of the next stage of the shift register circuit 10, which also helps to reduce the number of clock signals provided to each stage of the shift register circuit 10 in the shift register 100. Figure 18The first clock signal ck1 received by the i-th stage shift register circuit 10 is multiplexed as the second clock signal xck received by the (i+1)-th stage shift register circuit 10, and the second clock signal xck received by the i-th stage shift register circuit 10 is multiplexed as the first clock signal ck1 received by the (i+1)-th stage shift register circuit 10, but the present application is not limited thereto. Taking i=1 as an example, the first clock terminal CK1 of the first stage shift register circuit 10 and the second clock terminal XCK of the second stage shift register circuit 10 are electrically connected to the first clock signal line L1, and the second clock terminal XCK of the first stage shift register circuit 10 and the first clock terminal CK1 of the second stage shift register circuit 10 are electrically connected to the second clock signal line L2. In this way, the number of signal terminals in the driving chip for providing clock signals to the shift register 100 is reduced, which is conducive to the low cost of the driving chip. At the same time, when the number of clock signals provided to the shift register 100 is reduced, the number of signal lines for transmitting clock signals is also reduced, which is conducive to the narrow frame of the display panel.

[0127] Optionally, continuing to refer to Figure 18 As shown, the third clock signal ck2 received by the i-th stage shift register circuit 10 is multiplexed as the third clock signal ck2 received by the (i+2)-th stage shift register circuit 10; and / or, the first clock signal ck1 received by the i-th stage shift register circuit 10 is multiplexed as the first clock signal ck1 received by the (i+2)-th stage shift register circuit 10.

[0128] Specifically, the third clock signal ck2 received by the i-th stage shift register circuit 10 is multiplexed as the third clock signal ck2 received by the (i+2)-th stage shift register circuit 10, at this time, the third clock signal ck2 received by the i-th stage shift register circuit 10 and the third clock signal ck2 received by the (i+1)-th stage shift register circuit 10 can come from different clock signal lines, or can come from the same clock signal line, and the present application does not make specific limitation thereon. Exemplarily, referring to Figure 18 , the third clock signal ck2 received by the first stage shift register circuit 10 is multiplexed as the third clock signal ck2 received by the third stage shift register circuit 10, i.e., the third clock terminal CK2 of the first stage shift register circuit 10 and the third clock terminal CK2 of the third stage shift register circuit 10 are electrically connected to the third clock signal line L3. Correspondingly, the third clock signal ck2 received by the second stage shift register circuit 10 is multiplexed as the third clock signal ck2 received by the fourth stage shift register circuit 10, i.e., the third clock terminal CK2 of the second stage shift register circuit 10 and the third clock terminal CK2 of the fourth stage shift register circuit 10 are electrically connected to the fourth clock signal line L4.

[0129] Similarly, the first clock signal ck1 received by the i-th stage shift register circuit 10 is multiplexed as the first clock signal ck1 received by the i+2-th stage shift register circuit 10, i.e., the first clock terminal CK1 of the i-th stage shift register circuit 10 and the first clock terminal CK1 of the i+2-th stage shift register circuit 10 are electrically connected to the same clock signal line, so as to reduce the number of clock signal lines for transmitting the first clock signal ck1 to each stage shift register circuit. For example, Figure 17 It is also exemplarily shown that the first clock terminal CK1 of the first stage shift register circuit 10 and the first clock terminal CK1 of the third stage shift register circuit 10 are electrically connected to the first clock signal line L1, and the first clock terminal CK1 of the second stage shift register circuit 10 and the first clock terminal CK1 of the fourth stage shift register circuit 10 are electrically connected to the second clock signal line L2. In this way, the number of signal lines for transmitting the clock signal is reduced, which is beneficial to the narrow frame of the display panel.

[0130] Optionally, continuing to refer to Figure 17 It is shown that the time of the active pulse of the third clock signal ck2 received by the i-th stage shift register circuit 10 does not overlap with the time of the active pulse of the third clock signal ck2 received by the i+1-th stage shift register circuit 10.

[0131] Specifically, the time of the active pulse of the third clock signal ck2 received by the i-th stage shift register circuit 10 does not overlap with the time of the active pulse of the third clock signal ck2 received by the i+1-th stage shift register circuit 10, so as to ensure that the adjacent two stage shift register circuits 10 can work normally. At this time, the third clock terminal CK2 of the i-th stage shift register circuit 10 and the third clock terminal CK2 of the i+1-th stage shift register circuit 10 can be respectively electrically connected to different signal lines, and continuing to refer to Figure 18 For example, the third clock terminal CK2 of the first stage shift register circuit 10 is electrically connected to the third clock signal line L3, and the third clock terminal CK2 of the second stage shift register circuit 10 is electrically connected to the fourth clock signal line L4, but not limited thereto.

[0132] Optionally, continuing to refer to Figure 17 It is shown that the second clock signal xck received by the i-th stage shift register circuit 10 is multiplexed as the second clock signal xck received by the i+2-th stage shift register circuit 10.

[0133] Specifically, the second clock signal xck received by the i-th stage shift register circuit 10 is multiplexed as the second clock signal xck received by the i+2-th stage shift register circuit 10, i.e., the second clock terminal XCK of the i-th stage shift register circuit 10 and the second clock terminal XCK of the i+2-th stage shift register circuit 10 can be electrically connected to the same clock signal line, Figure 18The second clock terminal XCK of the first stage shift register circuit 10 and the second clock terminal XCK of the third stage shift register circuit 10 are both electrically connected with the second clock signal line L2, and the second clock terminal XCK of the second stage shift register circuit 10 and the second clock terminal XCK of the fourth stage shift register circuit 10 are both electrically connected with the first clock signal line L1, so as to reduce the number of signal terminals in the driving chip for providing the clock signal to each stage shift register circuit 10 in the shift register 100, simplify the structure and reduce the cost, and meanwhile, the number of signal lines for transmitting the clock signal can be reduced, thereby facilitating the narrow frame of the display panel.

[0134] Based on the same inventive concept, the embodiment of the present application also provides a display panel, which comprises the shift register in any of the above embodiments, so that the display panel provided by the embodiment of the present application comprises the technical features of the shift register circuit provided by the embodiment of the present application, and can achieve the beneficial effects of the shift register circuit provided by the embodiment of the present application. The same parts can be referred to the above description of the shift register circuit provided by the embodiment of the present application, which will not be repeated here.

[0135] Optionally, Figure 18 The structural schematic diagram of the display panel provided by the embodiment of the present application is shown in FIG. 1. Figure 19 As shown in FIG. 1, the display panel 01 comprises a display area AA and a non-display area NA, the display area AA is provided with pixel circuits P and scan signal lines S arranged in an array, and the non-display area NA is provided with a shift register 100; at least part of the pixel circuits P in the same row are electrically connected with the same scan signal line S, the signal output terminals OUT of each stage shift register circuit 10 (i.e. ASG1-ASGn) of the shift register 100 are electrically connected with at least one scan signal line S, and each scan signal line S is electrically connected with one shift register circuit 10, so that each stage shift register circuit 10 can provide corresponding scan signals to each scan signal line S, so that the transistors in the pixel circuit P are turned on or off under the control of the scan signals, and the line-by-line scanning of each pixel circuit P in the display panel 01 is realized.

[0136] Based on the same inventive concept, the embodiment of the present application also provides a display device, Figure 19 The structural schematic diagram of the display device provided by the embodiment of the present application is shown in FIG. 2. Figure 20 Figure 20 As shown in FIG. 2, the display device 02 comprises the display panel 01 provided by any of the embodiments of the present application, and the display device 02 provided by the embodiment of the present application can be a mobile phone or any electronic product with display function, including but not limited to the following categories: television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interactive terminal, etc., and the embodiment of the present application does not make special limitation to this.

[0137] Note that the above merely describes preferred embodiments of the application and the principles of the technology applied. Those skilled in the art will understand that the application is not limited to the specific embodiments described herein, and that various obvious changes, modifications, combinations and substitutions can be made thereto without departing from the scope of the application. Therefore, although the application has been described in detail by the above embodiments, the application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the application, and the scope of the application is determined by the appended claims.

Claims

1. A shift register, characterized in that, include: Multiple cascaded shift register circuits; each shift register circuit includes a first clock terminal, a second clock terminal, a third clock terminal, a first level terminal, a second level terminal, a signal input terminal, a signal output terminal, a first control module, a second control module, and an output module; In the same shift register circuit, the first control module and the output module are electrically connected to the first node; the first control module is also electrically connected to the first clock terminal, the second clock terminal and the signal input terminal; The first control module is used to control the potential of the first node according to the first clock signal at the first clock terminal, the second clock signal at the second clock terminal, and the input signal at the signal input terminal; The second control module is electrically connected to the output module at the second node; The second control module is also electrically connected to the third clock terminal, the first level terminal, and the first node; The second control module is used to control the potential of the second node according to the third clock signal of the third clock terminal, the first level signal of the first level terminal and the potential of the first node; The output module is also electrically connected to the first level terminal, the second level terminal and the signal output terminal respectively; The output module is used to control the duration of the first level signal output by the signal output terminal under the control of the potential of the first node, and to control the duration of the second level signal output by the signal output terminal under the control of the potential of the second node. Each drive cycle of the shift register includes a data write phase and a hold phase; the hold phase includes at least one first hold frame; during the data write phase, the third clock signal includes multiple valid pulses, and the second level signals output by the signal output terminals of each stage of the shift register circuit are shifted sequentially; during the hold phase, each stage of the shift register circuit outputs the first level signal; at least during the first hold frame, the third clock signal is an invalid fixed level.

2. The shift register according to claim 1, characterized in that, The second control module includes a second node control unit and a third node control unit; In the same shift register circuit: The third node control unit is electrically connected to the second node control unit at the third node; the third node control unit is also electrically connected to the first node, the third clock terminal, and the first level terminal respectively. The third node control unit is used to control the transmission time of the third clock signal to the third node under the control of the potential of the first node, and to control the transmission time of the first level signal to the third node under the control of the third clock signal. The second node control unit is also electrically connected to the second clock terminal and the second node, respectively. The second node control unit is used to control the potential of the second node according to the second clock signal and the potential of the third node.

3. The shift register according to claim 2, characterized in that, The second node control unit includes a first capacitor, a first transistor, and a second transistor; In the same shift register circuit: The first plate of the first capacitor and the gate of the first transistor are both coupled to the third node; the first terminal of the first transistor is electrically connected to the second clock terminal; the second terminal of the first transistor is electrically connected to the second plate of the first capacitor. The gate of the second transistor is electrically connected to the second clock terminal, the first terminal of the second transistor is electrically connected to the second plate of the first capacitor, and the second terminal of the second transistor is electrically connected to the second node.

4. The shift register according to claim 1, characterized in that, In the hold phase, the clock period of the first clock signal is the same as the clock period of the first clock signal in the data write phase; and, in the hold phase, the width of the effective pulse of the first clock signal is the same as the width of the effective pulse of the first clock signal in the data write phase; and / or, In the hold phase, the clock period of the second clock signal is the same as that in the data write phase; and in the hold phase, the width of the effective pulse of the second clock signal is the same as that in the data write phase.

5. The shift register according to claim 1, characterized in that, The hold phase further includes at least one second hold frame; in the second hold frame, the third clock signal includes at least one valid pulse.

6. The shift register according to claim 5, characterized in that, The width of the effective pulse of the third clock signal in the second holding frame is less than or equal to the width of the effective pulse of the third clock signal in the data writing phase.

7. The shift register according to claim 6, characterized in that, The clock period of the third clock signal in the second hold frame is greater than the clock period of the third clock signal in the data write phase.

8. The shift register according to claim 5, characterized in that, The time of the second hold frame is located after the time of at least one of the first hold frames.

9. The shift register according to claim 5, characterized in that, The time of the second hold frame lies between the times of two adjacent first hold frames.

10. The shift register according to claim 1, characterized in that, For the third clock signal, the time during which the invalid fixed level is maintained in the first holding frame is greater than the interval between two adjacent valid pulses in the data writing phase.

11. The shift register according to claim 1, characterized in that, During the data writing phase, the clock period of the first clock signal is a first clock period; during at least a portion of the first hold frame, the clock period of the first clock signal is a second clock period; the first clock period is less than or equal to the second clock period.

12. The shift register according to claim 11, characterized in that, The holding phase further includes at least one second holding frame; in the second holding frame, the third clock signal includes at least one valid pulse; In the second hold frame, the timing of the effective pulse of the first clock signal overlaps with the timing of the effective pulse of the third clock signal.

13. The shift register according to claim 1, characterized in that, During the data writing phase, the clock period of the second clock signal is a third clock cycle; during at least part of the holding phase, the clock period of the second clock signal is a fourth clock cycle. The third clock cycle is less than or equal to the fourth clock cycle.

14. The shift register according to claim 13, characterized in that, The holding phase further includes at least one second holding frame; in the second holding frame, the third clock signal includes at least one valid pulse; In the second hold frame, the timing of the effective pulse of the second clock signal does not overlap with the timing of the effective pulse of the third clock signal.

15. The shift register according to claim 14, characterized in that, In the first hold frame, the clock period of the first clock signal is the same as the clock period of the second clock signal; and / or, In the second hold frame, the clock period of the first clock signal is the same as the clock period of the second clock signal.

16. The shift register according to claim 1, characterized in that, In each stage of the shift register circuit, the signal input terminal of the (i+1)th stage shift register circuit is electrically connected to the signal output terminal of the ith stage shift register circuit; the signal input terminal of the first stage shift register circuit receives a start pulse signal; where i is a positive integer; The first clock signal received by the shift register circuit of the i-th stage is multiplexed into the second clock signal received by the shift register circuit of the (i+1)-th stage; and / or, the second clock signal received by the shift register circuit of the i-th stage is multiplexed into the first clock signal received by the shift register circuit of the (i+1)-th stage.

17. The shift register according to claim 16, characterized in that, The third clock signal received by the shift register circuit of the i-th stage is multiplexed into the third clock signal received by the shift register circuit of the (i+2)-th stage; and / or, the first clock signal received by the shift register circuit of the i-th stage is multiplexed into the first clock signal received by the shift register circuit of the (i+2)-th stage.

18. The shift register according to claim 16, characterized in that, The effective pulse time of the third clock signal received by the shift register circuit of stage i does not overlap with the effective pulse time of the third clock signal received by the shift register circuit of stage i+1.

19. The shift register according to claim 16, characterized in that, The second clock signal received by the shift register circuit of the i-th stage is multiplexed into the second clock signal received by the shift register circuit of the (i+2)-th stage.

20. The shift register according to claim 1, characterized in that, The shift register circuit also includes an interlock module; In the same shift register circuit, the interlock module is electrically connected to the second level terminal, the first control module, and the second control module respectively. The interlock module is used to control the transmission time of the second level signal to the second node under the control of the first control module, and to control the transmission time of the second level signal to the first node under the control of the second control module.

21. A display panel, characterized in that, include: The shift register according to any one of claims 1-20.

22. A display device, characterized in that, include: The display panel according to claim 21.

Images