Shift register unit and driving method therefor, gate driving circuit, and display device

Abstract

Provided are a shift register unit and a driving method therefor, a gate driving circuit, and a display device, relating to the technical field of display. The shift register unit comprises an input control circuit (01) and an output control circuit (02). Since the input control circuit (01) can reliably and flexibly control the potentials of a pull-up node (Q) and a pull-down node (QB), the output control circuit (02) can reliably output a high-potential or low-potential signal to an output signal terminal (OUT) under the control of the pull-up node (Q) and the pull-down node (QB). Thus, the shift register unit can reliably output a gate driving signal to pixels via the output signal terminal (OUT), thereby reliably driving the pixels to emit light, achieving a better display effect for a display panel.

Description

Shift register unit and its driving method, gate driving circuit, display device Technical Field

[0001] This application relates to the field of display technology, and in particular to a shift register unit and its driving method, gate driving circuit, and display device. Background Technology

[0002] With the development of display technology, the gate drive on array (GOA) technology is now widely used to integrate gate drive circuits on the display panel to drive pixel light emission. Correspondingly, the gate drive circuit is also called a GOA circuit.

[0003] In related technologies, GOA circuits generally include multiple cascaded shift register units (also called GOA units). These multiple GOA units are connected to multiple rows of pixels in the display panel and are used to transmit the required gate drive signals to the multiple rows of pixels to drive them to emit light. Furthermore, each GOA unit generally includes multiple transistors, and each transistor is mostly an N-type transistor made of oxide material.

[0004] However, due to limitations in manufacturing processes and materials, current GOA units are often unable to reliably output gate drive signals to pixels, thus failing to reliably drive pixels to emit light, resulting in poor display performance of the display panel.

[0005] Summary of the Invention

[0006] A shift register unit and its driving method, a gate driving circuit, and a display device are provided. The technical solution is as follows:

[0007] On the one hand, a shift register unit is provided, the shift register unit comprising:

[0008] An input control circuit is connected to an input signal terminal, a first clock terminal, a first power supply terminal, a first target terminal, a pull-up node, and a pull-down node, respectively. It is used to control the connection and disconnection between the input signal terminal and the pull-up node, the connection and disconnection between the first target terminal and the pull-down node, and the connection and disconnection between the first power supply terminal and the pull-down node, in response to an input signal provided by the input signal terminal, a first clock signal provided by the first clock terminal, a first power supply signal provided by the first power supply terminal, and a first target signal provided by the first target terminal. The first target terminal is either a second power supply terminal or shared with the first clock terminal.

[0009] The output control circuit is connected to the pull-up node, the pull-down node, the second clock terminal, the third power supply terminal, and the output signal terminal, respectively, and is used to control the connection and disconnection of the second clock terminal and the output signal terminal in response to the potential of the pull-up node, and to control the connection and disconnection of the third power supply terminal and the output signal terminal in response to the potential of the pull-down node.

[0010] Optionally, the input control circuit includes:

[0011] The first input control sub-circuit is connected to the first clock terminal, the input signal terminal and the pull-up node respectively, and is used to control the on / off state of the input signal terminal and the pull-up node in response to the first clock signal;

[0012] The second input control sub-circuit is connected to the input signal terminal, the first power supply terminal, the first clock terminal, the control signal terminal, the intermediate node, and the pull-down node, respectively. It is used to control the potential of the intermediate node in response to the input signal, the first power supply signal, and the first clock signal, and to control the on / off state of the first power supply terminal and the pull-down node in response to the control signal provided by the control signal terminal. The control signal terminal is shared with or connected to the pull-up node.

[0013] The third input control sub-circuit is connected to the intermediate node, the first target terminal, and the pull-down node respectively, and is used to control the on / off state of the first target terminal and the pull-down node in response to the potential of the intermediate node.

[0014] Optionally, the second input control sub-circuit includes:

[0015] The first input control unit is connected to the input signal terminal, the first power supply terminal, the first clock terminal and the intermediate node respectively, and is used to control the connection and disconnection between the first power supply terminal and the intermediate node in response to the input signal, and to control the potential of the intermediate node in response to the first clock signal, or to control the connection and disconnection between the first power supply terminal and the intermediate node in response to the input signal and the first clock signal.

[0016] The second input control unit is connected to the control signal terminal, the first power supply terminal, and the pull-down node respectively, and is used to control the on / off state of the first power supply terminal and the pull-down node in response to the control signal.

[0017] Optionally, when the first input control unit controls the switching between the first power supply terminal and the intermediate node in response to the input signal, and controls the potential of the intermediate node in response to the first clock signal, the first input control unit includes: a first transistor and a first capacitor; and the gate of the first transistor is connected to the input signal terminal, the first electrode of the first transistor is connected to the first power supply terminal, the second electrode of the first transistor is connected to the intermediate node, one end of the first capacitor is connected to the first clock terminal, and the other end of the first capacitor is connected to the intermediate node;

[0018] When the first input control unit controls the connection and disconnection between the first power supply terminal and the intermediate node in response to the input signal and the first clock signal, the first input control unit includes: a first transistor and a second transistor; and the gate of the first transistor is connected to the input signal terminal, the first electrode of the first transistor is connected to the first power supply terminal, the second electrode of the first transistor is connected to the first electrode of the second transistor, the gate of the second transistor is connected to the first clock terminal, and the second electrode of the second transistor is connected to the intermediate node.

[0019] The second input control unit includes a third transistor; and the gate of the third transistor is connected to the control signal terminal, the first terminal of the third transistor is connected to the first power supply terminal, and the second terminal of the third transistor is connected to the pull-down node.

[0020] Optionally, the first transistor includes two first sub-transistors with their first and second terminals connected in series; the third transistor includes two second sub-transistors with their first and second terminals connected in series; the shift register unit further includes:

[0021] The first leakage protection circuit is connected to the intermediate node, the fourth power supply terminal, the series node of the two first sub-transistors, and the series node of the two second sub-transistors, respectively, and is used to control the on / off state of the fourth power supply terminal and the connected series node in response to the potential of the intermediate node.

[0022] Optionally, the first leakage protection circuit includes: a fourth transistor;

[0023] Furthermore, the gate of the fourth transistor is connected to the intermediate node, the first terminal of the fourth transistor is connected to the fourth power supply terminal, and the second terminal of the fourth transistor is connected to the series node of the two first sub-transistors and the series node of the two second sub-transistors.

[0024] Optionally, the first input control sub-circuit includes: a fifth transistor;

[0025] Furthermore, the gate of the fifth transistor is connected to the first clock terminal, the first terminal of the fifth transistor is connected to the input signal terminal, and the second terminal of the fifth transistor is connected to the pull-up node.

[0026] Optionally, the third input control sub-circuit includes: a sixth transistor;

[0027] Furthermore, the gate of the sixth transistor is connected to the intermediate node, the first electrode of the sixth transistor is connected to the first target terminal, and the second electrode of the sixth transistor is connected to the pull-down node.

[0028] Optionally, the pull-up node includes: a first pull-up node and a second pull-up node; the input control circuit is connected to the first pull-up node, and the output control circuit is connected to the second pull-up node; the shift register unit further includes:

[0029] The first intermediate control circuit is connected to the fifth power supply terminal, the first pull-up node and the second pull-up node respectively, and is used to control the on and off of the first pull-up node and the second pull-up node in response to the fifth power supply signal provided by the fifth power supply terminal.

[0030] And / or,

[0031] The pull-down node includes: a first pull-down node and a second pull-down node; the input control circuit is connected to the first pull-down node, and the output control circuit is connected to the second pull-up node; the shift register unit further includes:

[0032] The second intermediate control circuit is connected to the first clock terminal, the first pull-down node, and the second pull-down node respectively, and is used to control the on / off state of the first pull-down node and the second pull-down node in response to the first clock signal.

[0033] Optionally, the first intermediate control circuit includes a seventh transistor; the second intermediate control circuit includes an eighth transistor.

[0034] Furthermore, the gate of the seventh transistor is connected to the fifth power supply terminal, the first terminal of the seventh transistor is connected to the first pull-up node, and the second terminal of the seventh transistor is connected to the second pull-up node;

[0035] The gate of the eighth transistor is connected to the first clock terminal, the first terminal of the eighth transistor is connected to the first pull-down node, and the second terminal of the eighth transistor is connected to the second pull-down node.

[0036] Optionally, the shift register unit further includes:

[0037] A reset control circuit is connected to a reset control terminal, a reset power supply terminal, and the second pull-down node, respectively, and is used to control the on / off state of the reset power supply terminal and the second pull-up node in response to a reset control signal provided by the reset control terminal; wherein the reset power supply terminal is shared with the second power supply terminal.

[0038] Optionally, the reset control circuit includes: a ninth transistor;

[0039] The gate of the ninth transistor is connected to the reset control terminal, the first terminal of the ninth transistor is connected to the reset power supply terminal, and the second terminal of the ninth transistor is connected to the second pull-down node.

[0040] Optionally, the output control circuit includes: a tenth transistor, a second capacitor, an eleventh transistor, and a third capacitor;

[0041] Furthermore, the gate of the tenth transistor is connected to the pull-up node, the first terminal of the tenth transistor is connected to the second clock terminal, and the second terminal of the tenth transistor is connected to the output signal terminal;

[0042] One end of the second capacitor is connected to the pull-up node, and the other end of the second capacitor is connected to the output signal terminal;

[0043] The gate of the eleventh transistor is connected to the pull-down node, the first terminal of the eleventh transistor is connected to the third power supply terminal, and the second terminal of the eleventh transistor is connected to the output signal terminal.

[0044] One end of the third capacitor is connected to the pull-down node, and the other end of the third capacitor is connected to the third power supply terminal.

[0045] Optionally, the eleventh transistor includes two third sub-transistors connected in series with their first and second terminals; the shift register unit further includes:

[0046] The second leakage protection circuit is connected to the output signal terminal, the sixth power supply terminal, and the series node of the two third sub-transistors, respectively, and is used to control the on / off state of the sixth power supply terminal and the connected series node in response to the signal output through the output signal terminal.

[0047] Optionally, the second leakage protection circuit includes: a twelfth transistor;

[0048] The gate of the twelfth transistor is connected to the output signal terminal, the first terminal of the twelfth transistor is connected to the sixth power supply terminal, and the second terminal of the twelfth transistor is connected to the series node of the two third sub-transistors.

[0049] Optionally, the output signal terminal includes: a shift output signal terminal and a drive output signal terminal, wherein the shift output signal terminal is used to connect with other cascaded shift register units, and the drive output signal terminal is used to connect with pixels in the display panel; furthermore, the output control circuit is also connected to a seventh power supply terminal and a second target terminal, wherein the second target terminal is an eighth power supply terminal or a third clock terminal; the output control circuit includes:

[0050] The first output control sub-circuit is connected to the pull-up node, the pull-down node, the third power supply terminal, the second target terminal, and the shift output signal terminal, respectively, and is used to control the on / off state of the second target terminal and the shift output signal terminal in response to the potential of the pull-up node, and to control the on / off state of the third power supply terminal and the shift output signal terminal in response to the potential of the pull-down node.

[0051] The second output control sub-circuit is connected to the pull-up node, the pull-down node, the second clock terminal, the seventh power supply terminal, and the drive output signal terminal, respectively. It is used to control the on / off state of the second clock terminal and the drive output signal terminal in response to the potential of the pull-up node, and to control the on / off state of the seventh power supply terminal and the drive output signal terminal in response to the potential of the pull-down node.

[0052] Optionally, the potential of the seventh power signal provided by the seventh power terminal is less than or equal to the potential of the third power signal provided by the third power terminal.

[0053] Optionally, the first output control sub-circuit includes: a tenth transistor, a second capacitor, an eleventh transistor, and a third capacitor; the second output control sub-circuit includes: a twelfth transistor and a thirteenth transistor;

[0054] Furthermore, the gate of the tenth transistor is connected to the pull-up node, the first terminal of the tenth transistor is connected to the second target terminal, and the second terminal of the tenth transistor is connected to the shift output signal terminal;

[0055] One end of the second capacitor is connected to the pull-up node, and the other end of the second capacitor is connected to the shift output signal terminal;

[0056] The gate of the eleventh transistor is connected to the pull-down node, the first terminal of the eleventh transistor is connected to the third power supply terminal, and the second terminal of the eleventh transistor is connected to the shift output signal terminal.

[0057] One end of the third capacitor is connected to the pull-down node, and the other end of the third capacitor is connected to the third power supply terminal.

[0058] The gate of the twelfth transistor is connected to the pull-up node, the first terminal of the twelfth transistor is connected to the second clock terminal, and the second terminal of the twelfth transistor is connected to the drive output signal terminal.

[0059] The gate of the thirteenth transistor is connected to the pull-down node, the first terminal of the thirteenth transistor is connected to the seventh power supply terminal, and the second terminal of the thirteenth transistor is connected to the drive output signal terminal.

[0060] Optionally, the first output control sub-circuit includes: a tenth transistor, a second capacitor, an eleventh transistor, and a third capacitor; the second output control sub-circuit includes: a twelfth transistor and a thirteenth transistor; and the second target terminal is the third clock terminal;

[0061] The gate of the tenth transistor is connected to the pull-up node, the first terminal of the tenth transistor is connected to the third clock terminal, and the second terminal of the tenth transistor is connected to the shift output signal terminal.

[0062] One end of the second capacitor is connected to the pull-up node, and the other end of the second capacitor is connected to the shift output signal terminal;

[0063] The gate of the eleventh transistor is connected to the pull-down node, the first terminal of the eleventh transistor is connected to the third power supply terminal, and the second terminal of the eleventh transistor is connected to the shift output signal terminal.

[0064] One end of the third capacitor is connected to the pull-down node, and the other end of the third capacitor is connected to the third power supply terminal.

[0065] The gate of the twelfth transistor is connected to the pull-up node, the first terminal of the twelfth transistor is connected to the second clock terminal, and the second terminal of the twelfth transistor is connected to the drive output signal terminal.

[0066] The gate of the thirteenth transistor is connected to the pull-down node, the first terminal of the thirteenth transistor is connected to the seventh power supply terminal, and the second terminal of the thirteenth transistor is connected to the drive output signal terminal.

[0067] Optionally, the first clock terminal, the second clock terminal, and the third clock terminal are independent of each other;

[0068] Furthermore, the second clock signal provided by the second clock terminal is a different group of clock signals from the first clock terminal, and the second clock signal provided by the second clock terminal is a different group of clock signals from the third clock terminal.

[0069] Optionally, the potential of the second clock signal provided by the second clock terminal is located between the potential of the seventh power signal provided by the seventh power terminal and the potential of the reference power signal;

[0070] Wherein, the potential of the reference power signal is greater than or equal to the potential of the eighth power signal provided by the eighth power terminal, and the potential of the eighth power signal provided by the eighth power terminal is greater than the potential of the seventh power signal provided by the seventh power terminal.

[0071] Optionally, within one clock cycle, the duration for which the third clock signal provided by the third clock terminal is at an effective potential includes the duration for which the second clock signal provided by the second clock terminal is at an effective potential.

[0072] On the other hand, a method for driving a shift register unit is provided, for driving the shift register unit as described in the above aspect; the method includes:

[0073] In the first stage, the input control circuit responds to the input signal provided by the input signal terminal, the first clock signal provided by the first clock terminal, the first power signal provided by the first power supply terminal, and the first target signal provided by the first target terminal, by controlling the input signal terminal to be connected to the pull-up node, controlling the first target terminal to be disconnected from the pull-down node, and controlling the first power supply terminal to be connected to the pull-down node. The output control circuit responds to the potential of the pull-up node by controlling the second clock terminal to be connected to the output signal terminal, and responds to the potential of the pull-down node by controlling the third power supply terminal to be disconnected from the output signal terminal.

[0074] In the second stage, the input control circuit responds to the input signal, the first clock signal, the first power signal, and the first target signal by controlling the input signal terminal to be connected to the pull-up node, controlling the first target terminal to be connected to the pull-down node, and controlling the first power terminal to be disconnected from the pull-down node. The output control circuit responds to the potential of the pull-up node by controlling the second clock terminal to be disconnected from the output signal terminal, and responds to the potential of the pull-down node by controlling the third power terminal to be connected to the output signal terminal.

[0075] In another aspect, a gate driving circuit is provided, the gate driving circuit comprising: cascaded multiple shift register units as described in the above aspect.

[0076] In another aspect, a display device is provided, the display device comprising: a display panel, and a gate driving circuit as described in yet another aspect above; the display panel comprising a plurality of pixels;

[0077] The gate driving circuit is connected to the plurality of pixels via an output signal terminal and is used to transmit gate driving signals to the plurality of pixels to drive the plurality of pixels to emit light. Attached Figure Description

[0078] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0079] Figure 1 is a schematic diagram of the structure of a shift register unit provided in an embodiment of this application;

[0080] Figure 2 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0081] Figure 3 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0082] Figure 4 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0083] Figure 5 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0084] Figure 6 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0085] Figure 7 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0086] Figure 8 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0087] Figure 9 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0088] Figure 10 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0089] Figure 11 is a schematic diagram of the structure of a shift register control module in a shift register unit provided in an embodiment of this application;

[0090] Figure 12 is a schematic diagram of the shift register control module in another shift register unit provided in an embodiment of this application;

[0091] Figure 13 is a schematic diagram of the shift register control module in another shift register unit provided in an embodiment of this application;

[0092] Figure 14 is a schematic diagram of the shift register control module in another shift register unit provided in an embodiment of this application;

[0093] Figure 15 is a schematic diagram of the shift register control module in another shift register unit provided in an embodiment of this application;

[0094] Figure 16 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0095] Figure 17 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0096] Figure 18 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0097] Figure 19 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0098] Figure 20 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0099] Figure 21 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0100] Figure 22 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0101] Figure 23 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0102] Figure 24 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0103] Figure 25 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0104] Figure 26 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0105] Figure 27 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0106] Figure 28 is a flowchart illustrating a method for driving a shift register unit according to an embodiment of this application;

[0107] Figure 29 is a schematic diagram of the driving timing of a shift register unit provided in an embodiment of this application;

[0108] Figure 30 is a schematic diagram of the driving timing of another shift register unit provided in an embodiment of this application;

[0109] Figure 31 is a schematic diagram of a gate driving circuit provided in an embodiment of this application;

[0110] Figure 32 is a schematic diagram of another gate driving circuit provided in an embodiment of this application;

[0111] Figure 33 is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0112] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0113] It should be noted that the transistors used in the embodiments of this application can be thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. An example of a FET is a metal-oxide-semiconductor (MOS) FET, also known as a MOS transistor. Furthermore, based on their function in the circuit, the transistors used in the embodiments of this application are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their sources and drains are interchangeable. In the embodiments of this application, the source can be referred to as the first electrode, and the drain as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is the control electrode, also known as the gate; the signal input terminal is the source, and the signal output terminal is the drain. In addition, the switching transistors used in the embodiments of this application can include either P-type transistors or N-type transistors. A P-type transistor conducts when the gate is at a low potential and is cut off when the gate is at a high potential; an N-type transistor conducts when the gate is at a high potential and is cut off when the gate is at a low potential. Furthermore, multiple signals in the various embodiments of this application correspond to a first potential and a second potential. The first potential can refer to an effective potential, and the second potential can refer to an ineffective potential. Furthermore, the first potential and the second potential only represent that the potential of the signal has two state variables, and do not mean that the first potential or the second potential has a specific value throughout the text.

[0114] In the display field, especially in organic light-emitting diode (OLED) displays, backplanes have gradually transitioned from amorphous silicon (a-Si) to oxide and then to low-temperature polycrystalline oxide (LTPO). All-oxygen TFT backplanes will also be a future technological route for display development. Here, "material" refers to the material of the transistors in the backplane, and the example transistor is the one included in a GOA (Glass On-Area) circuit.

[0115] Specifically, the threshold voltage (Vth) of transistors fabricated from oxide materials is generally between 0.4 volts (V) and 1 V. Under long-term bias temperature stress (BTS) operating conditions, especially negative bias stress (NBTS), Vth may become negatively biased. When Vth is less than or equal to 0, the transistor exhibits leakage current under off-state conditions, causing the GOA circuit, which includes the transistor, to fail to reliably output the required signal to the pixel. For example, the signal output by the GOA circuit is prone to step-like patterns. Consequently, the GOA circuit cannot reliably drive the pixel to emit light, affecting the yield of the display panel and resulting in poor display quality. Here, the signal output by the GOA circuit can be the gate drive signal (GATE) pointing to the data write transistor output in the pixel circuit.

[0116] Based on this, this application proposes a stepless and leakage-proof oxide TFT GATE GOA circuit (i.e., a GOA circuit capable of outputting a gate drive signal GATE and whose transistors are oxide TFT transistors) based on an all-oxide TFT architecture to improve the yield and display effect of the display panel. The GOA circuit includes multiple cascaded GOA units. Of course, in some other embodiments, it is not limited to an all-oxide TFT architecture, nor is it limited to outputting a gate drive signal GATE.

[0117] Figure 1 is a schematic diagram of a shift register unit (i.e., a GOA unit) provided in an embodiment of this application. As shown in Figure 1, the shift register unit includes an input control circuit 01 and an output control circuit 02.

[0118] The input control circuit 01 is connected to the input signal terminal IN, the first clock terminal CK1, the first power supply terminal V1, the first target terminal Vo1, the pull-up node Q, and the pull-down node QB, respectively. Furthermore, the input control circuit 01 is used to control the on / off state of the input signal terminal IN and the pull-up node Q, the on / off state of the first target terminal Vo1 and the pull-down node QB, and the on / off state of the first power supply terminal V1 and the pull-down node QB, respectively, in response to the input signal provided by the input signal terminal IN, the first clock signal provided by the first clock terminal CK1, the first power supply signal provided by the first power supply terminal V1, and the first target signal provided by the first target terminal Vo1.

[0119] Wherein, the first target terminal Vo1 is the second power supply terminal V2 or shared with the first clock terminal CK1. That is, the first target terminal Vo1 can be a separate second power supply terminal V2, and correspondingly, the first target signal can be the second power supply signal provided by the second power supply terminal V2; or, the first target terminal Vo1 can be the first clock terminal CK1, and correspondingly, the first target signal can be the first clock signal provided by the first clock terminal CK1.

[0120] Optionally, the first clock signal provided by the first clock terminal CK1 can be a periodic pulse signal. The potential of the first power supply signal provided by the first power supply terminal V1 can be a low potential, and the potential of the second power supply signal provided by the second power supply terminal V2 can be a high potential. Correspondingly, the first power supply terminal V1 can also be referred to as the pull-down power supply terminal VGL, and the second power supply terminal V2 can also be referred to as the pull-up power supply terminal VGH. Furthermore, each transistor described in the following embodiments can be an N-type transistor, and correspondingly, the first potential (i.e., the effective potential) can be a high potential, and the second potential (i.e., the ineffective potential) can be a low potential. Here, high potential and low potential are relative.

[0121] For example, referring to Figure 1, the first target terminal Vo1 is shown as the second power supply terminal V2. Based on this, the input control circuit 01 can control the input signal terminal IN to be connected to the pull-up node Q when the potential of the input signal provided by the input signal terminal IN is a first potential (e.g., high potential) and the potential of the first clock signal provided by the first clock terminal CK1 is high potential. It can also control the second power supply terminal V2, as the first target terminal Vo1, to be disconnected from the pull-down node QB, and control the first power supply terminal V1 to be connected to the pull-down node QB. This allows the high-potential input signal provided by the input signal terminal IN to be transmitted to the pull-up node Q, and allows the low-potential first power signal provided by the first power supply terminal V1 to be transmitted to the pull-down node QB. The input control circuit 01 can control the input signal terminal IN to conduct with the pull-up node Q when the potential of the input signal provided by the input signal terminal IN is a second potential (e.g., low potential) and the potential of the first clock signal provided by the first clock terminal CK1 is a high potential. It also controls the second power supply terminal V2 to conduct with the pull-down node QB as the first target terminal Vo1, and controls the first power supply terminal V1 to disconnect from the pull-down node QB. This allows the low-potential input signal provided by the input signal terminal IN to be transmitted to the pull-up node Q, and allows the high-potential second power supply signal provided by the second power supply terminal V2 to be transmitted to the pull-down node QB. Accordingly, the input control circuit 01 can also be called a control circuit. Of course, this is only an illustrative description of part of the control method of the input control circuit 01.

[0122] The output control circuit 02 is connected to the pull-up node Q, the pull-down node QB, the second clock terminal CK2, the third power supply terminal V3, and the output signal terminal OUT. Furthermore, the output control circuit 02 controls the switching between the second clock terminal CK2 and the output signal terminal OUT in response to the potential of the pull-up node Q, and controls the switching between the third power supply terminal V3 and the output signal terminal OUT in response to the potential of the pull-down node QB.

[0123] Optionally, the second clock signal provided by the second clock terminal CK2 can also be a periodic pulse signal. The potential of the third power supply signal provided by the third power supply terminal V3 can be a low potential. Correspondingly, the third power supply terminal V3 can also be called the pull-down power supply terminal VGL. Furthermore, the third power supply terminal V3 and the first power supply terminal V1 can be shared or can be independent of each other. That is, the power supply terminal connected to the input control circuit 01 can be the power supply terminal connected to the output control circuit 02, or it can be an additional power supply terminal. In other words, the power supply terminal connected to the input control circuit 01 and the power supply terminal connected to the output control circuit 02 can be the same power supply terminal; or the power supply terminal connected to the input control circuit 01 and the power supply terminal connected to the output control circuit 02 can be different power supply terminals.

[0124] The shared power supply terminal simplifies wiring, saving costs and facilitating narrow bezel designs. Wiring here refers to laying out the power lines connected to the power supply terminal on the display panel, providing the necessary power signals. Other terminals can similarly be connected to signal lines that provide the required signals. For example, the first clock terminal CK1 can be connected to a clock signal line to receive the first clock signal provided by the clock signal line. Setting each power supply terminal independently ensures that the power signals received by the input control circuit 01 and the output control circuit 02 do not interfere with each other, thus ensuring the reliable operation of both the input control circuit 01 and the output control circuit 02, enabling the shift register unit to reliably output signals to the output signal terminal OUT. The effects of sharing or separating other power supplies as described in the following embodiments are similar and will not be elaborated upon individually.

[0125] For example, the output control circuit 02 can control the second clock terminal CK2 to conduct with the output signal terminal OUT when the potential of the pull-up node Q is at a first potential (e.g., high potential), so that the second clock signal provided by the second clock terminal CK2 can be transmitted to the output signal terminal OUT; and it can control the second clock terminal CK2 to disconnect from the output signal terminal OUT when the potential of the pull-up node Q is at a second potential (e.g., low potential). Similarly, the output control circuit 02 can control the third power supply terminal V3 to conduct with the output signal terminal OUT when the potential of the pull-down node QB is at a first potential (e.g., high potential), so that the low-potential third power supply signal provided by the third power supply terminal V3 can be transmitted to the output signal terminal OUT; and it can control the third power supply terminal V3 to disconnect from the output signal terminal OUT when the potential of the pull-down node QB is at a second potential (e.g., low potential). In this way, the output control circuit 02 can output signals with high and low potentials through the output signal terminal OUT, and make the signals output through the output signal terminal OUT match the pulses of the second clock signal.

[0126] Optionally, the output signal terminal OUT can be connected to a pixel. Correspondingly, the signal output from the OUT terminal can be transmitted to the pixel as a gate drive signal to drive the pixel to emit light. Furthermore, the OUT terminal can also be connected to the input signal terminal IN of other cascaded shift register units to transmit the required input signals to the IN terminals of those other shift register units. Of course, the IN terminal of the first-stage shift register unit can be connected to an additional enable signal line STV to receive the start signal provided by the enable signal line STV.

[0127] Based on the above description, the input control circuit 01 provided in this application embodiment can transmit signals to the pull-up node Q and pull-down node QB under the control of the signals provided by the connected signal terminals, thereby controlling the potential of the pull-up node Q and the potential of the pull-down node QB. The output control circuit 02 can transmit high-potential and low-potential signals to the output signal terminal OUT under the control of the potential of the pull-up node Q and the potential of the pull-down node QB. In this way, signal output of the shift register unit can be realized. Furthermore, the sign of the pulse of the input signal provided by the input signal terminal IN can determine the sign of the pulse of the signal output by the shift register unit through the output signal terminal OUT.

[0128] In summary, this application provides a shift register unit. This shift register unit includes an input control circuit and an output control circuit. Since the input control circuit can reliably and flexibly control the potentials of the pull-up and pull-down nodes under the control of various received signals, the output control circuit can reliably output high or low potential signals to the output signal terminal under the control of the pull-up and pull-down nodes. Therefore, this shift register unit can reliably output gate drive signals to the pixels via the output signal terminal, thereby reliably driving the pixels to emit light, resulting in better display performance of the display panel.

[0129] Optionally, Figure 2 is a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 2, the input control circuit 01 may include: a first input control sub-circuit 011, a second input control sub-circuit 012, and a third input control sub-circuit 013.

[0130] The first input control sub-circuit 011 can be connected to the first clock terminal CK1, the input signal terminal IN, and the pull-up node Q, respectively. Furthermore, the first input control sub-circuit 011 can be used to control the on / off state of the input signal terminal IN and the pull-up node Q in response to the first clock signal. That is, the first input control sub-circuit 011 can be used to control the potential of the pull-up node Q.

[0131] For example, the first input control sub-circuit 011 can control the input signal terminal IN to be connected to the pull-up node Q when the potential of the first clock signal is a first potential (e.g., high potential), so that the input signal provided by the input signal terminal IN can be transmitted to the pull-up node Q; and can control the input signal terminal IN to be disconnected from the pull-up node Q when the potential of the first clock signal is a second potential (e.g., low potential).

[0132] The second input control sub-circuit 012 can be connected to the input signal terminal IN, the first power supply terminal V1, the first clock terminal CK1, the control signal terminal Con, the intermediate node Q0, and the pull-down node QB, respectively. Furthermore, the second input control sub-circuit 012 can control the potential of the intermediate node Q0 in response to the input signal, the first power supply signal, and the first clock signal, and control the on / off state of the first power supply terminal V1 and the pull-down node QB in response to the control signal provided by the control signal terminal Con.

[0133] The control signal terminal Con can be shared with the input signal terminal IN or connected to the pull-up node Q. That is, the control signal terminal Con can be the input signal terminal IN, and correspondingly, the control signal provided by the control signal terminal Con can be the input signal provided by the input signal terminal IN. Alternatively, the control signal terminal Con can be connected to the pull-up node Q, and correspondingly, the control signal provided by the control signal terminal Con can be the signal transmitted to the pull-up node Q. In other words, the second input control sub-circuit 012 can be used to control the potentials of the intermediate node Q0 and the pull-down node QB.

[0134] For example, the second input control sub-circuit 012 can control the potential of intermediate node Q0 to be low in response to the high-potential input signal, the low-potential first power supply signal, and the low-potential first clock signal when the potential of the input signal is a first potential (e.g., high potential) and the potential of the first clock signal is a second potential (e.g., low potential); and can control the potential of intermediate node Q0 to be high in response to the low-potential input signal, the low-potential first power supply signal, and the high-potential first clock signal when the potential of the input signal is a second potential (e.g., low potential) and the potential of the first clock signal is a first potential (e.g., high potential).

[0135] For example, the control signal terminal Con shown in Figure 2 can be the input signal terminal IN. Correspondingly, the control signal provided by the control signal terminal Con is the input signal provided by the input signal terminal IN. Based on this, the second input control sub-circuit 012 can also control the first power supply terminal V1 to conduct with the pull-down node QB when the potential of the input signal (i.e., the control signal) provided by the input signal terminal IN is a first potential (e.g., a high potential), so that the low-potential first power signal provided by the first power supply terminal V1 can be transmitted to the pull-down node QB; and can control the first power supply terminal V1 to disconnect from the pull-down node QB when the potential of the input signal (i.e., the control signal) provided by the input signal terminal IN is a second potential (e.g., a low potential).

[0136] The third input control sub-circuit 013 can be connected to the intermediate node Q0, the first target terminal Vo1 (i.e., the first clock terminal CK1 or the second power supply terminal V2), and the pull-down node QB, respectively. Furthermore, the third input control sub-circuit 013 can be used to control the on / off state of the first target terminal Vo1 and the pull-down node QB in response to the potential of the intermediate node Q0. That is, the third input control sub-circuit 013 can also be used to control the potential of the pull-down node QB.

[0137] For example, the first target terminal Vo1 shown in Figure 2 is the second power supply terminal V2. Based on this, the third input control sub-circuit 013 can control the second power supply terminal V2 as the first target terminal Vo1 to be connected to the pull-down node QB when the potential of the intermediate node Q0 is the first potential (e.g., high potential), so that the high potential second power signal provided by the second power supply terminal V2 can be transmitted to the pull-down node QB; and can control the second power supply terminal V2 as the first target terminal Vo1 to be disconnected from the pull-down node QB when the potential of the intermediate node Q0 is the second potential (e.g., low potential).

[0138] Optionally, Figure 3 is a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 3, the second input control sub-circuit 012 may include: a first input control unit 0121 and a second input control unit 0122.

[0139] The first input control unit 0121 can be connected to the input signal terminal IN, the first power supply terminal V1, the first clock terminal CK1, and the intermediate node Q0, respectively. Furthermore, the first input control unit 0121 can be used to control the on / off state of the first power supply terminal V1 and the intermediate node Q0 in response to the input signal, and to control the potential of the intermediate node Q0 in response to the first clock signal; alternatively, the first input control unit 0121 can be used to control the on / off state of the first power supply terminal V1 and the intermediate node Q0 in response to both the input signal and the first clock signal. In other words, the first input control unit 0121 can be used to control the potential of the intermediate node Q0 through at least two control methods.

[0140] For example, in the first control method: the first input control unit 0121 can control the first power supply terminal V1 to conduct with the intermediate node Q0 when the potential of the input signal is a first potential (e.g., high potential), so that the low-potential first power signal provided by the first power supply terminal V1 can be transmitted to the intermediate node Q0; and can control the first power supply terminal V1 to disconnect from the intermediate node Q0 when the potential of the input signal is a second potential (e.g., low potential). Furthermore, the first input control unit 0121 can control the potential of the intermediate node Q0 to be high when the potential of the first clock signal is a first potential (e.g., high potential); and can control the potential of the intermediate node Q0 to be low when the potential of the first clock signal is a second potential (e.g., low potential).

[0141] For example, in the second control method: the first input control unit 0121 can control the first power supply terminal V1 to conduct with the intermediate node Q0 when the potential of the input signal and the potential of the first clock signal are both at the first potential (e.g., high potential), so that the low potential first power signal provided by the first power supply terminal V1 can be transmitted to the intermediate node Q0; and can control the first power supply terminal V1 to disconnect from the intermediate node Q0 when the potential of the input signal and / or the potential of the first clock signal are at the second potential (e.g., low potential).

[0142] The second input control unit 0122 can be connected to the control signal terminal Con (i.e., the input signal terminal IN or connected to the pull-up node Q), the first power supply terminal V1, and the pull-down node QB, respectively. Furthermore, the second input control unit 0122 can be used to control the on / off state of the first power supply terminal V1 and the pull-down node QB in response to the control signal. That is, the second input control unit 0122 can be used to control the potential of the pull-down node QB.

[0143] For example, the control signal terminal Con shown in Figure 3 is also the input signal terminal IN. Accordingly, the control signal provided by the control signal terminal Con is the input signal provided by the input signal terminal IN. Based on this, the second input control unit 0122 can control the first power supply terminal V1 to conduct with the pull-down node QB when the potential of the input signal (i.e., the control signal) provided by the input signal terminal IN is a first potential (e.g., a high potential), so that the low-potential first power signal provided by the first power supply terminal V1 can be transmitted to the pull-down node QB; and can control the first power supply terminal V1 to disconnect from the pull-down node QB when the potential of the input signal (i.e., the control signal) provided by the input signal terminal IN is a second potential (e.g., a low potential).

[0144] Optionally, the first input control unit 0121 controls the switching between the first power supply terminal V1 and the intermediate node Q0 in response to the input signal, and controls the potential of the intermediate node Q0 in response to the first clock signal. That is, based on the first control method described above, as shown in Figure 4, in an implementation corresponding to the first control method:

[0145] The first input control unit 0121 may include a first transistor T1 and a first capacitor C1. The gate of the first transistor T1 may be connected to the input signal terminal IN, the first terminal of the first transistor T1 may be connected to the first power supply terminal V1, and the second terminal of the first transistor T1 may be connected to the intermediate node Q0. One end of the first capacitor C1 may be connected to the first clock terminal CK1, and the other end of the first capacitor C1 may be connected to the intermediate node Q0.

[0146] Optionally, when the first input control unit 0121 controls the switching between the first power supply terminal V1 and the intermediate node Q0 in response to the input signal and the first clock signal, that is, based on the second control method described above, as shown in Figure 5, in another implementation corresponding to the second control method:

[0147] The first input control unit 0121 may include a first transistor T1 and a second transistor T2. The gate of the first transistor T1 may be connected to the input signal terminal IN, the first terminal of the first transistor T1 may be connected to the first power supply terminal V1, the second terminal of the first transistor T1 may be connected to the first terminal of the second transistor T2, the gate of the second transistor T2 may be connected to the first clock terminal CK1, and the second terminal of the second transistor T2 may be connected to the intermediate node Q0.

[0148] Optionally, referring further to Figures 4 and 5, the second input control unit 0122 may include a third transistor T3. Furthermore, the gate of the third transistor T3 may be connected to the control signal terminal Con, the first terminal of the third transistor T3 may be connected to the first power supply terminal V1, and the second terminal of the third transistor T3 may be connected to the pull-down node QB. For example, the control signal terminal Con shown in Figures 4 and 5 is the input signal terminal IN.

[0149] Optionally, referring to Figures 4 and 5, the first transistor T1 may include two first sub-transistors T11 and T12 connected in series with their first and second terminals. The third transistor T3 may include two second sub-transistors T31 and T32 connected in series with their first and second terminals. That is, the first transistor T1 and the third transistor T3 can be transistors with a dual-gate structure or a dual-TFT series architecture.

[0150] In this configuration, the gates of both first sub-transistors T11 and T12 can be connected to the input signal terminal IN. The first terminal of the first sub-transistor T11 can be connected to the first power supply terminal V1, and the second terminal of the first sub-transistor T11 can be connected to the first terminal of the first sub-transistor T12. The second terminal of the first sub-transistor T12 can be connected to the intermediate node Q0 or the first terminal of the second transistor T2. Similarly, the gates of both second sub-transistors T31 and T32 can be connected to the control signal terminal Con (e.g., the input signal terminal IN). The first terminal of the second sub-transistor T31 can be connected to the first power supply terminal V1, and the second terminal of the second sub-transistor T31 can be connected to the first terminal of the second sub-transistor T32. The second terminal of the second sub-transistor T32 can be connected to the pull-down node QB.

[0151] Furthermore, based on this, referring to Figures 4 and 5, it can be seen that the shift register unit may also include: a first leakage protection circuit 03.

[0152] The first leakage protection circuit 03 can be connected to the intermediate node Q0, the fourth power supply terminal V4, the series connection node P1 of the two first sub-transistors T11 and T12, and the series connection node P2 of the two second sub-transistors T31 and T32, respectively. Furthermore, the first leakage protection circuit 03 can be used to control the switching on and off of the fourth power supply terminal V4 with the connected series connection nodes (i.e., P1 & P2) in response to the potential of the intermediate node Q0. Based on this connection, it can also be seen that the series connection node P1 of the two first sub-transistors T11 and T12 and the series connection node P2 of the two second sub-transistors T31 and T32 are also interconnected. That is, the first leakage protection circuit 03 can be used to control the potential of the series connection nodes P1 & P2.

[0153] Optionally, the potential of the fourth power signal provided by the fourth power terminal V4 can be a high potential. Correspondingly, the fourth power terminal V4 can also be referred to as the pull-up power terminal VGH. Furthermore, the fourth power terminal V4 can be independent of other power terminals (e.g., the second power terminal V2). That is, the fourth power terminal V4 can be a separate power terminal, which can be connected to a separate power line. Alternatively, the fourth power terminal V4 can be set as GVGH (i.e., Global VGH). Of course, in some other embodiments, the fourth power terminal V4 can also be shared with other power terminals (e.g., the second power terminal V2).

[0154] As is understandable, VGH typically refers to the high-voltage source used to drive the display panel, primarily for controlling the panel's on / off state and brightness. GVGH, on the other hand, can refer to an additional, independent voltage source distinct from VGH, usually powered by a separate voltage source.

[0155] For example, the first leakage protection circuit 03 can control the fourth power supply terminal V4 to conduct with the series nodes P1 & P2 when the potential of the intermediate node Q0 is a first potential (e.g., high potential), so that the high potential fourth power signal provided by the fourth power supply terminal V4 can be transmitted to the series nodes P1 & P2; and can control the fourth power supply terminal V4 to disconnect from the series nodes P1 & P2 when the potential of the intermediate node Q0 is a second potential (e.g., low potential).

[0156] It is understandable that, taking the first transistor T1 as an example, by setting this transistor as a dual-gate structure, the leakage problem that exists during the turn-on process can be effectively reduced, ensuring that the potential of the intermediate node Q0 can be reliably controlled by this transistor, thereby ensuring that the shift register unit can reliably output a signal to the output signal terminal OUT. The leakage problem is usually caused by the input signal received by the gate of the first transistor T1 having a rising edge transitioning from a low potential to a high potential and a falling edge transitioning from a high potential to a low potential, resulting in a potential conflict with the intermediate node Q0. Setting the third transistor T3 as a dual-gate structure transistor has the same effect, ensuring that the potential of the pull-down node QB can be reliably controlled by this transistor, which will not be elaborated further here. Of course, in some other embodiments, the first transistor T1 and / or the third transistor T3 can also be single-gate structure transistors like the second transistor T2.

[0157] Furthermore, by configuring both the first transistor T1 and the third transistor T3 as dual-gate transistors, the shift register unit also includes a first leakage protection circuit 03 to perform the aforementioned functions. This circuit prevents the first power supply terminal V1 from mistakenly connecting with the intermediate node Q1 and the pull-down node QB when the potential of the signal received at the gate changes abruptly or becomes unstable, thus preventing the low-potential first power supply signal from leaking to the intermediate node Q1 and the pull-down node QB. In other words, it further enhances the leakage protection capability, ensuring better potential stability of the intermediate node Q1 and the pull-down node QB, thereby further ensuring that the shift register unit can reliably output a signal to the output signal terminal OUT.

[0158] Furthermore, as mentioned earlier, by setting the fourth power terminal V4 to be independent of the other power terminals, interference between the power signals provided by the power terminals can be avoided, thus preventing leakage current from occurring and improving leakage current protection. Conversely, by sharing the fourth power terminal V4 with the other power terminals, wiring can be simplified, saving costs and facilitating narrow bezel designs.

[0159] Optionally, based on Figure 4, Figure 6 shows a schematic diagram of another shift register unit provided in an embodiment of this application. Referring to Figure 6, it can be seen that the first leakage protection circuit 03 may include: a fourth transistor T4.

[0160] Furthermore, the gate of the fourth transistor T4 can be connected to the intermediate node Q0, the first terminal of the fourth transistor T4 can be connected to the fourth power supply terminal V4, and the second terminal of the fourth transistor T4 can be connected to the series node P1 of the two first sub-transistors T11 and T12 and the series node P2 of the two second sub-transistors T31 and T32.

[0161] Optionally, the fourth transistor T4 can be a single-gate structure or a dual-gate structure. Setting the fourth transistor T4 to a dual-gate structure can further improve leakage current protection.

[0162] Optionally, referring to Figures 4 through 6, the first input control sub-circuit 011 may include a fifth transistor T5. The third input control sub-circuit 013 may include a sixth transistor T6.

[0163] Furthermore, the gate of the fifth transistor T5 can be connected to the first clock terminal CK1, the first terminal of the fifth transistor T5 can be connected to the input signal terminal IN, and the second terminal of the fifth transistor T5 can be connected to the pull-up node Q.

[0164] The gate of the sixth transistor T6 can be connected to the intermediate node Q0, the first terminal of the sixth transistor T6 can be connected to the first target terminal Vo1, and the second terminal of the sixth transistor T6 can be connected to the pull-down node QB. For example, the first target terminal Vo1 shown in Figures 4 to 6 is the second power supply terminal V2.

[0165] Optionally, based on Figure 6, Figure 7 shows a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 7, the pull-up node Q may include: a first pull-up node Q1 and a second pull-up node Q2. The input control circuit 01 may be connected to the first pull-up node Q1, and the output control circuit 02 may be connected to the second pull-up node Q2. That is, the input control circuit 01 can control the potential of the first pull-up node Q1; while the output control circuit 02 can output a signal to the output signal terminal OUT under the control of the potential of the second pull-up node Q2.

[0166] Based on this, referring to Figure 7, it can also be seen that the shift register unit may include: a first intermediate control circuit 04.

[0167] The first intermediate control circuit 04 can be connected to the fifth power supply terminal V5, the first pull-up node Q1, and the second pull-up node Q2, respectively. Furthermore, the first intermediate control circuit 04 can be used to control the on / off state of the first pull-up node Q1 and the second pull-up node Q2 in response to the fifth power supply signal provided by the fifth power supply terminal V5.

[0168] Optionally, the potential of the fifth power signal provided by the fifth power supply terminal V5 can be a high potential; correspondingly, the fifth power supply terminal V5 can also be called the pull-up power supply terminal VGH. Furthermore, the fifth power supply terminal V5 and the second power supply terminal V2 can be shared or can be independent of each other. That is, the power supply terminal connected to the first intermediate control circuit 04 can be the power supply terminal connected to the input control circuit 01, or it can be an additional power supply terminal.

[0169] For example, the first intermediate control circuit 04 can control the first pull-up node Q1 and the second pull-up node Q2 to be turned on under the control of the high-potential fifth power supply signal, so that the signal transmitted to the first pull-up node Q1 can be further transmitted to the second pull-up node Q2.

[0170] It is understandable that by dividing the pull-up node Q into two pull-up nodes and setting the first intermediate control circuit 04 to perform the above function, the first pull-up node Q1 and the second pull-up node Q2 can be isolated, avoiding the problem of voltage backflow from the output control circuit 02 causing the potential of the first pull-up node Q1 to be unstable. This also protects the transistor (e.g., the fifth transistor T5) that controls the potential of the first pull-up node Q1, thereby ensuring better output stability of the shift register unit.

[0171] And / or,

[0172] Referring to Figure 7, similar to the pull-up node Q, the pull-down node QB can also include: a first pull-down node QB1 and a second pull-down node QB2. The input control circuit 01 can be connected to the first pull-down node QB1, and the output control circuit 02 can be connected to the second pull-down node QB2. That is, the input control circuit 01 can control the potential of the first pull-down node QB1; while the output control circuit 02, under the control of the potential of the second pull-down node QB2, can output a signal to the output signal terminal OUT.

[0173] Based on this, referring to Figure 7, it can also be seen that the shift register unit may include: a second intermediate control circuit 05.

[0174] The second intermediate control circuit 05 can be connected to the first clock terminal CK1, the first pull-down node QB1, and the second pull-down node QB2, respectively. Furthermore, the second intermediate control circuit 05 can be used to control the on / off state of the first pull-down node QB1 and the second pull-down node QB2 in response to the first clock signal.

[0175] For example, the second intermediate control circuit 05 can control the first pull-down node QB1 and the second pull-down node QB2 to be turned on when the potential of the first clock signal is a first potential (e.g., high potential), so that the signal transmitted to the first pull-down node QB1 can be further transmitted to the second pull-down node QB2; and can control the first pull-down node QB1 and the second pull-down node QB2 to be disconnected when the potential of the first clock signal is a second potential (e.g., low potential).

[0176] It is understandable that by dividing the pull-down node QB into two pull-down nodes and setting the second intermediate control circuit 05 to perform the above function, the purpose of isolating the first pull-down node QB1 and the second pull-down node QB2 can be achieved, thereby ensuring better output stability of the shift register unit.

[0177] Optionally, based on Figure 7, Figure 8 shows a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 8, the first intermediate control circuit 04 may include a seventh transistor T7. The second intermediate control circuit 05 may include an eighth transistor T8.

[0178] Furthermore, the gate of the seventh transistor T7 can be connected to the fifth power supply terminal V5, the first terminal of the seventh transistor T7 can be connected to the first pull-up node Q1, and the second terminal of the seventh transistor T7 can be connected to the second pull-up node Q2.

[0179] The gate of the eighth transistor T8 can be connected to the first clock terminal CK1, the first terminal of the eighth transistor T8 can be connected to the first pull-down node QB1, and the second terminal of the eighth transistor T8 can be connected to the second pull-down node QB2.

[0180] Optionally, based on Figure 8, Figure 9 shows a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 9, the shift register unit may further include a reset control circuit 06.

[0181] The reset control circuit 06 can be connected to the reset control terminal TRST, the reset power supply terminal Vrst, and the second pull-down node QB2, respectively. The reset control circuit 06 can be used to control the on / off state of the reset power supply terminal Vrst and the second pull-down node QB2 in response to the reset control signal provided by the reset control terminal TRST. That is, the reset control circuit 06 can be used to control the potential of the second pull-down node QB2.

[0182] The reset power supply terminal Vrst can be shared with either the second power supply terminal V2 or the third power supply terminal V3. That is, the reset power supply terminal Vrst can be the second power supply terminal V2 (i.e., the pull-up power supply terminal VGH) or the third power supply terminal V3 (i.e., the pull-down power supply terminal VGL).

[0183] For example, referring to Figure 9, the reset power supply terminal Vrst is shared with the second power supply terminal V2. Based on this, the reset control circuit 06 can control the second power supply terminal V2 to conduct with the second pull-down node QB2 when the reset control signal provided by the reset control terminal TRST is at a first potential (e.g., a high potential), allowing the high-potential second power signal provided by the second power supply terminal V2 to be transmitted to the second pull-down node QB2; and can control the second power supply terminal V2 to disconnect from the second pull-down node QB2 when the reset control signal provided by the reset control terminal TRST is at a second potential (e.g., a low potential).

[0184] It is understandable that by sharing the reset power supply terminal Vrst with the second power supply terminal V2, and by transmitting a high-level second power supply signal to the second pull-down node QB2 under the control of the reset control signal, it can be ensured that the transistor connected to the second pull-down node QB2 in the output control circuit 02 can be fully turned on. This allows for a reliable output of a low-level third power supply signal to the output signal terminal OUT under the control of the potential of the second pull-down node QB2. Similarly, by sharing the reset power supply terminal Vrst with the third power supply terminal V3, and by transmitting a low-level third power supply signal to the second pull-down node QB2 under the control of the reset control signal, it can be ensured that the transistor connected to the second pull-down node QB2 in the output control circuit 02 can be fully turned off. This avoids the erroneous output of the third power supply signal when it is not necessary to output a low-level third power supply signal to the output signal terminal OUT. In summary, by configuring this reset control circuit 06, the output stability and reliability of the shift register unit can be ensured to be good. The general reset control circuit 06 is mostly used to control the reset power supply terminal Vrst to conduct with the second pull-down node QB2 at the moment of power-on, so as to realize the initialization reset of the second pull-down node QB2.

[0185] Of course, in some other embodiments, the reset control circuit 06 can also be connected to the first pull-up node Q1 and / or the second pull-up node Q2 to control the on / off state of the reset power supply terminal Vrst and the connected pull-up node in response to the reset control signal provided by the reset control terminal TRST. This allows the output control circuit 02 to reliably output a second clock signal to the output signal terminal OUT under the control of the second pull-up node Q2, thereby further improving the output stability and reliability of the shift register unit.

[0186] Optionally, based on Figure 9, Figure 10 shows a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 10, the reset control circuit 06 may include: a ninth transistor T9.

[0187] The gate of the ninth transistor T9 can be connected to the reset control terminal TRST, the first terminal of the ninth transistor T9 can be connected to the reset power supply terminal Vrst (e.g., the second power supply terminal V2), and the second terminal of the ninth transistor T9 can be connected to the second pull-down node QB2.

[0188] Optionally, in the embodiments of this application, the part including the input control circuit 01, the first leakage protection circuit 03, and the second intermediate control circuit 05 can be referred to as the leakage protection shift register control module. Referring to the above embodiments, Figures 11 to 15 respectively show five types of shift register control modules: a, b, c, d, and e.

[0189] For example, referring to structure a in Figure 11, the shift register control module includes a first transistor T1, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, an eighth transistor T8, and a first capacitor C1. The first transistor T1 and the third transistor T3 are dual-gate transistors. Furthermore, as described above, the first transistor T1, the first capacitor C1, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 belong to the input control circuit 01, the fourth transistor T4 belongs to the first leakage protection circuit 03, and the eighth transistor T8 belongs to the second intermediate control circuit 05. The first target terminal Vo1 connected to this shift register control module is the second power supply terminal V2, and the connected control signal terminal Con is the input signal terminal IN.

[0190] For example, referring to structure b shown in Figure 12, the shift register control module includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and an eighth transistor T8. The first transistor T1 and the third transistor T3 are dual-gate transistors. Furthermore, as previously described, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 belong to the input control circuit 01, the fourth transistor T4 belongs to the first leakage protection circuit 03, and the eighth transistor T8 belongs to the second intermediate control circuit 05. The first target terminal Vo1 connected to this shift register control module is the second power supply terminal V2, and the connected control signal terminal Con is the input signal terminal IN. Comparing Figures 12 and 11, it can be seen that structure b, compared to structure a, mainly replaces the first capacitor C1 with the second transistor T2.

[0191] For example, referring to structure c shown in Figure 13, the shift register control module includes a first transistor T1, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, an eighth transistor T8, and a first capacitor C1. The first transistor T1 and the third transistor T3 are dual-gate transistors. Furthermore, as previously described, the first transistor T1, the first capacitor C1, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 belong to the input control circuit 01, the fourth transistor T4 belongs to the first leakage protection circuit 03, and the eighth transistor T8 belongs to the second intermediate control circuit 05. The first target terminal Vo1 connected to this shift register control module is the first clock terminal CK1, and the connected control signal terminal Con is the input signal terminal IN. Comparing Figures 13 and 11, it can be seen that structure c, compared to structure a, mainly replaces the second power supply terminal V2 with the first clock terminal CK1 for the first target terminal Vo1.

[0192] For example, referring to structure d shown in Figure 14, the shift register control module includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and an eighth transistor T8. The first transistor T1 and the third transistor T3 are dual-gate transistors. Furthermore, as previously described, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 belong to the input control circuit 01, the fourth transistor T4 belongs to the first leakage protection circuit 03, and the eighth transistor T8 belongs to the second intermediate control circuit 05. The first target terminal Vo1 connected to this shift register control module is the first clock terminal CK1, and the connected control signal terminal Con is the input signal terminal IN. Comparing Figures 14 and 13, it can be seen that structure d, compared to structure c, mainly replaces the first capacitor C1 with the second transistor T2.

[0193] For example, referring to structure e shown in Figure 15, the shift register control module includes a first transistor T1, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a first capacitor C1. The first transistor T1 and the third transistor T3 are dual-gate transistors. Furthermore, as previously described, the first transistor T1, the first capacitor C1, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 belong to the input control circuit 01, and the fourth transistor T4 belongs to the first leakage protection circuit 03. The first target terminal Vo1 connected to this shift register control module is the second power supply terminal V2, and the connected control signal terminal Con is the first pull-up node Q1. Comparing Figures 15 and 11, it can be seen that structure e, compared to structure a, mainly omits the second intermediate control circuit 05 and replaces the control signal terminal Con with the first pull-up node Q1 instead of the input signal terminal IN.

[0194] Of course, it is understood that the structures shown in Figures 11 to 15 are merely schematic representations of multiple shift register control modules, and the implementation of the shift register control modules is not limited to these. For example, as can be seen from Figures 11 to 15, in some embodiments, the first transistor T1 and / or the third transistor T3 can be single-gate transistors; correspondingly, the first leakage protection circuit 03 can be omitted, i.e., the fourth transistor T4 can be omitted. In other embodiments, the first capacitor C1 and the first transistor T1 can be omitted; correspondingly, the first leakage protection circuit 03 can be omitted, i.e., the fourth transistor T4 can be omitted. Based on this, the first target terminal Vo1 can be the second power supply terminal V2. In yet another embodiment, based on the above-described alternative embodiment, the sixth transistor T6 can also be a dual-gate transistor. In some embodiments, in addition to including the third transistor T3, two transistors connected in series between the first pull-up node Q1 and the first power supply terminal V1 may be included, and the gates of these two transistors may be connected to another clock terminal and the second pull-down node QB1, respectively; or, two transistors connected in series between the second pull-down node QB1 and the first power supply terminal V1 may be included, and the gates of these two transistors may be connected to another clock terminal and the first pull-up node Q1, respectively. The above are all illustrative and do not limit the implementation methods described in the embodiments of this application.

[0195] Optionally, the various shift register control modules described in the above embodiments are shown as modules. From the perspective of the output control circuit 02, Figures 16 to 21 respectively show schematic diagrams of the structures of various shift register units provided in the embodiments of this application. First, referring to Figures 16 to 21 and the foregoing description, it can be seen that the shift register control module can be connected to at least the first clock terminal CK1, the input signal terminal IN, the first pull-up node Q1, and the second pull-down node QB2. Furthermore, a seventh transistor T7 can be included between the shift register control module and the output control circuit 02 to isolate the first pull-up node Q1 and the second pull-up node Q2.

[0196] Furthermore, as can be seen from Figure 16, the output control circuit 02 may include: the tenth transistor T10, the second capacitor C2, the eleventh transistor T11, and the third capacitor C3.

[0197] Furthermore, the gate of the tenth transistor T10 can be connected to the pull-up node Q, the first terminal of the tenth transistor T10 can be connected to the second clock terminal CK2, and the second terminal of the tenth transistor T10 can be connected to the output signal terminal OUT.

[0198] One end of the second capacitor C2 can be connected to the pull-up node Q, and the other end of the second capacitor C2 can be connected to the output signal terminal OUT.

[0199] The gate of the eleventh transistor T11 can be connected to the pull-down node QB, the first terminal of the eleventh transistor T11 can be connected to the third power supply terminal V3, and the second terminal of the eleventh transistor T11 can be connected to the output signal terminal OUT.

[0200] One end of the third capacitor C3 can be connected to the pull-down node QB, and the other end of the third capacitor C3 can be connected to the third power supply terminal V3.

[0201] Understandably, as mentioned earlier, based on dividing the pull-up node Q into the first pull-up node Q1 and the second pull-up node Q2, the gate of the tenth transistor T10 and one end of the second capacitor C2 can be connected to the second pull-up node Q2. Similarly, based on dividing the pull-down node QB into the first pull-down node QB1 and the second pull-down node QB2, the gate of the eleventh transistor T11 and one end of the third capacitor C3 can be connected to the second pull-down node QB2.

[0202] Optionally, referring to Figure 17, in some embodiments, the eleventh transistor T11 may include two third sub-transistors T111 and T112 connected in series with the first and second terminals. That is, like the first transistor T1 and the third transistor T3, the eleventh transistor T11 may also be a transistor with a dual-gate structure.

[0203] Among them, the gates of the two third sub-transistors T111 and T112 can both be connected to the pull-down node QB (e.g., the second pull-down node QB2), the first terminal of the third sub-transistor T111 can be connected to the third power supply terminal V3, the second terminal of the third sub-transistor T111 can be connected to the first terminal of the third sub-transistor T112, and the second terminal of the third sub-transistor T112 can be connected to the output signal terminal OUT.

[0204] Furthermore, based on this, referring to Figure 17, it can be seen that the shift register unit may also include: a second leakage protection circuit 07.

[0205] The second leakage protection circuit 07 can be connected to the output signal terminal OUT, the sixth power supply terminal V6, and the series connection node P3 of the two third sub-transistors T111 and T112, respectively. Furthermore, this second leakage protection circuit 07 can be used to control the switching on and off of the sixth power supply terminal V6 and the connected series connection node P3 in response to a signal output through the output signal terminal OUT. That is, the second leakage protection circuit 07 can be used to control the potential of the series connection node P3.

[0206] Optionally, like the fourth power supply terminal V4, the sixth power supply terminal V6 can provide a high potential for the sixth power signal. Correspondingly, the sixth power supply terminal V6 can also be referred to as the pull-up power supply terminal VGH. Furthermore, like the fourth power supply terminal V4, the sixth power supply terminal V6 can be independent of other power supply terminals (e.g., the second power supply terminal V2). That is, the sixth power supply terminal V6 can be a separate power supply terminal, which can be connected to a separate power line. Alternatively, the sixth power supply terminal V6 can be set as GVGH. Based on this, in some embodiments, the sixth power supply terminal V6 can be shared with the fourth power supply terminal V4. Of course, in some other embodiments, the sixth power supply terminal V6 can also be shared with other power supply terminals (e.g., the second power supply terminal V2).

[0207] For example, the second leakage protection circuit 07 can control the sixth power supply terminal V6 to conduct with the series node P3 when the signal output through the output signal terminal OUT is at the first potential (e.g., high potential), so that the high potential sixth power signal provided by the sixth power supply terminal V6 can be transmitted to the series node P3; and can control the sixth power supply terminal V6 to disconnect from the series node P3 when the potential of the signal output through the output signal terminal OUT is at the second potential (e.g., low potential).

[0208] It is understandable that, similar to the first transistor T1, setting the eleventh transistor T11 as a dual-gate transistor can also achieve the purpose of preventing leakage current, ensuring that a low-potential third power supply signal is reliably output to the output signal terminal OUT through the eleventh transistor T11. Furthermore, by setting the eleventh transistor T11 as a dual-gate transistor and adding a second leakage current prevention circuit 07 to perform the above function in the shift register unit, the leakage current prevention capability can be further improved. Of course, in some other embodiments, the eleventh transistor T11 can also be a single-gate transistor.

[0209] Furthermore, by making the sixth power terminal V6 independent of the other power terminals, similar to the fourth power terminal V4, interference between the power signals provided by the power terminals can be avoided, thus improving the leakage protection capability. Sharing the sixth power terminal V6 with the other power terminals simplifies wiring, saves costs, and facilitates narrow bezel designs.

[0210] Optionally, in some embodiments, among the two third sub-transistors T111 and T112 included in the eleventh transistor T11, the channel width-to-length ratio of the transistor directly connected to the output signal terminal OUT (e.g., the third sub-transistor T111) can be greater than the channel width-to-length ratio of the transistor not directly connected to the output signal terminal OUT (e.g., the third sub-transistor T112). This ensures that the eleventh transistor T11 has good output drive capability.

[0211] Optionally, in some embodiments, the tenth transistor T10, which connects the pull-up node Q and the output signal terminal OUT, can also be designed as a dual-gate structure, just like the eleventh transistor T11. Furthermore, the second leakage protection circuit 07 can be connected to the series node of the dual-gate structure of the tenth transistor T10 to achieve the same purpose.

[0212] Optionally, based on Figure 17, and continuing to refer to Figure 18, it can be seen that the second leakage protection circuit 07 may include: the twelfth transistor T12.

[0213] The gate of the twelfth transistor T12 can be connected to the output signal terminal OUT, the first terminal of the twelfth transistor T12 can be connected to the sixth power supply terminal V6, and the second terminal of the twelfth transistor T12 can be connected to the series node P3 of the two third sub-transistors T111 and T112.

[0214] Optionally, referring to Figure 19, in some embodiments, the output signal terminal OUT may include a shift output signal terminal CR1 and a drive output signal terminal OUT1. The shift output signal terminal CR1 can be used to connect to other cascaded shift register units, and the drive output signal terminal OUT1 can be used to connect to pixels in the display panel. Furthermore, as described above, the shift output signal terminal CR1 can be connected to the input signal terminal IN of other cascaded shift register units. That is, the output signal terminal OUT can be divided into two output signal terminals to output signals to other shift register units to drive them to work, thus achieving cascaded driving; and to output signals to pixels to drive them to emit light, thus achieving light emission driving. In this way, compared to simultaneously outputting signals to other shift register units and pixels through the same output signal terminal OUT, cascaded driving and light emission driving can be made independent of each other, ensuring better cascade functionality and reliable pixel light emission driving.

[0215] Furthermore, the output control circuit 02 can also be connected to the seventh power supply terminal V7 and the second target terminal Vo2, which can be the eighth power supply terminal V8 or the third clock terminal CK3.

[0216] Optionally, the third clock terminal CK3 can also be a periodic pulse signal, the seventh power supply terminal V7 can be at a low potential, and the eighth power supply terminal V8 can be at a high potential. Correspondingly, the seventh power supply terminal V7 can also be called a pull-down power supply terminal VGL, and the eighth power supply terminal V8 can also be called a pull-up power supply terminal VGH. Furthermore, the seventh power supply terminal V7 and the third power supply terminal V3 can be shared or independent of each other. The eighth power supply terminal V8 and the second power supply terminal V2 can also be shared or independent of each other.

[0217] Furthermore, referring to Figure 19, it can be seen that the output control circuit 02 may include: a first output control sub-circuit 021 and a second output control sub-circuit 022.

[0218] The first output control sub-circuit 021 can be connected to the pull-up node Q, the pull-down node QB, the third power supply terminal V3, the second target terminal Vo2, and the shift output signal terminal CR1, respectively. Furthermore, this first output control sub-circuit 021 can control the switching between the second target terminal Vo2 and the shift output signal terminal CR1 in response to the potential of the pull-up node Q, and control the switching between the third power supply terminal V3 and the shift output signal terminal CR1 in response to the potential of the pull-down node QB. That is, the first output control sub-circuit 021 can output the required input signal to the input signal terminal IN of other shift register units via the shift output signal terminal CR1.

[0219] For example, the first output control sub-circuit 021 can control the third clock terminal CK3 or the eighth power supply terminal V8, which serves as the second target terminal Vo2, to be connected to the shift output signal terminal CR1 when the potential of the pull-up node Q is a first potential (e.g., high potential), so that the third clock signal provided by the third clock terminal CK3 can be transmitted to the shift output signal terminal CR1, or the high-potential eighth power supply signal provided by the eighth power supply terminal V8 can be transmitted to the shift output signal terminal CR1; and can control the third clock terminal CK3 or the eighth power supply terminal V8, which serves as the second target terminal Vo2, to be disconnected from the shift output signal terminal CR1 when the potential of the pull-up node Q is a second potential (e.g., low potential). Similarly, the first output control sub-circuit 021 can control the third power supply terminal V3 to conduct with the shift output signal terminal CR1 when the potential of the pull-down node QB is the first potential (e.g., high potential), so that the low potential third power supply signal provided by the third power supply terminal V3 can be transmitted to the shift output signal terminal CR1; and can control the third power supply terminal V3 to disconnect from the shift output signal terminal CR1 when the potential of the pull-down node QB is the second potential (e.g., low potential).

[0220] The second output control sub-circuit 022 can be connected to the pull-up node Q, the pull-down node QB, the second clock terminal CK2, the seventh power supply terminal V7, and the drive output signal terminal OUT1, respectively. Furthermore, this second output control sub-circuit 022 can control the switching between the second clock terminal CK2 and the drive output signal terminal OUT1 in response to the potential of the pull-up node Q, and control the switching between the seventh power supply terminal V7 and the drive output signal terminal OUT1 in response to the potential of the pull-down node QB. That is, the second output control sub-circuit 022 can output the required gate drive signal to the pixel via the drive output signal terminal OUT1.

[0221] For example, the second output control sub-circuit 022 can control the second clock terminal CK2 to conduct with the drive output signal terminal OUT1 when the potential of the pull-up node Q is a first potential (e.g., high potential), so that the second clock signal provided by the second clock terminal CK2 can be transmitted to the drive output signal terminal OUT1; and can control the second clock terminal CK2 to disconnect from the drive output signal terminal OUT1 when the potential of the pull-up node Q is a second potential (e.g., low potential). Similarly, the second output control sub-circuit 022 can control the seventh power supply terminal V7 to conduct with the drive output signal terminal OUT1 when the potential of the pull-down node QB is a first potential (e.g., high potential), so that the low-potential seventh power supply signal provided by the seventh power supply terminal V7 can be transmitted to the drive output signal terminal OUT1; and can control the seventh power supply terminal V7 to disconnect from the drive output signal terminal OUT1 when the potential of the pull-down node QB is a second potential (e.g., low potential).

[0222] It is understandable that, based on dividing the pull-up node Q into a first pull-up node Q1 and a second pull-up node Q2, and dividing the pull-down node QB into a first pull-down node QB1 and a second pull-down node QB2, as shown in Figure 19 and as described above, both the first output control sub-circuit 021 and the second output control sub-circuit 022 can be connected to the second pull-up node Q2 and the second pull-down node QB2. Of course, in some other embodiments, the second output control sub-circuit 022 can also be connected to the first pull-down node QB1.

[0223] Optionally, in some other embodiments, based on dividing the output control circuit 02 into a first output control sub-circuit 021 and a second output control sub-circuit 022, the second pull-down node QB2 can be further divided into two pull-down nodes (e.g., pull-down node 1 and pull-down node 2). Furthermore, another transistor connected to the seventh transistor T7 is positioned between pull-down node 1 and pull-down node 2 to isolate them. Simultaneously, the first output control sub-circuit 021 is connected to pull-down node 1, and the second output control sub-circuit 022 is connected to pull-down node 2, enabling the first output control sub-circuit 021 and the second output control sub-circuit 022 to independently output signals under the control of different pull-down nodes, thereby improving output flexibility and reliability.

[0224] Optionally, based on Figure 19, Figure 20 shows a schematic diagram of another shift register unit, taking the second target terminal Vo2 as the third clock terminal CK3 as an example; and Figure 21 shows a schematic diagram of another shift register unit, taking the second target terminal Vo2 as the eighth power supply terminal V8 as an example.

[0225] Referring to Figures 20 and 21, it can be seen that the first output control sub-circuit 021 may include: the tenth transistor T10, the second capacitor C2, the eleventh transistor T11, and the third capacitor C3. The second output control sub-circuit 022 may include: the twelfth transistor T12 and the thirteenth transistor T13.

[0226] Furthermore, the gate of the tenth transistor T10 can be connected to the pull-up node Q, the first terminal of the tenth transistor T10 can be connected to the second target terminal Vo2, and the second terminal of the tenth transistor T10 can be connected to the shift output signal terminal CR1. In Figure 20, the second target terminal Vo2 is the third clock terminal CK3. In Figure 21, the second target terminal Vo2 is the eighth power supply terminal V8.

[0227] One end of the second capacitor C2 can be connected to the pull-up node Q, and the other end of the second capacitor C2 can be connected to the shift output signal terminal CR1.

[0228] The gate of the eleventh transistor T11 can be connected to the pull-down node QB, the first terminal of the eleventh transistor T11 can be connected to the third power supply terminal V3, and the second terminal of the eleventh transistor T11 can be connected to the shift output signal terminal CR1.

[0229] One end of the third capacitor C3 can be connected to the pull-down node QB, and the other end of the third capacitor C3 can be connected to the third power supply terminal V3.

[0230] The gate of the twelfth transistor T12 can be connected to the pull-up node Q, the first terminal of the twelfth transistor T12 can be connected to the second clock terminal CK2, and the second terminal of the twelfth transistor T12 can be connected to the drive output signal terminal OUT1.

[0231] The gate of the thirteenth transistor T13 can be connected to the pull-down node QB, the first terminal of the thirteenth transistor T13 can be connected to the seventh power supply terminal V7, and the second terminal of the thirteenth transistor T13 can be connected to the drive output signal terminal OUT1.

[0232] The second capacitor C2 can raise the potential of the pull-up node Q through bootstrapping, ensuring that the tenth transistor T10 and the twelfth transistor T12 can be fully turned on, avoiding a step between the signals output by the tenth transistor T10 and the twelfth transistor T12. The effect of the third capacitor C3 is similar and will not be described further. Based on this, in some embodiments, a capacitor can also be connected in series between the drive output signal terminal OUT1 and the second pull-down node QB2 to achieve the same effect.

[0233] It is understandable that, based on dividing the pull-up node Q into the first pull-up node Q1 and the second pull-up node Q2, and dividing the pull-down node QB into the first pull-down node QB1 and the second pull-down node QB2, as shown in Figure 21 and as described above, the gate of the tenth transistor T10, the gate of the twelfth transistor T12, and one end of the second capacitor C2 can all be connected to the second pull-up node Q2; the gate of the eleventh transistor T11, the gate of the thirteenth transistor T13, and one end of the third capacitor C3 can all be connected to the second pull-down node QB2.

[0234] Optionally, in this embodiment, the seventh power supply terminal V7 and the third power supply terminal V3 can be independent of each other. For distinction, in Figures 20 and 21, the third power supply terminal V3 and the seventh power supply terminal V7, which are both pull-down power supply terminals VGL, are labeled as VGL1 and VGL2, respectively. Based on this structure, the output control circuit 02 can also be considered to adopt a dual VGL design. In this way, the second output control sub-circuit 022 can independently transmit the required signal to the pixel via the drive output signal terminal OUT1, improving the ability to drive the pixel to emit light, reducing leakage current, and thus ensuring reliable pixel emission.

[0235] Furthermore, based on the dual VGL design, the low potential of the seventh power signal provided by the seventh power terminal V7 (i.e., VGL2) can be lower than the low potential of the third power signal provided by the third power terminal V3 (i.e., VGL1). In this embodiment, the potential relationship refers to the absolute value of the potentials. For example, the low potential of the power signal provided by VGL2 can differ from the low potential of the power signal provided by VGL1 by approximately 2V. In some embodiments, the low potential of the power signal provided by VGL2 can be between -5V and -10V, and the low potential of the power signal provided by VGL1 can be between -7V and -12V. For example, the low potential of the power signal provided by VGL2 can be -8V, and the low potential of the power signal provided by VGL1 can be -10V. This also ensures that when the potential of the pull-down node QB (e.g., the second pull-down node QB2) is at the low potential Vgl1 of the power supply signal provided by VGL1, the gate-source voltage difference Vgs of the thirteenth transistor T13 is much smaller than the threshold voltage Vth of the thirteenth transistor T13, ensuring that the thirteenth transistor T13 is fully turned off and ensuring a reliable output signal to the drive output signal terminal OUT1. The gate-source voltage difference Vgs of the thirteenth transistor T13 satisfies: Vgs = Vgl2 - Vgl1, where Vgl2 refers to the potential of the power supply signal provided by VGL2.

[0236] Alternatively, for the structure shown in Figure 20:

[0237] On the one hand, the first clock terminal CK1, the second clock terminal CK2, and the third clock terminal CK3 can operate independently of each other. Furthermore, the second clock signal provided by the second clock terminal CK2 is from a different group than the first clock signal provided by the first clock terminal CK1, and the second clock signal provided by the second clock terminal CK2 is from a different group than the third clock signal provided by the third clock terminal CK3. That is, the second clock terminal CK2 can be from a different group than the first clock terminal CK1 and the third clock terminal CK3, and the clock signals it provides may not be from the same group.

[0238] On the other hand, the potential of the second clock signal provided by the second clock terminal CK2 can be located between the potential of the seventh power signal provided by the seventh power supply terminal V7 and the potential of the reference power signal. Specifically, the potential of the reference power signal can be greater than or equal to the potential of the eighth power signal provided by the eighth power supply terminal V8, and the potential of the eighth power signal provided by the eighth power supply terminal V8 can be greater than the potential of the seventh power signal provided by the seventh power supply terminal V7. For example, the seventh power supply terminal V7 can be VGL2, and the potential of the seventh power signal provided by the seventh power supply terminal V7 can be Vgl2; the eighth power supply terminal V8 can be VGH, and the potential of the eighth power signal provided by the eighth power supply terminal V8 can be Vgh; the potential of the reference power signal can be Vgh2, which is different from the potential of the power signal provided by another pull-up power supply terminal VGH2 of the eighth power supply terminal V8 (which is also a pull-up power supply terminal VGH), and Vgh2 can be greater than or equal to Vgh. That is, in this application embodiment, a dual VGL design can also be used, along with a dual VGH design. Thus, by setting the potential variation range of the second clock signal provided by the second clock terminal CK2 to be between Vgh2 and Vgl2, it can be further ensured that the output of the output control circuit 02 will not be affected by the negative bias of the threshold voltage of the transistor therein.

[0239] On the other hand, within one clock cycle, the duration for which the third clock signal provided by the third clock terminal CK3 is at an effective potential can include the duration for which the second clock signal provided by the second clock terminal CK2 is at an effective potential. As described above, the effective potential can be used to control the transistor to turn on, and in this embodiment, the effective potential can be, for example, a high potential. This avoids the second clock signal provided by the second clock terminal CK2 being mistakenly transmitted to the drive output terminal OUT1 via the twelfth transistor T12 before the potential of the third clock signal provided by the third clock terminal CK3 changes from low to high, allowing the second capacitor C2 to sufficiently pull up the potential of the second pull-up node Q2 through its bootstrap function. That is, it ensures that the required gate drive signal is reliably output to the pixel via the drive output terminal OUT1, thereby reliably driving the pixel to emit light. Furthermore, the high-potential pulse width of the second clock signal provided by the second clock terminal CK2 can range from 0 to the signal cycle period of the first clock signal provided by the first clock terminal CK1 / the third clock signal provided by the third clock terminal CK3, to ensure the periodic and reliable output of the second clock signal to the pixel.

[0240] Furthermore, within the same time period, the potentials of the first clock signal provided by the first clock terminal CK1 and the third clock signal provided by the third clock segment CK3 will not be high simultaneously. This avoids the possibility of the potentials of the second pull-up node Q2 and the second pull-down node QB2 being pulled high at the same time, which could lead to output abnormalities. This further ensures that the shift register unit reliably outputs signals via the shift output signal terminal CR1 and the drive output terminal OUT1.

[0241] Optionally, the above embodiments are merely illustrative of various possible implementations of the output control circuit 02, and do not limit its implementation. For example, referring to Figures 16 to 21 and the foregoing description, in some embodiments, the tenth transistor T10 can also be configured as a dual-gate structure. In other embodiments, another capacitor can be connected in series between the thirteenth transistor T13 and the second pull-down node QB2.

[0242] Optionally, taking the shift register control module of structure a shown in Figure 11 as an example, and referring to Figure 9, as well as Figures 16 to 21, and Figures 22 to 26, we can illustrate the structural schematic diagrams of the shift register unit under various implementation methods. Taking the shift register control module of structure e shown in Figure 15 as an example, and referring to Figure 16, Figure 27 schematically illustrates the structural schematic diagram of the shift register unit under one implementation method. Furthermore, Figures 22 to 27 schematically indicate the design of the pull-up power supply terminal VGH and the pull-down power supply terminal VGL.

[0243] Optionally, the power signals provided by the pull-up power supply terminal VGH and the pull-down power supply terminal VGL described in this application embodiment can be fixed-potential power signals or dynamically adjustable power signals. During use, a separate control chip can flexibly adjust these signals based on the display screen, ensuring good display flexibility and achieving a good display effect.

[0244] As described above, the key transistor for preventing leakage current mentioned in the embodiments of this application includes: the fourth transistor T4 shown in Figure 22 and the twelfth transistor T12 shown in Figure 24. This key transistor can be a single transistor, i.e., a single-gate structure; or it can be a dual-gate structure transistor. The pull-up power supply terminal VGH connected to this key transistor can be connected to a separate power line, distinguishing it from the power lines connected to other pull-up power supply terminals VGH, or it can be set as GVGH separately. Furthermore, it is understood that each transistor described in the embodiments of this application can be a single-gate structure or a dual-gate structure.

[0245] Optionally, the dual-gate structure described in this application embodiment can cover various methods such as bottom gate connected to the source, bottom gate connected to the top gate, and bottom gate connected to other signals. The bottom gate refers to a gate metal layer that is closer to the substrate than the top gate and is used to form a transistor; conversely, the top gate refers to another gate metal layer that is farther from the substrate than the bottom gate and is used to form a transistor; the source refers to one of the electrodes included in the source and drain metal layers used to form a transistor.

[0246] As described above, current oxide transistors are affected by process fluctuations and BTS (Bottom-Threshold Voltage) issues, causing the threshold voltage Vth to become negatively biased, resulting in significant leakage current. This leads to the failure of the shift register unit and unstable output. In contrast, this application's embodiment, combining a new shift register control module and a leakage-proof structure, designs a stepless and shiftable all-oxide gate GOA (Gate-Output Atomic Array), which can effectively drive the display panel and improve its display performance.

[0247] In summary, this application provides a shift register unit. This shift register unit includes an input control circuit and an output control circuit. Since the input control circuit can reliably and flexibly control the potentials of the pull-up and pull-down nodes under the control of various received signals, the output control circuit can reliably output high or low potential signals to the output signal terminal under the control of the pull-up and pull-down nodes. Therefore, this shift register unit can reliably output gate drive signals to the pixels via the output signal terminal, thereby reliably driving the pixels to emit light, resulting in better display performance of the display panel.

[0248] This application also provides a method for driving a shift register unit, used to drive the shift register unit as described in the above embodiments. As shown in FIG28, the method includes:

[0249] Step 2801, First Stage: The input control circuit responds to the input signal provided by the input signal terminal, the first clock signal provided by the first clock terminal, the first power signal provided by the first power supply terminal, and the first target signal provided by the first target terminal. It controls the input signal terminal to be connected to the pull-up node, controls the first target terminal to be disconnected from the pull-down node, and controls the first power supply terminal to be connected to the pull-down node. The output control circuit responds to the potential of the pull-up node, controls the second clock terminal to be connected to the output signal terminal, and responds to the potential of the pull-down node, controls the third power supply terminal to be disconnected from the output signal terminal.

[0250] Step 2802, Second Stage: The input control circuit responds to the input signal, the first clock signal, the first power signal, and the first target signal by controlling the input signal terminal to be connected to the pull-up node, controlling the first target terminal to be connected to the pull-down node, and controlling the first power terminal to be disconnected from the pull-down node. The output control circuit responds to the potential of the pull-up node by controlling the second clock terminal to be disconnected from the output signal terminal, and responds to the potential of the pull-down node by controlling the third power terminal to be connected to the output signal terminal.

[0251] Taking the structure shown in Figure 22 as an example, where each transistor in the shift register unit is an N-type transistor, the first potential (i.e., the effective potential) is high, the second potential (i.e., the ineffective potential) is low, the first target terminal Vo1 is the second power supply terminal V2, and the control signal terminal Con is the input signal terminal IN, the driving method of the shift register unit is explained as follows, in conjunction with the signal timing diagram shown in Figure 29:

[0252] (1) In stage T01, the input signal provided by the input signal terminal IN (e.g., the turn-on signal line STV) is at a high potential, and the first clock signal provided by the first clock terminal CK1 is at a low potential. This allows the two first sub-transistors T11 and T12 of the first transistor T1, and the two second sub-transistors T31 and T32 of the third transistor T3, to be turned on, while the fifth transistor T5 and the eighth transistor T8 are turned off. Furthermore, since the fifth power supply terminal V5 can provide a high-potential sixth power supply signal, the seventh transistor T7 can also be turned on. Consequently, the low-potential first power supply signal provided by the first power supply terminal V1 can be transmitted to the intermediate node Q0 via the two turned-on first sub-transistors T11 and T12, and to the first pull-down node QB1 via the two turned-on second sub-transistors T31 and T32. That is, in stage T01, the potential of the intermediate node Q0 and the potential of the first pull-down node QB1 can be low. Therefore, the fourth transistor T4 and the sixth transistor T6 can also be turned off. Based on this, it can be seen that the potentials of the first pull-up node Q1 and the second pull-up node Q2 can both be maintained at the low potential of the previous stage of T01, and the potential of the second pull-down node QB2 can be maintained at the high potential of the previous stage of T01. Therefore, the tenth transistor T10 can be turned off, and the eleventh transistor T11 can be turned on. Furthermore, the low-potential third power supply signal provided by the third power supply terminal V3 can be transmitted to the output signal terminal OUT via the turned-on eleventh transistor T11, and a low-potential signal (e.g., a gate drive signal) can be output via the output signal terminal OUT.

[0253] (2) In stage T02, the input signal provided by the input signal terminal IN is at a high potential, the first clock signal provided by the first clock terminal CK1 changes from a low potential to a high potential, and the second clock signal provided by the second clock terminal CK2 is at a low potential. This allows the two first sub-transistors T11 and T12 of the first transistor T1, the two second sub-transistors T31 and T32 of the third transistor T3, the fifth transistor T5, and the eighth transistor T8 to all be turned on. Furthermore, since the fifth power supply terminal V5 can provide a high-potential sixth power supply signal, the seventh transistor T7 can also be turned on. Furthermore, the low-potential first power signal provided by the first power supply terminal V1 can be transmitted to the intermediate node Q0 via the two activated first sub-transistors T11 and T12, and to the first pull-down node QB1 via the two activated second sub-transistors T31 and T32. The high-potential input signal provided by the input signal terminal IN can be transmitted to the first pull-up node Q1 via the activated fifth transistor T5. The low-potential first power signal transmitted to the first pull-down node QB1 can then be transmitted to the second pull-down node QB1 via the activated eighth transistor T8. The high-potential input signal transmitted to the first pull-up node Q1 can then be transmitted to the second pull-up node Q2 via the activated seventh transistor T7. That is, in stage T02, the potentials of the first pull-up node Q1 and the second pull-up node Q2 can become high, and the potentials of the intermediate node Q0, the first pull-down node QB1, and the second pull-down node QB2 can all become low. Therefore, the tenth transistor T10 can be turned on, while the fourth transistor T4, the sixth transistor T6, and the eleventh transistor T11 can all be turned off. Consequently, the second clock signal provided by the second clock terminal CK2 can be transmitted to the output signal terminal OUT via the turned-on tenth transistor T10. Since the second clock signal is at a low potential during stage T02, it can be seen that a low-potential signal can still be output via the output signal terminal OUT during this stage.

[0254] (3) In stage T03, the input signal provided by the input signal terminal IN is at a high potential, the first clock signal provided by the first clock terminal CK1 changes from a high potential to a low potential, and the second clock signal provided by the second clock terminal CK2 is at a low potential. This allows the two first sub-transistors T11 and T12 of the first transistor T1, and the two second sub-transistors T31 and T32 of the third transistor T3, to be turned on, while the fifth transistor T5 and the eighth transistor T8 are turned off. Furthermore, the low-potential first power signal provided by the first power terminal V1 can be transmitted to the intermediate node Q0 via the two turned-on first sub-transistors T11 and T12, and to the first pull-down node QB1 via the two turned-on second sub-transistors T31 and T32. That is, in stage T03, the potential of the intermediate node Q0 and the potential of the first pull-down node QB1 are both low potentials. Therefore, the fourth transistor T4 and the sixth transistor T6 are also turned off. Furthermore, based on this, it can be seen that due to the voltage stabilizing effect of the second capacitor C2 and the third capacitor C3, the potentials of the first pull-up node Q1 and the second pull-up node Q2 can both be maintained at the high potential of the previous stage (i.e., stage T02) before stage T03, and the potential of the second pull-down node QB2 can be maintained at the low potential of the previous stage (i.e., stage T02) before stage T03. Therefore, the tenth transistor T10 can remain on, and the fourth transistor T4, the sixth transistor T6, and the eleventh transistor T11 can remain off. Consequently, the second clock signal provided by the second clock terminal CK2 can continue to be transmitted to the output signal terminal OUT via the on tenth transistor T10. Since the potential of the second clock signal is still low in stage T03, it can be seen that a low-potential signal can continue to be output via the output signal terminal OUT during stage T03.

[0255] (4) In stage T04, the input signal provided by the input signal terminal IN is at a high potential, the first clock signal provided by the first clock terminal CK1 is at a low potential, and the second clock signal provided by the second clock terminal CK2 changes from a low potential to a high potential. This allows the two first sub-transistors T11 and T12 of the first transistor T1, and the two second sub-transistors T31 and T32 of the third transistor T3, to be turned on, while the fifth transistor T5 and the eighth transistor T8 are turned off. Furthermore, the low-potential first power signal provided by the first power terminal V1 can be transmitted to the intermediate node Q0 via the two turned-on first sub-transistors T11 and T12, and to the first pull-down node QB1 via the two turned-on second sub-transistors T31 and T32. That is, in stage T04, the potential of the intermediate node Q0 and the potential of the first pull-down node QB1 are both low potentials. Therefore, the fourth transistor T4 and the sixth transistor T6 are also turned off. Furthermore, based on this, it can be seen that the potential of the second pull-down node QB2 can be maintained at the low potential of the previous stage (i.e., stage T03) of T04, and due to the coupling effect of the second capacitor C2, the potential of the second pull-up node Q2 can be further pulled up by the potential change of the second clock signal output to the output terminal OUT. Due to the voltage limiting effect of the seventh transistor T7, the potential of the first pull-up node Q1 is pulled up by a much smaller amount than the potential of the second pull-up node Q2. Thus, the tenth transistor T10 can be fully turned on, and the fourth transistor T4, the sixth transistor T6, and the eleventh transistor T11 can all remain off. Consequently, the second clock signal provided by the second clock terminal CK2 can continue to be transmitted to the output signal terminal OUT through the turned-on tenth transistor T10. Since the potential of the second clock signal has become high in stage T04, it can be seen that a high-potential signal can be output through the output signal terminal OUT in stage T04.

[0256] (5) In stage T05, the input signal provided by the input signal terminal IN is at a low potential, and the first clock signal provided by the first clock terminal CK1 is at a low potential. This allows the two first sub-transistors T11 and T12 of the first transistor T1, the two second sub-transistors T31 and T32 of the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 to all be turned off. Based on this, it can be seen that the potentials of the intermediate node Q0, the first pull-down node QB1, and the second pull-down node QB2 can all be maintained at the low potentials of the adjacent previous stage (i.e., stage T04), and the potentials of the first pull-up node Q1 and the second pull-up node Q2 can all be maintained at the high potentials of the adjacent previous stage (i.e., stage T04). Therefore, the eleventh transistor T11 can remain on, and the tenth transistor T10 can remain off. Therefore, the second clock signal provided by the second clock terminal CK2 can continue to be transmitted to the output signal terminal OUT through the turned-on eleventh transistor T11, and the output signal terminal OUT can continuously output a signal that is consistent with the second clock signal.

[0257] (6) In stage T06, the input signal provided by the input signal terminal IN is at a low potential, and the first clock signal provided by the first clock terminal CK1 changes from a low potential to a high potential. This pulls the potential of the intermediate node Q0 high. Consequently, the two first sub-transistors T11 and T12 of the first transistor T1, and the two second sub-transistors T31 and T32 of the third transistor T3, are turned off, and the fourth transistor T4, fifth transistor T5, sixth transistor T6, and eighth transistor T8 are all turned on. Furthermore, since the fifth power supply terminal V5 can provide a high-potential fifth power supply signal, the seventh transistor T7 is also turned on. Furthermore, this not only allows the high-potential fourth power signal provided by the fourth power supply terminal V4 to be transmitted to the series nodes P1 & P2 via the activated fourth transistor T4, preventing leakage, but also allows the low-potential input signal provided by the input signal terminal IN to be transmitted to the first pull-up node Q1 via the activated fifth transistor T5. It also allows the high-potential second power signal provided by the second power supply terminal V2 (serving as the first target terminal Vo1) to be transmitted to the first pull-down node QB1 via the activated sixth transistor T6. Additionally, the low-potential input signal transmitted to the first pull-up node Q1 can be transmitted to the second pull-up node Q2 via the activated seventh transistor T7, and the high-potential second power signal transmitted to the first pull-down node QB1 can be transmitted to the second pull-down node QB2 via the activated eighth transistor T8. In other words, in stage T06, the potentials of the first pull-up node Q1 and the second pull-up node Q2 can be made low, while the potentials of the intermediate node Q0, the first pull-down node QB1, and the second pull-down node QB2 can all be made high. Therefore, the tenth transistor T10 can be turned off, and the eleventh transistor T11 can be turned on. Furthermore, the low-potential third power supply signal provided by the third power supply terminal V3 can be transmitted to the output signal terminal OUT via the turned-on eleventh transistor T11, and a low-potential signal can be output via the output signal terminal OUT.

[0258] It is understood that the operation of the shift register unit described in other embodiments is similar, and will not be repeated here.

[0259] It is also understood that the first clock input CK1 and the second clock input CK2 of each shift register unit can both be connected to the clock signal line CLK. Furthermore, in one implementation, two clock signal lines CLK1 and CLK2 can be provided for connecting cascaded multi-stage shift register units. In each shift register unit, the first clock input CK1 can be connected to one clock signal line CLK1, and the second clock input CK2 can be connected to another clock signal line CLK2. The first clock input CK1 of two adjacent shift register units can be connected to both clock signal lines CLK1 and CLK2, respectively, and the second clock input CK1 of two adjacent shift register units can also be connected to both clock signal lines CLK1 and CLK2, respectively. That is, a two-phase clock can be used to drive the operation of the multi-stage shift register units.

[0260] Figure 29 shows a timing diagram illustrating the operation of a shift register unit using a two-phase clock drive as an example. Furthermore, referring to Figure 29, it can be seen that during the same time period, the first clock signals provided by the two clock signal lines CLK1 and CLK2 are exactly opposite. Based on this, Figure 29 not only schematically shows the signal output by the current-stage shift register unit to its connected output signal terminal OUT, but also schematically shows the signal output by the next-stage shift register unit adjacent to the current-stage shift register unit to its connected output signal terminal OUT.

[0261] Of course, it is not limited to using a 2-phase clock drive. For example, in some other embodiments, a 4-phase clock can be used to drive the multi-stage shift register unit. Each adjacent 4-stage shift register unit is a group. The first clock terminal CK1 of the 4-stage shift register unit can be alternately connected to 4 different clock signal lines CLK1 to CLK4 in sequence. The first clock terminal CK2 can be alternately connected to 4 different clock signal lines CLK1 to CLK4 in sequence. The first clock terminal CK1 and the second clock terminal CK2 of each stage shift register unit can be connected to different clock signal lines (e.g., CLK1 and CLK3). Based on this, Figure 30 also schematically shows the signals output by the first stage shift register unit GOA-1 to the fourth stage shift register unit GOA-4 through their respective output signal terminals OUT when using a 4-phase clock drive. These signals are labeled as OUT[1] to OUT[4].

[0262] Optionally, referring to Figures 29 and 30, it can also be seen that under the above driving method, the shift register unit described in this application embodiment can output a gate drive signal with an effective high potential through the output terminal OUT. Thus, the shift register unit can output the required gate drive signal to the N-type transistor in the pixel. Furthermore, the shift register unit can also be called an NGATE GOA. That is, the embodiment of this application provides an all-oxide NGATE GOA. Of course, by adjusting the clock signal or adding an inverter between the output control circuit 02 and the output terminal OUT, the shift register unit can output a signal with an effective low potential through the output terminal OUT, i.e., a PGATE GOA can also be provided. This application embodiment does not limit this.

[0263] It is also understandable that, since the driving method of the shift register unit can have the same technical effect as the shift register unit described in the previous embodiments, the technical effect of the driving method of the shift register unit will not be described again here for the sake of brevity.

[0264] This application also provides a gate driving circuit. As shown in FIG31, the gate driving circuit includes: cascaded multiple shift register units as described in the foregoing embodiments, i.e., GOA units, also called GOA. The figure schematically shows 6 cascaded GOA units, labeled GOA-1 to GOA-6 respectively.

[0265] Optionally, referring to Figure 31, the output signal terminal OUT of the i-th stage GOA unit can be connected to the input signal terminal IN of the (i+L)-th stage GOA unit. Furthermore, the output signal terminal OUT of the i-th stage GOA unit can also be connected to a pixel to transmit the required input signal to the input signal terminal IN of the (i+L)-th stage GOA unit and the required gate drive signal to the pixel. Here, 1 ≤ i ≤ ML, M is the total number of GOA units, M ≥ 1, and L is a positive integer greater than or equal to 1. Of course, the input signal terminal IN of the first stage GOA unit can be connected to the enable signal line STV to receive the enable signal provided by the enable signal line STV, thereby realizing shift drive.

[0266] It is understandable that, based on dividing the output signal terminal OUT into the shift output signal terminal CR1 and the drive output signal terminal OUT1, the shift output signal terminal CR1 of the i-th level GOA unit can be connected to the input signal terminal IN of the (i+L)-th level GOA unit, and the drive output signal terminal OUT1 of the i-th level GOA unit can be connected to the pixels in the display panel.

[0267] Optionally, as can be seen from the foregoing description and Figure 31, the first clock terminal CK1 of each GOA unit can also be connected to a clock signal line. Furthermore, in one implementation, a two-phase clock can be used to drive the gate drive circuit. That is, as shown in Figure 31, two clock signal lines CLK1 and CLK2 can be provided for connecting multiple cascaded GOA units. The first clock terminal CK1 of two adjacent and cascaded GOA units can be connected to the two clock signal lines CLK1 and CLK2 respectively. The second clock terminal CK2 of two adjacent and cascaded GOA units can also be connected to the two clock signal lines CLK1 and CLK2 respectively. Additionally, the first clock terminal CK1 and the second clock terminal CK2 of each GOA unit can be connected to the two clock signal lines CLK1 and CLK2 respectively. Alternatively, in another implementation, a four-phase clock can be used to drive the gate drive circuit. That is, as shown in Figure 32, four clock signal lines CLK1 to CLK4 can be provided for connecting multiple cascaded GOA units. Furthermore, the first clock input CK1 of the 4M-3 level GOA unit can be connected to clock signal line CLK1, and the second clock input CK2 can be connected to the third clock signal line CK3; the first clock input CK1 of the 4M-2 level GOA unit can be connected to clock signal line CLK2, and the second clock input CK2 can be connected to clock signal line CLK4; the first clock input CK1 of the 4M-1 level GOA unit can be connected to clock signal line CLK3, and the second clock input CK2 can be connected to clock signal line CLK1; the first clock input CK1 of the 4M level GOA unit can be connected to clock signal line CLK4, and the second clock input CK2 can be connected to clock signal line CLK2; where M is the total number of levels of the shift register, M≥1. Of course, this is only an illustrative explanation.

[0268] It is understood that Figures 31 and 32 do not distinguish between the first clock terminal CK1 and the second clock terminal CK2, but directly use the clock terminal CK as an example to schematically illustrate the connection relationship with the clock signal line. Of course, this is not limited to the cascaded architecture of 2-phase or 4-phase clocks described above. For example, in some other embodiments, special cascaded architectures such as 6-phase or 8-phase clocks can also be covered. Furthermore, it is not limited to cascading every two adjacent GOA units. For example, in some other embodiments, odd-numbered GOA units can be cascaded, and even-numbered GOA units can be cascaded.

[0269] It is understood that since the gate drive circuit can have essentially the same technical effect as the shift register unit described in the previous embodiments, the technical effect of the gate drive circuit will not be described again here for the sake of brevity.

[0270] This application also provides a display device. As shown in FIG33, the display device includes: a display panel 100, and a gate driving circuit 000 as described in the foregoing embodiments.

[0271] The display panel 100 includes multiple pixels (not shown in the figure). The gate drive circuit 000 is connected to the multiple pixels via an output signal terminal OUT (e.g., drive output signal terminal OUT1) and is used to transmit gate drive signals to the multiple pixels to drive the multiple pixels to emit light.

[0272] Optionally, the display panel in the display device may generally include a substrate, and the substrate may have a display area and a non-display area at least partially surrounding the display area. Multiple pixels may be located in the display area, and the gate driving circuit 000 may be located in the non-display area. Furthermore, at least one pixel may include interconnected pixel circuitry and light-emitting elements, and the pixel circuitry may include at least one data writing transistor. The GOA unit in the gate driving circuit 000 can be connected to the gate of the at least one data writing transistor via its output signal terminal OUT to transmit the required gate driving signal to the gate of the at least one data writing transistor.

[0273] Optionally, the display device described in this application embodiment can be any product or component with display function, such as an organic light-emitting diode (OLED) display device, an active-matrix organic light-emitting diode (AMOLED) display device, or a liquid crystal display device. Furthermore, the display device can be any suitable display device, including but not limited to mobile phones, tablet computers, televisions, monitors, laptops, digital photo frames, navigators, and e-books, etc., any product or component with display function.

[0274] Optionally, the gate driving circuit described in this application embodiment is not limited to application in display panels, that is, it is not limited to the display field. For example, in some other embodiments, it can also be applied to other scenarios such as chips or integrated circuits.

[0275] Since the display device can have essentially the same technical effect as the gate drive circuit described in the previous embodiments, for the sake of brevity, the technical effect of the display device will not be described again here.

[0276] It should be noted that the terminology used in the embodiments of this application is for illustrative purposes only and is not intended to limit the application. Unless otherwise defined, the technical or scientific terms used in the implementation of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0277] For example, the terms "first," "second," or "third," and similar terms used in the patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0278] Similarly, words like "one" or "one" do not indicate a quantity limit, but rather that there is at least one.

[0279] The word “includes” or similar terms means that the elements or objects preceding “includes” or “include” cover the elements or objects listed after “includes” or “include” or their equivalents, and do not exclude other elements or objects.

[0280] Terms like "up," "down," "left," or "right" are used only to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly. "Connection" or "coupled" refers to an electrical connection.

[0281] The "and / or" signifies that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0282] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A shift register unit, the shift register unit comprising: An input control circuit is connected to an input signal terminal, a first clock terminal, a first power supply terminal, a first target terminal, a pull-up node, and a pull-down node, respectively. It is used to control the connection and disconnection between the input signal terminal and the pull-up node, the connection and disconnection between the first target terminal and the pull-down node, and the connection and disconnection between the first power supply terminal and the pull-down node, in response to an input signal provided by the input signal terminal, a first clock signal provided by the first clock terminal, a first power supply signal provided by the first power supply terminal, and a first target signal provided by the first target terminal. The first target terminal is either a second power supply terminal or shared with the first clock terminal. The output control circuit is connected to the pull-up node, the pull-down node, the second clock terminal, the third power supply terminal, and the output signal terminal, respectively, and is used to control the connection and disconnection of the second clock terminal and the output signal terminal in response to the potential of the pull-up node, and to control the connection and disconnection of the third power supply terminal and the output signal terminal in response to the potential of the pull-down node.

2. The shift register unit according to claim 1, wherein, The input control circuit includes: The first input control sub-circuit is connected to the first clock terminal, the input signal terminal and the pull-up node respectively, and is used to control the on / off state of the input signal terminal and the pull-up node in response to the first clock signal; The second input control sub-circuit is connected to the input signal terminal, the first power supply terminal, the first clock terminal, the control signal terminal, the intermediate node, and the pull-down node, respectively. It is used to control the potential of the intermediate node in response to the input signal, the first power supply signal, and the first clock signal, and to control the on / off state of the first power supply terminal and the pull-down node in response to the control signal provided by the control signal terminal. The control signal terminal is shared with or connected to the pull-up node. The third input control sub-circuit is connected to the intermediate node, the first target terminal, and the pull-down node respectively, and is used to control the on / off state of the first target terminal and the pull-down node in response to the potential of the intermediate node.

3. The shift register unit according to claim 2, wherein, The second input control sub-circuit includes: The first input control unit is connected to the input signal terminal, the first power supply terminal, the first clock terminal and the intermediate node respectively, and is used to control the connection and disconnection between the first power supply terminal and the intermediate node in response to the input signal, and to control the potential of the intermediate node in response to the first clock signal, or to control the connection and disconnection between the first power supply terminal and the intermediate node in response to the input signal and the first clock signal. The second input control unit is connected to the control signal terminal, the first power supply terminal, and the pull-down node respectively, and is used to control the on / off state of the first power supply terminal and the pull-down node in response to the control signal.

4. The shift register unit according to claim 3, wherein, When the first input control unit controls the switching between the first power supply terminal and the intermediate node in response to the input signal, and controls the potential of the intermediate node in response to the first clock signal, the first input control unit includes: a first transistor and a first capacitor; and the gate of the first transistor is connected to the input signal terminal, the first electrode of the first transistor is connected to the first power supply terminal, the second electrode of the first transistor is connected to the intermediate node, one end of the first capacitor is connected to the first clock terminal, and the other end of the first capacitor is connected to the intermediate node; When the first input control unit controls the connection and disconnection between the first power supply terminal and the intermediate node in response to the input signal and the first clock signal, the first input control unit includes: a first transistor and a second transistor; and the gate of the first transistor is connected to the input signal terminal, the first electrode of the first transistor is connected to the first power supply terminal, the second electrode of the first transistor is connected to the first electrode of the second transistor, the gate of the second transistor is connected to the first clock terminal, and the second electrode of the second transistor is connected to the intermediate node. The second input control unit includes a third transistor; and the gate of the third transistor is connected to the control signal terminal, the first terminal of the third transistor is connected to the first power supply terminal, and the second terminal of the third transistor is connected to the pull-down node.

5. The shift register unit according to claim 4, wherein, The first transistor includes two first sub-transistors with their first and second terminals connected in series; the third transistor includes two second sub-transistors with their first and second terminals connected in series; the shift register unit further includes: The first leakage protection circuit is connected to the intermediate node, the fourth power supply terminal, and the two first sub-crystals, respectively. The series node of the body transistor is connected to the series node of the two second sub-transistors, and is used to control the on / off state of the fourth power supply terminal and the connected series node in response to the potential of the intermediate node.

6. The shift register unit according to claim 5, wherein, The first leakage protection circuit includes: a fourth transistor; Furthermore, the gate of the fourth transistor is connected to the intermediate node, the first terminal of the fourth transistor is connected to the fourth power supply terminal, and the second terminal of the fourth transistor is connected to the series node of the two first sub-transistors and the series node of the two second sub-transistors.

7. The shift register unit according to any one of claims 2 to 6, wherein, The first input control sub-circuit includes: a fifth transistor; Furthermore, the gate of the fifth transistor is connected to the first clock terminal, the first terminal of the fifth transistor is connected to the input signal terminal, and the second terminal of the fifth transistor is connected to the pull-up node.

8. The shift register unit according to any one of claims 2 to 7, wherein, The third input control sub-circuit includes: a sixth transistor; Furthermore, the gate of the sixth transistor is connected to the intermediate node, the first electrode of the sixth transistor is connected to the first target terminal, and the second electrode of the sixth transistor is connected to the pull-down node.

9. The shift register unit according to any one of claims 1 to 8, wherein, The pull-up node includes: a first pull-up node and a second pull-up node; the input control circuit is connected to the first pull-up node, and the output control circuit is connected to the second pull-up node; the shift register unit further includes: The first intermediate control circuit is connected to the fifth power supply terminal, the first pull-up node and the second pull-up node respectively, and is used to control the on and off of the first pull-up node and the second pull-up node in response to the fifth power supply signal provided by the fifth power supply terminal. And / or, The pull-down node includes: a first pull-down node and a second pull-down node; the input control circuit is connected to the first pull-down node, and the output control circuit is connected to the second pull-up node; the shift register unit further includes: The second intermediate control circuit is connected to the first clock terminal, the first pull-down node, and the first... The two pull-down nodes are connected and used to control the on / off state of the first pull-down node and the second pull-down node in response to the first clock signal.

10. The shift register unit according to claim 9, wherein, The first intermediate control circuit includes a seventh transistor; the second intermediate control circuit includes an eighth transistor. Furthermore, the gate of the seventh transistor is connected to the fifth power supply terminal, the first terminal of the seventh transistor is connected to the first pull-up node, and the second terminal of the seventh transistor is connected to the second pull-up node; The gate of the eighth transistor is connected to the first clock terminal, the first terminal of the eighth transistor is connected to the first pull-down node, and the second terminal of the eighth transistor is connected to the second pull-down node.

11. The shift register unit according to claim 9 or 10, wherein, The shift register unit further includes: A reset control circuit is connected to a reset control terminal, a reset power supply terminal, and the second pull-down node, respectively, and is used to control the on / off state of the reset power supply terminal and the second pull-up node in response to a reset control signal provided by the reset control terminal; wherein the reset power supply terminal is shared with the second power supply terminal or the third power supply terminal.

12. The shift register unit according to claim 11, wherein, The reset control circuit includes: a ninth transistor; The gate of the ninth transistor is connected to the reset control terminal, the first terminal of the ninth transistor is connected to the reset power supply terminal, and the second terminal of the ninth transistor is connected to the second pull-down node.

13. The shift register unit according to any one of claims 1 to 12, wherein, The output control circuit includes: a tenth transistor, a second capacitor, an eleventh transistor, and a third capacitor; Furthermore, the gate of the tenth transistor is connected to the pull-up node, the first terminal of the tenth transistor is connected to the second clock terminal, and the second terminal of the tenth transistor is connected to the output signal terminal; One end of the second capacitor is connected to the pull-up node, and the other end of the second capacitor is connected to the output signal terminal; The gate of the eleventh transistor is connected to the pull-down node, and the first of the eleventh transistor... The second terminal of the eleventh transistor is connected to the third power supply terminal, and the second terminal of the eleventh transistor is connected to the output signal terminal. One end of the third capacitor is connected to the pull-down node, and the other end of the third capacitor is connected to the third power supply terminal.

14. The shift register unit according to claim 13, wherein, The eleventh transistor includes: two third sub-transistors connected in series with their first and second terminals; the shift register unit further includes: The second leakage protection circuit is connected to the output signal terminal, the sixth power supply terminal, and the series node of the two third sub-transistors, respectively, and is used to control the on / off state of the sixth power supply terminal and the connected series node in response to the signal output through the output signal terminal.

15. The shift register unit according to claim 14, wherein, The second leakage protection circuit includes: a twelfth transistor; The gate of the twelfth transistor is connected to the output signal terminal, the first terminal of the twelfth transistor is connected to the sixth power supply terminal, and the second terminal of the twelfth transistor is connected to the series node of the two third sub-transistors.

16. The shift register unit according to any one of claims 1 to 15, wherein, The output signal terminal includes a shift output signal terminal and a drive output signal terminal. The shift output signal terminal is used to connect with other cascaded shift register units, and the drive output signal terminal is used to connect with pixels in the display panel. Furthermore, the output control circuit is also connected to a seventh power supply terminal and a second target terminal, where the second target terminal is either an eighth power supply terminal or a third clock terminal. The output control circuit includes: The first output control sub-circuit is connected to the pull-up node, the pull-down node, the third power supply terminal, the second target terminal, and the shift output signal terminal, respectively, and is used to control the on / off state of the second target terminal and the shift output signal terminal in response to the potential of the pull-up node, and to control the on / off state of the third power supply terminal and the shift output signal terminal in response to the potential of the pull-down node. The second output control sub-circuit is connected to the pull-up node, the pull-down node, the second clock terminal, the seventh power supply terminal, and the drive output signal terminal, respectively. It is used to control the on / off state of the second clock terminal and the drive output signal terminal in response to the potential of the pull-up node, and to control the on / off state of the seventh power supply terminal and the drive output signal terminal in response to the potential of the pull-down node.

17. The shift register unit according to claim 16, wherein, The potential of the seventh power signal provided by the seventh power terminal is less than or equal to the potential of the third power signal provided by the third power terminal.

18. The shift register unit according to claim 16 or 17, wherein, The first output control sub-circuit includes: a tenth transistor, a second capacitor, an eleventh transistor, and a third capacitor; the second output control sub-circuit includes: a twelfth transistor and a thirteenth transistor; and the second target terminal is the eighth power supply terminal; The gate of the tenth transistor is connected to the pull-up node, the first terminal of the tenth transistor is connected to the eighth power supply terminal, and the second terminal of the tenth transistor is connected to the shift output signal terminal. One end of the second capacitor is connected to the pull-up node, and the other end of the second capacitor is connected to the shift output signal terminal; The gate of the eleventh transistor is connected to the pull-down node, the first terminal of the eleventh transistor is connected to the third power supply terminal, and the second terminal of the eleventh transistor is connected to the shift output signal terminal. One end of the third capacitor is connected to the pull-down node, and the other end of the third capacitor is connected to the third power supply terminal. The gate of the twelfth transistor is connected to the pull-up node, the first terminal of the twelfth transistor is connected to the second clock terminal, and the second terminal of the twelfth transistor is connected to the drive output signal terminal. The gate of the thirteenth transistor is connected to the pull-down node, the first terminal of the thirteenth transistor is connected to the seventh power supply terminal, and the second terminal of the thirteenth transistor is connected to the drive output signal terminal.

19. The shift register unit according to claim 16 or 17, wherein, The first output control sub-circuit includes: a tenth transistor, a second capacitor, an eleventh transistor, and a third capacitor; the second output control sub-circuit includes: a twelfth transistor and a thirteenth transistor; and the second target terminal is the third clock terminal; The gate of the tenth transistor is connected to the pull-up node, the first terminal of the tenth transistor is connected to the third clock terminal, and the second terminal of the tenth transistor is connected to the shift output signal terminal. connect; One end of the second capacitor is connected to the pull-up node, and the other end of the second capacitor is connected to the shift output signal terminal; The gate of the eleventh transistor is connected to the pull-down node, the first terminal of the eleventh transistor is connected to the third power supply terminal, and the second terminal of the eleventh transistor is connected to the shift output signal terminal. One end of the third capacitor is connected to the pull-down node, and the other end of the third capacitor is connected to the third power supply terminal. The gate of the twelfth transistor is connected to the pull-up node, the first terminal of the twelfth transistor is connected to the second clock terminal, and the second terminal of the twelfth transistor is connected to the drive output signal terminal. The gate of the thirteenth transistor is connected to the pull-down node, the first terminal of the thirteenth transistor is connected to the seventh power supply terminal, and the second terminal of the thirteenth transistor is connected to the drive output signal terminal.

20. The shift register unit according to claim 19, wherein, The first clock terminal, the second clock terminal, and the third clock terminal are independent of each other; Furthermore, the second clock signal provided by the second clock terminal is a different group of clock signals from the first clock terminal, and the second clock signal provided by the second clock terminal is a different group of clock signals from the third clock terminal.

21. The shift register unit according to claim 19 or 20, wherein, The potential of the second clock signal provided by the second clock terminal is located between the potential of the seventh power signal provided by the seventh power terminal and the potential of the reference power signal; Wherein, the potential of the reference power signal is greater than or equal to the potential of the eighth power signal provided by the eighth power terminal, and the potential of the eighth power signal provided by the eighth power terminal is greater than the potential of the seventh power signal provided by the seventh power terminal.

22. The shift register unit according to any one of claims 19 to 21, wherein, Within one clock cycle, the duration for which the third clock signal provided by the third clock terminal is at an effective potential includes the duration for which the second clock signal provided by the second clock terminal is at an effective potential.

23. A method for driving a shift register unit, used to drive a shift register unit as described in any one of claims 1 to 22; the method comprising: In the first stage, the input control circuit responds to the input signal provided by the input signal terminal, the first clock signal provided by the first clock terminal, the first power signal provided by the first power supply terminal, and the first target signal provided by the first target terminal, by controlling the input signal terminal to be connected to the pull-up node, controlling the first target terminal to be disconnected from the pull-down node, and controlling the first power supply terminal to be connected to the pull-down node. The output control circuit responds to the potential of the pull-up node by controlling the second clock terminal to be connected to the output signal terminal, and responds to the potential of the pull-down node by controlling the third power supply terminal to be disconnected from the output signal terminal. In the second stage, the input control circuit responds to the input signal, the first clock signal, the first power signal, and the first target signal by controlling the input signal terminal to be connected to the pull-up node, controlling the first target terminal to be connected to the pull-down node, and controlling the first power terminal to be disconnected from the pull-down node. The output control circuit responds to the potential of the pull-up node by controlling the second clock terminal to be disconnected from the output signal terminal, and responds to the potential of the pull-down node by controlling the third power terminal to be connected to the output signal terminal.

24. A gate driving circuit, the gate driving circuit comprising: Cascaded multi-stage shift register units as described in any one of claims 1 to 22.

25. A display device, the display device comprising: The display panel, and the gate driving circuit as described in claim 24; The display panel includes multiple pixels; The gate driving circuit is connected to the plurality of pixels via an output signal terminal and is used to transmit gate driving signals to the plurality of pixels to drive the plurality of pixels to emit light.

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