Gate driver circuit, display panel and display device comprising the same

Abstract

The present disclosure relates to a display panel, a display device, and a gate driver circuit. According to one embodiment of the present disclosure, a display panel includes a gate driver circuit in which the voltage of a Q node between an input and an output of a gate shift register in the gate driver circuit (GIP) does not rise but is maintained at a value below a certain voltage when the display device is operated at a low speed for a long time. To this end, a potential holding device is connected to the Q node, a Q2 node, or a weak node between an input unit and an output unit of the gate shift register. The potential holding device maintains the potential of the Q node at a value below a predefined level during a light emission operation for display. Accordingly, image quality defects due to damage to the output voltage caused by leakage and noise at the output node are prevented.

Description

background Technical Field

[0002] The present invention relates to a gate driver circuit, a display panel, and a display device including a gate driver circuit, wherein when the display panel emits light for display, the voltage of the Q node in the gate shift register of the gate driver circuit of the display panel for applying a scan signal to the display device does not rise and remains stable. Background Technology

[0004] Display devices may include pixels, each pixel having a light-emitting element and pixel circuitry for operating the light-emitting element.

[0005] For example, a pixel circuit includes a drive transistor that controls the drive current flowing through the light-emitting element, and at least one switching transistor that controls (or programs) the gate-source voltage of the drive transistor based on a gate signal (scan signal).

[0006] The switching transistors of the pixel circuit can be switched based on the gate signal output from the gate driver circuit (e.g., GIP (Gate In-Panel) driver circuit) disposed on the substrate of the display panel.

[0007] In display devices, the gate driver circuitry comprises multiple stages. Each stage includes multiple shift registers for generating the gate signal (scan signal). Summary of the Invention

[0008] In display devices such as liquid crystal displays (LCDs) or organic light-emitting displays (OLEDs), GIP circuits using output Q-node structures structurally control the voltage of the Q-nodes via transfer transistors.

[0009] The connection point between the transfer transistor and the output is the Q node, and the connection point between the transfer transistor and the input is the Q2 node. A low-level voltage is input from the input to the Q2 node and then transmitted to the output through the Q node.

[0010] However, when the display panel operates at low speed for an extended period of time, the voltage at the Q node rises during frame skipping, and the output voltage at the output node is damaged due to leakage and noise, resulting in image quality defects.

[0011] Therefore, in order to solve the above problems, the applicant of this disclosure has invented a gate driver circuit in which the voltage of the Q node between the input and output of the gate shift register in the gate driver circuit does not rise, but remains at a value below a certain voltage.

[0012] Furthermore, the applicant of this disclosure has invented a display device including a gate driver circuit, wherein a potential holding device is connected to a weak node between the input and output of a Q node or a Q2 node or a gate shift register, and the potential holding device maintains the voltage of the Q node at a voltage value below a predefined level during the light-emitting operation of the display, thereby preventing image quality defects caused by damage to the output voltage due to leakage and noise at the output node.

[0013] The purposes of this disclosure are not limited to those mentioned above. Other purposes and advantages not mentioned in this disclosure may be understood based on the following description and may be more clearly understood from embodiments according to this disclosure. Furthermore, it will be readily understood that the purposes and advantages of this disclosure can be achieved using the means shown in the claims and combinations thereof.

[0014] A gate driver circuit according to an embodiment of the present disclosure may be provided. In the gate driver circuit, a potential holding device is connected to the Q node between the input and output units of each gate shift register, and the potential holding device operates based on a drive signal Vr to maintain the potential of the Q node at a value below a predefined level.

[0015] Furthermore, a display device according to embodiments of the present disclosure may be provided. The display device may include a display panel comprising a plurality of gate lines; a gate driver circuit wherein a potential holding device is connected to a Q node between the input and output units of a gate shift register, and the potential holding device operates based on a drive signal Vr to maintain the potential of the Q node at a value below a predefined level; a data driver circuit for applying a data signal to the display panel; and a timing controller for controlling the gate driver circuit and the data driver circuit.

[0016] According to embodiments of the present disclosure, in a display device, a gate driver circuit is disposed on one side of the display panel, or multiple gate driver circuits are disposed on opposite sides of the display panel respectively, and a potential holding device for maintaining the Q node voltage is disposed between the input of the shift register of the gate driver circuit and the output of the shift register.

[0017] Furthermore, according to embodiments of this disclosure, additional charge can be provided by a potential holding device disposed between the input and output of the shift register, such that the Q node has a wider voltage range compared to the voltage range of the logic voltage.

[0018] Furthermore, according to embodiments of this disclosure, even when low-speed operation can be maintained for an extended period, the potential holding device can maintain the voltage of the Q node at a value below a predefined level.

[0019] Furthermore, according to embodiments of this disclosure, a potential holding device can be connected to the Q node to maintain the voltage of the Q node below a predefined level, thereby compensating for leakage discharge and improving the reliability of low-speed operation.

[0020] Furthermore, according to embodiments of this disclosure, when the potentiometer is connected to the QB node, the gate voltage of the thin-film transistor can be further reduced, thereby achieving robustness of high-voltage output.

[0021] Furthermore, according to embodiments of this disclosure, the potential holding device is connected to the QB node, thereby enhancing the driving force for high-voltage output without additionally increasing the TR size.

[0022] Furthermore, according to embodiments of this disclosure, a charge of appropriate polarity can be additionally supplied to a node that has been in a floating state for a long time via a potential holding device.

[0023] Furthermore, according to embodiments of this disclosure, when the display panel operates at low speed for an extended period of time, the voltage of the Q node will not rise and will remain below a predefined level during frame skipping, thereby preventing damage to the output voltage and image quality defects caused by leakage and noise at the output node.

[0024] Furthermore, according to embodiments of this disclosure, each shift register of the gate driver circuit has a potential holding device, thereby achieving improved reliability and thus cost reduction, as well as robustness of high voltage output and enhanced driving force and thus reduced GIP area.

[0025] According to one embodiment of this disclosure, a gate driver circuit for a display panel includes a gate shift register; wherein the gate shift register is configured to provide gate signals to a plurality of gate lines of the display panel based on a plurality of gate control signals provided from a timing controller of the display panel; the gate shift register includes a plurality of stages connected to each other in a dependent manner; each of the plurality of stages includes: an input unit connected to each of a start signal line and a clock signal line; a Q-node controller connected to the input unit via a Q2 node; an output unit connected to the Q-node controller via a Q-node; a potential holding device connected to the Q-node; and a QB-node controller, one side of the QB-node controller connected to the output unit via a QB-node, and the other side connected to the output unit via a gate turn-off signal line, wherein the potential holding device is configured to operate based on a drive signal to maintain the potential of the Q-node at a value below a predefined level.

[0026] The effects of this disclosure are not limited to those mentioned above, and those skilled in the art will clearly understand other effects not mentioned based on the following description.

[0027] In addition to the effects described above, the specific effects of this disclosure will be described below along with the specific details of how this disclosure is implemented. Attached Figure Description

[0028] Figure 1 This is a schematic diagram illustrating the overall configuration of a display device with a gate shift register according to the present disclosure.

[0029] Figure 2 It constitutes as Figure 1 The block diagram of the gate shift register of the gate driver circuit is shown.

[0030] Figure 3 This is a circuit diagram showing the configuration of any k-th stage STk in the gate shift register of the gate driver circuit according to a first embodiment of this disclosure.

[0031] Figure 4 This is a circuit diagram showing the configuration of any k-th stage STk in the gate shift register of the gate driver circuit according to the second embodiment of this disclosure.

[0032] Figure 5 This is a circuit diagram showing the configuration of any k-th stage STk in the gate shift register of the gate driver circuit according to the third embodiment of this disclosure.

[0033] Figure 6 This is a configuration circuit diagram of any k-th stage STk in the gate shift register of the gate driver circuit according to the fourth embodiment of this disclosure.

[0034] Figure 7 This is a circuit diagram showing the configuration of any k-th stage STk in the gate shift register of the gate driver circuit according to the fifth embodiment of this disclosure.

[0035] Figure 8 This is a configuration circuit diagram of any k-th stage STk in the gate shift register of the gate driver circuit according to the sixth embodiment of this disclosure.

[0036] Figure 9 This is a circuit diagram showing the configuration of any k-th stage STk in the gate shift register of the gate driver circuit according to the seventh embodiment of this disclosure.

[0037] Figure 10 This is a configuration circuit diagram of any k-th stage STk in the gate shift register of the gate driver circuit according to the eighth embodiment of this disclosure.

[0038] Figure 11 This is a graph showing the voltage change of each of the output node and Q node in the gate shift register of a gate driver circuit according to an embodiment of the present disclosure.

[0039] Figure 12 This is a diagram illustrating various structures of a potential-maintaining device for providing negative charge according to a ninth embodiment of this disclosure.

[0040] Figure 13 This is a diagram illustrating various structures of a potential-maintaining device for providing positive charge according to the tenth embodiment of this disclosure. Detailed Implementation

[0041] For the sake of brevity and clarity, the elements in the figures are not necessarily drawn to scale. The same reference numerals in different figures denote the same or similar elements and therefore perform similar functions. Furthermore, for the sake of simplicity, descriptions and details of well-known steps and elements have been omitted. In addition, numerous specific details are set forth in the following detailed description of this disclosure to provide a thorough understanding of it. However, it will be understood that this disclosure can be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits have not been described in detail to avoid unnecessarily obscuring aspects of this disclosure. Examples of various embodiments are further shown and described below. It will be understood that the description herein is not intended to limit the claims to the specific embodiments described. Rather, it is intended to cover alternatives, modifications, and equivalents that may be found within the spirit and scope of this disclosure as defined by the appended claims.

[0042] The shapes, sizes, proportions, angles, numbers, etc., disclosed in the figures used to describe embodiments of this disclosure are exemplary, and this disclosure is not limited thereto. The same reference numerals denote the same elements herein. Furthermore, for the sake of simplicity, descriptions and details of well-known steps and elements have been omitted. In addition, numerous specific details are set forth in the following detailed description of this disclosure to provide a thorough understanding of it. However, it will be understood that this disclosure can be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of this disclosure.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used herein, unless the context clearly indicates otherwise, the singular can constitute "a" and "an," and is intended to also include the plural can constitute "a" and "an." It will also be understood that, when used in this specification, the terms "comprising," "including," "having," and "including...include" specify the presence of the stated features, integers, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, operations, elements, components, and / or portions thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one" when preceding a list of elements may modify the entire list of elements without modifying any individual element in that list. When referring to "C to D," this means that C is included to D is included, unless otherwise stated.

[0044] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or part described below may be referred to as the second element, component, region, layer, or part.

[0045] It will be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, the component or layer may be directly on the other component or layer, directly connected to or coupled to the other component or layer, or there may be one or more intermediate components or layers. Additionally, it will be understood that when a component or layer is referred to as being "between" two components or layers, the component or layer may be the only component or layer between the two components or layers, or there may be one or more intermediate components or layers.

[0046] Unless otherwise defined, all terms used herein, including technical and scientific terms, shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will also be understood that terms—such as those defined in commonly used dictionaries—shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0047] Features of the various embodiments of this disclosure can be combined in part or in whole with each other, and can be technically related to or operable on each other. Embodiments can be implemented independently of each other, or can be implemented together in an associated relationship.

[0048] When interpreting numerical values ​​in this disclosure, a range of error may be inherent, even without their separate explicit description.

[0049] In the description of signal flow relationships, for example, when a signal is sent from node A to node B, the signal can be sent from node A to node B through node C, unless an indication is given that the signal is sent directly from node A to node B.

[0050] According to this disclosure, each of the sub-pixel circuits and gate driver circuits formed on the substrate of the display panel can be implemented as an n-type MOSFET transistor. However, this disclosure is not limited thereto. Each of the sub-pixel circuits and gate driver circuits formed on the substrate of the display panel can be implemented as a p-type MOSFET transistor. A transistor may include a gate, a source, and a drain. In a transistor, charge carriers can flow from the source to the drain. In an n-type transistor, the charge carriers are electrons, and therefore the source voltage can be lower than the drain voltage, allowing electrons to flow from the source to the drain. In an n-type transistor, electrons flow from the source to the drain. The current direction is from the drain to the source. In a p-type transistor, the charge carriers are holes. Therefore, the source voltage can be higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-type transistor, holes flow from the source to the drain. Therefore, the current direction is from the source to the drain. In a MOSFET transistor, the source and drain may not be fixed, but can be changed based on the applied voltage. Therefore, in the present invention, one of the source and the drain is referred to as the first source / drain electrode, and the other of the source and the drain is referred to as the second source / drain electrode.

[0051] In the following, preferred examples of a gate driver circuit and a display device including the gate driver circuit according to the present disclosure will be described in detail with reference to the accompanying drawings. The same elements may have the same reference numerals across different figures. Furthermore, for ease of description, each of the components shown in the drawings is at a different scale than the actual scale. Therefore, each of the components is not limited to the scale shown in the figures.

[0052] Hereinafter, a gate driver circuit and a display device including the gate driver circuit will be described according to embodiments of the present disclosure.

[0053] Figure 1 This is a configuration diagram schematically illustrating the overall configuration of a display device with a gate shift register according to the present disclosure, and Figure 2 It constitutes as Figure 1 The diagram shows the configuration of the gate shift register in the gate driver circuit.

[0054] Reference Figure 1The display device 100 according to embodiments of the present disclosure may include a display panel 120, a gate driver circuit 140, a data driver circuit 160, and a timing controller 180.

[0055] Display panel 120 may include an OLED panel that emits light through organic light-emitting diode (OLED) elements to display images or a liquid crystal panel that displays images through liquid crystal (LCD) elements.

[0056] In the display panel 120, a plurality of gate lines GL and a plurality of data lines DL can be intersected in a matrix and arranged on a substrate made of glass, and each of a plurality of pixels P can be defined at each of the intersections between the plurality of gate lines GL and the plurality of data lines DL.

[0057] Each pixel P responds to a scan signal provided from the gate line GL and displays an image based on an image signal (data voltage) provided from the data line DL.

[0058] Each pixel may include a thin-film transistor (TFT) and a storage capacitor (Cst). All pixels can constitute a single display area A / A. An area without defined pixels can be a non-display area N / A.

[0059] The display panel 120 may include a plurality of pixels P, each defined at the intersection between the gate line GL and the data line DL. According to one example, each of the plurality of pixels P may be a red pixel, a green pixel, or a blue pixel. In this case, adjacent red, green, and blue pixels may constitute a single unit pixel. According to another example, each of the plurality of pixels P may be a red pixel, a green pixel, a blue pixel, or a white pixel. In this case, adjacent red, green, blue, and white pixels may constitute a single unit pixel for displaying a single color image.

[0060] In addition, the display panel 120 may include a display area A / A, a non-display area N / A, and a curved area.

[0061] The display area A / A may include multiple gate lines GL, multiple data lines DL, multiple reference lines (not shown), and multiple pixels P.

[0062] The display mode of the display panel 120 can sequentially display an input image and a black image with a predetermined time difference between them on multiple horizontal lines. According to one example, the display mode may include: an image display period (or an luminous display period) for displaying the input image; and a black display period (or a pulsed non-luminous period) for displaying the black image.

[0063] The sensing mode (or real-time sensing mode) of the display panel 120 can sense the operational characteristics of each of the pixels P arranged in a single horizontal line among multiple horizontal lines after an image display period of one frame.

[0064] Then, the sensing mode can update the pixel-based compensation value used to compensate for changes in the operational characteristics of the corresponding pixel P based on the sensed value.

[0065] According to an example sensing mode, the operational characteristics of each of the pixels P in a single horizontal line arranged in an irregular sequence can be sensed during the vertical blank period of each frame. Pixel P that emits light according to the display mode does not emit light in the sensing mode. Therefore, when horizontal lines are sensed sequentially in the sensing mode, line dimming may occur in the sensed horizontal lines due to their lack of illumination. Conversely, when horizontal lines are sensed in an irregular or random sequence in the sensing mode, line dimming can be minimized or prevented due to the visual diffusion effect.

[0066] The gate driver circuit 140 can be implemented as, for example, a GIP (Gate In-Panel) gate driver. The gate driver circuit 140 can be located in the non-display area of ​​the display panel 120.

[0067] The gate driver circuit 140 includes a gate shift register that provides scan signals (gate signals) to multiple gate lines GL based on multiple gate control signals GCS provided from the timing controller 180.

[0068] The multiple gate control signals GCS include multiple clock signals CLK1 to CLK4 with different phases and a gate start signal VST indicating the start of operation of the gate driver circuit 140. (See below for further details.) Figure 2 Describe the gate shift register in detail.

[0069] The data driver circuit 160 uses a reference gamma voltage to convert the digital image data RGB input from the timing controller 180 into a data voltage, and provides the converted data voltage to multiple data lines DL. The data driver circuit 160 is controlled based on multiple data control signals DCS provided from the timing controller 180.

[0070] That is, the data driver circuit 160 can selectively convert the digital modulated image data RGBv input in response to the data control signal DCS input from the timing controller 180 into an analog data voltage VDATA based on a reference voltage Vref, and can provide the converted data voltage to multiple data lines DL. The data voltage VDATA can be latched on a horizontal line basis and can be simultaneously input to the display panel 120 through all data lines DL during a horizontal time period 1H.

[0071] The timing controller 180 can receive image signals RGB sent from an external system, as well as timing signals such as clock signal CLK, horizontal synchronization signal Hsync, vertical synchronization signal Vsync, and data enable signal DE, and can generate control signals for controlling data driver circuit 160 and gate driver circuit 140 based on the received signals.

[0072] In this regard, the horizontal synchronization signal Hsync refers to the signal that indicates the time taken to display a horizontal line on the screen, and the vertical synchronization signal Vsync refers to the signal that indicates the time taken to display one frame of the screen. Furthermore, the data enable signal DE is a signal that indicates the time period for providing data voltage to pixels P defined in the display panel 120.

[0073] In addition, the timing controller 180 can generate, in sync with the input timing signal, a gate control signal GCS for controlling the gate driver circuit 140 and a data control signal DCS for controlling the data driver circuit 160.

[0074] Additionally, the timing controller 180 can generate multiple clock signals CLK1 to CLK4 that determine the operating timing of each stage of the gate driver circuit 140, and can provide the multiple clock signals CLK1 to CLK4 to the gate driver circuit 140. In this respect, each of the first clock signals CLK1 to the fourth clock signal CLK4 has a high period lasting two horizontal time intervals (2H). Temporarily adjacent clock signals among the first clock signals CLK1 to the fourth clock signal CLK4 can overlap each other by one horizontal time interval (1H).

[0075] Furthermore, the timing controller 180 can align and modulate the received image data RGB DATA into a form that can be processed by the data driver circuit 160 and output the modulated data. In this respect, the aligned image data RGBv can have a form in which a color coordinate correction algorithm for image quality improvement is applied.

[0076] The gate driver circuit 140 can provide a scan signal to each of the gate lines GL.

[0077] The gate driver circuit 140 may include a first gate driver and a second gate driver respectively disposed on the left and right sides of the display panel 120.

[0078] The gate driver circuit 140 may include two gate drivers, namely, a first gate driver and a second gate driver that may be respectively disposed on two opposite sides of the display panel 120 and in the non-display area N / A.

[0079] In one example, the first gate driver may be located on one side (left side) of the display panel 120, and the second gate driver may be located on the opposite side (right side) of the display panel 120.

[0080] In this respect, in the gate driver circuit 140, the odd-numbered output lines of the first gate driver can be connected to the even-numbered output lines of the second gate driver 140b, while the even-numbered output lines of the first gate driver can be connected to the odd-numbered output lines of the second gate driver.

[0081] Each of the first gate driver and the second gate driver may include at least one stage, preferably multiple stages, each stage including a shift register. During the manufacturing process of the substrate of the display panel 120, the gate driver circuit 140 may be embedded in the non-display area in the form of a thin-film pattern and in a gate in-panel (GIP) manner.

[0082] The gate driver circuit 140, in response to the gate control signal GCS input from the timing controller 180, alternately outputs a gate high voltage VGH every two horizontal time periods (2H) through multiple gate lines GL formed on the display panel 120. At this point, the output of the gate high voltage VGH can be maintained for two horizontal time periods (2H). Temporarily adjacent gate high voltages VGH can overlap each other by one horizontal time period (1H). This is for pre-charging the gate lines GL. Therefore, more stable pixel charging can be performed when a data voltage is applied.

[0083] Therefore, a first clock signal CLK1 and a third clock signal CLK3, each with two horizontal time periods (2H), can be applied to the first gate driver, while two second clock signals CLK2 and two fourth clock signals CLK4, each with two horizontal time periods (2H), can be applied to the second gate driver. In this respect, the second clock signal CLK2 and the fourth clock signal CLK4 can overlap with the first clock signal CLK1 and the third clock signal CLK3 by one horizontal time period (1H), respectively.

[0084] In one example, the first gate driver can output the gate high voltage VGH to the nth gate line GLn. Then, after a horizontal period (1H), the second gate driver can output the gate high voltage VGH to the (n+1)th gate line GLn+1.

[0085] Next, after a horizontal time period (1H), the first gate driver can output the high gate voltage VGH to the (n+2)th gate line GLn+2. Simultaneously, the first gate driver can output the low gate voltage VGL to the nth gate line GLn to turn off the thin-film transistor TFT, thereby maintaining the data voltage charged in the storage capacitor Cst within a frame.

[0086] In particular, in embodiments of this disclosure, the discharge circuit can be activated at the point when the voltage of the gate line GL switches from the high gate voltage VGH to the low voltage VGL, so as to minimize the discharge delay of the gate line GL.

[0087] In this respect, each discharge circuit can be connected to the far end of each of the gate lines GL. Therefore, the R (right) discharge circuits, connected to the odd-numbered gate lines respectively, can be arranged adjacent to the second gate driver. The L (left) discharge circuits, connected to the even-numbered gate lines respectively, can be arranged adjacent to the first gate driver.

[0088] In this respect, each of the discharge circuits can be connected to the second gate line after a single gate line GL, and a gate low voltage VGL can be applied to the corresponding gate line GL.

[0089] Each of these discharge circuits can be implemented as a thin-film transistor between adjacent stages in the gate driver circuit 140. Therefore, a narrow bezel can be achieved, comprising a portion of the non-display area N / A of the display panel 120 where each of the first and second gate drivers is disposed.

[0090] Reference Figure 2 The gate driver circuit 140 according to embodiments of the present disclosure includes a gate shift register. The gate shift register may include a plurality of stages ST1, ST2, ..., STn connected to each other in a dependent manner.

[0091] Multiple ST stages can be selectively connected to lines provided with multiple clock signals CLK1 to CLK4, and can sequentially output scan pulses G: G1, G2, G3, ... as their gate signals.

[0092] Specifically, each of the multiple ST stages can receive at least one of a plurality of clock signals CLK1 to CLK4, gate on voltage VGL, gate off voltage VGH, and blank signal BS.

[0093] Multiple clock signals CLK1 to CLK4 may include four-phase clock signals shifted for a certain period of time and output, namely, the first clock signal CLK1 to the fourth clock signal CLK4. Three clock signals can be selected from the first clock signal CLK1 to the fourth clock signal CLK4 and can be provided to each ST level. For example, the first clock signal CLK1, the third clock signal CLK3, and the fourth clock signal CLK4 are provided to each of the (4k-3)th levels ST1, ST5, ST9, ..., where k is a natural number. The second clock signal CLK2, the fourth clock signal CLK4, and the first clock signal CLK1 are provided to each of the (4k-2)th levels ST2, ST6, ST10, ... The third clock signal CLK3, the first clock signal CLK1, and the second clock signal CLK2 are provided to the (4k-1)th levels ST3, ST7, ST11, ... The fourth clock signal CLK4, the second clock signal CLK2, and the third clock signal CLK3 are provided to the 4kth levels ST4, ST8, ST12, ...

[0094] The blank signal BS can be provided for the blank period and can be the source output enable signal SOE provided by the timing controller 180. In this respect, the blank period refers to the period set after the scan period in which the scan pulse G is output once from multiple stages ST.

[0095] Specifically, the gate shift register according to this disclosure uses a blank signal BS provided during a blank period to charge the voltage of the QB node to which the gate electrode of the pull-down transistor in each ST stage is connected to the gate turn-off voltage VGH. Therefore, the gate shift register according to this disclosure can prevent pull-down transistor PD failure due to leakage current at the QB node and the resulting multiple outputs, thereby improving operational reliability.

[0096] In one example, the gate shift register according to an embodiment of this disclosure may include a pre-virtual stage circuitry preceding the first stage ST1. Figure 2 (not shown in the diagram) and the post-virtual stage circuitry following the nth stage STn ( Figure 2 (Not shown in the image).

[0097] The gate driver circuit 140 can receive the gate control signal GCS via the gate control signal line. That is, the gate control signal line receives the gate control signal GCS provided from the timing controller 180. According to the example, the gate control signal line may include a gate start signal line, a first reset signal line, a second reset signal line, a plurality of gate drive clock lines, a display panel turn-on signal line, and a sensing preparation signal line.

[0098] The gate start signal line can receive a gate start signal VST provided by the timing controller 180. For example, the gate start signal line can be connected to the previous virtual stage circuitry.

[0099] The first reset signal line can receive a first reset signal provided by the timing controller 180. The second reset signal line can receive a second reset signal provided by the timing controller 180. For example, each of the first and second reset signal lines can be connected together to the front virtual stage circuit system, the first stage circuit ST1 to the m-th stage circuit STm, and the rear virtual stage circuit system.

[0100] The multiple gate drive clock lines may include multiple carry clock lines, multiple scan clock lines, and multiple sense clock lines that respectively receive multiple carry shift clocks, multiple scan shift clocks, and multiple sense shift clocks provided from the timing controller 180. The multiple gate drive clock lines can be selectively connected to the front virtual stage circuit system, the first stage circuit ST1 to the m-th stage circuit STm, and the rear virtual stage circuit system.

[0101] The display panel turn-on signal line can receive a display panel turn-on signal provided by the timing controller 180. For example, the display panel turn-on signal line can typically be connected to the front virtual stage circuit system and the first stage circuit ST1 to the m-th stage circuit STm.

[0102] The sense preparation signal line can receive a line sense preparation signal provided by the timing controller 180. For example, the sense preparation signal line can typically be connected to the first stage circuit ST1 through the m-th stage circuit STm. Alternatively, the sense preparation signal line can be additionally connected to the preceding virtual stage circuitry.

[0103] The gate drive voltage line may include a first gate high potential voltage line to a fourth gate high potential voltage line for receiving first gate high potential voltages to fourth gate high potential voltages with different voltage levels from a power supply circuit, and a first gate low potential voltage line to a third gate low potential voltage line for receiving first gate low potential voltages to third gate low potential voltages with different voltage levels from a power supply circuit.

[0104] According to the example, the first gate high potential voltage can have a higher voltage level compared to the second gate high potential voltage. The third and fourth gate high potential voltages can swing in opposite directions between a high voltage (or TFT turn-on voltage or the first voltage) and a low voltage (or TFT turn-off voltage or the second voltage), or they can be reversed for alternating current (AC) operation. For example, when the third gate high potential voltage (or odd-numbered gate high potential voltage) has a high voltage, the fourth gate high potential voltage (or even-numbered gate high potential voltage) can have a low voltage. Thus, when the third gate high potential voltage has a low voltage, the fourth gate high potential voltage can have a high voltage.

[0105] Each of the first gate high potential voltage line and the second gate high potential voltage line can be connected together to the first stage circuit ST1 to the m-th stage circuit STm, the front virtual stage circuit system and the rear virtual stage circuit system.

[0106] The third gate high-potential voltage line can be connected together to the odd-numbered stage circuits in the first stage circuit ST1 to the m-th stage circuit STm, and can also be connected together to the odd-numbered virtual stage circuits of each of the front virtual stage circuit system and the rear virtual stage circuit system.

[0107] The fourth gate high-potential voltage line can be connected to the even-numbered stage circuits in the first stage circuit ST1 to the m-th stage circuit STm, and can also be connected to the even-numbered virtual stage circuits of each of the front virtual stage circuit system and the rear virtual stage circuit system.

[0108] According to the example, the first gate low potential voltage and the second gate low potential voltage can have substantially the same voltage level. The third gate low potential voltage can have a TFT turn-off voltage level. The first gate low potential voltage can have a higher voltage level compared to the third gate low potential voltage. According to the example of this disclosure, the first gate low potential voltage can be set to have a higher voltage level compared to the third gate low potential voltage, thereby reliably blocking the turn-off current of the TFT having the gate electrode connected to the control node of the stage circuit, which will be described later. Therefore, the stability and reliability of the operation of the corresponding TFT can be ensured.

[0109] Each of the first gate low potential voltage lines to the third gate low potential voltage lines can be connected together to the first stage circuit ST1 to the m-th stage circuit STm.

[0110] The preceding virtual stage circuitry can sequentially generate multiple carry signals in response to the gate start signal VST provided from the timing controller 180, and provide the generated signals as carry signals or gate start signals to one of its subsequent stages.

[0111] The post-virtual stage circuit system can sequentially generate multiple carry signals and provide the generated signals as carry signals (or stage reset signals) to one of the preceding stages.

[0112] The first-stage circuits ST1 to STm can be connected to each other in a dependent manner. The first-stage circuits ST1 to STm can generate first scan signals SC1 to STm and first sensing signals SE1 to STm, respectively, and output the generated signals to the corresponding gate lines GL provided in the display panel 120. Furthermore, each of the first-stage circuits ST1 to STm can generate each of the first carry signals CS1 to STm and provide the generated signal as a carry signal (or gate start signal) to one of the subsequent stages, and simultaneously provide the generated signal as a carry signal (or stage reset signal) to one of the preceding stages.

[0113] Two adjacent stages, from the first stage ST1 to the m-th stage STm, can share a portion of the sensing control circuit and control nodes. Therefore, the circuit configuration of the gate driver circuit 140 can be simplified, and the area occupied by the gate driver circuit 140 in the display panel 120 can be reduced.

[0114] Figure 3 This is a circuit diagram showing the configuration of any k-th stage STk in the gate shift register of the gate driver circuit according to a first embodiment of this disclosure.

[0115] Reference Figure 3 In the gate shift register according to the embodiments of the present disclosure, the k-th stage STk may include an input unit 310, a Q-node controller 320, an output unit 330, a first potential holding device 340, and a first QB-node controller 350.

[0116] Input unit 310 is connected to each of the start signal (GVST) line and the clock signal (GCLK) line.

[0117] Q-node controller 320 is connected to input unit 310 via Q2 node.

[0118] Output unit 330 is connected to Q node controller 320 via Q node.

[0119] The first potential holding device 340 is connected to the Q node.

[0120] One side of the first QB node controller 350 is connected to the output unit 330 via a QB node, and the other side is connected to the output unit 330 via a gate turn-off signal (VGH) line.

[0121] The first potential holding device 340 operates based on the drive signal Vr to maintain the potential of the Q node below a predefined level.

[0122] Input unit 310 includes a third thin-film transistor T3. The gate electrode of the third thin-film transistor T3 is connected to the clock signal (GCLK) line, its first electrode is connected to the start signal (GVST) line, and its second electrode is connected to the Q2 node.

[0123] Input unit 310 can operate based on one of the multiple clock signals CLK1 to CLK4, namely clock signal GCLK, to input a high-level or low-level start signal GVST to the second node Q2.

[0124] Q-node controller 320 includes a TFT active anti-backflow (TA) thin-film transistor. The gate electrode of the TA thin-film transistor is connected to the gate on signal (VGL) line, its first electrode is connected to the Q-node, and its second electrode is connected to the Q2 node. The TA thin-film transistor operates as shown in Table 1 below.

[0125] Table 1

[0126]

[0127] When a gate-on signal (VGL) is applied to the gate electrode of the TA thin-film transistor TA, the Q-node controller 320 is turned on. Therefore, the Q2 node voltage of the second electrode is transmitted to the Q-node of the first electrode through the TA thin-film transistor TA, thereby controlling the voltage of the Q-node.

[0128] Output unit 330 includes a pull-up transistor and a pull-down transistor. The pull-up transistor outputs a scan signal to the output terminal Output based on the voltage level of the Q node. The pull-down transistor provides a gate turn-off signal (VGH) to the output terminal Output based on the voltage level of the QB node.

[0129] The pull-up transistor may include a first thin-film transistor T1, wherein its gate electrode is connected to a Q node, its first electrode is connected to a first gate on signal (VGL) line, and its second electrode is connected to an output terminal Output.

[0130] The pull-down transistor may include a second thin-film transistor T2, wherein its gate electrode is connected to the QB node, its first electrode is connected to the output terminal Output, and its second electrode is connected to the gate turn-off signal (VGH) line.

[0131] In this respect, the first capacitor CQ can be connected and positioned between the Q node to which the gate electrode of the first thin-film transistor T1 is connected and the output terminal Output to which the second electrode of the first thin-film transistor T1 is connected.

[0132] The first potential holding device 340 may include a seventh thin-film transistor T7. The gate electrode of the seventh thin-film transistor T7 is connected to a drive signal (Vr) line, its first electrode is connected to a low signal (VL) line, and its second electrode is connected to the contact point between the Q node and the first capacitor CQ. Furthermore, the first potential holding device 340 also includes a diode D connected and disposed between the contact point between the Q node and the first capacitor CQ and the second electrode of the seventh thin-film transistor T7, and a second capacitor C connected to the second electrode of the seventh thin-film transistor T7. An applied signal (Vp) line is connected to the second electrode of the seventh thin-film transistor T7 through the second capacitor C.

[0133] The first QB node controller 350 may include a fourth thin-film transistor T4, a fifth thin-film transistor T5, and a sixth thin-film transistor T6.

[0134] The gate electrode of the fourth thin-film transistor T4 is connected to the start signal (GVST) line, its first electrode is connected to the gate electrode of the fifth thin-film transistor T5, and its second electrode is connected to the output unit 330 through the gate turn-off signal (VGH) line.

[0135] The first electrode of the fifth thin-film transistor T5 is connected to the clock signal (GCLK) line, its gate electrode is connected to the clock signal (GCLK) line through the third capacitor C_ON, and its second electrode is connected to the QB node.

[0136] The gate electrode of the sixth thin-film transistor T6 is connected to the Q2 node, its first electrode is connected to the QB node, and its second electrode is connected to the output unit 330 via the gate turn-off signal (VGH) line.

[0137] Each of the TA transistor TA and the first thin-film transistors T1 to the seventh thin-film transistors T7 can have a P-type MOS structure.

[0138] Each of the TA transistor TA and the first thin-film transistors T1 to the seventh thin-film transistors T7 can be implemented as an oxide thin-film transistor (Oxide TFT) or a low-temperature polycrystalline silicon thin-film transistor (LTPS TFT).

[0139] Figure 4 This is a circuit diagram showing the configuration of any k-th stage STk in the gate shift register of the gate driver circuit according to the second embodiment of this disclosure.

[0140] Reference Figure 4In the gate shift register according to the second embodiment of the present disclosure, the k-th stage STk may include an input unit 310, a Q-node controller 320, an output unit 330, a second potential holding device 340b, and a first QB-node controller 350.

[0141] That is, in the k-th stage STk of the gate shift register according to the second embodiment of the present disclosure, the first potential holding device 340 is replaced by the second potential holding device 340b.

[0142] The second potential holding device 340b includes a seventh thin-film transistor T7 and an eighth thin-film transistor T8.

[0143] The first electrode of the eighth thin-film transistor T8 is connected to the Q node, its second electrode is connected to the applied signal (Vp) line through the second capacitor C, and its gate electrode is connected to the second electrode.

[0144] The first electrode of the seventh thin-film transistor T7 is connected to the second electrode of the eighth thin-film transistor T8, the second electrode of which is connected to the gate conduction signal (VGL) line, and the gate electrode of which is connected to the output terminal Output.

[0145] Figure 5 This is a configuration circuit diagram of any k-th stage STk in the gate shift register according to the third embodiment of this disclosure.

[0146] Reference Figure 5 According to the third embodiment of this disclosure, the k-th stage STk in the gate shift register may include an input unit 310, a Q-node controller 320, an output unit 330, a first potential holding device 340, and a second QB-node controller 350b.

[0147] That is, in the k-th stage STk of the gate shift register according to the third embodiment of the present disclosure, the first QB node controller 350 is replaced by the second QB node controller 350b.

[0148] The second QB node controller 350b may include a fourth thin-film transistor T4 and a fifth thin-film transistor T5.

[0149] The first electrode of the fourth thin-film transistor T4 is connected to the gate on signal (VGL) line, its second electrode is connected to the QB node, and its gate electrode is connected to the Q node.

[0150] The first electrode of the fifth thin-film transistor T5 is connected to the QB node, its second electrode is connected to the output terminal Output via the gate turn-off signal (VGH) line, and its gate electrode is connected to the Q2 node.

[0151] Figure 6This is a configuration circuit diagram of any k-th stage STk in the gate shift register of the gate driver circuit according to the fourth embodiment of this disclosure.

[0152] Reference Figure 6 According to the fourth embodiment of this disclosure, the k-th stage STk in the gate shift register may include an input unit 310, a Q-node controller 320, an output unit 330, a third potential holding device 340c, and a second QB-node controller 350b.

[0153] That is, the k-th stage STk in the gate shift register according to the fourth embodiment of the present disclosure has a structure in which the first potential holding device 340 is replaced by the third potential holding device 340c and the first QB node controller 350 is replaced by the second QB node controller 350b.

[0154] The third potential holding device 340c is connected to node Q2.

[0155] Each of the first potential holding device 340 and the second potential holding device 340b is connected to the Q node, while the third potential holding device 340c according to the fourth embodiment of the present disclosure is connected to the Q2 node.

[0156] In this respect, the third potential holding device 340c may include a thin-film transistor, a diode, and a capacitor.

[0157] In addition, the third potential holding device 340c can be connected to the drive signal (Vr) line and the application signal (Vp) line.

[0158] Figure 7 This is a circuit diagram showing the configuration of any k-th stage STk in the gate shift register of the gate driver circuit according to the fifth embodiment of this disclosure.

[0159] Reference Figure 7 According to the fifth embodiment of this disclosure, the k-th stage STk in the gate shift register may include an input unit 310, a Q-node controller 320, an output unit 330, a fourth potential holding device 340d, and a second QB-node controller 350b.

[0160] That is, the k-th stage STk in the gate shift register according to the fifth embodiment of the present disclosure has a structure in which the first potential holding device 340 is replaced by the fourth potential holding device 340d and the first QB node controller 350 is replaced by the second QB node controller 350b.

[0161] The fourth potential holding device 340d is connected to the QB node.

[0162] The fourth potential holding device 340d operates based on the drive signal Vr to maintain the potential of the QB node below a predefined level.

[0163] In this respect, the second QB node controller 350b has a structure in which one side is connected to the output unit 330 via the QB node and the other side is connected to the output unit 330 via the gate turn-off signal (VGH) line.

[0164] Figure 8 This is a configuration circuit diagram of any k-th stage STk in the gate shift register of the gate driver circuit according to the sixth embodiment of this disclosure.

[0165] Reference Figure 8 According to the sixth embodiment of this disclosure, the k-th stage STk in the gate shift register may include an input unit 310, a Q-node controller 320, an output unit 330, a fifth potential holding device 340e, and a second QB-node controller 350b.

[0166] That is, the k-th stage STk in the gate shift register according to the sixth embodiment of the present disclosure has a structure in which the first potential holding device 340 is replaced by the fifth potential holding device 340e and the first QB node controller 350 is replaced by the second QB node controller 350b.

[0167] One side of the fifth potential holding device 340e is connected to the Q node, and the other side is connected to the output terminal Output of the output unit 330.

[0168] The fifth potential holding device 340e operates based on the light emission signal EM(N) to maintain the potential of the Q node below a predefined level.

[0169] The fifth potential holding device 340e may include a sixth thin-film transistor T6 and a seventh thin-film transistor T7.

[0170] The first electrode of the sixth thin-film transistor T6 is connected to the Q node, its second electrode is connected to the light-emitting signal (EM(N)) line through the second capacitor C, and its gate electrode is connected to the second electrode.

[0171] The seventh thin-film transistor T7 is configured such that its first electrode is connected to the second electrode of the sixth thin-film transistor T6, its second electrode is connected to the gate conduction signal (VGL) line, and its gate electrode is connected to the output terminal Output.

[0172] In this respect, the second QB node controller 350b has a structure in which one side is connected to the output unit 330 via the QB node and the other side is connected to the output unit 330 via the gate turn-off signal (VGH) line.

[0173] Figure 9 This is a circuit diagram showing the configuration of any k-th stage STk in the gate shift register of the gate driver circuit according to the seventh embodiment of this disclosure.

[0174] Reference Figure 9 According to the seventh embodiment of this disclosure, the k-th stage STk in the gate shift register may include an input unit 310, a Q-node controller 320, an output unit 330, a sixth potential holding device 340f, and a third QB-node controller 350c.

[0175] That is, the k-th stage STk in the gate shift register according to the seventh embodiment of the present disclosure has a structure in which the first potential holding device 340 is replaced by the sixth potential holding device 340f and the first QB node controller 350 is replaced by the third QB node controller 350c.

[0176] In this respect, the sixth potential holding device 340f is configured such that one side of it is connected to the Q node, the other side is connected to the QB node, and yet another side of it is connected to the input unit 310.

[0177] The sixth potential holding device 340f operates based on the voltage level of the Q node to maintain the potential of the Q node below a predefined level.

[0178] The sixth potential holding device 340f may include a fourth thin-film transistor T4, a fifth thin-film transistor T5, and a sixth thin-film transistor T6.

[0179] The fourth thin-film transistor T4 is configured such that its first electrode is connected to the gate on signal (VGL) line, its gate electrode is connected to the Q node, and its second electrode is connected to the fifth thin-film transistor T5.

[0180] The fifth thin-film transistor T5 is configured such that its first electrode is connected to the second point electrode of the fourth thin-film transistor T4, its gate electrode is connected to the first electrode, and its second electrode is connected to the input unit 310 through the second capacitor C.

[0181] The sixth thin-film transistor T6 is configured such that its first electrode is connected to the second electrode of the fifth thin-film transistor T5, the second electrode is connected to the QB node, and its gate electrode is connected to the first electrode.

[0182] The third QB node controller 350c has a structure in which one side is connected to the output unit 330 via a QB node and the other side is connected to the output unit 330 via a gate turn-off signal (VGH) line.

[0183] The third QB node controller 350c may include a seventh thin-film transistor T7.

[0184] That is, the seventh thin-film transistor T7 is configured such that its first electrode is connected to the QB node, its second electrode is connected to the output unit 330 via the gate turn-off signal (VGH) line, and its gate electrode is connected to the Q2 node.

[0185] Figure 10 This is a configuration circuit diagram of any k-th stage STk in the gate shift register of the gate driver circuit according to the eighth embodiment of this disclosure.

[0186] Reference Figure 10 According to the eighth embodiment of this disclosure, the k-th stage STk in the gate shift register may include an input unit 310, a Q-node controller 320, an output unit 330, a seventh potential holding device 340g, a third QB-node controller 350c, and a Q2-node controller 360.

[0187] That is, the k-th stage STk in the gate shift register according to the eighth embodiment of the present disclosure has a structure in which the first potential holding device 340 is replaced by the seventh potential holding device 340g, the first QB node controller 350 is replaced by the third QB node controller 350c, and a Q2 node controller 360 is also added.

[0188] In this respect, the seventh potential holding device 340g can be connected to the Q node and can be connected and positioned between the Q node and the third QB node controller 350c. Furthermore, the drive signal (Vr) line and the application signal (Vp) line can be connected to the seventh potential holding device 340g. Additionally, the seventh potential holding device 340g is connected to the Q node via the first capacitor CQ.

[0189] The third QB node controller 350c can be connected to the seventh potential holding device 340g and can be connected to the gate electrode of the second thin film transistor T2 of the output unit 330 via the QB node, and can be connected to the second electrode of the second thin film transistor T2 of the output unit 330 via the gate high voltage (VGH) line.

[0190] The third QB node controller 350c may include a fourth thin-film transistor T4, a fifth thin-film transistor T5, a sixth thin-film transistor T6, a seventh thin-film transistor T7, an eighth thin-film transistor T8, a ninth thin-film transistor T9, a tenth thin-film transistor T10, and an eleventh thin-film transistor T11.

[0191] The fourth thin-film transistor T4 is configured such that its gate electrode is connected to the CQ node, its first electrode is connected to the first clock signal (GCLK1) line, and its second electrode is connected to the first electrode of the fifth thin-film transistor T5.

[0192] The fifth thin-film transistor T5 is configured such that its first electrode is connected to the second electrode of the fourth thin-film transistor T4, its gate electrode is connected to the first clock signal (GCLK1) line, and its second electrode is connected to the QB node.

[0193] At this point, the connection point between the second electrode of the fourth thin-film transistor T4 and the first electrode of the fifth thin-film transistor T5 is connected to the CQ node through the second capacitor CC.

[0194] The sixth thin-film transistor T6 is configured such that its gate electrode is connected to the Q2 node, its first electrode is connected to the QB node, and its second electrode is connected to the output unit 330 via the gate turn-off signal (VGH) line.

[0195] The seventh thin-film transistor T7 is configured such that its gate electrode is connected to the Q node, its first electrode is connected to the first clock signal (GCLK1) line, and its second electrode is connected to the first electrode of the seventh potential holding device 340g and the eighth thin-film transistor T8.

[0196] The eighth thin-film transistor T8 is configured such that its first electrode is connected to the second electrode of the seventh thin-film transistor T7 and the seventh potential holding device 340g, its gate electrode is connected to the CQ node, and its second electrode is connected to the gate turn-off signal (VGH) line.

[0197] The ninth thin-film transistor T9 is configured such that its first electrode is connected to the gate on signal (VGL) line, its gate electrode is connected to the second clock signal (GCLK2) line, and its second electrode is connected to the CQ node and the first electrode of the tenth thin-film transistor T10.

[0198] The tenth thin-film transistor T10 is configured such that its first electrode is connected to the second electrode of the ninth thin-film transistor T9, its gate electrode is connected to the gate on signal (VGL) line, and its second electrode is connected to the first electrode of the eleventh thin-film transistor T11.

[0199] The eleventh thin-film transistor T11 is configured such that its first electrode is connected to the second electrode of the tenth thin-film transistor T10, its gate electrode is connected to the Q2 node, and its second electrode is connected to the second clock signal (GCLK2) line.

[0200] The Q2 node controller 360 may include a twelfth thin-film transistor T12. The twelfth thin-film transistor T12 has a gate electrode connected to a reset signal (RST) line, a first electrode connected to the Q2 node, and a second electrode connected to a gate turn-off signal (VGH) line.

[0201] Figure 11It is a graph showing the voltage change of each of the output node and Q node in the gate shift register of the gate driver circuit according to an embodiment of the present disclosure.

[0202] Reference Figure 11 Regarding any k-th stage STk in the gate shift register of the gate driver circuit 140 according to an embodiment of the present disclosure, in the conventional case where the potential holding device 340 is not connected to the Q node or Q2 node, a voltage (b) is generated in the Q node that causes the output to rise, and thus an output error (a) appears in the voltage of the output node Output.

[0203] However, in any k-th stage STk of the gate shift register according to an embodiment of this disclosure, where the potential holding device 340 is connected to the Q node or Q2 node, the voltage generated in the Q node that causes the output to rise is lower than a predefined level (b), and therefore no output error occurs in the voltage of the output node Output (a).

[0204] Figure 12 This is a diagram illustrating various structures of a potential-maintaining device for providing negative charge according to a ninth embodiment of this disclosure.

[0205] Reference Figure 12 In the potential holding device according to the ninth embodiment of this disclosure, as shown in (a), the first diode D1 can be connected to the applied signal (Vp) line via capacitor C, the second electrode of the switching element SW can be connected to the connection point between the first diode D1 and the applied signal (Vp) line, and the low voltage (VL) line can be connected to the first electrode of the switching element SW via the second diode D2. The reverse drive signal (~Vr) line can be connected to the third electrode of the switching element SW. The first diode D1 has a positive direction toward the connection point, while the second diode D2 has a positive direction from the connection point to the low voltage (VL) line.

[0206] Furthermore, in the potential holding device according to the ninth embodiment of this disclosure, as shown in (b), the first diode D1 can be connected to the applied signal (Vp) line via capacitor C, and the second electrode of the switching element SW can be connected to the connection point between the first diode D1 and the applied signal (Vp) line via the second diode D2. The low voltage (VL) line can be connected to the first electrode of the switching element SW. The reverse drive signal (~Vr) line can be connected to the third electrode of the switching element SW. The first diode D1 has a positive direction toward the connection point, while the second diode D2 has a positive direction from the connection point to the low voltage (VL) line.

[0207] Furthermore, in the potential holding device according to the ninth embodiment of this disclosure, as shown in (c), the first diode D1 can be connected to the applied signal (Vp) line via capacitor C, and the second electrode of the N-MOS thin-film transistor T can be connected to the junction between the first diode D1 and the applied signal (Vp) line via the second diode D2. The low voltage (VL) line can be connected to the first electrode of the N-MOS thin-film transistor T. The reverse drive signal (~Vr) line can be connected to the gate electrode of the N-MOS thin-film transistor T. The first diode D1 has a forward direction toward the junction, while the second diode D2 has a forward direction from the junction to the low voltage (VL) line.

[0208] Furthermore, in the potential holding device according to the ninth embodiment of this disclosure, as shown in (d), the first thin-film transistor T1 can be connected to the applied signal (Vp) line via the first capacitor C1. The second thin-film transistor T2 and the third thin-film transistor T3, connected in series, can be connected to the connection point between the first thin-film transistor T1 and the applied signal (Vp) line. Each of the first thin-film transistor T1 and the second thin-film transistor T2 has a P-MOS structure, and the third thin-film transistor T3 has an N-MOS structure. The gate electrode of the first thin-film transistor T1 can be connected to the drive signal (Vr) line via the second capacitor C2, and can also be connected to the connection point therebetween. The second thin-film transistor T2 is configured such that its second electrode is connected to the connection point, its gate electrode is connected to the drive signal (Vr) line via the third capacitor C3, and its first electrode is connected to its gate electrode and to the second electrode of the third thin-film transistor T3. The third thin-film transistor T3 is configured such that its first electrode is connected to the low voltage (VL) line, its second electrode is connected to the first electrode of the second thin-film transistor T2, and its gate electrode is connected to the reverse drive signal (~Vr) line.

[0209] Furthermore, in the potential holding device according to the ninth embodiment of this disclosure, as shown in (e), the first thin-film transistor T1 can be connected to the applied signal (Vp) line via a first capacitor C1. A second thin-film transistor T2 and a third thin-film transistor T3 connected in series can be connected to a first connection point between the first thin-film transistor T1 and the applied signal (Vp) line. Each of the first thin-film transistor T1, the second thin-film transistor T2, and the third thin-film transistor T3 has an N-MOS structure. The first thin-film transistor T1 has a gate electrode and a first electrode connected to each other. The gate electrode of the third thin-film transistor T3 can be connected to a second connection point therebetween via a second capacitor C2. The second thin-film transistor T2 is configured such that its first electrode is connected to the second electrode of the third thin-film transistor T3, its second electrode is connected to the first connection point, and its gate electrode is connected to the reverse drive signal (~Vr) line and its second electrode via the third capacitor C3. The third thin-film transistor T3 is configured such that its first electrode is connected to the low voltage (VL) line, its second electrode is connected to the first electrode of the second thin-film transistor T2, and its gate electrode is connected to the reverse drive signal (~Vr) line.

[0210] Furthermore, in the potential holding device according to the ninth embodiment of this disclosure, as shown in (f), the first thin-film transistor T1 can be connected to the applied signal (Vp) line via a first capacitor C1, and the second thin-film transistor T2 and the third thin-film transistor T3, connected in series, can be connected to the junction point therebetween. Each of the first thin-film transistor T1 and the second thin-film transistor T2 has a P-MOS structure, and the third thin-film transistor T3 has an N-MOS structure. The first thin-film transistor T1 is configured such that its gate electrode and second electrode are connected to the junction point. The second thin-film transistor T2 is configured such that its first electrode is connected to the second electrode of the third thin-film transistor T3, its second electrode is connected to the junction point, and its gate electrode is connected to the bias voltage (Vbias) line. The third thin-film transistor T3 is configured such that its first electrode is connected to the low voltage (VL) line, its second electrode is connected to the first electrode of the second thin-film transistor T2, and its gate electrode is connected to the reverse drive signal (~Vr) line.

[0211] Furthermore, in the potential holding device according to the ninth embodiment of this disclosure, as shown in (g), the first thin-film transistor T1 can be connected to the applied signal (Vp) line via the first capacitor C1, and the second thin-film transistor T2 and the third thin-film transistor T3, connected in series, can be connected to the connection point between the first thin-film transistor T1 and the applied signal (Vp) line. Each of the first thin-film transistor T1 and the third thin-film transistor T3 has an N-MOS structure, and the second thin-film transistor T2 has a P-MOS structure. The first thin-film transistor T1 is configured such that its gate electrode and first electrode are connected to each other, and its second electrode is connected to the connection point. The second thin-film transistor T2 is configured such that its first electrode is connected to the second electrode of the third thin-film transistor T3, its second electrode is connected to the connection point, and its gate electrode is connected to the bias voltage (Vbias) line. The third thin-film transistor T3 is configured such that its first electrode is connected to the low voltage (VL) line, its second electrode is connected to the first electrode of the second thin-film transistor T2, and its gate electrode is connected to the reverse drive signal (~Vr) line.

[0212] Furthermore, in the potential holding device according to the ninth embodiment of this disclosure, as shown in (h), diode D can be connected to the applied signal (Vp) line via capacitor C, and the second electrode of the P-MOS thin-film transistor T can be connected to the junction point between diode D and the applied signal (Vp) line. The low voltage (VL) line can be connected to the first electrode of the P-MOS thin-film transistor T, and the drive signal (Vr) line can be connected to its gate electrode. Diode D has a positive direction toward the junction point.

[0213] Furthermore, in the potential holding device according to the ninth embodiment of this disclosure, as shown in (i), the first thin-film transistor T1 can be connected to the applied signal (Vp) line via a capacitor C, and the second thin-film transistor T2 can be connected to the connection point between the first thin-film transistor T1 and the applied signal (Vp) line. Each of the first thin-film transistor T1 and the second thin-film transistor T2 has a P-MOS structure. The first thin-film transistor T1 has a gate electrode and a second electrode connected to the connection point. The second thin-film transistor T2 is configured such that its first electrode is connected to the low voltage (VL) line, its second electrode is connected to the connection point, and its gate electrode is connected to the drive signal (Vr) line.

[0214] Furthermore, in the potential holding device according to the ninth embodiment of this disclosure, as shown in (j), the first thin-film transistor T1 can be connected to the applied signal (Vp) line via a capacitor C, and the second thin-film transistor T2 can be connected to the connection point between the first thin-film transistor T1 and the applied signal (Vp) line. Each of the first thin-film transistor T1 and the second thin-film transistor T2 has a P-MOS structure. The first thin-film transistor T1 is configured such that its gate electrode and first electrode are connected to each other, and its second electrode is connected to the connection point. The second thin-film transistor T2 is configured such that its first electrode is connected to the low voltage (VL) line, its second electrode is connected to the connection point, and its gate electrode is connected to the drive signal (Vr) line.

[0215] The potential holding device 340, configured in various ways as described above, can provide negative charge to a specific node of the Q node or GIP. In this case, the potential holding device 340 can be configured to include a circuit acting as a diode, a capacitor, and a switching circuit. The diode provides a path from the Q2 node to provide negative charge to the specific node. The capacitor is coupled to the negative edge of Vp to provide a path to provide negative charge to the Q2 node. The switching circuit is controlled to conduct based on the Vr signal, such that when the voltage of the Q2 node is greater than the VL voltage, the voltage of the Q2 node can be set closer to the VL voltage.

[0216] When a negative charge is supplied from the potential holding device 340, the signals of the drive signal (Vr) line and the low voltage (VL) line, as well as the GIP signal, are shown in Table 2 below.

[0217] Table 2

[0218]

[0219] Figure 13 This is a diagram illustrating various structures of a potential-maintaining device for providing positive charge according to the tenth embodiment of this disclosure.

[0220] Reference Figure 13 In the potential holding device according to the tenth embodiment of this disclosure, as shown in (a), the first diode D1 can be connected to the applied signal (Vp) line via capacitor C, the second electrode of the switching element SW can be connected to the connection point between the first diode D1 and the applied signal (Vp) line, and the high voltage (VH) line can be connected to the first electrode of the switching element SW via the second diode D2. The drive signal (~Vr) line can be connected to the third electrode of the switching element SW. The first diode D1 has a positive direction from the connection point to the outside, while the second diode D2 has a positive direction from the high voltage (VH) line to the connection point.

[0221] Furthermore, in the potential holding device according to the tenth embodiment of this disclosure, as shown in (b), the first diode D1 can be connected to the applied signal (Vp) line via capacitor C, and the second electrode of the switching element SW can be connected to the connection point between the first diode D1 and the applied signal (Vp) line via the second diode D2. The high voltage (VH) line can be connected to the first electrode of the switching element SW. The drive signal (~Vr) line can be connected to the third electrode of the switching element SW. The first diode D1 has a positive direction from the connection point to the outside, while the second diode D2 has a positive direction from the high voltage (VH) line to the connection point.

[0222] Furthermore, in the potential holding device according to the tenth embodiment of this disclosure, as shown in (c), the first diode D1 can be connected to the applied signal (Vp) line via capacitor C, and the second electrode of the P-MOS thin film transistor T can be connected to the connection point between the first diode D1 and the applied signal (Vp) line via the second diode D2. The high voltage (VH) line can be connected to the first electrode of the P-MOS thin film transistor T. The reverse drive signal (~Vr) line can be connected to the gate electrode of the P-MOS thin film transistor T. The first diode D1 has a forward direction from the connection point to the outside, while the second diode D2 has a forward direction from the high voltage (VH) line to the connection point.

[0223] Furthermore, in the potential holding device according to the tenth embodiment of this disclosure, as shown in (d), the first thin-film transistor T1 can be connected to the applied signal (Vp) line via the first capacitor C1. The second thin-film transistor T2 and the third thin-film transistor T3, connected in series, can be connected to the first connection point between the first thin-film transistor T1 and the applied signal (Vp) line. Each of the first thin-film transistor T1 and the second thin-film transistor T2 has a P-MOS structure, and the third thin-film transistor T3 also has a P-MOS structure. The gate electrode of the first thin-film transistor T1 can be connected to the drive signal (Vr) line via the second capacitor C2, and can also be connected to its first electrode. The second thin-film transistor T2 is configured such that its second electrode is connected to the first connection point and connected to the drive signal (Vr) line via the third capacitor C3, its gate electrode is connected to its second electrode, and its first electrode is connected to the second electrode of the third thin-film transistor T3. The third thin-film transistor T3 is configured such that its first electrode is connected to the high voltage (VH) line, its second electrode is connected to the first electrode of the second thin-film transistor T2, and its gate electrode is connected to the reverse drive signal (~Vr) line.

[0224] Furthermore, in the potential holding device according to the tenth embodiment of this disclosure, as shown in (e), the first thin-film transistor T1 can be connected to the applied signal (Vp) line via a first capacitor C1. A second thin-film transistor T2 and a third thin-film transistor T3 connected in series can be connected to a first connection point between the first thin-film transistor T1 and the applied signal (Vp) line. Each of the first thin-film transistor T1 and the second thin-film transistor T2 has an N-MOS structure, and the third thin-film transistor T3 has a P-MOS structure. The first thin-film transistor T1 has a gate electrode and a second electrode connected to each other. The first connection point can be connected to a second connection point between the gate electrode and the second electrode of the first thin-film transistor T1. Its gate electrode is connected to the reverse drive signal (~Vr) line via a third capacitor C3. The second thin-film transistor T2 is configured such that its first electrode is connected to the second electrode of the third thin-film transistor T3, its second electrode is connected to the first connection point, and its gate electrode is connected to the reverse drive signal (~Vr) line and its first electrode via a second capacitor C2. The third thin-film transistor T3 is configured such that its first electrode is connected to the high voltage (VH) line, its second electrode is connected to the first electrode of the second thin-film transistor T2, and its gate electrode is connected to the reverse drive signal (~Vr) line.

[0225] Furthermore, in the potential holding device according to the tenth embodiment of this disclosure, as shown in (f), the first thin-film transistor T1 can be connected to the applied signal (Vp) line via the first capacitor C1, and the second thin-film transistor T2 and the third thin-film transistor T3, connected in series, can be connected to the junction point therebetween. Each of the first thin-film transistor T1 and the second thin-film transistor T2 has an N-MOS structure, and the third thin-film transistor T3 has a P-MOS structure. The first thin-film transistor T1 is configured such that its gate electrode and second electrode are connected to the junction point. The second thin-film transistor T2 is configured such that its first electrode is connected to the second electrode of the third thin-film transistor T3, its second electrode is connected to the junction point, and its gate electrode is connected to the bias voltage (Vbias) line. The third thin-film transistor T3 is configured such that its first electrode is connected to the high voltage (VH) line, its second electrode is connected to the first electrode of the second thin-film transistor T2, and its gate electrode is connected to the reverse drive signal (~Vr) line.

[0226] Furthermore, in the potential holding device according to the tenth embodiment of this disclosure, as shown in (g), the first thin-film transistor T1 can be connected to the applied signal (Vp) line via the first capacitor C1, and the second thin-film transistor T2 and the third thin-film transistor T3, connected in series, can be connected to the connection point between the first thin-film transistor T1 and the applied signal (Vp) line. Each of the first thin-film transistor T1 and the second thin-film transistor T3 has an N-MOS structure, and the third thin-film transistor T2 has a P-MOS structure. The first thin-film transistor T1 is configured such that its gate electrode and second electrode are connected to the connection point. The second thin-film transistor T2 is configured such that its first electrode is connected to the second electrode of the third thin-film transistor T3, its second electrode is connected to the connection point, and its gate electrode is connected to the bias voltage (Vbias) line. The third thin-film transistor T3 is configured such that its first electrode is connected to the high voltage (VH) line, its second electrode is connected to the first electrode of the second thin-film transistor T2, and its gate electrode is connected to the reverse drive signal (~Vr) line.

[0227] Furthermore, in the potential holding device according to the tenth embodiment of this disclosure, as shown in (h), diode D can be connected to the applied signal (Vp) line via capacitor C, and the second electrode of N-MOS thin-film transistor T can be connected to the junction point between diode D and the applied signal (Vp) line. A high voltage (VH) line can be connected to the first electrode of N-MOS thin-film transistor T, and a drive signal (Vr) line can be connected to its gate electrode. Diode D has a forward direction from the junction point to the outside.

[0228] Furthermore, in the potential holding device according to the tenth embodiment of this disclosure, as shown in (i), the first thin-film transistor T1 can be connected to the applied signal (Vp) line via a capacitor C, and the second electrode of the second thin-film transistor T2 can be connected to the connection point between the first thin-film transistor T1 and the applied signal (Vp) line. The first thin-film transistor T1 has a P-MOS structure, and the second thin-film transistor T2 has an N-MOS structure. The first thin-film transistor T1 has a gate electrode and a first electrode connected to each other, and a second electrode connected to the connection point. The second thin-film transistor T2 is configured such that its first electrode is connected to the high voltage (VH) line, its second electrode is connected to the connection point, and its gate electrode is connected to the drive signal (Vr) line.

[0229] Furthermore, in the potential holding device according to the tenth embodiment of this disclosure, as shown in (j), the first thin-film transistor T1 can be connected to the applied signal (Vp) line via a capacitor C, and the second electrode of the second thin-film transistor T2 can be connected to the connection point between the first thin-film transistor T1 and the applied signal (Vp) line. Each of the first thin-film transistor T1 and the second thin-film transistor T2 has an N-MOS structure. The first thin-film transistor T1 is configured such that its gate electrode and second electrode are connected to the connection point. The second thin-film transistor T2 is configured such that its first electrode is connected to the high voltage (VH) line, its second electrode is connected to the connection point, and its gate electrode is connected to the drive signal (Vr) line.

[0230] The potential holding device 340, configured in various ways as described above, can supply positive charge to the Q node of the GIP. In this case, the potential holding device 340 can be configured to include a circuit acting as a diode, a capacitor, and a switching circuit. The diode provides a path from the Q2 node to supply positive charge to a specific node. The capacitor is coupled to the positive edge of Vp to provide a path to supply positive charge to the Q2 node. The switching circuit is controlled to be turned on based on the Vr signal, so that when the voltage of the Q2 node is lower than the VL voltage, the voltage of the Q2 node can be set to be closer to the VL voltage.

[0231] When a positive charge is supplied from the potential holding device 340, the signals of the drive signal (Vr) line and the low voltage (VL) line, as well as the GIP signal, are shown in Table 3 below.

[0232] Table 3

[0233]

[0234] In one example, in the potential holding device 340, the applied signal Vp generated through the capacitor coupling is a pulse voltage and has a waveform that does not have a positive edge during the period when the reset switch is off.

[0235] Furthermore, the applied signal Vp has a waveform with at least one negative edge during the period when the reset switch is short-circuited. Individual pulse waveforms can be applied to one or more GIPs.

[0236] Furthermore, the applied signal Vp can be an externally applied voltage (SC1, SC2, EM, GCLK (GCLK1, GCLK2), GIP_Start) used in various GIPs present in the display panel. In particular, when the corresponding GIP in the AMOLED is not an emitting GIP, the emission control signal for controlling OLED emission in the control pixel can be applied to the Vp line.

[0237] In addition, the output of GIPs from levels before or after the GIP can be applied to the Vp line. The output of other GIPs used in a pixel can also be applied to the Vp line.

[0238] Furthermore, the potential holding device 340 can be implemented as a number of process elements such as LTPS, oxide and a-Si, or it can be implemented as a process element corresponding to a combination of various processes.

[0239] In addition, the potential holding device 340 can be applied to the scan driver of an active matrix display such as LCD, AMOLED and QNED.

[0240] Furthermore, the potential holding device 340 can be applied to electronic devices such as mobile phones, laptops, TVs, monitors, smartwatches, and automotive displays including displays with corresponding GIPs, the GIPs including potential holding devices.

[0241] As described above, in the display device 100 according to this disclosure, even when performing low-speed operation for a long time, the voltage of the Q node in each gate shift register of the gate driver circuit does not rise, but remains at a voltage below a predefined level.

[0242] Therefore, according to embodiments of this disclosure, the output voltage at the output node of the gate shift register of the gate driver circuit 140 will not be damaged due to leakage and noise during low-speed driving, thereby preventing image quality defects.

[0243] As described above, according to this disclosure, gate driver circuits and display devices including gate driver circuits can be implemented, wherein each gate shift register has a potential holding device for a Q node connected between its input and output, such that the voltage of the Q node is stably maintained below a predefined level even during long periods of low-speed operation.

[0244] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to these embodiments. Various modifications can be made to the present disclosure without departing from the technical spirit of the present disclosure. Therefore, the embodiments disclosed herein are not intended to limit the technical spirit of the present disclosure, but rather to describe it, and the scope of the technical spirit of the present disclosure is not limited by the embodiments. Therefore, it should be understood that the above embodiments are illustrative and not restrictive in all respects. The scope of protection of the present disclosure should be interpreted by the claims, and all technical ideas within the scope of the present disclosure should be interpreted as including within the scope of the present disclosure.

Claims

1. A display panel, comprising: Multiple stages, selectively connected to lines provided with multiple clock signals, wherein the multiple stages are configured to sequentially output scan pulses. Each of the plurality of levels includes: An input unit is connected to each of the start signal line and the clock signal line; Q-node controller, which is connected to the input unit via Q2 node; Output unit, the output unit being connected to the Q node controller via a Q node; A potential holding device, the potential holding device being connected to the Q node; A first capacitor, connected to the Q node and the output terminal of the output unit and disposed between the Q node and the output terminal of the output unit; and A QB node controller, one side of which is connected to the output unit via a QB node, and the other side of which is connected to the output unit via a gate turn-off signal line. The potential holding device is configured to operate based on a drive signal to maintain the potential of the Q node at a value below a predefined level. The potential holding device includes: A thin-film transistor having a gate electrode connected to a drive signal line, a first electrode connected to a low signal line, and a second electrode connected to a contact point between the Q node and the first capacitor; A diode, the diode being connected to the contact point between the Q node and the first capacitor and the second electrode of the thin-film transistor, and disposed between the contact point and the second electrode of the thin-film transistor; and A second capacitor is connected to the second electrode of the thin-film transistor, wherein the applied signal line is connected to the second electrode of the thin-film transistor through the second capacitor.

2. The display panel of claim 1, wherein, The output unit includes: A pull-up transistor, the pull-up transistor being used to output a scan signal to an output terminal based on the voltage level of the Q node; and A pull-down transistor is used to provide a gate turn-off signal to the output terminal based on the voltage level of the QB node.

3. The display panel of claim 2, wherein, The pull-up transistor includes a first thin-film transistor having a gate electrode connected to the Q node, a first electrode connected to a gate conduction signal line, and a second electrode connected to the output terminal. The pull-down transistor includes a second thin-film transistor, which has a gate electrode connected to the QB node, a first electrode connected to the output terminal, and a second electrode connected to the gate turn-off signal line.

4. The display panel of claim 3, wherein, The Q node is connected to the gate electrode of the first thin-film transistor, and the output terminal is connected to the second electrode of the first thin-film transistor.

5. The display panel according to claim 3, wherein, The input unit includes a third thin-film transistor having a gate electrode connected to the clock signal line, a first electrode connected to the start signal line, and a second electrode connected to the Q2 node.

6. The display panel according to claim 1, wherein, The Q-node controller includes a TFT active anti-backflow thin-film transistor, which has a gate electrode connected to a gate conduction signal line, a first electrode connected to the Q-node, and a second electrode connected to the Q2 node.

7. The display panel according to claim 1, wherein, The QB node controller includes: A fifth thin-film transistor has a first electrode connected to the clock signal line, a gate electrode connected to the clock signal line via a third capacitor, and a second electrode connected to the QB node; A fourth thin-film transistor, the fourth thin-film transistor having a gate electrode connected to the start signal line, a first electrode connected to the gate electrode of the fifth thin-film transistor, and a second electrode connected to the output unit via the gate turn-off signal line; and A sixth thin-film transistor having a gate electrode connected to the Q2 node, a first electrode connected to the QB node, and a second electrode connected to the output unit via the gate turn-off signal line.

8. The display panel according to claim 1, wherein, The QB node controller includes: A fourth thin-film transistor, the fourth thin-film transistor having a first electrode connected to a gate conduction signal line, a second electrode connected to the QB node, and a gate electrode connected to the Q node; and A fifth thin-film transistor having a first electrode connected to the QB node, a second electrode connected to the output terminal via the gate turn-off signal line, and a gate electrode connected to the Q2 node.

9. A display panel, comprising: Multiple stages, selectively connected to lines provided with multiple clock signals, wherein the multiple stages are configured to sequentially output scan pulses. Each of the plurality of levels includes: An input unit is connected to each of the start signal line and the clock signal line; Q-node controller, which is connected to the input unit via Q2 node; Output unit, the output unit being connected to the Q node controller via a Q node; A potential holding device, the potential holding device being connected to the Q node; A first capacitor, connected to the Q node and the output terminal of the output unit and disposed between the Q node and the output terminal of the output unit; and A QB node controller, one side of which is connected to the output unit via a QB node, and the other side of which is connected to the output unit via a gate turn-off signal line. The potential holding device is configured to operate based on an applied signal to maintain the potential of the Q node at a value below a predefined level. The potential holding device includes: An eighth thin-film transistor, the eighth thin-film transistor having a first electrode connected to the Q node, a second electrode connected to an applied signal line via a second capacitor, and a gate electrode connected to the second electrode of the eighth thin-film transistor; and A seventh thin-film transistor having a first electrode connected to the second electrode of the eighth thin-film transistor, a second electrode connected to the gate conduction signal line, and a gate electrode connected to the output terminal.

10. A display panel, comprising: Multiple stages, selectively connected to lines provided with multiple clock signals, wherein the multiple stages are configured to sequentially output scan pulses. Each of the plurality of levels includes: An input unit is connected to each of the start signal line and the clock signal line; Q-node controller, which is connected to the input unit via Q2 node; Output unit, the output unit being connected to the Q node controller via a Q node; A potential holding device, the potential holding device being connected to the Q node; and A QB node controller, one side of which is connected to the output unit via the QB node, and the other side of which is connected to the output unit via a gate turn-off signal line. The potential holding device is configured to operate based on an applied signal to maintain the potential of the Q node at a value below a predefined level. The potential holding device includes: An eighth thin-film transistor, the eighth thin-film transistor having a first electrode connected to the Q node, a second electrode connected to an applied signal line via a second capacitor, and a gate electrode connected to the second electrode of the eighth thin-film transistor; and A seventh thin-film transistor having a first electrode connected to the second electrode of the eighth thin-film transistor, a second electrode connected to the gate conduction signal line, and a gate electrode connected to the output terminal of the output unit.

11. A display panel, comprising: Multiple stages, selectively connected to lines provided with multiple clock signals, wherein the multiple stages are configured to sequentially output scan pulses. Each of the plurality of levels includes: An input unit is connected to each of the start signal line and the clock signal line; A Q-node controller is connected to the input unit via a Q2 node and operates based on a gate-on signal; Output unit, the output unit being connected to the Q node controller via a Q node; A QB node controller, one side of which is connected to the output unit via a QB node, and the other side of which is connected to the output unit via a gate turn-off signal line; and A potential holding device, which is connected to the Q node, is provided. The potential holding device is configured to operate based on an applied signal to maintain the potential of the Q node at a value below a predefined level. The potential holding device includes: An eighth thin-film transistor, the eighth thin-film transistor having a first electrode connected to the Q node, a second electrode connected to an applied signal line via a second capacitor, and a gate electrode connected to the second electrode of the eighth thin-film transistor; and A seventh thin-film transistor having a first electrode connected to the second electrode of the eighth thin-film transistor, a second electrode connected to the gate conduction signal line, and a gate electrode connected to the output terminal of the output unit.

12. A display panel, comprising: Multiple stages, selectively connected to lines provided with multiple clock signals, wherein the multiple stages are configured to sequentially output scan pulses. Each of the plurality of levels includes: An input unit is connected to each of the start signal line and the clock signal line; Q-node controller, which is connected to the input unit via Q2 node; Output unit, the output unit being connected to the Q node controller via a Q node; A QB node controller, one side of which is connected to the output unit via a QB node, and the other side of which is connected to the output unit via a gate turn-off signal line; and A potential holding device, one side of which is connected to the Q node and the other side of which is connected to the output terminal of the output unit. The potential holding device is configured to operate based on a gate on signal to maintain the potential of the Q node at a value below a predefined level. The potential holding device includes: A sixth thin-film transistor, the sixth thin-film transistor having a first electrode connected to the Q node, a second electrode connected to the output terminal of the output unit via a second capacitor, and a gate electrode connected to its second electrode; and A seventh thin-film transistor having a first electrode connected to the second electrode of the sixth thin-film transistor, a second electrode connected to the gate conduction signal line, and a gate electrode connected to the output terminal.

13. A display panel, comprising: Multiple stages, selectively connected to lines provided with multiple clock signals, wherein the multiple stages are configured to sequentially output scan pulses. Each of the plurality of levels includes: An input unit is connected to each of the start signal line and the clock signal line; Q-node controller, which is connected to the input unit via Q2 node; Output unit, the output unit being connected to the Q node controller via a Q node; A QB node controller, one side of which is connected to the output unit via a QB node, and the other side of which is connected to the output unit via a gate turn-off signal line; and A potential holding device is provided, with one side connected to the Q node, the other side connected to the QB node, and another side connected to the input unit. The potential holding device is configured to operate based on the voltage level of the Q node to maintain the potential of the Q node at a value below a predefined level. The potential holding device includes: A fourth thin-film transistor has a first electrode connected to a gate conduction signal line, a gate electrode connected to the Q node, and a second electrode connected to a fifth thin-film transistor. The fifth thin-film transistor has a first electrode connected to the second electrode of the fourth thin-film transistor, a gate electrode connected to its first electrode, and a second electrode connected to the input unit via a second capacitor; and A sixth thin-film transistor having a first electrode connected to a second electrode of the fifth thin-film transistor, a second electrode connected to the QB node, and a gate electrode connected to its first electrode.

14. The display panel according to claim 13, wherein, The QB node controller includes: A seventh thin-film transistor having a first electrode connected to the QB node, a second electrode connected to the output unit via the gate turn-off signal line, and a gate electrode connected to the Q2 node.

15. A display device, comprising: A display panel having a plurality of gate lines; A gate driver circuit comprising multiple stages selectively connected to lines provided with multiple clock signals, wherein the multiple stages are configured to sequentially output scan pulses, wherein each of the multiple stages includes: An input unit is connected to each of the start signal line and the clock signal line; Q-node controller, which is connected to the input unit via Q2 node; Output unit, the output unit being connected to the Q node controller via a Q node; A QB node controller, one side of which is connected to the output unit via a QB node, and the other side of which is connected to the output unit via a gate turn-off signal line; A first capacitor, connected to the Q node and the output terminal of the output unit and disposed between the Q node and the output terminal of the output unit; and A potential holding device connected to the Q node, wherein the potential holding device is configured to operate based on a drive signal to maintain the potential of the Q node at a value below a predefined level. The gate driver circuit applies the scan pulse to the plurality of gate lines through the output unit; The potential holding device includes: A thin-film transistor having a gate electrode connected to a drive signal line, a first electrode connected to a low signal line, and a second electrode connected to a contact point between the Q node and the first capacitor; A diode, the diode being connected to the contact point between the Q node and the first capacitor and the second electrode of the thin-film transistor, and disposed between the contact point and the second electrode of the thin-film transistor; and A second capacitor is connected to the second electrode of the thin-film transistor, wherein the applied signal line is connected to the second electrode of the thin-film transistor through the second capacitor; A data driver circuit, the data driver circuit being used to apply data signals to the display panel; and A timing controller is used to control the data driver circuit and the gate driver circuit.

Images