Display panel, display device and test method of display panel

Abstract

The application provides a display panel, a display device and a test method of the display panel. The display panel comprises a non-display area, a shift register located in the non-display area, the shift register comprising an output transistor, the output transistor comprising a signal driving end, a signal input end and a signal output end, the signal output end being an output end of the shift register, and a scanning signal test unit located in the non-display area, the scanning signal test unit being composed of first test pads and second test pads which are spaced apart, the first test pads being electrically connected to the signal driving end of the output transistor, and the second test pads being electrically connected to the signal input end of the output transistor. The application at least solves the problem that the display panel in the prior art is difficult to realize narrow frame.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel, a display device, and a method for testing the display panel. Background Technology

[0002] Display panels are currently widely used in portable electronic products such as mobile phones and PDAs. Driven by market competition, display devices that are lighter, have better display effects, and are cheaper are gaining increasing popularity.

[0003] In the manufacturing process of thin-film transistor liquid crystal display panels, after the display panel is completed, its performance needs to be tested. A visual text pad (VT pad) is set on the display panel. The performance of the panel is tested by inputting test signals to the VT pad on the panel. This test method is called VT test. Currently, VT test uses the probe test method. The VT pad is designed at the step of the panel, and the voltage signal of the test screen is input through the probe.

[0004] The VT pad includes STV pad, CKB pad, CK pad, DIR pad, Reset pad, VGL pad, Gout pad, and source control signal pad. There are many pads, and the spacing between two adjacent VT pads is also required, so it occupies a large area on the panel, which is not conducive to achieving a narrow bezel. Summary of the Invention

[0005] The main objective of this application is to provide a display panel, a display device, and a testing method for the display panel, so as to at least solve the problem that it is difficult to achieve narrow bezels in the display panel in the prior art.

[0006] To achieve the above objectives, according to one aspect of this application, a display panel is provided, comprising:

[0007] The non-display area, specifically, may be provided with a binding area and multiplexers, etc. In practical applications, the display panel also includes a display area surrounded by the non-display area. The display area includes multiple scan lines and multiple data lines, and the scan lines intersect with the data lines.

[0008] A shift register, located in the non-display area, includes an output transistor. Specifically, the output transistor can be a field-effect transistor, a transistor, a thyristor, or other three-terminal semiconductor switching transistor. The output transistor includes a signal drive terminal, a signal input terminal, and a signal output terminal. The signal output terminal is the output terminal of the shift register. When the output transistor is a field-effect transistor, the signal drive terminal is the gate of the output transistor, the signal input terminal is the source of the output transistor, and the signal output terminal is the drain of the output transistor.

[0009] The scan signal test unit, also known as the gate drive circuit, is located in the non-display area. The scan signal test unit consists of a first test pad and a second test pad that are spaced apart. In specific applications, the first test pad and the second test pad can be rectangular pads, but are not limited to rectangular pads; they can also be pads of any other suitable shape. The first test pad is electrically connected to the signal drive terminal of the output transistor, and the second test pad is electrically connected to the signal input terminal of the output transistor. Voltage signals are input to the first test pad and the second test pad using tools such as test probes.

[0010] According to another aspect of this application, a display device is also provided, comprising: any of the aforementioned display panels.

[0011] According to another aspect of this application, a testing method for the aforementioned display panel is also provided, comprising:

[0012] At least a test voltage is input to the first test pad and the second test pad so that the display panel displays the test screen.

[0013] By applying the technical solution of this application, in the non-display area of ​​the display panel, the scan signal test unit consists of only two test pads: a first test pad and a second test pad. The first test pad provides voltage to the signal drive terminal of the output transistor in the shift register to control the switching state of the output transistor. The second test pad provides voltage to the signal input terminal of the output transistor to control the output transistor to output the corresponding scan signal, thus achieving control over the switching state and output signal of the output transistor in the shift register. Compared to the prior art, which uses multiple (three or more) test pads to control the shift register to generate the scan signal, resulting in multiple pads occupying a large area of ​​the display panel and hindering the achievement of a narrow bezel, this application reduces the multiple test pads used to control the shift register to generate the scan signal to two. Without affecting the output of the scan signal from the output transistor in the shift register, it effectively reduces the space occupied by the test pads in the non-display area, thereby enabling a narrow bezel. Attached Figure Description

[0014] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0015] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of this application is shown;

[0016] Figure 2 A schematic diagram of the structure of another display panel provided in an embodiment according to this application is shown;

[0017] Figure 3 A schematic diagram of an equivalent circuit of a shift register provided in an embodiment of this application is shown;

[0018] Figure 4 A schematic diagram of an equivalent circuit of a shift register provided in an embodiment of this application is shown;

[0019] Figure 5 An equivalent circuit diagram of another shift register provided in an embodiment of this application is shown;

[0020] Figure 6 A schematic diagram of an equivalent circuit of a shift register provided in an embodiment of this application is shown;

[0021] Figure 7 A schematic diagram of the structure of a shift register provided in an embodiment of this application is shown;

[0022] Figure 8 A schematic diagram of the structure of another display panel provided in an embodiment according to this application is shown;

[0023] Figure 9 A test flowchart of a display panel provided in an embodiment of this application is shown;

[0024] Figure 10 An input voltage timing diagram of a test pad provided in an embodiment of this application is shown;

[0025] Figure 11 A test flowchart of another display panel provided according to an embodiment of this application is shown.

[0026] The above figures include the following reference numerals:

[0027] 10. Non-display area; 100. Target border; 11. Display area; 20. Shift register; 21. Output transistor; 22. First transistor; 23. Second transistor; 24. Third transistor; 25. Fourth transistor; 26. Fifth transistor; 27. Sixth transistor; 28. Seventh transistor; 29. ​​Eighth transistor; 200. First capacitor structure; 201. Second capacitor structure; 202. Shift register group; 30. Scan signal test unit; 31. First test pad; 32. Second test pad; 40. Source drive circuit; 50. Third test pad; 51. First sub-pad; 52. Second sub-pad; 60. Bonding pad. Detailed Implementation

[0028] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0029] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0030] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0032] As described in the background section, it is difficult to achieve narrow bezels in existing display panels. To address this issue, embodiments of this application provide a display panel, a display device, and a method for testing the display panel.

[0033] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0034] Embodiments of this application provide a display panel, such as Figure 1 As shown, the above display panel includes:

[0035] The non-display area 10 may specifically include a binding area and multiplexers. In practical applications, the display panel may also include a display area 11 surrounded by the non-display area 10. The display area includes multiple scan lines and multiple data lines, and the scan lines intersect with the data lines.

[0036] Shift register 20 is located in the aforementioned non-display area 10, such as Figure 3 or Figure 5 As shown, the shift register 20 includes an output transistor 21. Specifically, the output transistor can be a field-effect transistor, a transistor, a thyristor, or other three-terminal semiconductor switching transistor. The output transistor 21 includes a signal driving terminal, a signal input terminal VGL, and a signal output terminal Gn. The signal output terminal Gn is the output terminal of the shift register. When the output transistor is a field-effect transistor, the signal driving terminal is the gate of the output transistor, the signal input terminal VGL is the source of the output transistor, and the signal output terminal Gn is the drain of the output transistor.

[0037] The scan signal test unit 30, also known as the gate drive circuit, is located in the non-display area 10. The scan signal test unit 30 is composed of a first test pad 31 and a second test pad 32 spaced apart. In specific applications, the first test pad and the second test pad can be rectangular pads. Of course, they are not limited to rectangular pads and can be pads of any other suitable shape. The first test pad 31 is electrically connected to the signal drive terminal of the output transistor 21, and the second test pad 32 is electrically connected to the signal input terminal VGL of the output transistor 21. A voltage signal is input to the first test pad and the second test pad through a test probe or other tool.

[0038] Through the above-described technical solution of this application, in the non-display area of ​​the display panel, the scan signal test unit consists of only two test pads: a first test pad and a second test pad. The first test pad provides voltage to the signal drive terminal of the output transistor in the shift register to control the switching state of the output transistor. The second test pad provides voltage to the signal input terminal of the output transistor to control the output transistor to output the corresponding scan signal, thus achieving control over the switching state and output signal of the output transistor in the shift register. Compared to the prior art, which uses multiple (three or more) test pads to control the shift register to generate the scan signal, resulting in multiple pads occupying a large area of ​​the display panel and hindering the achievement of a narrow bezel, this application reduces the multiple test pads used to control the shift register to generate the scan signal to two. Without affecting the output of the scan signal from the output transistor in the shift register, it effectively reduces the space occupied by the test pads in the non-display area, thereby achieving a narrow bezel.

[0039] Specifically, this application reduces the number of existing test pads electrically connected to shift registers for controlling scan signals, thereby reducing the area occupied by the test pads in the non-display area.

[0040] Specifically, since probes need to contact the test pads, to accommodate the size of the test probes and the spacing requirements between the two probes in existing technologies, the lengths of the first and second test pads are generally no less than 900 μm, the widths are no less than 600 μm, and the spacing between the first and second test pads is no less than 300 μm. Of course, in subsequent practical applications, the size and spacing of the test pads can be adjusted according to the size of the test probes and changes in the spacing between adjacent probes.

[0041] In practical applications, to prevent unrepairable or non-shipping defective display panels from flowing into subsequent module processing, defects can only be detected after driver chips or flip-chip films are bonded to the display panel. Due to process limitations, this results in waste of materials such as driver circuits and FPCs. However, the display panel described in this application, because it is equipped with the first test pad and the second test pad, allows for VT testing or array testing to be introduced into the display panel before bonding, thereby avoiding the material waste caused by testing defective products after bonding.

[0042] In one alternative approach, such as Figure 1 As shown, the above display panel also includes:

[0043] The source driving circuit 40, also called the data driving circuit, is used to provide data signals to the data lines of the display panel. The source driving circuit 40 may include a driving transistor. Specifically, the driving transistor may be a field-effect transistor, a transistor, a thyristor, or other three-terminal semiconductor switching transistor. The driving transistor includes a signal input terminal and a signal output terminal. The signal output terminal of the driving transistor is electrically connected to the data line. When the driving transistor is a field-effect transistor, the signal input terminal is the source of the driving transistor, and the signal output terminal is the drain of the driving transistor.

[0044] The data signal testing unit is located in the non-display area 10. The data signal testing unit includes a third test pad 50, which is electrically connected to the signal input terminal of the source drive circuit 40. A voltage signal is input to the third test pad through a test probe or other tool.

[0045] In the above embodiments, the display panel includes a third test pad electrically connected to the signal driving terminal of the source driving circuit. A voltage signal is sent to the signal input terminal of the source driving circuit through the third test pad to control the source driving circuit to output the corresponding RGB signal, thereby realizing the control of the signal line and realizing the display control of the display panel.

[0046] To further achieve drive control of the display panel data lines, and thus further achieve screen display control of the display panel, so as to facilitate VT testing of the display panel based on the displayed screen, according to another exemplary embodiment of this application, the signal input terminal of the above-mentioned source drive circuit includes the input terminal of the common data line and the input terminal of the pixel data line, such as... Figure 1 As shown, the third test pad 50 includes a first sub-pad 51 and a second sub-pad 52 spaced apart, wherein the first sub-pad 51 is electrically connected to the input end of the common data line, and the second sub-pad 52 is electrically connected to the input end of the data line of the pixel.

[0047] In practical applications, all of the aforementioned test pads in this application are placed on one or both sides of the long side of the bonding pad. Figure 1 An exemplary embodiment is shown in which the first test pad 31 and the second test pad 32 are located on one side of the bonding pad 60, and the first sub-pad 51 and the second sub-pad 52 are located on the other side of the bonding pad 60. (Except for...) Figure 1 In addition to the illustrated embodiments, those skilled in the art can flexibly set the positional relationship between the first test pad, the second test pad, and the third test pad according to actual arrangement requirements, for example, Figure 2This illustrates a scenario where the first test pad, the second test pad, and the third test pad are all positioned on the same side of the bonding pad.

[0048] The aforementioned pixels may include only one color of sub-pixels: red, green, and blue, or they may include sub-pixels of multiple colors. Specifically, for VT testing of a full-color display panel, in this application, the aforementioned pixels include red, green, and blue sub-pixels, and there are three corresponding second sub-pads. These three second sub-pads are electrically connected to the input terminals of the data lines of the red, green, and blue sub-pixels, respectively. The second sub-pad electrically connected to the input terminal of the data line of the red sub-pixel can be called the red pixel pad, the second sub-pad electrically connected to the input terminal of the data line of the green sub-pixel can be called the green pixel pad, and the second sub-pad electrically connected to the input terminal of the data line of the blue sub-pixel can be called the blue pixel pad. By inputting preset voltage signals to the red, green, and blue pixel pads, the display of images such as red, green, blue, and white can be achieved.

[0049] It should be noted that the above display panel includes multiple red sub-pixels, multiple green sub-pixels, and multiple blue sub-pixels. The red pixel pads are electrically connected to all of the red sub-pixels, the green pixel pads are electrically connected to all of the green sub-pixels, and the blue pixel pads are electrically connected to all of the blue sub-pixels.

[0050] Because probes are required to contact the test pads, to accommodate the size of the test probes and the spacing requirements between the two probes in existing technologies, the length of the first sub-pad and each of the second sub-pads is generally not less than 900 μm, the width of the first sub-pad and each of the second sub-pads is not less than 600 μm, and the spacing between the first sub-pad and the second sub-pad, and the spacing between the second sub-pads, is not less than 300 μm. Of course, in subsequent practical applications, the size and spacing of the test pads can be adjusted according to the size of the test probes and changes in the spacing between adjacent probes.

[0051] In practical applications, different types of display panels employ different shift register circuit structures, and the connection relationships of the output transistors within these shift registers also vary. The following two embodiments illustrate this further.

[0052] In one embodiment, the display panel further includes a first substrate, a second substrate, and a touch electrode layer, wherein:

[0053] The first substrate and the second substrate are disposed opposite to each other. In practical applications, the first substrate can be one of an array substrate and a color filter substrate, and the second substrate can be the other of the array substrate and the color filter substrate. The materials of the first substrate and the second substrate are both glass substrates, and their materials may include silicon dioxide.

[0054] The aforementioned touch electrode layer is located between the aforementioned first substrate and the aforementioned second substrate. In other words, the aforementioned display panel is a panel in which the touch panel function is embedded in the liquid crystal pixels, also known as an in-cell panel.

[0055] In the case where the display panel is an in-cell panel, the circuit structure of the shift register is exemplarily as follows: Figure 3 As shown, in addition to the aforementioned output transistor, the shift register also includes:

[0056] The first transistor 22 includes a control terminal, a first terminal, and a second terminal. The control terminal of the first transistor 22 is used to receive a first trigger signal STV, and the first terminal of the first transistor is used to receive a first scan direction signal DIR1. The first trigger signal DIR1 is provided to the first transistor to control the first transistor to turn on when the shift register is reset and is about to start working. The first scan direction signal DIR1 is one of a gate-on signal and a gate-off signal, and it is a DC signal. The scan direction of the shift register is controlled by the first scan direction signal DIR1.

[0057] The second transistor 23 includes a control terminal, a first terminal, and a second terminal. The control terminal of the second transistor 23 is used to receive a second trigger signal Gn+1, and the second trigger signal Gn+1 is used to control the switching of the second transistor. The first terminal of the second transistor 23 is electrically connected to the second terminal of the first transistor 22. The second terminal of the second transistor 23 is used to receive a second scan direction signal DIR2. The second scan direction signal DIR2 is the other of a gate-on signal and a gate-off signal, and it is a DC signal. The scan direction of the shift register is controlled by the second scan direction signal DIR2.

[0058] The third transistor 24 includes a control terminal, a first terminal, and a second terminal. The first terminal of the third transistor 24 is electrically connected to the first terminal of the second transistor 23, and the second terminal of the third transistor 24 is electrically connected to the signal input terminal of the output transistor 21.

[0059] The fourth transistor 25 includes a control terminal, a first terminal, and a second terminal. The control terminal of the fourth transistor 25 is electrically connected to the second terminal of the first transistor 22. The first terminal of the fourth transistor 25 is electrically connected to the control terminal of the third transistor 24. The second terminal of the fourth transistor 25 is electrically connected to the signal input terminal of the output transistor 21.

[0060] The fifth transistor 26 includes a control terminal, a first terminal, and a second terminal. The control terminal of the fifth transistor 26 is electrically connected to the second terminal of the first transistor 22. The first terminal of the fifth transistor 26 is used to receive a first clock signal CKB. The first clock signal CKB is provided after the first scan direction signal DIR1 is provided. The number of the first clock signals CKB is determined according to the phase. For example, when the phase is 4 phases, the number of the first clock signals CKB is 1, and when the phase is 8 phases, the number of the first clock signals CKB is 2. The second terminal of the fifth transistor 26 is electrically connected to the signal output terminal of the output transistor 21.

[0061] The sixth transistor 27 includes a control terminal, a first terminal, and a second terminal. The control terminal of the sixth transistor 27 is electrically connected to the control terminal of the third transistor 24. The first terminal of the sixth transistor 27 is electrically connected to the signal output terminal of the output transistor 21. The second terminal of the sixth transistor 27 is electrically connected to the signal input terminal of the output transistor 21.

[0062] The seventh transistor 28 includes a control terminal, a first terminal, and a second terminal. The control terminal of the seventh transistor 28 is used to receive the second clock signal CK. After providing the first scan direction signal DIR1, the second clock signal CK is provided. The number of the second clock signals CK is determined by the phase. For example, when the phase is 4-phase, the number of the second clock signals CK is 1, and when the phase is 8-phase, the number of the second clock signals CK is 2. Normally, the first clock signal CKB and the second clock signal CK are complementary signals, that is, when one is low, the other is high. However, after adjusting the duty cycle, these two signals are no longer completely complementary. The first terminal of the seventh transistor 28 is electrically connected to the signal output terminal of the output transistor 21, and the second terminal of the seventh transistor 28 is electrically connected to the signal input terminal of the output transistor 21.

[0063] The eighth transistor 29 includes a control terminal, a first terminal, and a second terminal. The first terminal of the eighth transistor 29 is electrically connected to the second terminal of the first transistor 22. The second terminal of the eighth transistor 29 is electrically connected to the signal input terminal of the output transistor 21. The control terminal of the eighth transistor 29 is electrically connected to the signal driving terminal of the output transistor 21.

[0064] The first capacitor structure 200 includes a first terminal and a second terminal. The first terminal of the first capacitor structure 200 is electrically connected to the control terminal of the fifth transistor 26, and the second terminal of the first capacitor structure 200 is electrically connected to the signal output terminal of the output transistor 21.

[0065] like Figure 3 As shown, in the circuit structure described above, the first trigger signal DIR1 controls the first transistor 22 to turn on, charging the PU point; the second trigger signal DIR2 controls the second transistor 23 to turn on, discharging the PU point; the third transistor 24 is used to maintain the voltage of the PD point when it is turned on; the fourth transistor 25 is used to lower the voltage of the PD point; the sixth transistor 27 and the seventh transistor 28 are used to maintain the voltage at the signal output terminal of the output transistor 21; the eighth transistor is used to lower the voltage of the PU point when a reset signal Reset is received; and the first capacitor structure is used to increase the voltage holding capability of the fifth transistor 26.

[0066] It should be noted that this application only exemplifies one circuit structure corresponding to the shift register when the display panel is an in-cell panel, and does not constitute a limitation on the circuit structure of the shift register. In addition to the circuit structure described above, the shift register can also adopt other circuit structures, such as other 7T2C constructions or 9T2C constructions, etc. Those skilled in the art can flexibly adjust the number of transistors or the connection relationship of transistors in the above part according to the functional requirements of the shift register.

[0067] In addition to the structures mentioned above, such as Figure 4 As shown, the shift register further includes a second capacitor structure 201, which includes a first terminal and a second terminal. The first terminal of the second capacitor structure 201 is electrically connected to the first terminal of the fourth transistor 25, and the second terminal of the second capacitor structure 201 is electrically connected to the first terminal of the fifth transistor 26. This second capacitor structure prevents excessive current from flowing between the first terminal of the fifth transistor and the second terminal of the fourth transistor, ensuring the safe operation of the shift register.

[0068] Specifically, the first capacitor structure and the second capacitor structure described above can each include one capacitor, or they can include multiple capacitors connected in series and parallel. The specific configuration can be determined based on actual needs or circumstances, using one or more capacitors connected in series and parallel to form the first and second capacitor structures.

[0069] When the display panel is an In-cell panel, the above signal driving terminal is the switch control signal terminal Goff of the shift register, that is, the above signal driving terminal is the switch control signal terminal Goff of the shift register in the In-cell panel.

[0070] In another embodiment, the display panel further includes a first substrate and a second substrate disposed opposite to each other. In practical applications, the first substrate can be one of an array substrate and a color filter substrate, and the second substrate can be the other of the array substrate and the color filter substrate. The material of the first substrate and the second substrate are both glass substrates, and their materials may include silicon dioxide. Furthermore, the display panel does not include a touch electrode layer located between the first substrate and the second substrate. That is to say, the display panel is not a panel in which touch panel functions are embedded in liquid crystal pixels, i.e., the display panel is a non-In-cell panel.

[0071] In the case where the display panel is an in-cell panel, the circuit structure of the shift register is exemplarily as follows: Figure 5 As shown, in addition to the aforementioned output transistor, the shift register also includes:

[0072] The first transistor 22 includes a control terminal, a first terminal, and a second terminal. The control terminal of the first transistor 22 is used to receive a first trigger signal STV, and the first terminal of the first transistor is used to receive a first scan direction signal DIR1. The first trigger signal DIR1 is provided to the first transistor to control the first transistor to turn on when the shift register is reset and is about to start working. The first scan direction signal DIR1 is one of a gate-on signal and a gate-off signal, and it is a DC signal. The scan direction of the shift register is controlled by the first scan direction signal DIR1.

[0073] The second transistor 23 includes a control terminal, a first terminal, and a second terminal. The control terminal of the second transistor 23 is used to receive a second trigger signal Gn+1, and the second trigger signal Gn+1 is used to control the switching of the second transistor. The first terminal of the second transistor 23 is electrically connected to the second terminal of the first transistor 22. The second terminal of the second transistor 23 is used to receive a second scan direction signal DIR2. The second scan direction signal DIR2 is the other of a gate-on signal and a gate-off signal, and it is a DC signal. The scan direction of the shift register is controlled by the second scan direction signal DIR2.

[0074] The third transistor 24 includes a control terminal, a first terminal, and a second terminal. The first terminal of the third transistor 24 is electrically connected to the first terminal of the second transistor 23, and the second terminal of the third transistor 24 is electrically connected to the signal input terminal of the output transistor 21.

[0075] The fourth transistor 25 includes a control terminal, a first terminal, and a second terminal. The control terminal of the fourth transistor 25 is electrically connected to the second terminal of the first transistor 22. The first terminal of the fourth transistor 25 is electrically connected to the control terminal of the third transistor 24. The second terminal of the fourth transistor 25 is electrically connected to the signal input terminal of the output transistor 21.

[0076] The fifth transistor 26 includes a control terminal, a first terminal, and a second terminal. The control terminal of the fifth transistor 26 is electrically connected to the second terminal of the first transistor 22. The first terminal of the fifth transistor 26 is used to receive a first clock signal CKB. The first clock signal CKB is provided after the first scan direction signal DIR1 is provided. The number of the first clock signals CKB is determined according to the phase. For example, when the phase is 4 phases, the number of the first clock signals CKB is 1, and when the phase is 8 phases, the number of the first clock signals CKB is 2. The second terminal of the fifth transistor 26 is electrically connected to the signal output terminal of the output transistor 21.

[0077] The sixth transistor 27 includes a control terminal, a first terminal, and a second terminal. The control terminal of the sixth transistor 27 is electrically connected to the control terminal of the third transistor 24. The first terminal of the sixth transistor 27 is electrically connected to the signal output terminal of the output transistor 21. The second terminal of the sixth transistor 27 is electrically connected to the signal input terminal of the output transistor 21.

[0078] The seventh transistor 28 includes a control terminal, a first terminal, and a second terminal. The control terminal of the seventh transistor 28 is used to receive the second clock signal CK. After providing the first scan direction signal DIR1, the second clock signal CK is provided. The number of the second clock signals CK is determined by the phase. For example, when the phase is 4-phase, the number of the second clock signals CK is 1, and when the phase is 8-phase, the number of the second clock signals CK is 2. Normally, the first clock signal CKB and the second clock signal CK are complementary signals, that is, when one is low, the other is high. However, after adjusting the duty cycle, these two signals are no longer completely complementary. The first terminal of the seventh transistor 28 is electrically connected to the signal output terminal of the output transistor 21, and the second terminal of the seventh transistor 28 is electrically connected to the signal input terminal of the output transistor 21.

[0079] The eighth transistor 29 includes a control terminal, a first terminal, and a second terminal. The first terminal of the eighth transistor 29 is electrically connected to the second terminal of the first transistor 22, and the second terminal of the eighth transistor 29 is electrically connected to the signal input terminal of the output transistor 21. The control terminal of the eighth transistor 29 is used to receive a reset signal Reset.

[0080] The first capacitor structure 200 includes a first terminal and a second terminal. The first terminal of the first capacitor structure 200 is electrically connected to the control terminal of the fifth transistor 26, and the second terminal of the first capacitor structure 200 is electrically connected to the signal output terminal of the output transistor 21.

[0081] like Figure 5 As shown, in the circuit structure described above, the first trigger signal DIR1 controls the first transistor 22 to turn on, charging the PU point; the second trigger signal DIR2 controls the second transistor 23 to turn on, discharging the PU point; the third transistor 24 is used to maintain the voltage of the PD point when it is turned on; the fourth transistor 25 is used to lower the voltage of the PD point; the sixth transistor 27 and the seventh transistor 28 are used to maintain the voltage at the signal output terminal of the output transistor 21; the eighth transistor is used to lower the voltage of the PU point and the signal output terminal when a reset signal Reset is received; and the first capacitor structure is used to increase the voltage holding capability of the fifth transistor 26.

[0082] It should be noted that this application only exemplifies one circuit structure for the shift register when the display panel is not an in-cell panel, and does not constitute a limitation on the circuit structure of the shift register. In addition to the circuit structure described above, the shift register can also adopt other circuit structures, such as other 7T2C structures or 9T2C structures, etc. Those skilled in the art can flexibly adjust the number of transistors or the connection relationship of transistors in the above part according to the functional requirements of the shift register.

[0083] In addition to the structures mentioned above, such as Figure 6 As shown, the shift register further includes a second capacitor structure 201, which includes a first terminal and a second terminal. The first terminal of the second capacitor structure 201 is electrically connected to the first terminal of the fourth transistor 25, and the second terminal of the second capacitor structure 201 is electrically connected to the first terminal of the fifth transistor 26. This second capacitor structure prevents excessive current from flowing between the first terminal of the fifth transistor and the second terminal of the fourth transistor, ensuring the safe operation of the shift register.

[0084] Specifically, the first capacitor structure and the second capacitor structure described above can each include one capacitor, or they can include multiple capacitors connected in series and parallel. The specific configuration can be determined based on actual needs or circumstances, using one or more capacitors connected in series and parallel to form the first and second capacitor structures.

[0085] When the display panel is not an in-cell panel, the above signal driving terminal is the reset signal terminal of the above shift register, that is, the above signal driving terminal is the reset signal terminal Reset of the shift register in the in-cell panel.

[0086] Specifically, in the two embodiments described above, where the display panel is an in-cell panel and the display panel is not an in-cell panel, the main difference in the shift register is the connection method of the control terminal of the eighth transistor.

[0087] In the display panel of this application, due to the need for narrow bezels and cost requirements, a shift register driving method is used instead of the traditional IC wiring method. The shift register driving method only requires a limited number of signals from the driving circuit to complete the gate control function. These signals include trigger signals (such as the first and second trigger signals mentioned above), clock signals (such as the first and second clock signals mentioned above), and high and low level signals (such as the high and low level signals input to the signal input terminal of the output transistor mentioned above). Furthermore, to avoid charge accumulation when the display panel is powered off and to prevent screen flickering caused by charge accumulation during power-on, the aforementioned output transistor and the aforementioned eighth transistor are provided. By inputting a reset signal to the signal driving terminal of the aforementioned output transistor or the control terminal of the aforementioned eighth transistor, the charge of all circuit structures in the shift register is cleared.

[0088] In practical applications, the aforementioned display panel includes multiple shift registers 20, which are cascaded to form a shift register group 202. The working principle diagram of the shift register group 202 is shown below. Figure 7 As shown, shift signals are provided by sequentially turning on each of the shift registers 20 in the shift register group 202, thereby realizing the line-by-line scanning of the scan lines.

[0089] In addition, while the signal input terminal and signal driving terminal of the above-mentioned output transistor are electrically connected to the test pad, the other input terminals in the circuit, specifically the receiving terminals of the first trigger signal, the second trigger signal Gn+1, the first scan direction signal DIR1, the second trigger signal Gn+1, the first clock signal CKB and the second clock signal CK, are all set to empty, that is, the test pad is not electrically connected to the above-mentioned receiving terminals.

[0090] According to another alternative embodiment of this application, such as Figure 8 As shown, the display panel also includes bonding pads 60 and a display area 11, and the non-display area 10 includes:

[0091] The target bezel 100 is located on one side of the display area 11. The target bezel 100 includes a first edge line l1 and a second edge line l2. The extension directions of the first edge line l1 and the second edge line l2 intersect on the side of the target bezel 100 away from the display area 11. That is, the width between the two edge lines of the target bezel 100 gradually decreases in the direction away from the display area 11. In other words, the target bezel 100 is an inverted trapezoidal shape that gradually narrows on both sides in the direction away from the display area. In other words, the target bezel is an irregular bezel. The first test pad 31, the second test pad 32, and the bonding pad 60 are located on the target bezel. For irregularly shaped display panels with narrow bezels, the existing scheme of setting multiple test pads may have the problem that the bezel cannot accommodate all the test pads. In the above embodiment of this application, for display panels with gradually narrowing bezels on both sides, reducing the number of test pads can greatly release the area occupied by excess test pads. The reduced number of test pads can better adapt to the requirements of the narrowing bezels on both sides, which is more conducive to the realization of narrow bezels.

[0092] Specifically, such as Figure 8 as well as Figure 3 or Figure 5 As shown, the signal driving terminal of the output transistor 21 of the shift register 20 is electrically connected to the bonding pad 60 through the first test pad 31, and the signal input terminal VGL of the output transistor 21 of the shift register 20 is electrically connected to the bonding pad 60 through the second test pad 32. The connection line between the first test pad 31 and the signal driving terminal of the output transistor 21 is the first connection line, and the connection line between the second test pad 32 and the signal input terminal VGL of the output transistor 21 is the second connection line. The ports of other devices in the shift register 20 besides the output transistor 21 are electrically connected to the bonding pad 60 through a third connection line. The line width of at least some positions of the first connection line and the second connection line is greater than the line width of each position of the third connection line.

[0093] Because the connection points of the test pads are relatively large, if the bonding pads and the device ports of the shift register are electrically connected through the test pads, the connection line from the test pads to the device ports will have a width that gradually increases from thick to thin. The width of this connection line at some points is greater than that of the connection line where the bonding pads are directly electrically connected to the device ports. Therefore, compared with the prior art which uses multiple test pads, the scanning signal test unit in the above embodiment of this application only has two test pads. Except for the signal drive terminal and input terminal of the output transistor which need to be electrically connected to the bonding pads through these two test pads, the other device ports in the shift register are directly electrically connected to the bonding pads, ensuring that the overall connection line width is small. This can further reduce the trace area, thereby reducing the area occupied by the traces on the border and further achieving a narrow border.

[0094] Similarly, such as Figure 8 As shown, some of the solder joints of the aforementioned bonding pad 60 are electrically connected to the source drive circuit through the third test pad in the aforementioned data signal test unit.

[0095] In practical applications, all of the aforementioned test pads in this application are placed on one or both sides of the long side of the bonding pad. Figure 8 An exemplary embodiment is shown in which the first test pad 31 and the second test pad 32 are located on one side of the bonding pad 60, and the third test pad 50 is located on the other side of the bonding pad 60. (Except for...) Figure 8 In addition to the embodiments shown, those skilled in the art can flexibly set the positional relationship between the first test pad, the second test pad, and the third test pad according to actual layout requirements, such as all being located on the same side of the bonding pad.

[0096] According to another aspect of this application, a display device is also provided, comprising: any of the above-described display panels.

[0097] The aforementioned display device includes any type of display panel. In the aforementioned display panel, the multiple test pads used to control the shift register to generate scan signals are reduced to two. Without affecting the control of the shift register's scan signal output, the space area of ​​the test pads in the non-display area is effectively reduced, thereby enabling a narrow bezel. This solves the problem in the prior art where multiple test pads are used to control the shift register to generate scan signals, occupying a large space area on the display panel and hindering the achievement of a narrow bezel.

[0098] According to another aspect of this application, a testing method for the above-mentioned display panel is also provided, comprising:

[0099] At least a test voltage is input to the first test pad and the second test pad so that the display panel displays the test screen.

[0100] In the aforementioned display panel testing method, the scan signal testing unit in the non-display area consists only of a first test pad and a second test pad. The first test pad is electrically connected to the signal drive terminal of the output transistor of the shift register, and the second test pad is electrically connected to the signal input terminal of the output transistor. By inputting a test voltage to at least the first and second test pads, the test screen of the display panel is displayed. This application reduces the multiple test pads used to control the shift register to generate the scan signal to two, effectively reducing the space area of ​​the test pads in the non-display area, thereby achieving a narrow bezel. Furthermore, even after reducing the number of test pads, the VT testing requirements for the display panel can still be met.

[0101] Optionally, the display panel further includes a source drive circuit, which includes a signal drive terminal and a data signal testing unit. The data signal testing unit is located in the non-display area and includes a third test pad electrically connected to the signal drive terminal of the source drive circuit. Multiple test screens are available, such as... Figure 9 As shown, at least a test voltage is input to the first test pad and the second test pad so that the display panel displays the test screen, including the following specific steps:

[0102] Step S100: Input a first voltage to the first test pad, wherein the first voltage is a constant voltage, that is, input the constant voltage to the signal drive terminal of the output transistor;

[0103] Step S101: Input a second voltage to the second test pad. The second voltage is a pulse voltage, that is, input the pulse voltage to the signal input terminal of the output transistor to drive the scan line.

[0104] Step S102: Input a third voltage to the third test pad. The third voltage is a pulse voltage, so that the display panel displays multiple test images in sequence. That is, input the pulse voltage to the signal input terminal of the source drive circuit to drive the data line.

[0105] In the above embodiment, a constant voltage is input to the first test pad to keep the output transistor in the open state; a pulse signal is input to the second test pad to realize the input of the scan signal; and a pulse voltage is input to the third test pad to realize the input of the data signal. This further ensures that the display panel can display multiple test screens in sequence, which facilitates visual testing of the test display panel, timely detection of defective products, and avoids the continuation of defective products.

[0106] In one exemplary embodiment, the timing diagram of the first voltage and the second voltage is as follows: Figure 10As shown, by setting the first voltage high, the output transistor is ensured to be turned on, and the second voltage is provided in the form of pulses so that the output transistor can output the second voltage.

[0107] Specifically, the high potential of the aforementioned second voltage can be set to 18V, and the low potential can be set to -10V. Furthermore, the duration of the high potential of the second voltage can be set according to the refresh time of the display panel during the VT test. For example, when the VT test time is set to 100Hz, i.e., the refresh time of each display frame is 10ms, the duration of the high potential of the second voltage can be set to 1ms, and the duration of the low potential of the second voltage can be set to 9ms. Of course, the specific values ​​of the second voltage and the output time value of the output transistor signal terminal are not limited to the values ​​mentioned above. Those skilled in the art can determine the specific values ​​of these parameters based on experience or simulation experiments.

[0108] Specifically, inputting a first voltage to the first test pad includes: when the last test screen is displayed on the display panel, adjusting the second voltage input to the first test pad to 0. When detecting the last screen, the signal drive terminal of the output transistor is pulled high and kept unchanged, while the voltage at the signal input terminal is pulled to GND, so that the gate voltage of each device in the shift register is returned to zero, thereby reducing the influence of bias voltage.

[0109] To ensure the stable and reliable operation of the shift register of the display panel after the VT test, the above method further includes: after displaying the last test screen, adjusting the first voltage to 0. After the test is completed, adjusting the first voltage to 0 resets the voltage of each component in the shift register, preventing accumulated charge after the display panel is powered off after the test, which could cause screen distortion upon the next power-on, thus ensuring the display panel can display normally.

[0110] To further achieve accurate testing of the display panel during the VT test, in other embodiments of this application, the third test pad includes a second sub-pad electrically connected to the input terminals of the data lines of the red, green, and blue sub-pixels in a one-to-one correspondence. A third voltage, which is a pulse voltage, is input to the third test pad so that the display panel sequentially displays multiple test images, including at least the following:

[0111] A first sub-voltage is input to the third test pad to make the display panel display a black screen. The first voltage is equal to the reference voltage of the pixel. Specifically, by displaying a black screen, it is possible to detect whether there are defects such as glass foreign objects in the display area of ​​the display panel. The reference voltage is generally 0V.

[0112] A second sub-voltage is input to the third test pad to make the display panel display a white screen. The absolute value of the second sub-voltage is greater than the absolute value of the first sub-voltage. Specifically, by displaying a white screen, it is possible to detect whether there are defects such as glass foreign objects in the display area of ​​the display panel. The second sub-voltage is generally the voltage with the largest absolute value of the difference from the reference voltage, such as ±6V.

[0113] A third sub-voltage is input to the third test pad, causing the display panel to display a grayscale image. The absolute value of the third sub-voltage is less than the absolute value of the second sub-voltage and greater than the absolute value of the first sub-voltage. Specifically, by displaying a grayscale image, it is possible to detect whether there are defects such as uneven display or indentations in the display area of ​​the display panel. The third sub-voltage corresponding to the grayscale image is generally taken as the voltage between the reference voltage and the second sub-voltage. For example, when the second sub-voltage is 6V, the third sub-voltage can be 3V, and when the second sub-voltage is -6V, the third sub-voltage can be -3V. In addition, those skilled in the art can display the grayscale image with the required grayscale value according to the actual design requirements of the display panel.

[0114] A fourth sub-voltage is input to the second sub-pad electrically connected to the input terminals of the data lines of all the first target sub-pixels, and a fifth sub-voltage is input to the second sub-pad electrically connected to the input terminals of the data lines of all the second target sub-pixels, so that the display panel displays an image of the target color. The first target sub-pixel is one of the red sub-pixel, the green sub-pixel, and the blue sub-pixel, and the second target sub-pixel is a sub-pixel other than the first target sub-pixel. The fourth sub-voltage is greater than the fifth sub-voltage, and the target color is the same as the color of the first target sub-pixel. Generally, the fourth sub-voltage is a high voltage, and the fifth sub-voltage is a low voltage. That is, when it is necessary to display an image of the target color, a high voltage is provided to the sub-pad electrically connected to the data lines of the sub-pixels corresponding to the target color, and a low voltage is provided to the sub-pad electrically connected to the data lines of the sub-pixels of other colors. For example, when it is necessary to display a green image, a high voltage is provided to all the green sub-pixel data lines through the electrically connected sub-pads, and a low voltage is provided to all the blue and red sub-pixel data lines.

[0115] In practical applications, it is also necessary to detect defects in the display panel. In this case, according to another exemplary embodiment of this application, such as... Figure 11 As shown, a third voltage, which is a pulse voltage, is input to the third test pad to cause the display panel to sequentially display multiple test screens. The method also includes:

[0116] Step S200: Input the first sub-voltage or the second sub-voltage into the third test pad to make the display screen show a white screen or a black screen;

[0117] Step S201: When the first voltage is stopped being input to the first test pad, a sixth sub-voltage is input to the third test pad, causing the display panel to display a discharge screen, wherein the fourth sub-voltage satisfies one of the following: has the same absolute value as the first sub-voltage and is opposite in direction to the first sub-voltage, or has the same absolute value as the second sub-voltage and is opposite in direction to the second sub-voltage.

[0118] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0119] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0120] The display panel described in this application comprises only two test pads: a first test pad and a second test pad. The first test pad provides voltage to the signal drive terminal of the output transistor in the shift register to control the switching state of the output transistor. The second test pad provides voltage to the signal input terminal of the output transistor to control the output transistor to output the corresponding scan signal. This achieves control over the switching state and output signal of the output transistor in the shift register. Compared to the prior art, which uses multiple (three or more) test pads to control the shift register to generate the scan signal, resulting in multiple pads occupying a large area of ​​the display panel and hindering the achievement of a narrow bezel, this application reduces the multiple test pads used to control the shift register to generate the scan signal to two. Without affecting the output transistor's ability to output the scan signal, this effectively reduces the space occupied by the test pads in the non-display area, thus enabling a narrow bezel.

[0121] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A display panel, characterized in that, include: Non-display area; A shift register is located in the non-display area. The shift register includes an output transistor, which includes a signal driving terminal, a signal input terminal, and a signal output terminal. The signal output terminal is the output terminal of the shift register. A scan signal testing unit is located in the non-display area. The scan signal testing unit consists of a first test pad and a second test pad spaced apart. The first test pad is electrically connected to the signal driving terminal of the output transistor, and the second test pad is electrically connected to the signal input terminal of the output transistor. The display panel also includes bonding pads and a display area. The signal driving terminal of the output transistor is electrically connected to the bonding pad through the first test pad, and the signal input terminal of the output transistor is electrically connected to the bonding pad through the second test pad. The connection line between the first test pad and the signal driving terminal of the output transistor is the first connection line, and the connection line between the second test pad and the signal input terminal of the output transistor is the second connection line. The ports of other devices in the shift register, except for the output transistor, are electrically connected to the bonding pad via a third connection line. The line width of at least some positions of the first connection line and the second connection line is greater than the line width of each position of the third connection line.

2. The display panel according to claim 1, characterized in that, The display panel also includes: Source drive circuit, including signal input terminal; A data signal testing unit is located in the non-display area. The data signal testing unit includes a third test pad, which is electrically connected to the signal input terminal of the source drive circuit.

3. The display panel according to claim 2, characterized in that, The signal input terminals of the source drive circuit include the input terminal of a common data line and the input terminal of the pixel data line. The third test pad includes a first sub-pad and a second sub-pad that are spaced apart. The first sub-pad is electrically connected to the input terminal of the common data line, and the second sub-pad is electrically connected to the input terminal of the pixel data line.

4. The display panel according to claim 3, characterized in that, The pixel includes red sub-pixels, green sub-pixels, and blue sub-pixels, and the second sub-pad has multiple sub-pads, wherein... The second sub-pad is electrically connected to the input terminals of the data lines of the red sub-pixel, the green sub-pixel, and the blue sub-pixel, respectively.

5. The display panel according to any one of claims 1 to 4, characterized in that, The display panel also includes: A first substrate and a second substrate arranged opposite to each other; A touch electrode layer is located between the first substrate and the second substrate; The signal driving terminal is the switch control signal terminal of the shift register.

6. The display panel according to any one of claims 1 to 4, characterized in that, The display panel further includes a first substrate and a second substrate disposed opposite to each other. The display panel does not include a touch electrode layer located between the first substrate and the second substrate. The signal driving terminal is the reset signal terminal of the shift register.

7. The display panel according to any one of claims 1 to 4, characterized in that, The shift register also includes: The first transistor includes a control terminal, a first terminal, and a second terminal. The control terminal of the first transistor is used to receive a first trigger signal, and the first terminal of the first transistor is used to receive a first scanning direction signal. The second transistor includes a control terminal, a first terminal, and a second terminal. The control terminal of the second transistor is used to receive a second trigger signal. The first terminal of the second transistor is electrically connected to the second terminal of the first transistor. The second terminal of the second transistor is used to receive a second scanning direction signal. The third transistor includes a control terminal, a first terminal, and a second terminal. The first terminal of the third transistor is electrically connected to the first terminal of the second transistor, and the second terminal of the third transistor is electrically connected to the signal input terminal of the output transistor. The fourth transistor includes a control terminal, a first terminal, and a second terminal. The control terminal of the fourth transistor is electrically connected to the second terminal of the first transistor, the first terminal of the fourth transistor is electrically connected to the control terminal of the third transistor, and the second terminal of the fourth transistor is electrically connected to the signal input terminal of the output transistor. The fifth transistor includes a control terminal, a first terminal, and a second terminal. The control terminal of the fifth transistor is electrically connected to the second terminal of the first transistor. The first terminal of the fifth transistor is used to receive a first clock signal, and the second terminal of the fifth transistor is electrically connected to the signal output terminal of the output transistor. The sixth transistor includes a control terminal, a first terminal, and a second terminal. The control terminal of the sixth transistor is electrically connected to the control terminal of the third transistor. The first terminal of the sixth transistor is electrically connected to the signal output terminal of the output transistor. The second terminal of the sixth transistor is electrically connected to the signal input terminal of the output transistor. The seventh transistor includes a control terminal, a first terminal, and a second terminal. The control terminal of the seventh transistor is used to receive a second clock signal. The first terminal of the seventh transistor is electrically connected to the signal output terminal of the output transistor, and the second terminal of the seventh transistor is electrically connected to the signal input terminal of the output transistor. The eighth transistor includes a control terminal, a first terminal, and a second terminal. The first terminal of the eighth transistor is electrically connected to the second terminal of the first transistor, and the second terminal of the eighth transistor is electrically connected to the signal input terminal of the output transistor. The control terminal of the eighth transistor is electrically connected to the signal driving terminal of the output transistor, or the control terminal of the eighth transistor is used to receive a reset signal. The first capacitor structure includes a first terminal and a second terminal. The first terminal of the first capacitor structure is electrically connected to the control terminal of the fifth transistor, and the second terminal of the first capacitor structure is electrically connected to the signal output terminal of the output transistor.

8. The display panel according to any one of claims 1 to 4, characterized in that, The non-display area includes: The target bezel is located on one side of the display area. The target bezel includes opposing first edge lines and second edge lines. The extension direction of the first edge line and the extension direction of the second edge line intersect on the side of the target bezel away from the display area. The first test pad, the second test pad, and the bonding pad are located on the target bezel.

9. The display panel according to any one of claims 1 to 4, characterized in that, The distance between the first test pad and the second test pad is not less than 300 μm.

10. A display device, characterized in that, include: The display panel according to any one of claims 1 to 9.

11. A testing method for a display panel according to any one of claims 1 to 9, characterized in that, include: At least a test voltage is input to the first test pad and the second test pad so that the display panel displays the test screen.

12. The method according to claim 11, characterized in that, The display panel further includes: a source drive circuit, including a signal input terminal; and a data signal testing unit located in the non-display area, the data signal testing unit including a third test pad, the third test pad being electrically connected to the signal input terminal of the source drive circuit. The test screen has multiple components, and at least a test voltage is input to the first test pad and the second test pad so that the display panel displays the test screen, including: A first voltage is applied to the first test pad, and the first voltage is a constant voltage. A second voltage, which is a pulse voltage, is input to the second test pad. A third voltage, which is a pulse voltage, is input to the third test pad so that the display panel sequentially displays multiple test images.

13. The method according to claim 12, characterized in that, Applying a first voltage to the first test pad includes: When the last test screen is displayed on the display panel, the first voltage input to the first test pad is adjusted to 0.

14. The method according to claim 12, characterized in that, The method further includes: After displaying the last test screen, adjust the first voltage to 0.

15. The method according to claim 12, characterized in that, The third test pad includes a second sub-pad that is electrically connected one-to-one with the input terminals of the data lines of the red, green, and blue sub-pixels. A third voltage, which is a pulse voltage, is input to the third test pad so that the display panel sequentially displays multiple test images, including at least the following: A first sub-voltage is input to the third test pad, causing the display panel to display a black screen. The first sub-voltage is equal to the reference voltage of the pixel. A second sub-voltage is input to the third test pad, causing the display panel to display a white screen, wherein the absolute value of the second sub-voltage is greater than the absolute value of the first sub-voltage; A third sub-voltage is input to the third test pad, causing the display panel to display a gray screen. The absolute value of the third sub-voltage is less than the absolute value of the second sub-voltage and greater than the absolute value of the first sub-voltage. A fourth sub-voltage is input to the second sub-pad, which is electrically connected to the input terminals of the data lines of all the first target sub-pixels, and a fifth sub-voltage is input to the second sub-pad, which is electrically connected to the input terminals of the data lines of all the second target sub-pixels, so that the display panel displays an image of the target color, wherein the first target sub-pixel is one of the red sub-pixel, the green sub-pixel, and the blue sub-pixel, the second target sub-pixel is a sub-pixel other than the first target sub-pixel, the fourth sub-voltage is greater than the fifth sub-voltage, and the target color is the same as the color of the first target sub-pixel.

16. The method according to claim 15, characterized in that, Inputting a third voltage, which is a pulse voltage, to the third test pad so that the display panel sequentially displays multiple test screens, further includes: The first sub-voltage or the second sub-voltage is input to the third test pad; When the first voltage is stopped being input to the first test pad, a sixth sub-voltage is input to the third test pad, causing the display panel to display a discharge image, wherein the sixth sub-voltage satisfies one of the following: has the same absolute value as the first sub-voltage and is opposite in direction to the first sub-voltage, or has the same absolute value as the second sub-voltage and is opposite in direction to the second sub-voltage.

Images