NVMe interface disk storage method, system, terminal and storage medium

Abstract

The present invention relates to the field of storage technology, and in particular to an NVMe interface disk storage method, system, terminal and storage medium. The SATA disk storage method of the NVMe interface includes: aggregation of work tasks in the NVMe queue and other processing. The processing of the processed data is handled by the SATA ACC, including searching for idle channels in the channel group. The Cmd Descriptor is configured for the idle channel. The DD of the channel is configured, and if there are multiple DDs, it is configured multiple times. The Cmd Descriptor is parsed to parse out the slot number used by this SATA command and its corresponding Command Table address. A PRDT list is constructed and written to the corresponding position in the Command Table. A CFIS is constructed. The SATA command is triggered by the slot number. The solution of the present invention greatly improves the performance of the storage device by aggregating a large number of small IOs into large IOs, and the processing performance is further improved by implementing the SATA ACC with hardware. The system's wide range of application scenarios is enhanced.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to an NVMe interface disk storage method, system, terminal, and storage medium. Background Art

[0002] In the enterprise storage market, SATA disks have long held a significant share of the market due to their advantages in capacity, durability, and cost. However, the insatiable demand for faster storage speeds in computer hosts has forced them to abandon SATA interfaces. Software interaction between computers and storage devices is now increasingly adopting the NVMe protocol as the data transmission protocol for storage devices.

[0003] NVMe (Non-Volatile Memory Express) disks improve disk performance on physical media. However, the original AHCI (Advanced Host Controller Interface) specification only defines one interaction queue, so data exchange between the host and the disk can only be communicated through one queue. In other words, multi-core processors can only exchange data with the disk through one queue, which cannot better utilize the physical characteristics of NVMe disks. The NVMe protocol can have up to 64K queues, and each CPU (Central Processing Unit) or core can have one queue, which greatly improves concurrency and naturally higher performance.

[0004] Therefore, designing a storage device with an NVMe protocol as the upstream interface and a SATA protocol as the downstream interface can cater to the advantages of the NVMe protocol interface such as high speed and strong customization, and can also cater to the advantages of SATA disks, especially SATA mechanical disks such as large capacity, low cost and high stability. This type of storage device is particularly valuable.

[0005] Among them, as such a storage device, how to convert the host's NVMe protocol request into a request for a SATA disk is a key issue, and the present invention focuses on disclosing a solution to this problem.

[0006] According to the NVMe protocol, data packets can be described using a PRP List. For convenience, data managed within storage devices is also described using a customized PRP List (CPRP List, or Customer PRP List). The PRP List specified by the NVMe protocol can be considered a special case of the CPRP List.

[0007] Similarly, within a storage device, disk-oriented data I / O requests are described using a Data Descriptor (DD). In addition to describing the CPRP List, the DD also defines command information such as the data I / O type (read or write), disk identifier, starting address, and data length. It also defines supplementary information, such as whether to enable reference data lists.

[0008] According to the AHCI specification, the SATA command sent to the AHCI controller is described using the Command Table, which mainly includes two parts: CFIS and PRDT list. The PRDT list describes the data information of the SATA command, such as Figure 1 shown.

[0009] SATA disks are mounted on a port of the AHCI controller. The AHCI controller reserves up to 32 SATA command slots for each port to store the SATA commands to be executed. To store a SATA command in a slot, the command information is written to the Command Table memory area corresponding to the slot number. Once the command is written, the AHCI controller is notified of the slot number, indicating that the CFIS and PRDT lists in the Command Table corresponding to that slot are ready. Subsequent execution is controlled by AHCI.

[0010] Sending the data request described by the CB to the SATA disk involves the following three steps:

[0011] The PRDT list construction converts the data described in the CPRP list in the CB into the data description format of the SATA disk controller. According to the AHCI specification, the data description format of the SATA disk controller is the PRDT format. Specifically, a PRDT list is used to describe the data of a SATA command (i.e., a SATA disk interaction). Each list element describes a data segment, including a pointer to the data packet and the data length. All data segments together constitute the complete data description of the SATA command.

[0012] The PRDT list construction is to cyclically find the data pointer and length of each data segment from the CPRP List, and write them to the corresponding position in the corresponding element of the PRDT until all data segments are processed.

[0013] CFIS construction, that is, extracting the command information in the CB and the data length information in the Cmd Descriptor, filling in the CFIS according to the SATA command specification requirements, and filling in the CFIS memory area of the corresponding Command Table according to the AHCI specification.

[0014] After the Command Table is completed, the slot number must be written to the SATA disk controller to complete the command issuance. Subsequent SATA commands are executed autonomously by the SATA disk controller.

[0015] The software involved in converting data from the CPRP list to the PRDT list, constructing the CFIS, and triggering the SATA controller to execute SATA commands is straightforward. However, due to the numerous software and hardware interactions, CPU performance is significantly impacted, especially when a large number of SATA drives are involved.

[0016] As mentioned above, the conversion from NVMe protocol to SATA protocol requires a complex software process and hardware-software interaction process, and there are many hardware and software design issues that need to be considered. The main issues are the waste of hardware acceleration engine channels on the one hand and the side effect of increased latency caused by the cache on the other. Summary of the Invention

[0017] In order to solve the technical problems existing in the above-mentioned prior art, namely, the waste of hardware acceleration engine channels on the one hand, and the side effect of increased latency caused by caching on the other hand, the present invention provides an NVMe interface disk storage method, system, terminal and storage medium. The present invention is about the acceleration engine, which defines two parts, a channel group and an acceleration engine. The channel group consists of multiple channels, and the acceleration engine corresponds to the channel one by one. The channel is responsible for receiving the Cmd Descriptor configuration information and one or more DD information of the software, and it also records the working status of the channel. The acceleration engine parses the CmdDescriptor and DD (Data Descriptor) passed by the channel, and constructs the PRDT list, CFIS and issues commands accordingly. After the command is issued, the working status of the corresponding channel is synchronously updated. Each channel and its engine works independently.

[0018] Among them, the software and hardware architecture design and workflow for the purpose of realizing the NVMe interface SATA storage system are the core technical points of the present invention.

[0019] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0020] In a first aspect, in one embodiment provided by the present invention, a method for storing disk data using an NVMe interface is provided. The method for storing disk data using a SATA NVMe interface includes:

[0021] S10, aggregation processing of work tasks in the NVMe queue;

[0022] S20, searching for an idle channel in the channel group;

[0023] S30, configuring a Cmd Descriptor for an idle channel;

[0024] S40, configure the DD of the channel. If there are multiple DDs, configure them multiple times.

[0025] S50, parse the Cmd Descriptor to obtain the slot number used by this SATA command and its corresponding Command Table address;

[0026] S60, constructing a PRDT list and writing it to the corresponding position in the Command Table;

[0027] S70, construct CFIS;

[0028] S80, triggering the SATA command by the slot number;

[0029] S90: Mark the channel as "Completed".

[0030] As a further solution of the present invention, the slot number triggering the SATA command includes:

[0031] S81, parse the SATA command slot number, Command Table address and data length in the Cmd Descriptor;

[0032] S82. Parse the CPRP List in the DD and the reference CPRP List;

[0033] S83, read the data pointer and data length of the CPRP List in sequence;

[0034] S84. If the reference CPRP List is enabled, process the data pointer and its length using the description of the data pointer related fields in the reference CPRP List;

[0035] S85. Write the elements in the PRDT list in the Command Table in sequence; the CPRP List data pointer corresponds to the elements in the PRDT list one by one, and the written content includes the data pointer and data length;

[0036] S86: Determine whether the CPRP List has been processed. If yes, execute S87; if not, execute S83.

[0037] S87, determine whether the data length of the SATA command is equal to the data length filled in the PRDT list, if yes, execute S88, if not, execute S83;

[0038] S88, triggering the SATA command, writing the slot number used by the SATA command into the AHCI trigger register, and completing the command triggering;

[0039] S89: Notify the channel to complete the command triggering.

[0040] As a further solution of the present invention, in the description process of the data pointer related fields, the data pointer is offset, that is, a fixed value is added or subtracted from the pointer; part of the data pointer is replaced with a fixed value; part of the data pointer is skipped.

[0041] As a further solution of the present invention, the lower 8 bits of the 64-bit reference pointer are used as the operation code, and the upper 56 bits are used to store one or more operands.

[0042] As a further solution of the present invention, the channel has four states, including idle, busy, completed, and abnormal.

[0043] As a further solution of the present invention, after a hardware power-on reset, the channel is in an idle state; after a CmdDescriptor is configured, the channel is in a busy state; after the acceleration engine completes sending a SATA command and responds with a completion signal to the channel, the channel is in a completed state; if in the completed state, the channel returns to an idle state after the software reads it once; after the channel is in a busy state, if the engine times out and fails to complete sending the SATA command, a timeout is triggered and the channel enters an abnormal state. After the software reads the status, the channel returns to an idle state.

[0044] In a second aspect, in another embodiment provided by the present invention, an NVMe interface disk storage system is provided, wherein the SATA disk storage system of the NVMe interface includes a channel scanning module, a channel configuration module, a parsing module, a construction module and a trigger module;

[0045] Channel scanning module, used to find idle channels in the channel group;

[0046] The channel configuration module is used to configure the Cmd Descriptor of the idle channel and the DD of the channel. If there are multiple DDs, they are configured multiple times.

[0047] The parsing module is used to parse the Cmd Descriptor and parse out the slot number used by the current SATA command and its corresponding Command Table address;

[0048] Construction module, used to construct the PRDT list, write it to the corresponding position in the Command Table, and construct CFIS;

[0049] The trigger module triggers the SATA command by the slot number and marks the channel as "completed".

[0050] In a third aspect, in another embodiment provided by the present invention, a terminal is provided, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the SATA disk storage method of the NVMe interface when loading and executing the computer program.

[0051] In a fourth aspect, in another embodiment provided by the present invention, a storage medium is provided, which stores a computer program, and when the computer program is loaded and executed by the processor, the steps of the SATA disk storage method of the NVMe interface are implemented.

[0052] The technical solution provided by the present invention has the following beneficial effects:

[0053] 1. This invention incorporates a caching mechanism that caches I / O from the NVMe protocol host computer according to the Name Space queue. A queue aggregation mechanism aggregates and queues cached I / O. This reduces hardware and software interaction, with an independent acceleration engine constructing and issuing SATA commands for aggregated I / O. Small I / O not suitable for aggregation is directly issued via software. This solution significantly improves storage device performance by aggregating a large number of small I / Os into larger I / Os, which are then accelerated by the acceleration engine. Aggregation suitability can be configured using aggregation parameters, enhancing the system's broad application scenarios.

[0054] 2. Establish a cache mechanism at the NVMe protocol IO request entry point to cache the host computer IO according to the Name Space queue, reducing the performance and transient pressure of small IO on the SATA interface; queue and aggregate the cached IO to convert a large number of small IO into a small number of large IO; use a hardware acceleration engine to offload the load on the CPU caused by a large amount of software and hardware interaction, solving the CPU performance bottleneck problem; it is not suitable for aggregated IO to follow the software delivery process.

[0055] The caching mechanism addresses the performance disparity between the low latency and high concurrency of the NVMe interface and the high latency and low concurrency of the SATA interface. The hardware acceleration engine implements CPRP list to PRDT list conversion, CFIS construction, and SATA command delivery to offload CPU load and address CPU performance bottlenecks. The I / O queue aggregation mechanism is designed to improve the efficiency of the hardware acceleration engine. It is not suitable for IO aggregation to be delivered through software. This avoids wasting hardware acceleration engine channels while also addressing the side effect of increased latency caused by I / O caching.

[0056] These and other aspects of the present invention will become more readily apparent in the following description of the embodiments. It should be understood that the above general description and the following detailed description are merely exemplary and explanatory and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying any creative work.

[0058] Figure 1 This is a data information diagram of a SATA command of an NVMe interface disk storage method according to an embodiment of the present invention;

[0059] Figure 2 This is a block diagram of an NVMe interface disk storage method according to an embodiment of the present invention;

[0060] Figure 3 This is a block diagram of the architecture of an acceleration engine in an NVMe interface disk storage method according to one embodiment of the present invention;

[0061] Figure 4 This is a flowchart of an NVMe interface disk storage method according to an embodiment of the present invention;

[0062] Figure 5 This is a channel workflow diagram of an NVMe interface disk storage method according to an embodiment of the present invention;

[0063] Figure 6 This is a workflow diagram of a high-speed engine in an NVMe interface disk storage method according to one embodiment of the present invention;

[0064] Figure 7 This is a structural block diagram of an NVMe interface disk storage system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0065] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0066] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, combined, or partially merged, so the actual execution order may vary depending on the actual situation.

[0067] It should be understood that the terms used in this specification are only for the purpose of describing particular embodiments and are not intended to limit the present invention. As used in the specification and appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0068] The usage scenarios of the embodiments of the present invention are as follows:

[0069] 1. The storage device interface is NVMe, but for other reasons, SATA interface disk media is required;

[0070] 2. High performance requirements;

[0071] 3. The CPU unit computing power needs to support more SATA disks.

[0072] In the embodiments of the present invention, the abbreviations and key terms used are defined as follows:

[0073] SATA: abbreviation of Serial-ATA, referring to the Serial ATA specification

[0074] SATA disk: A type of disk that uses the SATA interface to communicate with the host.

[0075] AHCI: Advanced Host Controller Interface, a SATA disk controller

[0076] SATA disk controller: The hardware unit that allows the host to interact with SATA disks, generally referring to AHCI. SATA command: In this article, SATA commands are used to represent a data interaction with a SATA disk. Command Table: Describes a SATA command.

[0077] CFIS: Command FIS, describes the basic information of SATA commands and together with the PRDT list constitutes the CommandTable;

[0078] PRDT: Physical Region Descriptor Table, describes the data part of the SATA command.

[0079] Cmd Descriptor: Command description, which describes the SATA command including the data length, the slot number to be used by the SATA command, and the Command Table address corresponding to the slot number

[0080] NVMe: Non-Volatile Memory Express, non-volatile memory host controller interface specification

[0081] PRP List: Physical Region Page List, physical region page list

[0082] CPRP List: Customer PRP List, customized PRP List

[0083] DD: Data Descriptor, data descriptor

[0084] CD: Command Descriptor (or Cmd Descriptor), command descriptor

[0085] Specifically, the embodiments of the present invention are further described below with reference to the accompanying drawings.

[0086] See also Figure 4 , Figure 4 This is a flowchart of an NVMe interface disk storage method provided by an embodiment of the present invention. Figure 4 As shown, the SATA disk storage method of the NVMe interface includes steps S10 to S11.

[0087] S10, aggregation processing of work tasks in the NVMe queue;

[0088] S20, searching for an idle channel in the channel group;

[0089] In an embodiment of the present invention, the channel group is composed of a plurality of channels, namely, Channel 1 to Channel n, where n represents the number of channels that can work in parallel.

[0090] In the embodiment of the present invention, the channel has four states: Idle, Busy, Completed, and Abnormal. In the specific implementation process, after the hardware is powered on and reset, the channel is in the Idle state; after the Cmd Descriptor is configured, the channel is in the Busy state; after the acceleration engine completes the SATA command and responds to the completion signal to the channel, it is in the Completed state; if it is in the Completed state, the channel returns to the Idle state after the software reads it once. For details, please refer to Figure 7 After the channel is in the busy state, the engine times out and fails to complete the SATA command, triggering a timeout and entering an abnormal state. After the software reads the status, the channel returns to the idle state.

[0091] S30, configuring a Cmd Descriptor for an idle channel;

[0092] In the embodiment of the present invention, each channel is scanned, the status of each channel is determined, each channel is marked in real time, and channels in an idle state are screened out, and Cmd Descriptors are configured for these idle channels;

[0093] S40, configure the DD of the channel. If there are multiple DDs, configure them multiple times.

[0094] In the embodiment of the present invention, the idle channel configured with the Cmd Descriptor is reconfigured with a DD, ie, a data descriptor. If there are multiple DDs, multiple configurations are performed, which will not be described in detail here.

[0095] S50, parse the Cmd Descriptor to obtain the slot number used by this SATA command and its corresponding Command Table address;

[0096] In an embodiment of the present invention, the Cmd Descriptor configured for the idle channel is extracted and parsed, and the parsed result includes the slot number used by the current SATA command and its corresponding Command Table address.

[0097] S60, constructing a PRDT list and writing it to the corresponding position in the Command Table;

[0098] S70, construct CFIS;

[0099] S80, triggering the SATA command by the slot number;

[0100] See also Figure 5 In an embodiment of the present invention, the SATA command is triggered by the slot number as an acceleration engine (ACCEngine), and its specific workflow is as follows.

[0101] S81, parse the SATA command slot number, Command Table address and data length in the Cmd Descriptor;

[0102] S82. Parse the CPRP List in the DD and the reference CPRP List (if enabled).

[0103] S83, read the data pointer and data length of the CPRP List in sequence;

[0104] S84. If the reference CPRP List is enabled, process the data pointer and its length using the description of the data pointer related fields in the reference CPRP List;

[0105] In embodiments of the present invention, for example, a data pointer can be offset, i.e., a fixed value can be added or subtracted from the pointer; part of the data pointer can be replaced with a fixed value; part of the data pointer can be skipped, etc. Specifically, the lower 8 bits of the 64-bit reference pointer can be used as the opcode, and the upper 56 bits can store one or more operands.

[0106] For example:

[0107]

[0108] S85. Write the elements of the PRDT list in the Command Table in sequence. The first CPRP List data pointer corresponds to the first element in the PRDT list, and so on. The written content includes the data pointer and data length;

[0109] S86: Determine whether the CPRP List has been processed. If yes, execute S87; if not, execute S83.

[0110] S87, determine whether the data length of the SATA command is equal to the data length filled in the PRDT list, if yes, execute S88, if not, execute S83;

[0111] S88, triggering the SATA command, writing the slot number used by the SATA command into the AHCI trigger register, and completing the command triggering;

[0112] S89: Notify the channel to complete the command triggering.

[0113] S90: Mark the channel as "Completed" and end the process.

[0114] It should be understood that, although the above is described in a certain order, these steps are not necessarily performed in sequence according to the above order. Unless there is clear explanation in this article, the execution of these steps does not have strict order restriction, and these steps can be performed in other orders. Moreover, a part of the steps of the present embodiment may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be performed in turn or alternately with at least a portion of the steps or stages in other steps or other steps.

[0115] In one embodiment, see Figure 6 As shown, an NVMe interface disk storage system is also provided in an embodiment of the present invention, which includes a channel scanning module, a channel configuration module, a parsing module, a construction module and a trigger module.

[0116] Channel scanning module, used to find idle channels in the channel group;

[0117] The channel configuration module is used to configure the Cmd Descriptor of the idle channel and the DD of the channel. If there are multiple DDs, they are configured multiple times.

[0118] The parsing module is used to parse the Cmd Descriptor and parse out the slot number used by the current SATA command and its corresponding Command Table address;

[0119] Construction module, used to construct the PRDT list, write it to the corresponding position in the Command Table, and construct CFIS;

[0120] The trigger module triggers the SATA command by the slot number and marks the channel as "Completed". The process ends.

[0121] See also Figure 2 ,In the embodiment of the present invention, Name Space x, i.e. the cache space of the cache mechanism, and x represents the disk code;

[0122] Gathering, which is the aggregation queuing mechanism;

[0123] NVMe queue Manager, NVMe queue management mechanism;

[0124] SATA Cmd Processor, SATA command software processing mechanism.

[0125] Name Space x: This cache space caches all IO commands from the NVMe interface to disk x.

[0126] Gathering reads IO commands from Name Space x and aggregates and queues them to generate a CmdDescriptor and one or more Data Descriptors to describe the aggregated IO commands and hand them over to the SATA ACC for distribution. IO commands that are not suitable for aggregation are directly handed over to the SATA Cmd Processor module for software distribution.

[0127] NVMe queue manager is responsible for the management queue processing of NVMe commands and host notification after SATA command processing.

[0128] The SATA Cmd Processor is responsible for issuing SATA commands and preventing small I / O from occupying the SATAACC hardware resources. Each module corresponds to a specific mechanism, so we will not go into detail here.

[0129] See also Figure 3 In this embodiment of the present invention, the acceleration engine module (ACC Engine) and the conversion engine module are composed of multiple engines, namely ACC Engine 1 to ACC Engine n. n represents the number of engines that can operate in parallel. Each engine corresponds to a channel one-to-one, receives and parses the command descriptor and data descriptor from the channel, and completes the construction of each part of the SATA command and finally issues the SATA command.

[0130] Channel: The channel is used to receive DD and Cmd Descriptors and record conversion results. Channels have three states: "Idle", "Busy", and "Complete", indicating the working status of the corresponding engine.

[0131] In one embodiment, a terminal is provided in an embodiment of the present invention, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus.

[0132] Memory for storing computer programs;

[0133] The processor is configured to execute the NVMe interface disk storage method when executing the computer program stored in the memory, and the processor implements the steps in the above method embodiment when executing the instructions:

[0134] The communication bus mentioned in the terminal can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is used in the figure, but this does not mean that there is only one bus or only one type of bus.

[0135] The communication interface is used for communication between the above terminal and other devices.

[0136] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage. Alternatively, the memory may be at least one storage device located away from the processor.

[0137] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components.

[0138] The terminal includes a user device and a network device. The user device includes, but is not limited to, a computer, a smartphone, a PDA, etc.; the network device includes, but is not limited to, a single network server, a server group consisting of multiple network servers, or a cloud based on cloud computing consisting of a large number of computers or network servers. Cloud computing is a type of distributed computing, a super virtual computer composed of a group of loosely coupled computers. The terminal can operate independently to implement the present invention, or it can access a network and implement the present invention through interactive operations with other terminals in the network. The network in which the terminal is located includes, but is not limited to, the Internet, a wide area network, a metropolitan area network, a local area network, a VPN network, etc.

[0139] The terminal includes a user device and a network device. The user device includes, but is not limited to, a computer, a smartphone, a PDA, etc.; the network device includes, but is not limited to, a single network server, a server group consisting of multiple network servers, or a cloud based on cloud computing consisting of a large number of computers or network servers. Cloud computing is a type of distributed computing, a super virtual computer composed of a group of loosely coupled computers. The terminal can operate independently to implement the present invention, or it can access a network and implement the present invention through interactive operations with other terminals in the network. The network in which the terminal is located includes, but is not limited to, the Internet, a wide area network, a metropolitan area network, a local area network, a VPN network, etc.

[0140] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0141] In one embodiment of the present invention, a storage medium is further provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above method embodiment are implemented:

[0142] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing related hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes in the above-described method embodiments. Any reference to memory, storage, database, or other media used in the various embodiments provided herein can include at least one of non-volatile and volatile memory.

[0143] It should be understood that, as used herein, the singular form "a" or "an" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the items listed in association. The serial numbers of the embodiments disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0144] It should also be noted that, in this document, relational terms such as first and second are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or device comprising a set of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. Without further limitation, elements defined by the phrase "comprising a..." do not preclude the presence of additional identical elements in the process, method, article, or device comprising the recited elements. The above detailed description of the NVMe disk mounting method, device, and storage medium provided by the present invention has been used. Specific examples have been used herein to illustrate the principles and implementations of the present invention. The description of the above embodiments is intended only to facilitate understanding of the method and its core concepts. Furthermore, those skilled in the art will appreciate that variations in the specific implementation and scope of application are possible based on the principles of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.

[0145] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples. Within the spirit of the embodiments of the present invention, the technical features of the above embodiments or different embodiments may be combined, and there are many other variations of different aspects of the above embodiments of the present invention, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the scope of protection of the embodiments of the present invention.

Claims

1. A NVMe interface disk storage method, characterized in that: The SATA disk storage method of the NVMe interface includes: S10, aggregation processing of work tasks in the NVMe queue; S20, searching for an idle channel in the channel group; S30, configuring a Cmd Descriptor for an idle channel; S40, configure the DD of the channel. If there are multiple DDs, configure them multiple times. S50, parse the Cmd Descriptor to obtain the slot number used by this SATA command and its corresponding CommandTable address; S60, constructing a PRDT list and writing it to the corresponding position in the Command Table; S70, construct CFIS; S80, triggering the SATA command by the slot number; S90: Mark the channel as "Completed".

2. The NVMe interface disk storage method according to claim 1, wherein: The slot number triggering the SATA command includes: S81, parse the SATA command slot number, Command Table address and data length in the Cmd Descriptor; S82. Parse the CPRP List in the DD and the reference CPRP List; S83, read the data pointer and data length of the CPRP List in sequence; S84. If the reference CPRP List is enabled, process the data pointer and its length using the description of the data pointer related fields in the reference CPRP List; S85. Write the elements in the PRDT list in the Command Table in sequence; the CPRP List data pointer corresponds to the elements in the PRDT list one by one, and the written content includes the data pointer and data length; S86: Determine whether the CPRP List has been processed. If yes, execute S87; if not, execute S83. S87, determine whether the data length of the SATA command is equal to the data length filled in the PRDT list, if yes, execute S88, if not, execute S83; S88, triggering the SATA command, writing the slot number used by the SATA command into the AHCI trigger register, and completing the command triggering; S89: Notify the channel to complete the command triggering.

3. The NVMe interface disk storage method according to claim 2, wherein: In the description process of the data pointer related fields, the data pointer is offset, that is, a fixed value is added to or subtracted from the pointer; part of the data pointer is replaced with a fixed value; and part of the data pointer is skipped.

4. The NVMe interface disk storage method according to claim 3, wherein: The lower 8 bits of the 64-bit reference pointer are used as the operation code, and the upper 56 bits store one or more operands.

5. The NVMe interface disk storage method according to claim 2, wherein: The channel has multiple states.

6. The NVMe interface disk storage method according to claim 5, wherein: The channel has four states, including idle, busy, completed, and abnormal.

7. The NVMe interface disk storage method according to claim 6, wherein: After the hardware is powered on and reset, the channel is in the idle state. After the Cmd Descriptor is configured, the channel is in the busy state. When the acceleration engine completes the SATA command and responds with a completion signal to the channel, it is in the completed state. If it is in the completed state, the channel returns to the idle state after the software reads it once. After the channel is in the busy state, the engine times out and fails to complete the SATA command, triggering a timeout and entering an abnormal state. After the software reads the status, the channel returns to the idle state.

8. An NVMe interface disk storage system, the SATA disk storage system of the NVMe interface comprising a channel scanning module, a channel configuration module, a parsing module, a construction module and a trigger module; Channel scanning module, used to find idle channels in the channel group; Channel configuration module, used to configure Cmd Descriptor for idle channels; and the DD of the channel. If there are multiple DDs, configure them multiple times; The parsing module is used to parse the Cmd Descriptor and parse out the slot number used by the current SATA command and its corresponding Command Table address; Construction module, used to construct the PRDT list, write it to the corresponding position in the Command Table, and construct CFIS; The trigger module triggers the SATA command by the slot number and marks the channel as "completed".

9. A terminal comprising a memory and a processor, wherein the memory stores a computer program, and when the processor loads and executes the computer program, the steps of the SATA disk storage method with an NVMe interface as described in any one of claims 1 to 7 are implemented.

10. A storage medium storing a computer program, wherein when the computer program is loaded and executed by a processor, the steps of the SATA disk storage method with an NVMe interface are implemented as described in any one of claims 1 to 7.

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