Driving method of display driving circuit, display driving circuit and display panel

Abstract

The application discloses a driving method of a display driving circuit, the display driving circuit and a display panel. The driving method comprises the following steps: input ends of two driving units in a driving unit group receive the same clock signal, and two corresponding same gate driving signals are generated; a pull-down circuit is started to pull down the gate driving signal of the output end of one of the two driving units, so that the gate driving signal output to the corresponding scan line is different from the waveform of the gate driving signal of the output end of the other driving unit. In the two adjacent driving units, the output end of one of the driving units is connected to the pull-down circuit to pull down the gate driving signal, so that the opening degrees of the gates of the two adjacent rows of pixels are different, the charging rates of the two rows of pixels which are opened at the same time are different, and different display effects are generated, so that the sawtooth feeling of the picture edge is optimized, and the display effect of the double-line gate mode is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving method for a display driving circuit, a display driving circuit, and a display panel. Background Technology

[0002] In the development of large-size and high-refresh-rate display panels, dual-line gate (DLG) technology has attracted attention. The principle of DLG technology is that the panel's GDL circuit simultaneously opens two rows of scan lines, and the two rows are input with the same gate drive signal. In this mode, it is equivalent to reducing the number of vertically displayed pixels by half. Without changing the original hardware and chip computing power, the refresh rate can be doubled. For example, a monitor with a resolution of 3840*2160 and a refresh rate of 120Hz can have its resolution become 3840*1080 and its refresh rate become 240Hz after enabling DLG mode, thus achieving a high refresh rate effect.

[0003] The drawback of DLG mode is that after the vertical resolution is halved, the image clarity decreases when displaying patterns at the original resolution, and the jagged edges at the curves are more obvious, resulting in an unsatisfactory display effect. Summary of the Invention

[0004] The purpose of this application is to provide a driving method for a display driving circuit, a display driving circuit, and a display panel, which aims to solve the problems of low image clarity and obvious jagged edges at the curved edges in DLG mode.

[0005] This application discloses a driving method for a display driving circuit. The display driving circuit includes multiple cascaded driving unit groups, each driving unit group including at least two driving units. At least one pull-down circuit is provided for each driving unit group, and the pull-down circuit is connected to the output terminal of the driving unit. The driving method includes the following steps:

[0006] The input terminals of the two driving units in the driving unit group receive the same clock signal and generate two corresponding identical gate driving signals; and

[0007] The pull-down circuit is activated to pull down the gate drive signal at the output of one of the two drive units, thereby obtaining a gate drive signal with a waveform different from the gate drive signal at the output of the other drive unit and outputting it to the corresponding scan line.

[0008] Optionally, each driving unit group includes a first driving unit and a second driving unit. A first pull-down circuit is provided for the first driving unit, and a second pull-down circuit is provided for the second driving unit. The step of activating the pull-down circuit to pull down the gate driving signal at the output terminal of one of the two driving units, thereby obtaining a gate driving signal with a waveform different from the gate driving signal at the output terminal of the other driving unit, and outputting it to the corresponding scan line includes:

[0009] The first pull-down circuit is activated to pull down the gate drive signal at the output terminal of the first drive unit, and the second pull-down circuit is activated at the same time to pull down the gate drive signal at the output terminal of the second drive unit, thereby obtaining a gate drive signal with a waveform different from the gate drive signal at the output terminal of the drive unit and outputting it to the corresponding scan line.

[0010] The gate drive signal generated by the first pull-down circuit pulling down the gate drive signal at the output of the first drive unit is different from the gate drive signal generated by the second pull-down circuit pulling down the gate drive signal at the output of the second drive unit.

[0011] Optionally, the distance between the first driving unit and the input end of the data line is less than the distance between the input end of the data line of the second driving unit, and the pull-down voltage in the first pull-down circuit is less than the pull-down voltage in the second pull-down circuit.

[0012] Optionally, the pull-down circuit includes a first pull-down voltage and a second pull-down voltage, wherein the value of the first pull-down voltage is greater than the value of the second pull-down voltage. The step of activating the pull-down circuit to pull down the gate drive signal at the output terminal of one of the two drive units, thereby obtaining a gate drive signal with a waveform different from the gate drive signal at the output terminal of the other drive unit, and outputting it to the corresponding scan line, further includes:

[0013] Detect the current frame refresh rate, obtain the next frame refresh rate, and calculate the difference between the current frame refresh rate and the next frame refresh rate; and

[0014] The difference is compared with a first preset value and a second preset value. When the difference is less than the first preset value, the pull-down circuit is not activated. When the difference is greater than the first preset value and less than the second preset value, the pull-down circuit is activated, and the first pull-down voltage is used to pull down the gate drive signal at the output terminal of the drive unit. When the difference is greater than the second preset value, the pull-down circuit is activated, and the second pull-down voltage is used to pull down the gate drive signal at the output terminal of the drive unit.

[0015] Optionally, the first pull-down circuit is turned on later than the second pull-down circuit.

[0016] Optionally, the pull-down circuit is turned on earlier than the falling edge of the high-level signal of the gate drive signal at the output of the driving unit, and the pull-down circuit is turned off earlier than the falling edge of the high-level signal of the gate drive signal of the next frame corresponding to the current driving unit.

[0017] This application also discloses a display driving circuit, which is driven using any of the driving methods described above. The display driving circuit includes multiple cascaded driving unit groups and pull-down circuits. Each driving unit group includes at least two driving units, and at least one pull-down circuit is provided for each driving unit group. The pull-down circuit is connected to the output terminal of the driving unit. The pull-down circuit is used to pull down the gate driving signal at the output terminal of the display driving circuit to generate a gate driving signal with a waveform different from the gate driving signal waveform at the output terminal of the display driving circuit, which is then output to the scan line.

[0018] Optionally, the input terminals of the two drive units in the drive unit group are connected to the same clock signal line and receive the same clock signal.

[0019] Optionally, the pull-down circuit includes a refresh rate detection module, a judgment module, a first switch module, and a second switch module. The detection module is connected to the judgment module, and the judgment module is connected to both the first and second switch modules. The input terminal of the first switch module is connected to the output terminal of a first pull-down voltage, and the input terminal of the second switch module is connected to the output terminal of a second pull-down voltage. The output terminals of the first and second switch modules are connected to the output terminal of the display driver circuit. The detection module detects the refresh rates of the current frame and the next frame, and the judgment module calculates the difference between the refresh rates of the current frame and the next frame and controls the conduction of the first and second switch modules accordingly. This allows for the input of different pull-down voltages to the output terminal of the driver unit to pull down the gate drive signal at the output terminal of the display driver circuit.

[0020] This application also discloses a display panel, which includes a display driving circuit as described above, as well as multiple clock signal lines and multiple scan lines. The input terminal of the display driving circuit is connected to the corresponding clock signal line, and the output terminal is connected to the corresponding scan line. The pull-down circuit in the display driving circuit is connected between the input terminal of the display driving circuit and the corresponding scan line.

[0021] Compared to display driver circuits without pull-down circuits, this application improves the GDL circuit by grouping two driver units that receive the same clock signal into a group. In the driver unit group, at least one pull-down circuit is connected to the GDL units of adjacent levels. By activating the pull-down circuit, the waveform of the gate drive signal output to the scan line is controlled. When the pull-down circuit is activated, the waveforms and voltages of the gate drive signals of the two GDL lines are different, resulting in different gate opening degrees for the two adjacent lines. This causes the two simultaneously activated pixels to have different charging rates, thus producing different display effects. Compared to the original pixels with the same charging rate, this can optimize the jagged edges of the screen and avoid obvious and strong jagged edges, thereby compensating for the display effect of DLG mode. Attached Figure Description

[0022] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:

[0023] Figure 1 This is a flowchart illustrating a driving method according to the first embodiment of this application;

[0024] Figure 2 This is a flowchart illustrating the driving method of the second embodiment of this application;

[0025] Figure 3 This is a flowchart illustrating the driving method of the third embodiment of this application;

[0026] Figure 4 This is a schematic diagram of the display driving circuit according to the fourth embodiment of this application;

[0027] Figure 5 This is a schematic diagram of the display driving circuit according to the fifth embodiment of this application;

[0028] Figure 6 This is a schematic diagram of the display driving circuit according to the sixth embodiment of this application;

[0029] Figure 7 This is a schematic diagram of the structure of the display panel according to the seventh embodiment of this application.

[0030] Among them, 100 is the display driving circuit; 110 is the pull-down circuit; 111 is the first pull-down circuit; 112 is the second pull-down circuit; 113 is the detection module; 114 is the judgment module; 115 is the first switch module; 116 is the second switch module; 200 is the driving unit group; 210 is the driving unit; 211 is the first driving unit; 212 is the second driving unit; 300 is the display panel; 310 is the scan line; and 320 is the clock signal line. Detailed Implementation

[0031] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0032] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. The term "comprising" and any variations thereof mean non-exclusive inclusion, where one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.

[0033] In addition, terms such as “center,” “horizontal,” “up,” “down,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer” that indicate orientation or positional relationship are based on the orientation or relative positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this application and do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0034] Furthermore, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0035] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0036] like Figure 1As shown, as a first embodiment of this application, a driving method for a display driving circuit is disclosed. The display driving circuit includes multiple cascaded driving unit groups, each driving unit group including at least two driving units, and at least one pull-down circuit is provided for each driving unit group. The pull-down circuit is connected to the output terminal of the driving unit. The driving method includes the following steps:

[0037] S1: The input terminals of the two driving units in the driving unit group receive the same clock signal and generate two corresponding identical gate driving signals; and

[0038] S2: Activate the pull-down circuit to pull down the gate drive signal at the output terminal of one of the two drive units, thereby obtaining a gate drive signal with a waveform different from the gate drive signal at the output terminal of the other drive unit and outputting it to the corresponding scan line.

[0039] In any driving unit group, there are at least two driving units, that is, three or four driving units can also be set. Taking two driving units as an example, this embodiment changes the gate driving signals of the two driving units, so that the waveforms of the gate driving signals output by the two driving units are different, so that the opening degree of the gate terminal of the thin film transistor of the corresponding pixel is different, thereby resulting in different charging efficiency and different charging amount. This changes the brightness difference between the two rows of pixels, avoiding the two rows of pixels having the same brightness and the same effect, which leads to strong jagged edges at the screen edges when the refresh rate is increased. The pull-down circuit is turned on to enter the VGL mode, thereby making adjacent rows of pixels produce different display effects, thereby compensating for the display effect of the dual-line gate mode and optimizing the jagged edges at the screen edges.

[0040] Generally, the opening or closing of VGL mode directly controls the switch of the pull-down circuit. To avoid the pull-down circuit affecting the charging effect of the next frame, the pull-down circuit is opened earlier than the falling edge of the high-level signal of the gate drive signal at the output of the driving unit, and the pull-down circuit is closed earlier than the falling edge of the high-level signal of the gate drive signal for the next frame corresponding to the current driving unit. That is, after the gate drive signal is pulled down in the current frame, the pull-down circuit cannot continue to pull down. When the gate drive signal opens the gate in the next frame, it needs to be closed to avoid changes in the gate opening timing that could cause charging disorder.

[0041] In a group of driving units, the pull-down circuit can be set to any one of them, as long as the waveforms of the gate driving signals output by the two driving units are different, thereby making the charging rates of the corresponding two rows of pixels different.

[0042] like Figure 2As shown, this second embodiment of the present application is a further refinement and improvement of the first embodiment. Each drive unit group includes a first drive unit and a second drive unit. A first pull-down circuit is provided for the first drive unit, and a second pull-down circuit is provided for the second drive unit. Step S2 includes:

[0043] S221: The first pull-down circuit is activated to pull down the gate drive signal at the output terminal of the first drive unit, and the second pull-down circuit is activated at the same time to pull down the gate drive signal at the output terminal of the second drive unit, thereby obtaining a gate drive signal with a waveform different from the gate drive signal at the output terminal of the drive unit and outputting it to the corresponding scan line.

[0044] The gate drive signal generated by the first pull-down circuit pulling down the gate drive signal at the output of the first drive unit is different from the gate drive signal generated by the second pull-down circuit pulling down the gate drive signal at the output of the second drive unit.

[0045] This embodiment considers that if one of the driving units in the driving unit group does not have a pull-down circuit, then only one of the two driving units can perform pull-down, while the other remains unchanged. Therefore, the charging rate of adjacent rows of pixels can only change in one row. Although it's possible to make the charging rates of the two rows of pixels different, the selectable charging magnitude is limited; only the voltage value of one pull-down circuit can be changed. This embodiment provides a pull-down circuit for each driving unit: a first pull-down circuit for the first driving unit and a second pull-down circuit for the second driving unit. Upon entering VGL mode, the first pull-down circuit is activated to control the gate voltage at the output of the first driving unit. The gate drive signal is pulled down, and at the same time, the second pull-down circuit is activated to pull down the gate drive signal at the output of the second drive unit, thereby obtaining a gate drive signal with a waveform different from the gate drive signal at the output of the drive unit and outputting it to the corresponding scan line. The two pull-downs can be the same or different. If the edge jaggedness has been improved under a certain voltage, the same pull-down voltage can be used for pull-down. In addition, it should be noted that the turn-on time of the first pull-down circuit is later than the turn-on time of the second pull-down circuit, and the turn-off time of the two pull-down circuits is earlier than the falling edge time of the high-level signal of the gate drive signal corresponding to the current drive unit in the next frame.

[0046] Furthermore, since the data line has line resistance, the charging voltage of the corresponding data line will have a certain loss. Considering the loss, when the distance between the first driving unit and the input end of the data line is less than the distance between the input end of the data line of the second driving unit, the pull-down voltage in the first pull-down circuit is less than the pull-down voltage in the second pull-down circuit.

[0047] Similarly, for multiple cascaded drive unit groups, the pull-down voltage of the pull-down circuit in the drive unit group closer to the input end of the data line is less than that in the drive unit group farther from the input end of the data line. The closer drive unit needs a smaller pull-down voltage to reduce the pixel charging efficiency.

[0048] like Figure 3 As shown, as a third embodiment of this application, based on a further improvement of the first embodiment, the pull-down circuit includes a first pull-down voltage and a second pull-down voltage, the value of the first pull-down voltage being greater than the value of the second pull-down voltage, and step S2 further includes:

[0049] S231: Detect the current frame refresh rate, obtain the next frame refresh rate, and calculate the difference between the current frame refresh rate and the next frame refresh rate; and

[0050] S232: Compare the difference with a first preset value and a second preset value respectively. When the difference is less than the first preset value, the pull-down circuit is not activated. When the difference is greater than the first preset value and less than the second preset value, the pull-down circuit is activated, and the first pull-down voltage is used to pull down the gate drive signal at the output terminal of the drive unit. When the difference is greater than the second preset value, the pull-down circuit is activated, and the second pull-down voltage is used to pull down the gate drive signal at the output terminal of the drive unit.

[0051] Considering that there are multiple possibilities for refresh rate switching, such as switching from 60Hz to 120Hz or from 120Hz to 240Hz, and considering that different refresh rate differences may result in different jagged edges, the greater the difference in refresh rates, the more obvious the jagged edges will be, and a stronger pull-down force is needed to improve the jagged edges of the screen and improve the display effect of the dual-gate mode. Therefore, the pull-down circuit can be set with two pull-down voltages, which can be used for switching between different refresh rates.

[0052] like Figure 4As shown, as a fourth embodiment of this application, a display driving circuit 100 is disclosed. The display driving circuit 100 can be driven using the driving method described in any of the above embodiments. The display driving circuit 100 includes multiple cascaded driving unit groups 200 and pull-down circuits 110. Each driving unit group 200 includes at least two driving units 210, and at least one pull-down circuit 110 is provided for each driving unit group 200. The pull-down circuit 110 is connected to the output terminal of the driving unit 210. The pull-down circuit 110 is used to pull down the gate driving signal at the output terminal of the display driving circuit 100 to generate a gate driving signal (Gaten, Gaten+1) with a waveform different from the gate driving signal at the output terminal of the display driving circuit 100 and output it to the scan line.

[0053] The drawback of DLG mode is that after the vertical resolution is halved, the image clarity decreases when displaying patterns at the original resolution, and the jagged edges at the curves are more obvious, resulting in an unsatisfactory display effect. Therefore, this embodiment designs a new GDL circuit to optimize the DLG display mode. The existing GDL circuit is improved by connecting a pull-down circuit 110 to the output of any one of the two GDL units in a driving unit group 200. The pull-down circuit 110 inputs a pull-down voltage, thereby changing the gate driving signal at the output of the driving unit 210, so that the charging amount of the corresponding two rows of pixels is different, thus optimizing the jagged edges of the image.

[0054] Generally, the input terminals of the two drive units 210 of the drive unit group 200 are connected to two adjacent clock signal lines 320. The two adjacent clock signals input have the same waveform, two clock signals CKn and CKn+1. Each drive unit 210 is connected to one clock signal line 320, which can avoid the situation of insufficient driving capability when one clock signal is connected to multiple drive units 210. Of course, while ensuring driving capability, the input terminals of the two drive units 210 of the drive unit group 200 are connected to the same clock signal line 320 to receive the same clock signal, reducing the number of clock signal lines and achieving a narrower bezel.

[0055] Furthermore, such as Figure 5As shown in the fifth embodiment of this application, a first pull-down circuit 111 is provided corresponding to the first driving unit 211, and a second pull-down circuit 112 is provided corresponding to the second driving unit 212. In the two GDL units in a driving unit group 200, different pull-down signals (VSSG1, VSSG2) are used to control the waveform of the gate driving signal output. When the DLG mode is enabled, the pull-down voltages VSSG1 and VSSG2 corresponding to the first pull-down circuit 111 are set to different voltages, so that the gate opening degree of the two adjacent rows is different, and the two rows that are opened at the same time have different charging rates, thereby producing different display effects, compensating for the display effect of the DLG mode, and optimizing the jaggedness of the screen edges; in addition, when the DLG mode is not enabled, VSSG1 and VSSG2 are set to the same voltage, so that the same display effect as the prior art can be achieved.

[0056] like Figure 6 As shown, in the fifth embodiment of this application, unlike the embodiments above, considering the different refresh rates of two consecutive frames, which may result in different jagged effects, the greater the difference in refresh rates, the more obvious the jaggedness, requiring a stronger pull-down to improve the jaggedness at the edges of the screen and enhance the display effect of the dual-line gate mode. Therefore, the pull-down circuit 110 can be equipped with two pull-down voltages, which can be used for switching between different refresh rates. Specifically, the pull-down circuit 110 includes a refresh rate detection module 113, a judgment module 114, a first switch module 115, and a second switch module 116. The detection module 113 is connected to the judgment module 114, and the judgment module 114 is connected to the first switch module 115 and the second switch module 116 respectively. The input terminal of the first switch module 115 is connected to the output terminal of the first pull-down voltage, and the input terminal of the second switch module 116 is connected to the output terminal of the second pull-down voltage. The output terminals of the first switch module 115 and the second switch module 116 are connected to the output terminal of the display driving circuit 100.

[0057] The detection module 113 is used to detect the refresh rate of the current frame and the next frame. The judgment module 114 calculates the result based on the difference between the refresh rates of the current frame and the next frame and controls the conduction of the first switch module 115 and the second switch module 116 respectively, so as to input different pull-down voltages to the output terminal of the driving unit 210 to pull down the gate driving signal of the output terminal of the display driving circuit 100. Generally, the judgment module 114 stores at least a first preset value and a second preset value. The difference is compared with the first preset value and the second preset value respectively. When the difference is less than the first preset value, the pull-down circuit 110 is not activated. When the difference is greater than the first preset value and less than the second preset value, the pull-down circuit 110 is activated and the first pull-down voltage VSS1 is used to pull down the gate driving signal of the output terminal of the driving unit 210. When the difference is greater than the second preset value, the pull-down circuit 110 is activated and the second pull-down voltage VSS2 is used to pull down the gate driving signal of the output terminal of the driving unit 210.

[0058] like Figure 7 As shown, as the seventh embodiment of this application, a display panel 300 is disclosed. The display panel 300 includes a display driving circuit 100 as described above, as well as multiple clock signal lines 320 and multiple scan lines 310. The input terminal of the display driving circuit 100 is connected to the corresponding clock signal line 320, and the output terminal is connected to the corresponding scan line 310. The pull-down circuit 110 in the display driving circuit 100 is connected between the input terminal of the display driving circuit 100 and the corresponding scan line 310.

[0059] It should be noted that the limitations on each step involved in this solution are not considered as limiting the order of steps, provided that they do not affect the implementation of the specific solution. The steps listed first can be executed first, later, or even simultaneously. As long as this solution can be implemented, it should be considered to fall within the scope of protection of this application.

[0060] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0061] The technical solution of this application can be widely used in various driving methods, such as TN (Twisted Nematic) driving method, IPS (In-Plane Switching) driving method, VA (Vertical Alignment) driving method, MVA (Multi-Domain Vertical Alignment) driving method, and of course, other types of driving methods, such as OLED (Organic Light-Emitting Diode) driving method, are also applicable to the above solution.

[0062] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A driving method for a display driving circuit, the display driving circuit comprising a plurality of cascaded driving unit groups, each driving unit group comprising at least two driving units, each driving unit group simultaneously opening two scan lines, and at least one pull-down circuit corresponding to each driving unit group, the pull-down circuit being connected to the output terminal of the driving unit, characterized in that, The driving method includes the following steps: The input terminals of the two driving units in the driving unit group receive the same clock signal and generate two corresponding identical gate driving signals; and The pull-down circuit is activated to pull down the gate drive signal at the output of one of the two drive units, thereby obtaining a gate drive signal with a waveform different from the gate drive signal at the output of the other drive unit and outputting it to the corresponding scan line. The pull-down circuit includes a first pull-down voltage and a second pull-down voltage, wherein the value of the first pull-down voltage is greater than the value of the second pull-down voltage. The step of activating the pull-down circuit to pull down the gate drive signal at the output terminal of one of the two drive units, thereby obtaining a gate drive signal with a waveform different from the gate drive signal at the output terminal of the other drive unit, and outputting it to the corresponding scan line, further includes: Detect the current frame refresh rate, obtain the next frame refresh rate, and calculate the difference between the current frame refresh rate and the next frame refresh rate; and The difference is compared with a first preset value and a second preset value. When the difference is less than the first preset value, the pull-down circuit is not activated. When the difference is greater than the first preset value and less than the second preset value, the pull-down circuit is activated, and the first pull-down voltage is used to pull down the gate drive signal at the output terminal of the drive unit. When the difference is greater than the second preset value, the pull-down circuit is activated, and the second pull-down voltage is used to pull down the gate drive signal at the output terminal of the drive unit.

2. The driving method as described in claim 1, characterized in that, Each drive unit group includes a first drive unit and a second drive unit. A first pull-down circuit is provided for the first drive unit, and a second pull-down circuit is provided for the second drive unit. The step of activating the pull-down circuit to pull down the gate drive signal at the output terminal of one of the two drive units, thereby obtaining a gate drive signal with a waveform different from the gate drive signal at the output terminal of the other drive unit, and outputting it to the corresponding scan line includes: The first pull-down circuit is activated to pull down the gate drive signal at the output terminal of the first drive unit, and the second pull-down circuit is activated at the same time to pull down the gate drive signal at the output terminal of the second drive unit, thereby obtaining a gate drive signal with a waveform different from the gate drive signal at the output terminal of the drive unit and outputting it to the corresponding scan line. The gate drive signal generated by the first pull-down circuit pulling down the gate drive signal at the output of the first drive unit is different from the gate drive signal generated by the second pull-down circuit pulling down the gate drive signal at the output of the second drive unit.

3. The driving method as described in claim 2, characterized in that, The distance between the first driving unit and the input end of the data line is less than the distance between the input end of the data line of the second driving unit, and the pull-down voltage in the first pull-down circuit is less than the pull-down voltage in the second pull-down circuit.

4. The driving method as described in claim 2, characterized in that, The first pull-down circuit is turned on later than the second pull-down circuit.

5. The driving method as described in claim 1, characterized in that, The pull-down circuit is turned on earlier than the falling edge of the high-level signal of the gate drive signal at the output of the driving unit, and the pull-down circuit is turned off earlier than the falling edge of the high-level signal of the gate drive signal of the next frame corresponding to the current driving unit.

6. A display driving circuit, driven using the driving method as described in any one of claims 1-5, characterized in that, The display driving circuit includes multiple cascaded driving unit groups and pull-down circuits; Each of the driving unit groups includes at least two driving units, and at least one pull-down circuit is provided for each driving unit group. The pull-down circuit is connected to the output terminal of the driving unit. The pull-down circuit is used to pull down the gate driving signal at the output terminal of the display driving circuit to generate a gate driving signal with a waveform different from the gate driving signal at the output terminal of the display driving circuit and output it to the scan line.

7. The display driving circuit as described in claim 6, characterized in that, The input terminals of the two drive units in the drive unit group are connected to the same clock signal line and receive the same clock signal.

8. The display driving circuit as described in claim 6, characterized in that, The pull-down circuit includes a refresh rate detection module, a judgment module, a first switch module, and a second switch module. The detection module is connected to the judgment module, and the judgment module is connected to the first switch module and the second switch module respectively. The input terminal of the first switch module is connected to the output terminal of the first pull-down voltage, the input terminal of the second switch module is connected to the output terminal of the second pull-down voltage, and the output terminals of the first switch module and the second switch module are connected to the output terminal of the display driver circuit. The detection module is used to detect the refresh rate of the current frame and the next frame. The judgment module calculates the result based on the difference between the refresh rates of the current frame and the next frame and controls the conduction of the first switch module and the second switch module respectively, so as to input different pull-down voltages to the output terminal of the driving unit to pull down the gate driving signal of the output terminal of the display driving circuit.

9. A display panel, characterized in that, The display panel includes a display driving circuit as described in any one of claims 6-8, as well as multiple clock signal lines and multiple scan lines. The input terminal of the display driving circuit is connected to the corresponding clock signal line, and the output terminal is connected to the corresponding scan line. The pull-down circuit in the display driving circuit is connected between the input terminal of the display driving circuit and the corresponding scan line.

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