Three-dimensional stacked chips and their power supply configuration method

Abstract

This application discloses a three-dimensional stacked chip and its power supply configuration method. The three-dimensional stacked chip includes: a logic wafer layer and a memory wafer layer stacked sequentially, and a power network including a logic power network and a memory power network. The power network is disposed on one of the logic wafer layer and the memory wafer layer; or, the logic power network is disposed on the memory wafer layer and the memory power network is disposed on the logic wafer layer. This facilitates full utilization of the wiring resources of each wafer layer, alleviates wiring congestion in the chip, and improves the chip's implementability.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a three-dimensional stacked chip and its power supply configuration method. Background Technology

[0002] With the continuous development of semiconductor packaging technology, three-dimensional stacked chips have gradually emerged. Compared with two-dimensional chips, the power supply difficulty of three-dimensional stacked chips is significantly increased. As the core of the entire chip, the power supply scheme plays a decisive role in the chip's functionality, performance, and stability. Therefore, the power supply scheme has attracted great attention from designers. Reducing the IR drop, improving power supply stability, and minimizing the occupation of chip wiring channels have become the main themes of current power supply scheme design.

[0003] As the demand for wiring resources in 3D stacked chips increases, chip wiring congestion can easily occur, making it difficult to achieve the expected functions of the chip. Summary of the Invention

[0004] This application provides a three-dimensional stacked chip and its power supply configuration method, which can effectively improve the technical problem of wiring congestion in the three-dimensional stacked chip.

[0005] In a first aspect, embodiments of this application provide a three-dimensional stacked chip, comprising:

[0006] The logic wafer layer and the memory wafer layer are stacked sequentially.

[0007] The power network includes a logic power network and a storage power network, wherein the power network is disposed on one of the logic wafer layer and the storage wafer layer; or...

[0008] The logic power network is disposed on the storage wafer layer, and the storage power network is disposed on the logic wafer layer.

[0009] Furthermore, the power network is disposed on the memory wafer layer, and the power pins of the logic chip units in the logic wafer layer are connected to the logic power network disposed on the memory wafer layer through a hybrid bonding structure.

[0010] Furthermore, the aforementioned three-dimensional stacked chip also includes: a logic power pump and a storage power pump disposed on the surface of the logic wafer layer.

[0011] The logic wafer layer is provided with a first through-silicon via (TSV) and a second TSV. The logic power network is connected to the logic power pump through the first TSV and a hybrid bonding structure. The storage power network is connected to the logic power pump through the second TSV and a hybrid bonding structure. The logic power pump is used to connect the logic power network to an external power source, and the storage power pump is used to connect the storage power network to an external power source.

[0012] Furthermore, the wiring resources of the multilayer metal near the top layer in the logic wafer layer are used for wiring of the logic chip cells.

[0013] Furthermore, the power network is disposed on the logic wafer layer, and the power pins of the memory chip units in the memory wafer layer are connected to the memory power network disposed on the logic wafer layer through a hybrid bonding structure.

[0014] Furthermore, the aforementioned three-dimensional stacked chip also includes: a logic power pump and a storage power pump disposed on the surface of the logic wafer layer.

[0015] The logic power network and storage power network provided in the logic wafer layer are directly connected to the logic power pump and storage power pump, respectively. The logic power pump is used to connect the logic power network to an external power source, and the storage power pump is used to connect the storage power network to an external power source.

[0016] Furthermore, the logic power network is disposed on the memory wafer layer, and the memory power network is disposed on the logic wafer layer. The power pins of the logic chip units in the logic wafer layer are connected to the logic power network disposed on the memory wafer layer through a hybrid bonding structure. The power pins of the memory chip units in the memory wafer layer are connected to the memory power network disposed on the logic wafer layer through a hybrid bonding structure.

[0017] Furthermore, the aforementioned three-dimensional stacked chip also includes: a logic power pump and a storage power pump disposed on the surface of the logic wafer layer.

[0018] The logic wafer layer is provided with through-silicon vias (TSVs). The logic power network is connected to the logic power pump through the TSVs and a hybrid bonding structure. The storage power network is directly connected to the storage power pump. The logic power pump is used to connect the logic power network to an external power source, and the storage power pump is used to connect the storage power network to an external power source.

[0019] Secondly, embodiments of this application also provide a power supply configuration method for three-dimensional stacked chips, the method comprising:

[0020] Determine the wiring resources for the logic wafer layer and memory wafer layer of the 3D stacked chip;

[0021] Determine the wiring resource requirements of the logic wafer layer and the memory wafer layer;

[0022] In response to the routing resources and the routing resource requirements meeting the preset layout routing conditions, the logic power network and the storage power network of the three-dimensional stacked chip are both set in one of the logic wafer layer and the storage wafer layer; or, the logic power network is set in the storage wafer layer and the storage power network is set in the logic wafer layer.

[0023] Furthermore, the above power supply configuration method also includes:

[0024] For the memory power network located on the logic wafer layer and / or the logic power network located on the memory wafer layer, hybrid bonding pads are provided to connect to the power output terminals;

[0025] The power pins of the chip cells in the corresponding wafer layer are interconnected with the hybrid bonding pads using hybrid bonding technology.

[0026] The three-dimensional stacked chip and its power supply configuration method provided in this application embodiment can transfer the power network corresponding to the wafer layer with relatively tight wiring resources to other wafer layers with relatively loose wiring resources by setting the entire power network in one of the logic wafer layer and the memory wafer layer; or, setting the logic power network in the memory wafer layer and the memory power network in the logic wafer layer. This is beneficial to make full use of the wiring resources of each wafer layer, realize the rational configuration of wiring resources, thereby alleviating the wiring congestion in the wafer layer with tight wiring and improving the chip's feasibility.

[0027] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0028] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0029] Figure 1 This specification shows a schematic diagram of a first structure of a three-dimensional stacked chip in an embodiment of the present specification;

[0030] Figure 2A schematic diagram of a second structure of a three-dimensional stacked chip is shown in the embodiments of this specification;

[0031] Figure 3 A schematic diagram of a third structure of a three-dimensional stacked chip is shown in the embodiments of this specification;

[0032] Figure 4 The diagram shows the congestion results before the improvement in the embodiments of this specification;

[0033] Figure 5 The improved congestion result diagram in the embodiments of this specification is shown;

[0034] Figure 6 This specification includes a flowchart of the power supply configuration method for the three-dimensional stacked chip in the embodiments. Detailed Implementation

[0035] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0036] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0037] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0038] As the demand for chip wiring resources increases, current power supply designs consume significant amounts of wiring resources for both logic and memory wafers, with each wafer layer requiring its own independent power supply. Therefore, distributing the power network across the top metal layer of each wafer would consume substantial wiring resources within that wafer. Considering the wiring resource requirements of logic and memory chip units, this can easily lead to severe wiring congestion, making it difficult to achieve the intended chip functionality.

[0039] In view of this, embodiments of this specification provide a three-dimensional stacked chip and its power supply configuration method. By setting the entire power network in one of the logic wafer layer and the memory wafer layer; or, setting the logic power network in the memory wafer layer and the memory power network in the logic wafer layer, the power network of the wafer layer with relatively tight wiring resources is transferred to other wafer layers with relatively loose wiring resources. This is beneficial to make full use of the wiring resources of each wafer layer, realize the rational configuration of wiring resources, thereby alleviating the wiring congestion in the wafer layer with tight wiring and improving the chip's implementability.

[0040] The specific implementation schemes provided in the embodiments of this specification will be described in detail below.

[0041] Figure 1 A schematic diagram of a three-dimensional stacked chip structure provided in an embodiment of this specification is shown. It should be noted that... Figure 1 The logic wafer layer 11 and the storage wafer layer 12 shown are for illustrative purposes only. This embodiment does not limit the number of logic wafer layers and the number of storage wafer layers contained in the three-dimensional stacked chip.

[0042] like Figure 1 As shown in the embodiments of this specification, the three-dimensional stacked chip includes: a power network, a logic wafer layer 11 and a memory wafer layer 12 stacked sequentially. Logic chip units (not shown in the figure) are disposed in the logic wafer layer 11, and memory chip units (not shown in the figure) are disposed in the memory wafer layer 12. The power network includes a logic power network and a memory power network. The logic power network provides operating voltage to the logic chip units, and the memory power network provides operating voltage to the memory chip units.

[0043] To implement chip functionality, multiple metal layers are set up in each wafer for wiring. However, if the available wiring resources in a wafer are less than the required wiring resources, i.e., the wiring resource demand, wiring congestion will occur. The wiring resource demand includes the wiring resources required by the chip units provided by the wafer layers and the wiring resources required by the corresponding power networks.

[0044] Considering that the wiring resource requirements of different wafers are different, the embodiments of this specification deploy the power network corresponding to the chip unit in the wafer layer with relatively tight wiring resources to the wafer layer with relatively loose wiring resources. For example, the entire power network (including the logic power network and the memory power network) is set in one of the logic wafer layer and the memory wafer layer; or, the logic power network is set in the memory wafer layer and the memory power network is set in the logic wafer layer. This is conducive to the rational use of wiring resources and alleviates wiring congestion.

[0045] For example, suppose a logic wafer layer contains 10 metal layers: layers M1-M8 and two metal layers TM1 and TM2 near the top. Typically, the power network of the logic wafer layer is configured in layers TM1 and TM2, while the circuit network of the logic chip cells is configured in layers M1-M8. When the routing requirements of the logic chip cell circuit network are large, routing congestion can easily occur. In this case, for the logic wafer layer, if the logic power network is moved to the memory wafer layer where routing resources are relatively relaxed, and the routing resources of layers TM1 and TM2 are also used for the routing of the logic chip cells, the routing layers for the logic chip cells can be increased. This greatly alleviates the layout congestion of the logic chip cells, thereby significantly improving the likelihood of successful routing of the logic chip cells.

[0046] In practical implementation, the placement of power networks in a 3D stacked chip can be determined based on the actual wiring resources and requirements of each wafer layer. For example, during the placement and routing stage, the congestion level of each wafer layer can be detected in advance based on the wiring resources and requirements of the logic and memory wafer layers. This determines whether the power networks need to be relocated to alleviate placement congestion and improve chip feasibility. For instance, if the wiring congestion level of the logic wafer layer exceeds a preset congestion level, while the memory wafer layer has sufficient remaining wiring resources beyond its own wiring resource requirements to place the logic power network, then both the logic power network and the memory power network can be placed on the memory wafer layer. The preset congestion level can be determined based on the needs of the actual application scenario and through multiple experiments.

[0047] It is understood that in a three-dimensional stacked chip, the power pins of the chip units provided by each wafer layer need to be connected to the corresponding power networks to provide the required operating voltage to the chip units. In an optional implementation, for chip units located on the same wafer layer as the corresponding power network, the connection between the power pins and the corresponding power network can be achieved through the wiring design of that wafer layer. For chip units located on different wafer layers from the corresponding power network, the power pins can be connected to the corresponding power networks located on other wafer layers through hybrid bonding technology. Of course, in other embodiments of the specification, other applicable inter-layer interconnection methods can also be used, which are not limited here.

[0048] Furthermore, in addition to the logic wafer layer 11 and the memory wafer layer 12, the three-dimensional stacked chip may also include a power bump, specifically including a logic power pump 101 and a memory power pump 102. For example, as Figure 1 As shown, the logic power pump 101 and the storage power pump 102 can be disposed on the side of the logic wafer layer 11 away from the storage wafer layer 12. The logic power pump 101 is used to connect an external power source to the logic power network 110; the storage power pump 102 is used to connect an external power source to the storage power network 120.

[0049] In one alternative implementation, for power networks located in wafer layers adjacent to power pumps, the corresponding power pump can be directly connected to the power network. For power networks located in wafer layers not adjacent to power pumps, the corresponding power pump and power network can be interconnected by using vias such as TSVs (Through Silicon Vias) and hybrid bonding structures. Of course, in other embodiments of the specification, other suitable interlayer interconnection methods can also be used, and are not limited here.

[0050] To better understand the technical solutions provided in the embodiments of this specification, the three-dimensional stacked chip structures for three different power network migration scenarios are described below.

[0051] The first type, such as Figure 1As shown, logic power network 110 is located on memory wafer layer 12, and memory power network 120 is located on logic wafer layer 11. This means that logic power network 110 and memory power network 120 require different amounts of wiring resources. Compared to routing the memory power network, the remaining wiring resources in memory wafer layer 12 (excluding logic chip units) are more suitable for routing logic power network 110. Similarly, logic wafer layer 11 is more suitable for routing memory power network 120, thus swapping the locations of logic power network 110 and memory power network 120.

[0052] At this point, the power supply pins of the memory chip unit are interconnected with the memory power network 120 arranged in the logic wafer layer 11 through a hybrid bonding structure. The power supply pins of the logic chip unit are interconnected with the logic power network 110 arranged in the memory wafer layer 12 through a hybrid bonding structure, thereby realizing the power supply of the entire 3D chip.

[0053] In addition, the logic wafer layer 11 is provided with a through silicon via 111, and the logic power pump 101 is connected to the logic power network 110 provided in the storage wafer layer 12 through the through silicon via 111 and the hybrid bonding structure.

[0054] The second scenario involves situations where wiring resources on the storage wafer layer 12 are relatively scarce, while wiring resources on the logic wafer layer 11 are relatively abundant and sufficient for routing the storage power network 120 and the logic power network 110. For example... Figure 2 As shown, the storage power network 120 and the logic power network 110 can both be disposed on the logic wafer layer 11.

[0055] At this time, the power supply pins of the memory chip unit are interconnected with the memory power network 120 arranged in the logic wafer layer 11 through a hybrid bonding structure, thereby realizing the power supply of the entire 3D chip. The logic power pump 101 and the memory power pump 102 are both disposed on the surface of the logic wafer layer 11 away from the memory wafer layer 12, and are directly connected to the logic power network 110 and the memory power network 120 disposed in the logic wafer layer 11.

[0056] Furthermore, the wiring resources of the multi-layer metal near the top layer in the memory wafer layer 12 can be used for wiring of the memory chip cells. Specifically, which metal layers near the top layer can be determined based on the metal layers used for routing the memory power network 120 in a traditional memory wafer layer. For example, the memory wafer layer 12 includes four metal layers, namely layers M1-M4. Among them, the multi-layer metal near the top layer, such as two metal layers, were originally used for wiring of the memory power network 120. Now, by transferring the memory power network 120 to the logic wafer layer 11 with relatively relaxed wiring resources, these metal layers can also be used for wiring of the memory chip cells. Because of the increase in wiring layers, the possibility of partial routing of the memory chip cells can be greatly improved, thereby improving the chip's feasibility.

[0057] The third scenario involves situations where wiring resources on the logic wafer layer 11 are relatively scarce, while wiring resources on the storage wafer layer 12 are relatively abundant and sufficient for routing the storage power network 120 and the logic power network 110. For example... Figure 3 As shown, both the logic power network 110 and the storage power network 120 can be located on the storage wafer layer 12. In an optional embodiment, the wiring resources of the multilayer metal near the top layer of the logic wafer layer are used for wiring of the logic chip cells. It is understood that in conventional chip structures, the metal layers near the top layer of the logic wafer layer were originally used to lay out the logic power network 110. By migrating the logic power network 110 to the storage wafer layer 12, the logic chip cells can occupy these wiring resources, which helps alleviate layout congestion of the logic chip cells.

[0058] At this point, the power pins of the logic chip unit are interconnected with the logic power network 110 arranged in the memory wafer layer 12 through a hybrid bonding structure. Then, the logic wafer layer 11 is provided with a first through-silicon via 112 and a second through-silicon via 113. The logic power pump 101 is connected to the logic power network 110 arranged in the memory wafer layer 12 through the first through-silicon via 112 and the hybrid bonding structure. The memory power pump 102 is connected to the memory power network 120, which is also arranged in the memory wafer layer 12, through the second through-silicon via 113 and the hybrid bonding structure, thereby supplying power to the two power networks and realizing the power supply of the entire 3D chip.

[0059] Furthermore, in order to verify the effectiveness of the technical solutions provided in the embodiments of this specification, the inventors also conducted comparative experiments, and the experimental results are described below.

[0060] The experiment uses a three-dimensional stacked structure, comprising a logic wafer layer 11 and a memory wafer layer 12, as an example, and employs a 40nm process for Place and Route (PR). The logic wafer layer 11 contains 10 metal layers, designated M1-M8, and two top metal layers, TM1 and TM2. The power networks of the logic chip cells are first laid out onto the TM1 and TM2 layers, and the placement and routing are then checked to obtain the congestion results.

[0061] Understandably, in practical applications, the degree of congestion in the congestion result image is represented by different colors, in the order of red, orange, yellow, green, cyan, blue, and purple, with red indicating the highest congestion and purple the lowest. The grayscale image converted from the congestion result image is shown below. Figure 4 As shown. From Figure 4 As can be seen, if the power network of the logic chip unit is placed in the logic wafer layer 11, occupying the wiring resources of the TM1 and TM2 layers, it will lead to very serious congestion.

[0062] In contrast, using the third approach described above, layers TM1 and TM2 are used for wiring of the logic chip cells, resulting in a congestion effect. The grayscale image of this congestion effect is shown below. Figure 5 As shown. Comparison Figure 4 and Figure 5 It is evident that by adopting the third approach described above, the layout congestion of the logic chip units is greatly alleviated due to the increase in wiring layers, and the possibility of partial routing of the logic chip units is greatly improved, thereby enhancing the chip's feasibility.

[0063] in addition, Figure 6 A flowchart illustrating a power supply configuration method for a three-dimensional stacked chip according to an embodiment of this specification is shown, used to configure the power network in the three-dimensional stacked chip provided in the above embodiment. Figure 6 As shown, the method may include the following steps S601 to S603.

[0064] Step S601: Determine the wiring resources of the logic wafer layer and the memory wafer layer of the three-dimensional stacked chip;

[0065] Step S602: Determine the wiring resource requirements for the logic wafer layer and the memory wafer layer;

[0066] In step S603, in response to the routing resources and routing resource requirements meeting the preset layout routing conditions, the logic power network and the memory power network of the three-dimensional stacked chip are both set on one of the logic wafer layer and the memory wafer layer; or, the logic power network is set on the memory wafer layer and the memory power network is set on the logic wafer layer.

[0067] Specifically, the DRC (Design Rules Check) rules for logic wafer layer 11 and memory wafer layer 12 can be obtained from the chip manufacturer, and the routing resources of logic wafer layer 11 and memory wafer layer 12 can be determined. For specific implementation details, please refer to relevant technologies, which will not be elaborated here.

[0068] In step S602 above, the wiring resource requirements include the wiring resources required by the chip units provided by the wafer layer and the wiring resources required by the corresponding power networks. The wiring resource requirements of the logic wafer layer 11 include the wiring resources required by the logic chip units and the wiring resources required by the logic power network 110. The wiring resource requirements of the storage wafer layer 12 include the wiring resources required by the storage chip units and the wiring resources required by the storage power network 120. By evaluating the wiring conditions and power supply stability of the logic wafer layer 11 and the storage wafer layer 12 respectively, the wiring resource requirements of the logic wafer layer 11 and the storage wafer layer 12 can be determined.

[0069] In practice, preset layout and routing conditions can be set in advance for each of the three power network migration methods based on multiple tests. For example, the preset layout and routing conditions can be set for the following parameters: routing requirements of logic power networks, routing requirements of logic chip cells, routing resources of logic wafer layers, routing requirements of storage power networks, routing requirements of storage chip cells, and routing resources of storage wafer layers.

[0070] For example, in the above embodiments, the preset layout and routing condition corresponding to the first power network migration scenario is condition ①, and the preset layout and routing condition corresponding to the second power network migration scenario is condition ②. In the above embodiments, the preset layout and routing condition corresponding to the third power network migration scenario is condition ③.

[0071] If the wiring resources and wiring resource requirements of logic wafer layer 11 and memory wafer layer 12 meet condition ①, it indicates that the remaining wiring resources in memory wafer layer 12, excluding logic chip units, are more suitable for routing logic power network 110. Similarly, logic wafer layer 11 is more suitable for routing memory power network 120. In this case, logic power network 110 can be located in memory wafer layer 12, and memory power network 120 can be located in logic wafer layer 11.

[0072] If the wiring resources and wiring resource requirements of logic wafer layer 11 and memory wafer layer 12 meet condition ②, it indicates that the wiring resources of memory wafer layer 12 are relatively tight, while the wiring resources of logic wafer layer 11 are relatively loose and sufficient to deploy memory power network 120 and logic power network 110. In this case, memory power network 120 and logic power network 110 can both be located on logic wafer layer 11.

[0073] If the wiring resources and wiring resource requirements of logic wafer layer 11 and memory wafer layer 12 meet condition ③, it indicates that the wiring resources of logic wafer layer 11 are relatively tight, while the wiring resources of memory wafer layer 12 are relatively loose and sufficient to deploy memory power network 120 and logic power network 110. In this case, both logic power network 110 and memory power network 120 can be located on memory wafer layer 12.

[0074] Furthermore, after setting the positions of the storage power network 120 and logic power network 110 in the three-dimensional stacked chip, it is necessary to interconnect the power networks with the power pins of the corresponding chip units.

[0075] For chip cells located on the same wafer layer as the corresponding power network, the power pins can be connected to the corresponding power network through the wiring design of that wafer layer. For memory power networks located on logic wafer layers and / or logic power networks located on memory wafer layers, hybrid bonding pads (PADs) can be set to connect to the power output terminals. Hybrid bonding technology can be used to interconnect the power pins of the chip cells in the corresponding wafer layer with these hybrid bonding pads, thereby achieving the connection between power networks and chip cells located on different wafer layers. It should be noted that the connection between the chip cell power pins and the migrated power network after migrating the power network, as well as the connection between the migrated power network and the power pump, has been described in detail in the above embodiments and will not be repeated here.

[0076] In one alternative implementation, if the power supply stability requirements of the 3D stacked chip are high, information such as the power stripes and power pitch of the logic wafer layer 11 and the memory wafer layer 12 can be determined according to DRC rules to classify the power supply stability of the logic wafer layer 11 and the memory wafer layer 12. Then, the power networks of the 3D stacked chip can be placed in the wafer layers with higher power supply stability, thereby improving the power supply stability of the 3D stacked chip.

[0077] The power supply configuration method provided in the embodiments of this specification allows for flexible setting of the power supply network location, freeing up scarce wiring resources to realize chip functionality. It is applicable to 3D stacked chips under different processes, effectively alleviating wiring congestion on wafer layers with limited wiring resources and improving chip feasibility. Furthermore, it can improve the stability of the power supply network for large chips, thereby enhancing chip reliability.

[0078] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The term "a plurality of" means two or more, including two or more cases.

[0079] Although preferred embodiments have been described in this specification, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this specification.

[0080] Obviously, those skilled in the art can make various modifications and variations to this specification without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims and their equivalents, this specification is also intended to include such modifications and variations.

Claims

1. A three-dimensional stacked chip, characterized in that, include: The logic wafer layer and the memory wafer layer are stacked sequentially. A power network, including a logic power network and a storage power network, wherein the power network is disposed on one of the logic wafer layer and the storage wafer layer; or, The logic power network is disposed on the memory wafer layer, and the memory power network is disposed on the logic wafer layer. Different wafers have different wiring resource requirements. The power network corresponding to the chip unit in the wafer layer with tight wiring resources is deployed to the wafer layer with loose wiring resources.

2. The three-dimensional stacked chip according to claim 1, characterized in that, The power network is disposed on the memory wafer layer, and the power pins of the logic chip units in the logic wafer layer are connected to the logic power network disposed on the memory wafer layer through a hybrid bonding structure.

3. The three-dimensional stacked chip according to claim 2, characterized in that, Also includes: A logic power pump and a storage power pump are disposed on the surface of the logic wafer layer. The logic wafer layer is provided with a first through-silicon via (TSV) and a second TSV. The logic power network is connected to the logic power pump through the first TSV and a hybrid bonding structure. The storage power network is connected to the logic power pump through the second TSV and a hybrid bonding structure. The logic power pump is used to connect the logic power network to an external power source, and the storage power pump is used to connect the storage power network to an external power source.

4. The three-dimensional stacked chip according to claim 2, characterized in that, The wiring resources of the multilayer metal near the top layer in the logic wafer layer are used for wiring of the logic chip unit.

5. The three-dimensional stacked chip according to claim 1, characterized in that, The power network is disposed on the logic wafer layer, and the power pins of the memory chip units in the memory wafer layer are connected to the memory power network disposed on the logic wafer layer through a hybrid bonding structure.

6. The three-dimensional stacked chip according to claim 5, characterized in that, Also includes: A logic power pump and a storage power pump are disposed on the surface of the logic wafer layer. The logic power network and the storage power network disposed in the logic wafer layer are directly connected to the logic power pump and the storage power pump, respectively. The logic power pump is used to connect the logic power network to an external power source, and the storage power pump is used to connect the storage power network to an external power source.

7. The three-dimensional stacked chip according to claim 1, characterized in that, The logic power network is disposed on the memory wafer layer, and the memory power network is disposed on the logic wafer layer. The power pins of the logic chip units in the logic wafer layer are connected to the logic power network disposed on the memory wafer layer through a hybrid bonding structure. The power pins of the memory chip units in the memory wafer layer are connected to the memory power network disposed on the logic wafer layer through a hybrid bonding structure.

8. The three-dimensional stacked chip according to claim 7, characterized in that, Also includes: Logic power pumps and storage power pumps are disposed on the surface of the logic wafer layer. The logic wafer layer is provided with through-silicon vias (TSVs). The logic power network is connected to the logic power pump through the TSVs and a hybrid bonding structure. The storage power network is directly connected to the storage power pump. The logic power pump is used to connect the logic power network to an external power source, and the storage power pump is used to connect the storage power network to an external power source.

9. A power supply configuration method for a three-dimensional stacked chip, characterized in that, The method includes: Determine the wiring resources for the logic wafer layer and memory wafer layer of the 3D stacked chip; Determine the wiring resource requirements of the logic wafer layer and the memory wafer layer; In response to the routing resources and the routing resource requirements meeting the preset layout routing conditions, the logic power network and the storage power network of the three-dimensional stacked chip are both set in one of the logic wafer layer and the storage wafer layer; or, the logic power network is set in the storage wafer layer and the storage power network is set in the logic wafer layer.

10. The power supply configuration method according to claim 9, characterized in that, Also includes: For the memory power network located on the logic wafer layer and / or the logic power network located on the memory wafer layer, hybrid bonding pads are provided to connect to the power output terminals; The power pins of the chip cells in the corresponding wafer layer are interconnected with the hybrid bonding pads using hybrid bonding technology.

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