A single-phase and multi-phase constant on-time dc-dc converter

Abstract

The application discloses a single-phase and multi-phase constant conduction time DC-DC converter, comprising a source signal generation module, a phase number indication module, a master-slave phase determination module, a PWM generation module, a driving module and a master-slave phase synchronization signal generation module; the input end of the master-slave phase synchronization signal generation module is connected with a signal SYNC; the master-slave phase synchronization signal generation module outputs a signal SET and a signal SYNC_BUF. The signal SET output by the master-slave phase synchronization signal generation module in the application is used as a global control signal of a multi-phase constant conduction time control technology, the signal SYNC and the signal SYNC_BUF are used as synchronization control signals; single-chip separate control can be realized, multi-chip parallel control can be adopted, and multi-phase control technology can be realized in a single-chip multi-phase parallel controller.

Description

Technical Field

[0001] This invention relates to the field of DC-DC converter technology, and in particular to a DC-DC converter with constant on-time for single-phase and multi-phase applications. Background Technology

[0002] Constant on-time control schemes inherently possess high transient response capabilities, thus they are increasingly being applied in high-transient scenarios. Single-phase constant on-time control has the advantages of simple structure and high transient response, while multi-phase parallel power management technology can improve maximum current output capability and transient response performance, making it particularly suitable for low-voltage, high-current load power supply. The technology of cascading single-phase constant on-time control into multi-phase systems is becoming increasingly advantageous.

[0003] In low to medium current scenarios, such as Figure 1 The diagram shows a single-chip power supply. The SYNC pin is connected to DVDD (which can be generated by the chip itself or supplied externally) via resistor R0 to confirm that this chip is the master phase chip. The SET pin, SYNC_BUF pin, and ISUM pin are left floating. A suitable value for R1 is chosen to ensure single-phase operation. SW and VOUT are connected to a conventional constant-on-time DC-DC converter to achieve individual single-phase control. In high-current scenarios, such as... Figure 2 As shown, multiple chips can be connected in parallel to achieve balanced power supply to the load simultaneously. The SYNC pin of the master phase chip is connected to DVDD through resistor R0 to confirm that this chip is the master phase chip. The PHASE pin of the master phase chip is connected to a resistor of different values ​​to ground or to the power supply to confirm the overall control phase. The PHASE pin of the slave phase chip is connected to a resistor of different values ​​to ground to confirm its slave phase phase. The SET pin is controlled by the master phase for global interconnection. The SYNC pin and SYNC_BUF pin of each phase are connected in sequence to form a closed loop. The ISUM pin is used for global interconnection and is used for current sharing among the chips of each phase. The output voltage signal VOUT is connected to the SW pin of each chip through different inductors, so that each chip can provide a larger current to the output voltage signal VOUT together.

[0004] Currently available DC control technologies that can cascade single-phase to multi-phase still have some problems, such as insufficient anti-interference capability, or the inability to add or subtract phases in real time due to the influence of the speed of the upstream controller when the phase addition or subtraction is controlled in the slave phase. Summary of the Invention

[0005] Based on this, the purpose of this invention is to provide a DC-DC converter with constant on-time for single-phase and multi-phase applications, enabling transient enhancement in multi-chip scenarios and adaptive phase switching based on current.

[0006] To achieve the above objectives, the present invention provides the following solution:

[0007] A single-phase and multi-phase constant on-time DC-DC converter includes: a source signal generation module, a phase number indication module, a master-slave phase determination module, a PWM generation module, a drive module, and a master-slave phase synchronization signal generation module; the input terminal of the master-slave phase synchronization signal generation module is connected to the output terminal of the source signal generation module, the output terminal of the master-slave phase determination module, and the output terminal of the phase number indication module, respectively; the input terminal of the master-slave phase synchronization signal generation module is also connected to the signal SYNC; the master-slave phase synchronization signal generation module outputs the signal SET and the signal SYNC_BUF; the output terminal of the master-slave phase synchronization signal generation module is connected to the input terminal of the PWM generation module, the output terminal of the PWM generation module is connected to the drive module, and the drive module outputs the signal SW.

[0008] Optionally, the source signal generation module includes: a resistor voltage divider circuit, an operational amplifier, a loop compensation network, a triangular wave signal generation module, and a comparator; the input terminal of the resistor voltage divider circuit is connected to the output voltage, and the input terminal of the resistor voltage divider circuit is connected to the first input terminal of the operational amplifier and the first input terminal of the comparator, respectively; the second input terminal of the operational amplifier is connected to a reference voltage, and the output terminal of the operational amplifier is connected to the third input terminal of the comparator; the output terminal of the triangular wave signal generation module is connected to the second input terminal of the comparator; and the output terminal of the comparator is connected to the input terminal of the master-slave phase synchronization signal generation module.

[0009] Optionally, the resistor divider submodule includes a first resistor, a second resistor, and a capacitor; one end of the first resistor is connected to one end of the second capacitor and the output voltage, and the other end of the first resistor is connected to one end of the second resistor, the other end of the second capacitor, and the first input terminal of the comparator; the other end of the second resistor is grounded.

[0010] Optionally, the master-slave synchronization signal generation module includes: a control processor, a master-slave synchronization control operation module, and a selection module;

[0011] The input terminal of the control processor is connected to the output terminal of the comparator; the output signal of the control processor is SET; the output terminal of the control processor is connected to the output terminal of the master-slave phase determination module; the input terminal of the master-slave phase synchronization control operation module is connected to the output terminal of the control processor, the output terminal of the master-slave phase determination module, and the output terminal of the phase number indicator module, respectively; the input terminal of the master-slave phase synchronization control operation module is also connected to the signal SYNC; the output terminal of the master-slave phase synchronization control operation module is connected to the input terminal of the PWM module and the input terminal of the selection module, respectively, and the input terminal of the selection module is also connected to the signal SYNC; the output signal of the selection module is SYNC_BUF.

[0012] Optionally, the SET signal is used as a global control signal, and the SYNC and SYNC_BUF signals are used as synchronization control signals.

[0013] Optionally, the SYNC_BUF signal generated by the master phase chip is used for multiphase control between the master phase chip and the slave phase chip, and is propagated in a low-latency chain between the master phase chip and the slave phase chip, eventually returning to the SYNC port of the master phase chip; the SYNC and SYNC_BUF signals generated by the slave phase chip are independent of the control of the SET signal.

[0014] Optionally, if the DC-DC converter is operating in single-phase mode, there is no interval between the SYNC_BUF signals and the SET signal; if the DC-DC converter is operating in N-phase mode, there are N-1 intervals between the SYNC_BUF signals and the SET signal, where N is a positive integer greater than or equal to 2.

[0015] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0016] The master-slave phase synchronization signal generation module outputs the signal SET in the single-phase and multi-phase constant on-time DC-DC converter provided by this invention. This signal serves as the global control signal for multi-phase constant on-time control, while SYNC and SYNC_BUF serve as synchronization control signals. This allows for individual control of a single chip, multi-chip parallel control, or multi-phase control within a single-chip multi-phase parallel controller. In this invention, the slave phase's on / off state is entirely controlled by the master phase, enabling transient enhancement and adaptive phase switching based on current in multi-chip scenarios. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This diagram illustrates the application of single-phase control technology that allows single-phase systems to be cascaded into multi-phase systems.

[0019] Figure 2 This diagram illustrates the multiphase application of control technology that allows single-phase systems to be cascaded into multiphase systems.

[0020] Figure 3 Circuit diagrams of single-phase and multi-phase constant on-time DC-DC converters provided by the present invention;

[0021] Figure 4Circuit diagram of a DC-DC converter with a pin-saving solution provided by the present invention;

[0022] Figure 5 Multiphase application diagram of control technology that saves pins by cascading single-phase to multiphase control.

[0023] Figure 6 A schematic diagram of a control scheme for controlling four single-phase DC-DC converters with constant on-time or a multiphase parallel controller.

[0024] Figure 7 This diagram illustrates the switching from 4-phase control to 3-phase control in either a 4-phase constant-on-time DC-DC converter control scheme or a multiphase parallel controller scheme.

[0025] Figure 8 This diagram illustrates the switching from 3-phase control to 2-phase control in either a 4-phase constant-on-time DC-DC converter control scheme or a multi-phase parallel controller multi-phase control scheme.

[0026] Figure 9 This diagram illustrates the switching from 2-phase control to 3-phase control in either a 4-phase constant-on-time DC-DC converter control scheme or a multi-phase parallel controller multi-phase control scheme.

[0027] Figure 10 This diagram illustrates the switching from 3-phase control to 4-phase control in a control scheme for 4 single-phase constant-time DC-DC converters or a multi-phase parallel controller. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] The purpose of this invention is to provide a DC-DC converter with constant on-time for single-phase and multi-phase applications, which can not only realize individual control of a single chip, but also realize multi-phase parallel control of multiple chips.

[0030] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0031] like Figure 3As shown, the present invention provides a DC-DC converter with single-phase and multi-phase constant on-time, comprising: a source signal generation module, a phase number indication module, a master-slave phase determination module, a PWM generation module, a driver (Driver+PowerMOS) module, and a master-slave phase synchronization signal generation module; the input terminal of the master-slave phase synchronization signal generation module is connected to the output terminal of the source signal generation module, the output terminal of the master-slave phase determination module, and the output terminal of the phase number indication module, respectively; the input terminal of the master-slave phase synchronization signal generation module is also connected to the signal SYNC (SYNC is short for synchronous); the master-slave phase synchronization signal generation module outputs a set signal, namely the signal SET, and the signal SYNC_BUF (BUF is short for buffer), where SYNC_BUF is a synchronization enhancement of SYNC, and SYNC_BUF and SYNC are in phase; the output terminal of the master-slave phase synchronization signal generation module is connected to the input terminal of the PWM generation module, the output terminal of the PWM generation module is connected to the driver module, and the driver module outputs the signal SW (SWITCH).

[0032] The source signal generation module includes: a resistor divider circuit, an operational amplifier EA, a loop compensation network, a triangular wave signal (RAMP) generation module, and a comparator. The input terminal of the resistor divider circuit is connected to the output voltage VOUT, and the input terminals of the resistor divider circuit are connected to the first input terminal of the operational amplifier EA and the first input terminal of the comparator, respectively. The second input terminal of the operational amplifier is connected to the reference voltage, and the output terminal of the operational amplifier is connected to the third input terminal of the comparator. The output terminal of the triangular wave signal generation module is connected to the second input terminal of the comparator. The output terminal of the comparator is connected to the input terminal of the master-slave synchronization signal generation module.

[0033] The resistor voltage divider module includes a first resistor, a second resistor, and a capacitor; one end of the first resistor is connected to one end of the second capacitor and the output voltage, and the other end of the first resistor is connected to one end of the second resistor, the other end of the second capacitor, and the first input terminal of the comparator; the other end of the second resistor is grounded.

[0034] The master-slave synchronization signal generation module includes: a control processor, a master-slave synchronization control and operation module, and a selection module SEL.

[0035] The input terminal of the control processor is connected to the output terminal of the comparator; the output signal of the control processor is SET; the output terminal of the control processor is connected to the output terminal of the master-slave phase determination module; the input terminal of the master-slave phase synchronization control operation module is connected to the output terminal of the control processor, the output terminal of the master-slave phase determination module, and the output terminal of the phase number indicator module, respectively; the input terminal of the master-slave phase synchronization control operation module is also connected to the signal SYNC; the output terminal of the master-slave phase synchronization control operation module is connected to the input terminal of the PWM module and the input terminal of the selection module, respectively; the input terminal of the selection module is also connected to the signal SYNC; the output signal of the selection module is SYNC_BUF.

[0036] The working principle of this invention is as follows:

[0037] The output voltage signal VOUT generates a feedback voltage VFB through a resistor divider circuit. VFB and the reference voltage VREF generate a signal VEA (output voltage of error amplifier) ​​through an operational amplifier EA and a loop compensation network. VEA is compared with the internal / external triangular wave signal generated by VFB and the RAMP generation module to generate the signal SET_TON, which is used as the source signal for single-phase or multi-phase constant conduction time control.

[0038] The master-slave phase determination module generates an MPH (masterphase) signal to determine the master-slave phase of the chip. The MPH signal can be generated by external resistors, capacitors, or input voltages connected to external pins, or it can be written to the chip through the communication interface.

[0039] The signal MPH generated by the master-slave phase determination module controls a built-in switch. The master phase generates the signal SET, while the slave phase only receives the signal SET. The signal SET_TON of the master phase is sent to the control processor for transient enhancement or single pulse (one_pulse) or similar processing, and then generates the switch output signal SET to perform global control of single-phase or multi-phase constant conduction time control.

[0040] The phase number indicator module generates a phase indicator signal (which can be represented by PHASE_NUM). Different phases are represented by different signals. PHASE_NUM = N means that the multiphase controller has N phases. The master phase controller needs to know the total number of supported phases (N), and the slave phase needs to know its own phase number so that control can be performed. This signal can be generated by external resistors, capacitors or input voltages connected to external pins, or it can be written to the chip through the communication interface.

[0041] The master-slave phase synchronization control operation module is mainly controlled by signals SET, MPH, SYNC and PHASE_NUM. Its main function is to generate the signal SYNC_BUF for the master phase and the signal SET_CHIP for the local phase. The signal SYNC_BUF is input to the signal SYNC of the subsequent stage, and the signal SET_CHIP is input to the PWM generation module and the drive module to finally turn on the upper MOSFET.

[0042] One of the protection points of this invention is the use of the SYNC and SET signals to achieve multiphase control. Here, a control method is provided: the master phase generates a SYNC_BUF signal to perform multiphase control between the master and slave phases, propagating in a low-delay chain between them, ultimately returning to the SYNC pin of the master phase. The slave phase signals SYNC and SYNC_BUF only perform signal amplification, transmission, or simple signal processing, and are unrelated to the control of the SET signal. The SYNC_BUF signal transmitted by the master phase can be the SET signal of the master phase itself, and the slave phase 1 receives the SYNC signal. After receiving the SYNC_BUF signal from phase 2, the current phase starts after waiting for the second SET signal to arrive; after receiving the SYNC_BUF signal from phase 3, the current phase starts after waiting for the third SET signal to arrive, and so on. In short, if a single phase is operating, there is no SET signal between SYNC_BUF signals; if two phases are operating, there is one SE signal T between SYNC_BUF signals; if three phases are operating, there are two SET signals between SYNC_BUF signals, and so on.

[0043] A control signal that can be received across different phases can be called a global control signal. In one embodiment, the signal SET can be used as the global control signal for multi-phase constant on-time control technology, and the signal SYNC can also be used as a global control signal. Signals SYNC and SYNC_BUF serve as synchronization control signals. Unlike the control method where the next phase is pulled high after the current phase is turned on, in this control method, signals SYNC and SYNC_BUF are low-latency global signals. After determining the master-slave phase phase based on the communication interface or external passive components, the master and slave phases internally set their own phases and coordinate with signals SET / SYNC / SYNC_BUF. The timing of BUF determines the control of the constant conduction time of the main phase. These schemes all fall within the protection scope of this invention, including but not limited to the following: the polarity of the signal SYNC / SYNC_BUF and the main phase signal SET are the same or opposite; the signal SYNC / SYNC_BUF and the main phase signal SET are synchronized or delayed by a certain period of time; the signal SYNC / SYNC_BUF and the first slave phase signal SET are synchronized or delayed by a certain period of time; it also includes the signal SET / SYNC / SYNC_BUF cooperating to sequentially activate the slave phase with single pulses and the signal SET / SYNC / SYNC_BUF cooperating to sequentially activate the main and slave phases with single and multi-pulse intervals.

[0044] In the embodiments and accompanying drawings of this invention, the pins SW, SET, SYNC and signals SW, SET, SYNC, VFB, VREF, etc. are named only for ease of description and do not represent a limitation on the pins or signals.

[0045] This invention can be used for single-phase constant on-time control technology, or for multi-phase parallel control of multiple single-phase constant on-time control chips. It can also achieve multiple outputs on a single chip, which can power a high-current application simultaneously in multi-phase parallel connection, or serve as the core technology of a multi-phase parallel controller. In this invention, the signals SYNC and SYNC_BUF are low-latency global signals. After determining the master-slave phase phase based on the communication interface or external passive components, the master and slave phases internally determine their own constant on-time control based on their own set phase, in conjunction with the timing of signals SET / SYNC / SYNC_BUF. This results in stronger anti-interference and robustness, and more reliable circuitry. More importantly, the slave phase's on / off state is completely controlled by the master phase, enabling transient enhancement in multi-chip scenarios and adaptive phase switching based on current.

[0046] In this invention, the SYNC_BUF signal is only used for chip select and drive enhancement of the SYNC signal. In scenarios where pins are scarce, the SYNC pin and SET pin can be globally connected, thereby saving the SYNC_BUF pin. The internal circuit diagram of the chip is shown below. Figure 4 As shown, the system application block diagram is as follows: Figure 5As shown, since the control methods are similar, they will not be described again here.

[0047] Figure 6 This is a schematic diagram of the control scheme for a DC-DC converter with four single-phase constant on-time DC-DC converters or a multi-phase parallel controller proposed in this invention. L1 is the master phase, L2 is slave phase 1, L3 is slave phase 2, and L4 is slave phase 3. The four phases are turned on sequentially. The SET signal performs overall pulse distribution control, and SYNC is synchronized with one of the SET signals. Referring to the diagram, it is synchronized with the master phase, or it can be synchronized with slave phase 1, slave phase 2, or slave phase 3. The SYNC signal is separated by three SET signals, indicating that there are three slave phases. Including the master phase, a total of four phases are controlled. The master-slave phase control chip or control module proposed in this invention determines the constant on-time control of the current phase based on its own set phase and the timing of the SET / SYNC / SYNC_BUF signals. This results in stronger anti-interference and robustness, and more reliable circuitry.

[0048] Figure 7 This is a schematic diagram illustrating the switching from 4-phase control to 3-phase control in a multi-phase control scheme of a 4-phase constant conduction time DC-DC converter or a multi-phase parallel controller proposed in this invention. L1 is the master phase, L2 is slave phase 1, L3 is slave phase 2, and L4 is slave phase 3. The signal SET performs overall pulse distribution control, and the signal SYNC is synchronized with one of the phase signals SET. Referring to the diagram, it is synchronized with the master phase, or it can be synchronized with slave phase 1, slave phase 2, or slave phase 3. When PHASE_NUM = 4, the 4 phases are turned on sequentially. When the communication protocol or external pin controls PHASE_NUM = 3, only 3 phases need to work. At this time, the number of SET signals between the two SYNC signals controlled by the master phase decreases from 3 to 2. At this time, slave phase 3 is no longer turned on, and the current of inductor L4 gradually decreases to 0.

[0049] Figure 8 This is a schematic diagram illustrating the switching from 3-phase control to 2-phase control in a multi-phase control scheme of a 4-phase constant conduction time DC-DC converter or a multi-phase parallel controller proposed in this invention. L1 is the master phase, L2 is slave phase 1, L3 is slave phase 2, and L4 is slave phase 3. The signal SET performs overall pulse distribution control, and the signal SYNC is synchronized with one of the phase signals SET. Referring to the diagram, it is synchronized with the master phase, or it can be synchronized with slave phase 1, slave phase 2, or slave phase 3. When PHASE_NUM = 3, the 3 phases are turned on sequentially. When the communication protocol or external pin control PHASE_NUM = 2, only 2 phases need to work. At this time, the number of SET signals between the two SYNC signals controlled by the master phase decreases from 2 to 1. At this time, slave phases 2 and 3 are no longer turned on, and the current of inductor L3 gradually decreases to 0.

[0050] Figure 9This is a schematic diagram illustrating the switching from 2-phase control to 3-phase control in a multi-phase control scheme of a 4-phase constant conduction time DC-DC converter or a multi-phase parallel controller proposed in this invention. L1 is the master phase, L2 is slave phase 1, L3 is slave phase 2, and L4 is slave phase 3. The signal SET performs overall pulse distribution control, and the signal SYNC is synchronized with one of the phase SET signals. Referring to the diagram, it is synchronized with the master phase, or it can be synchronized with slave phase 1, slave phase 2, or slave phase 3. When PHASE_NUM = 2, the two phases are turned on sequentially. When the communication protocol or external pin control PHASE_NUM = 3, only 3 phases need to work. At this time, the number of SET signals between the two SYNC signals controlled by the master phase decreases from 1 to 2. At this time, slave phase 2 is turned on, and the current of inductor L3 gradually increases to be equal to that of inductors L1 and L2.

[0051] Figure 10 This invention presents a schematic diagram illustrating the switching from 3-phase control to 4-phase control in a multi-phase parallel controller or a control scheme for four single-phase constant-time DC-DC converters. L1 is the master phase, L2 is slave phase 1, L3 is slave phase 2, and L4 is slave phase 3. The signal SET performs overall pulse distribution control, and the signal SYNC is synchronized with one of the phase SET signals. Referring to the diagram, it is synchronized with the master phase, or it can be synchronized with slave phase 1, slave phase 2, or slave phase 3. When PHASE_NUM = 3, the three phases are turned on sequentially. When the communication protocol or external pin control PHASE_NUM = 4, all four phases need to work simultaneously. In this case, the number of SET signals between the two SYNC signals controlling the master phase decreases from two to three. At this time, slave phase 3 is turned on, and the current in inductor L4 gradually increases to be equal to that of inductors L1, L2, and L3.

[0052] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A DC-DC converter with constant on-time for single-phase and multi-phase applications, characterized in that, include: The module includes a source signal generation module, a phase number indicator module, a master-slave phase determination module, a PWM generation module, a drive module, and a master-slave phase synchronization signal generation module. The input terminal of the master-slave phase synchronization signal generation module is connected to the output terminal of the source signal generation module, the output terminal of the master-slave phase determination module, and the output terminal of the phase number indicator module, respectively; the input terminal of the master-slave phase synchronization signal generation module is also connected to the signal SYNC; the master-slave phase synchronization signal generation module outputs the signal SET and the signal SYNC_BUF; the output terminal of the master-slave phase synchronization signal generation module is connected to the input terminal of the PWM generation module, the output terminal of the PWM generation module is connected to the drive module, and the drive module outputs the signal SW; The master-slave synchronization signal generation module includes: a control processor, a master-slave synchronization control operation module, and a selection module; The input terminal of the control processor is connected to the output terminal of the comparator in the source signal generation module; the output signal of the control processor is SET; the output terminal of the control processor is connected to the output terminal of the master-slave phase determination module; the input terminal of the master-slave phase synchronization control operation module is connected to the output terminal of the control processor, the output terminal of the master-slave phase determination module, and the output terminal of the phase number indicator module, respectively; the input terminal of the master-slave phase synchronization control operation module is also connected to the signal SYNC; the output terminal of the master-slave phase synchronization control operation module is connected to the input terminal of the PWM generation module and the input terminal of the selection module, respectively, and the input terminal of the selection module is also connected to the signal SYNC; the output signal of the selection module is SYNC_BUF.

2. The DC-DC converter with single-phase and multi-phase constant on-time according to claim 1, characterized in that, The source signal generation module includes: a resistor voltage divider circuit, an operational amplifier, a loop compensation network, a triangular wave signal generation module, and a comparator; the input terminal of the resistor voltage divider circuit is connected to the output voltage, and the output terminal of the resistor voltage divider circuit is connected to the first input terminal of the operational amplifier and the first input terminal of the comparator, respectively; the second input terminal of the operational amplifier is connected to a reference voltage, and the output terminal of the operational amplifier is connected to the third input terminal of the comparator; the output terminal of the triangular wave signal generation module is connected to the second input terminal of the comparator; and the output terminal of the comparator is connected to the input terminal of the master-slave phase synchronization signal generation module.

3. The DC-DC converter with single-phase and multi-phase constant on-time according to claim 2, characterized in that, The resistor voltage divider circuit includes a first resistor, a second resistor, and a capacitor; one end of the first resistor is connected to one end of the capacitor and the output voltage, and the other end of the first resistor is connected to one end of the second resistor, the other end of the capacitor, and the first input terminal of the comparator; the other end of the second resistor is grounded.

4. The DC-DC converter with single-phase and multi-phase constant on-time according to claim 1, characterized in that, The SET signal serves as the global control signal, while the SYNC and SYNC_BUF signals serve as synchronization control signals.

5. The DC-DC converter with single-phase and multi-phase constant on-time according to claim 1, characterized in that, The SYNC_BUF signal generated by the master phase chip is used for multiphase control between the master phase chip and the slave phase chip. It propagates in a low-latency chain between the master phase chip and the slave phase chip and finally returns to the SYNC port of the master phase chip. The SYNC and SYNC_BUF signals generated by the slave phase chip are unrelated to the control of the SET signal.

6. The DC-DC converter with single-phase and multi-phase constant on-time according to claim 1, characterized in that, If the DC-DC converter is operating in single-phase mode, there is no interval between the SYNC_BUF signals and the SET signal; if the DC-DC converter is operating in N-phase mode, there are N-1 intervals between the SYNC_BUF signals and the SET signal, where N is a positive integer greater than or equal to 2.

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